drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c

   1 /*
   2  * c8sectpfe-core.c - C8SECTPFE STi DVB driver
   3  *
   4  * Copyright (c) STMicroelectronics 2015
   5  *
   6  *   Author:Peter Bennett <peter.bennett@st.com>
   7  *          Peter Griffin <peter.griffin@linaro.org>
   8  *
   9  *      This program is free software; you can redistribute it and/or
  10  *      modify it under the terms of the GNU General Public License as
  11  *      published by the Free Software Foundation; either version 2 of
  12  *      the License, or (at your option) any later version.
  13  */
  14 #include <linux/atomic.h>
  15 #include <linux/clk.h>
  16 #include <linux/completion.h>
  17 #include <linux/delay.h>
  18 #include <linux/device.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/dvb/dmx.h>
  21 #include <linux/dvb/frontend.h>
  22 #include <linux/errno.h>
  23 #include <linux/firmware.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/module.h>
  28 #include <linux/of_gpio.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/usb.h>
  32 #include <linux/slab.h>
  33 #include <linux/time.h>
  34 #include <linux/version.h>
  35 #include <linux/wait.h>
  36 #include <linux/pinctrl/pinctrl.h>
  37
  38 #include "c8sectpfe-core.h"
  39 #include "c8sectpfe-common.h"
  40 #include "c8sectpfe-debugfs.h"
  41 #include "dmxdev.h"
  42 #include "dvb_demux.h"
  43 #include "dvb_frontend.h"
  44 #include "dvb_net.h"
  45
  46 #define FIRMWARE_MEMDMA "pti_memdma_h407.elf"
  47 MODULE_FIRMWARE(FIRMWARE_MEMDMA);
  48
  49 #define PID_TABLE_SIZE 1024
  50 #define POLL_MSECS 50
  51
  52 static int load_c8sectpfe_fw(struct c8sectpfei *fei);
  53
  54 #define TS_PKT_SIZE 188
  55 #define HEADER_SIZE (4)
  56 #define PACKET_SIZE (TS_PKT_SIZE+HEADER_SIZE)
  57
  58 #define FEI_ALIGNMENT (32)
  59 /* hw requires minimum of 8*PACKET_SIZE and padded to 8byte boundary */
  60 #define FEI_BUFFER_SIZE (8*PACKET_SIZE*340)
  61
  62 #define FIFO_LEN 1024
  63
  64 static void c8sectpfe_timer_interrupt(unsigned long ac8sectpfei)
  65 {
  66         struct c8sectpfei *fei = (struct c8sectpfei *)ac8sectpfei;
  67         struct channel_info *channel;
  68         int chan_num;
  69
  70         /* iterate through input block channels */
  71         for (chan_num = 0; chan_num < fei->tsin_count; chan_num++) {
  72                 channel = fei->channel_data[chan_num];
  73
  74                 /* is this descriptor initialised and TP enabled */
  75                 if (channel->irec && readl(channel->irec + DMA_PRDS_TPENABLE))
  76                         tasklet_schedule(&channel->tsklet);
  77         }
  78
  79         fei->timer.expires = jiffies +  msecs_to_jiffies(POLL_MSECS);
  80         add_timer(&fei->timer);
  81 }
  82
  83 static void channel_swdemux_tsklet(unsigned long data)
  84 {
  85         struct channel_info *channel = (struct channel_info *)data;
  86         struct c8sectpfei *fei = channel->fei;
  87         unsigned long wp, rp;
  88         int pos, num_packets, n, size;
  89         u8 *buf;
  90
  91         if (unlikely(!channel || !channel->irec))
  92                 return;
  93
  94         wp = readl(channel->irec + DMA_PRDS_BUSWP_TP(0));
  95         rp = readl(channel->irec + DMA_PRDS_BUSRP_TP(0));
  96
  97         pos = rp - channel->back_buffer_busaddr;
  98
  99         /* has it wrapped */
 100         if (wp < rp)
 101                 wp = channel->back_buffer_busaddr + FEI_BUFFER_SIZE;
 102
 103         size = wp - rp;
 104         num_packets = size / PACKET_SIZE;
 105
 106         /* manage cache so data is visible to CPU */
 107         dma_sync_single_for_cpu(fei->dev,
 108                                 rp,
 109                                 size,
 110                                 DMA_FROM_DEVICE);
 111
 112         buf = (u8 *) channel->back_buffer_aligned;
 113
 114         dev_dbg(fei->dev,
 115                 "chan=%d channel=%p num_packets = %d, buf = %p, pos = 0x%x\n\trp=0x%lx, wp=0x%lx\n",
 116                 channel->tsin_id, channel, num_packets, buf, pos, rp, wp);
 117
 118         for (n = 0; n < num_packets; n++) {
 119                 dvb_dmx_swfilter_packets(
 120                         &fei->c8sectpfe[0]->
 121                                 demux[channel->demux_mapping].dvb_demux,
 122                         &buf[pos], 1);
 123
 124                 pos += PACKET_SIZE;
 125         }
 126
 127         /* advance the read pointer */
 128         if (wp == (channel->back_buffer_busaddr + FEI_BUFFER_SIZE))
 129                 writel(channel->back_buffer_busaddr, channel->irec +
 130                         DMA_PRDS_BUSRP_TP(0));
 131         else
 132                 writel(wp, channel->irec + DMA_PRDS_BUSRP_TP(0));
 133 }
 134
 135 static int c8sectpfe_start_feed(struct dvb_demux_feed *dvbdmxfeed)
 136 {
 137         struct dvb_demux *demux = dvbdmxfeed->demux;
 138         struct stdemux *stdemux = (struct stdemux *)demux->priv;
 139         struct c8sectpfei *fei = stdemux->c8sectpfei;
 140         struct channel_info *channel;
 141         u32 tmp;
 142         unsigned long *bitmap;
 143         int ret;
 144
 145         switch (dvbdmxfeed->type) {
 146         case DMX_TYPE_TS:
 147                 break;
 148         case DMX_TYPE_SEC:
 149                 break;
 150         default:
 151                 dev_err(fei->dev, "%s:%d Error bailing\n"
 152                         , __func__, __LINE__);
 153                 return -EINVAL;
 154         }
 155
 156         if (dvbdmxfeed->type == DMX_TYPE_TS) {
 157                 switch (dvbdmxfeed->pes_type) {
 158                 case DMX_PES_VIDEO:
 159                 case DMX_PES_AUDIO:
 160                 case DMX_PES_TELETEXT:
 161                 case DMX_PES_PCR:
 162                 case DMX_PES_OTHER:
 163                         break;
 164                 default:
 165                         dev_err(fei->dev, "%s:%d Error bailing\n"
 166                                 , __func__, __LINE__);
 167                         return -EINVAL;
 168                 }
 169         }
 170
 171         if (!atomic_read(&fei->fw_loaded)) {
 172                 ret = load_c8sectpfe_fw(fei);
 173                 if (ret)
 174                         return ret;
 175         }
 176
 177         mutex_lock(&fei->lock);
 178
 179         channel = fei->channel_data[stdemux->tsin_index];
 180
 181         bitmap = (unsigned long *) channel->pid_buffer_aligned;
 182
 183         /* 8192 is a special PID */
 184         if (dvbdmxfeed->pid == 8192) {
 185                 tmp = readl(fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id));
 186                 tmp &= ~C8SECTPFE_PID_ENABLE;
 187                 writel(tmp, fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id));
 188
 189         } else {
 190                 bitmap_set(bitmap, dvbdmxfeed->pid, 1);
 191         }
 192
 193         /* manage cache so PID bitmap is visible to HW */
 194         dma_sync_single_for_device(fei->dev,
 195                                         channel->pid_buffer_busaddr,
 196                                         PID_TABLE_SIZE,
 197                                         DMA_TO_DEVICE);
 198
 199         channel->active = 1;
 200
 201         if (fei->global_feed_count == 0) {
 202                 fei->timer.expires = jiffies +
 203                         msecs_to_jiffies(msecs_to_jiffies(POLL_MSECS));
 204
 205                 add_timer(&fei->timer);
 206         }
 207
 208         if (stdemux->running_feed_count == 0) {
 209
 210                 dev_dbg(fei->dev, "Starting channel=%p\n", channel);
 211
 212                 tasklet_init(&channel->tsklet, channel_swdemux_tsklet,
 213                              (unsigned long) channel);
 214
 215                 /* Reset the internal inputblock sram pointers */
 216                 writel(channel->fifo,
 217                         fei->io + C8SECTPFE_IB_BUFF_STRT(channel->tsin_id));
 218                 writel(channel->fifo + FIFO_LEN - 1,
 219                         fei->io + C8SECTPFE_IB_BUFF_END(channel->tsin_id));
 220
 221                 writel(channel->fifo,
 222                         fei->io + C8SECTPFE_IB_READ_PNT(channel->tsin_id));
 223                 writel(channel->fifo,
 224                         fei->io + C8SECTPFE_IB_WRT_PNT(channel->tsin_id));
 225
 226
 227                 /* reset read / write memdma ptrs for this channel */
 228                 writel(channel->back_buffer_busaddr, channel->irec +
 229                         DMA_PRDS_BUSBASE_TP(0));
 230
 231                 tmp = channel->back_buffer_busaddr + FEI_BUFFER_SIZE - 1;
 232                 writel(tmp, channel->irec + DMA_PRDS_BUSTOP_TP(0));
 233
 234                 writel(channel->back_buffer_busaddr, channel->irec +
 235                         DMA_PRDS_BUSWP_TP(0));
 236
 237                 /* Issue a reset and enable InputBlock */
 238                 writel(C8SECTPFE_SYS_ENABLE | C8SECTPFE_SYS_RESET
 239                         , fei->io + C8SECTPFE_IB_SYS(channel->tsin_id));
 240
 241                 /* and enable the tp */
 242                 writel(0x1, channel->irec + DMA_PRDS_TPENABLE);
 243
 244                 dev_dbg(fei->dev, "%s:%d Starting DMA feed on stdemux=%p\n"
 245                         , __func__, __LINE__, stdemux);
 246         }
 247
 248         stdemux->running_feed_count++;
 249         fei->global_feed_count++;
 250
 251         mutex_unlock(&fei->lock);
 252
 253         return 0;
 254 }
 255
 256 static int c8sectpfe_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
 257 {
 258
 259         struct dvb_demux *demux = dvbdmxfeed->demux;
 260         struct stdemux *stdemux = (struct stdemux *)demux->priv;
 261         struct c8sectpfei *fei = stdemux->c8sectpfei;
 262         struct channel_info *channel;
 263         int idlereq;
 264         u32 tmp;
 265         int ret;
 266         unsigned long *bitmap;
 267
 268         if (!atomic_read(&fei->fw_loaded)) {
 269                 ret = load_c8sectpfe_fw(fei);
 270                 if (ret)
 271                         return ret;
 272         }
 273
 274         mutex_lock(&fei->lock);
 275
 276         channel = fei->channel_data[stdemux->tsin_index];
 277
 278         bitmap = (unsigned long *) channel->pid_buffer_aligned;
 279
 280         if (dvbdmxfeed->pid == 8192) {
 281                 tmp = readl(fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id));
 282                 tmp |= C8SECTPFE_PID_ENABLE;
 283                 writel(tmp, fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id));
 284         } else {
 285                 bitmap_clear(bitmap, dvbdmxfeed->pid, 1);
 286         }
 287
 288         /* manage cache so data is visible to HW */
 289         dma_sync_single_for_device(fei->dev,
 290                                         channel->pid_buffer_busaddr,
 291                                         PID_TABLE_SIZE,
 292                                         DMA_TO_DEVICE);
 293
 294         if (--stdemux->running_feed_count == 0) {
 295
 296                 channel = fei->channel_data[stdemux->tsin_index];
 297
 298                 /* TP re-configuration on page 168 of functional spec */
 299
 300                 /* disable IB (prevents more TS data going to memdma) */
 301                 writel(0, fei->io + C8SECTPFE_IB_SYS(channel->tsin_id));
 302
 303                 /* disable this channels descriptor */
 304                 writel(0,  channel->irec + DMA_PRDS_TPENABLE);
 305
 306                 tasklet_disable(&channel->tsklet);
 307
 308                 /* now request memdma channel goes idle */
 309                 idlereq = (1 << channel->tsin_id) | IDLEREQ;
 310                 writel(idlereq, fei->io + DMA_IDLE_REQ);
 311
 312                 /* wait for idle irq handler to signal completion */
 313                 ret = wait_for_completion_timeout(&channel->idle_completion,
 314                                                 msecs_to_jiffies(100));
 315
 316                 if (ret == 0)
 317                         dev_warn(fei->dev,
 318                                 "Timeout waiting for idle irq on tsin%d\n",
 319                                 channel->tsin_id);
 320
 321                 reinit_completion(&channel->idle_completion);
 322
 323                 /* reset read / write ptrs for this channel */
 324
 325                 writel(channel->back_buffer_busaddr,
 326                         channel->irec + DMA_PRDS_BUSBASE_TP(0));
 327
 328                 tmp = channel->back_buffer_busaddr + FEI_BUFFER_SIZE - 1;
 329                 writel(tmp, channel->irec + DMA_PRDS_BUSTOP_TP(0));
 330
 331                 writel(channel->back_buffer_busaddr,
 332                         channel->irec + DMA_PRDS_BUSWP_TP(0));
 333
 334                 dev_dbg(fei->dev,
 335                         "%s:%d stopping DMA feed on stdemux=%p channel=%d\n",
 336                         __func__, __LINE__, stdemux, channel->tsin_id);
 337
 338                 /* turn off all PIDS in the bitmap */
 339                 memset((void *)channel->pid_buffer_aligned
 340                         , 0x00, PID_TABLE_SIZE);
 341
 342                 /* manage cache so data is visible to HW */
 343                 dma_sync_single_for_device(fei->dev,
 344                                         channel->pid_buffer_busaddr,
 345                                         PID_TABLE_SIZE,
 346                                         DMA_TO_DEVICE);
 347
 348                 channel->active = 0;
 349         }
 350
 351         if (--fei->global_feed_count == 0) {
 352                 dev_dbg(fei->dev, "%s:%d global_feed_count=%d\n"
 353                         , __func__, __LINE__, fei->global_feed_count);
 354
 355                 del_timer(&fei->timer);
 356         }
 357
 358         mutex_unlock(&fei->lock);
 359
 360         return 0;
 361 }
 362
 363 static struct channel_info *find_channel(struct c8sectpfei *fei, int tsin_num)
 364 {
 365         int i;
 366
 367         for (i = 0; i < C8SECTPFE_MAX_TSIN_CHAN; i++) {
 368                 if (!fei->channel_data[i])
 369                         continue;
 370
 371                 if (fei->channel_data[i]->tsin_id == tsin_num)
 372                         return fei->channel_data[i];
 373         }
 374
 375         return NULL;
 376 }
 377
 378 static void c8sectpfe_getconfig(struct c8sectpfei *fei)
 379 {
 380         struct c8sectpfe_hw *hw = &fei->hw_stats;
 381
 382         hw->num_ib = readl(fei->io + SYS_CFG_NUM_IB);
 383         hw->num_mib = readl(fei->io + SYS_CFG_NUM_MIB);
 384         hw->num_swts = readl(fei->io + SYS_CFG_NUM_SWTS);
 385         hw->num_tsout = readl(fei->io + SYS_CFG_NUM_TSOUT);
 386         hw->num_ccsc = readl(fei->io + SYS_CFG_NUM_CCSC);
 387         hw->num_ram = readl(fei->io + SYS_CFG_NUM_RAM);
 388         hw->num_tp = readl(fei->io + SYS_CFG_NUM_TP);
 389
 390         dev_info(fei->dev, "C8SECTPFE hw supports the following:\n");
 391         dev_info(fei->dev, "Input Blocks: %d\n", hw->num_ib);
 392         dev_info(fei->dev, "Merged Input Blocks: %d\n", hw->num_mib);
 393         dev_info(fei->dev, "Software Transport Stream Inputs: %d\n"
 394                                 , hw->num_swts);
 395         dev_info(fei->dev, "Transport Stream Output: %d\n", hw->num_tsout);
 396         dev_info(fei->dev, "Cable Card Converter: %d\n", hw->num_ccsc);
 397         dev_info(fei->dev, "RAMs supported by C8SECTPFE: %d\n", hw->num_ram);
 398         dev_info(fei->dev, "Tango TPs supported by C8SECTPFE: %d\n"
 399                         , hw->num_tp);
 400 }
 401
 402 static irqreturn_t c8sectpfe_idle_irq_handler(int irq, void *priv)
 403 {
 404         struct c8sectpfei *fei = priv;
 405         struct channel_info *chan;
 406         int bit;
 407         unsigned long tmp = readl(fei->io + DMA_IDLE_REQ);
 408
 409         /* page 168 of functional spec: Clear the idle request
 410            by writing 0 to the C8SECTPFE_DMA_IDLE_REQ register. */
 411
 412         /* signal idle completion */
 413         for_each_set_bit(bit, &tmp, fei->hw_stats.num_ib) {
 414
 415                 chan = find_channel(fei, bit);
 416
 417                 if (chan)
 418                         complete(&chan->idle_completion);
 419         }
 420
 421         writel(0, fei->io + DMA_IDLE_REQ);
 422
 423         return IRQ_HANDLED;
 424 }
 425
 426
 427 static void free_input_block(struct c8sectpfei *fei, struct channel_info *tsin)
 428 {
 429         if (!fei || !tsin)
 430                 return;
 431
 432         if (tsin->back_buffer_busaddr)
 433                 if (!dma_mapping_error(fei->dev, tsin->back_buffer_busaddr))
 434                         dma_unmap_single(fei->dev, tsin->back_buffer_busaddr,
 435                                 FEI_BUFFER_SIZE, DMA_BIDIRECTIONAL);
 436
 437         kfree(tsin->back_buffer_start);
 438
 439         if (tsin->pid_buffer_busaddr)
 440                 if (!dma_mapping_error(fei->dev, tsin->pid_buffer_busaddr))
 441                         dma_unmap_single(fei->dev, tsin->pid_buffer_busaddr,
 442                                 PID_TABLE_SIZE, DMA_BIDIRECTIONAL);
 443
 444         kfree(tsin->pid_buffer_start);
 445 }
 446
 447 #define MAX_NAME 20
 448
 449 static int configure_memdma_and_inputblock(struct c8sectpfei *fei,
 450                                 struct channel_info *tsin)
 451 {
 452         int ret;
 453         u32 tmp;
 454         char tsin_pin_name[MAX_NAME];
 455
 456         if (!fei || !tsin)
 457                 return -EINVAL;
 458
 459         dev_dbg(fei->dev, "%s:%d Configuring channel=%p tsin=%d\n"
 460                 , __func__, __LINE__, tsin, tsin->tsin_id);
 461
 462         init_completion(&tsin->idle_completion);
 463
 464         tsin->back_buffer_start = kzalloc(FEI_BUFFER_SIZE +
 465                                         FEI_ALIGNMENT, GFP_KERNEL);
 466
 467         if (!tsin->back_buffer_start) {
 468                 ret = -ENOMEM;
 469                 goto err_unmap;
 470         }
 471
 472         /* Ensure backbuffer is 32byte aligned */
 473         tsin->back_buffer_aligned = tsin->back_buffer_start
 474                 + FEI_ALIGNMENT;
 475
 476         tsin->back_buffer_aligned = (void *)
 477                 (((uintptr_t) tsin->back_buffer_aligned) & ~0x1F);
 478
 479         tsin->back_buffer_busaddr = dma_map_single(fei->dev,
 480                                         (void *)tsin->back_buffer_aligned,
 481                                         FEI_BUFFER_SIZE,
 482                                         DMA_BIDIRECTIONAL);
 483
 484         if (dma_mapping_error(fei->dev, tsin->back_buffer_busaddr)) {
 485                 dev_err(fei->dev, "failed to map back_buffer\n");
 486                 ret = -EFAULT;
 487                 goto err_unmap;
 488         }
 489
 490         /*
 491          * The pid buffer can be configured (in hw) for byte or bit
 492          * per pid. By powers of deduction we conclude stih407 family
 493          * is configured (at SoC design stage) for bit per pid.
 494          */
 495         tsin->pid_buffer_start = kzalloc(2048, GFP_KERNEL);
 496
 497         if (!tsin->pid_buffer_start) {
 498                 ret = -ENOMEM;
 499                 goto err_unmap;
 500         }
 501
 502         /*
 503          * PID buffer needs to be aligned to size of the pid table
 504          * which at bit per pid is 1024 bytes (8192 pids / 8).
 505          * PIDF_BASE register enforces this alignment when writing
 506          * the register.
 507          */
 508
 509         tsin->pid_buffer_aligned = tsin->pid_buffer_start +
 510                 PID_TABLE_SIZE;
 511
 512         tsin->pid_buffer_aligned = (void *)
 513                 (((uintptr_t) tsin->pid_buffer_aligned) & ~0x3ff);
 514
 515         tsin->pid_buffer_busaddr = dma_map_single(fei->dev,
 516                                                 tsin->pid_buffer_aligned,
 517                                                 PID_TABLE_SIZE,
 518                                                 DMA_BIDIRECTIONAL);
 519
 520         if (dma_mapping_error(fei->dev, tsin->pid_buffer_busaddr)) {
 521                 dev_err(fei->dev, "failed to map pid_bitmap\n");
 522                 ret = -EFAULT;
 523                 goto err_unmap;
 524         }
 525
 526         /* manage cache so pid bitmap is visible to HW */
 527         dma_sync_single_for_device(fei->dev,
 528                                 tsin->pid_buffer_busaddr,
 529                                 PID_TABLE_SIZE,
 530                                 DMA_TO_DEVICE);
 531
 532         snprintf(tsin_pin_name, MAX_NAME, "tsin%d-%s", tsin->tsin_id,
 533                 (tsin->serial_not_parallel ? "serial" : "parallel"));
 534
 535         tsin->pstate = pinctrl_lookup_state(fei->pinctrl, tsin_pin_name);
 536         if (IS_ERR(tsin->pstate)) {
 537                 dev_err(fei->dev, "%s: pinctrl_lookup_state couldn't find %s state\n"
 538                         , __func__, tsin_pin_name);
 539                 ret = PTR_ERR(tsin->pstate);
 540                 goto err_unmap;
 541         }
 542
 543         ret = pinctrl_select_state(fei->pinctrl, tsin->pstate);
 544
 545         if (ret) {
 546                 dev_err(fei->dev, "%s: pinctrl_select_state failed\n"
 547                         , __func__);
 548                 goto err_unmap;
 549         }
 550
 551         /* Enable this input block */
 552         tmp = readl(fei->io + SYS_INPUT_CLKEN);
 553         tmp |= BIT(tsin->tsin_id);
 554         writel(tmp, fei->io + SYS_INPUT_CLKEN);
 555
 556         if (tsin->serial_not_parallel)
 557                 tmp |= C8SECTPFE_SERIAL_NOT_PARALLEL;
 558
 559         if (tsin->invert_ts_clk)
 560                 tmp |= C8SECTPFE_INVERT_TSCLK;
 561
 562         if (tsin->async_not_sync)
 563                 tmp |= C8SECTPFE_ASYNC_NOT_SYNC;
 564
 565         tmp |= C8SECTPFE_ALIGN_BYTE_SOP | C8SECTPFE_BYTE_ENDIANNESS_MSB;
 566
 567         writel(tmp, fei->io + C8SECTPFE_IB_IP_FMT_CFG(tsin->tsin_id));
 568
 569         writel(C8SECTPFE_SYNC(0x9) |
 570                 C8SECTPFE_DROP(0x9) |
 571                 C8SECTPFE_TOKEN(0x47),
 572                 fei->io + C8SECTPFE_IB_SYNCLCKDRP_CFG(tsin->tsin_id));
 573
 574         writel(TS_PKT_SIZE, fei->io + C8SECTPFE_IB_PKT_LEN(tsin->tsin_id));
 575
 576         /* Place the FIFO's at the end of the irec descriptors */
 577
 578         tsin->fifo = (tsin->tsin_id * FIFO_LEN);
 579
 580         writel(tsin->fifo, fei->io + C8SECTPFE_IB_BUFF_STRT(tsin->tsin_id));
 581         writel(tsin->fifo + FIFO_LEN - 1,
 582                 fei->io + C8SECTPFE_IB_BUFF_END(tsin->tsin_id));
 583
 584         writel(tsin->fifo, fei->io + C8SECTPFE_IB_READ_PNT(tsin->tsin_id));
 585         writel(tsin->fifo, fei->io + C8SECTPFE_IB_WRT_PNT(tsin->tsin_id));
 586
 587         writel(tsin->pid_buffer_busaddr,
 588                 fei->io + PIDF_BASE(tsin->tsin_id));
 589
 590         dev_dbg(fei->dev, "chan=%d PIDF_BASE=0x%x pid_bus_addr=%pad\n",
 591                 tsin->tsin_id, readl(fei->io + PIDF_BASE(tsin->tsin_id)),
 592                 &tsin->pid_buffer_busaddr);
 593
 594         /* Configure and enable HW PID filtering */
 595
 596         /*
 597          * The PID value is created by assembling the first 8 bytes of
 598          * the TS packet into a 64-bit word in big-endian format. A
 599          * slice of that 64-bit word is taken from
 600          * (PID_OFFSET+PID_NUM_BITS-1) to PID_OFFSET.
 601          */
 602         tmp = (C8SECTPFE_PID_ENABLE | C8SECTPFE_PID_NUMBITS(13)
 603                 | C8SECTPFE_PID_OFFSET(40));
 604
 605         writel(tmp, fei->io + C8SECTPFE_IB_PID_SET(tsin->tsin_id));
 606
 607         dev_dbg(fei->dev, "chan=%d setting wp: %d, rp: %d, buf: %d-%d\n",
 608                 tsin->tsin_id,
 609                 readl(fei->io + C8SECTPFE_IB_WRT_PNT(tsin->tsin_id)),
 610                 readl(fei->io + C8SECTPFE_IB_READ_PNT(tsin->tsin_id)),
 611                 readl(fei->io + C8SECTPFE_IB_BUFF_STRT(tsin->tsin_id)),
 612                 readl(fei->io + C8SECTPFE_IB_BUFF_END(tsin->tsin_id)));
 613
 614         /* Get base addpress of pointer record block from DMEM */
 615         tsin->irec = fei->io + DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET +
 616                         readl(fei->io + DMA_PTRREC_BASE);
 617
 618         /* fill out pointer record data structure */
 619
 620         /* advance pointer record block to our channel */
 621         tsin->irec += (tsin->tsin_id * DMA_PRDS_SIZE);
 622
 623         writel(tsin->fifo, tsin->irec + DMA_PRDS_MEMBASE);
 624
 625         writel(tsin->fifo + FIFO_LEN - 1, tsin->irec + DMA_PRDS_MEMTOP);
 626
 627         writel((188 + 7)&~7, tsin->irec + DMA_PRDS_PKTSIZE);
 628
 629         writel(0x1, tsin->irec + DMA_PRDS_TPENABLE);
 630
 631         /* read/write pointers with physical bus address */
 632
 633         writel(tsin->back_buffer_busaddr, tsin->irec + DMA_PRDS_BUSBASE_TP(0));
 634
 635         tmp = tsin->back_buffer_busaddr + FEI_BUFFER_SIZE - 1;
 636         writel(tmp, tsin->irec + DMA_PRDS_BUSTOP_TP(0));
 637
 638         writel(tsin->back_buffer_busaddr, tsin->irec + DMA_PRDS_BUSWP_TP(0));
 639         writel(tsin->back_buffer_busaddr, tsin->irec + DMA_PRDS_BUSRP_TP(0));
 640
 641         /* initialize tasklet */
 642         tasklet_init(&tsin->tsklet, channel_swdemux_tsklet,
 643                 (unsigned long) tsin);
 644
 645         return 0;
 646
 647 err_unmap:
 648         free_input_block(fei, tsin);
 649         return ret;
 650 }
 651
 652 static irqreturn_t c8sectpfe_error_irq_handler(int irq, void *priv)
 653 {
 654         struct c8sectpfei *fei = priv;
 655
 656         dev_err(fei->dev, "%s: error handling not yet implemented\n"
 657                 , __func__);
 658
 659         /*
 660          * TODO FIXME we should detect some error conditions here
 661          * and ideally so something about them!
 662          */
 663
 664         return IRQ_HANDLED;
 665 }
 666
 667 static int c8sectpfe_probe(struct platform_device *pdev)
 668 {
 669         struct device *dev = &pdev->dev;
 670         struct device_node *child, *np = dev->of_node;
 671         struct c8sectpfei *fei;
 672         struct resource *res;
 673         int ret, index = 0;
 674         struct channel_info *tsin;
 675
 676         /* Allocate the c8sectpfei structure */
 677         fei = devm_kzalloc(dev, sizeof(struct c8sectpfei), GFP_KERNEL);
 678         if (!fei)
 679                 return -ENOMEM;
 680
 681         fei->dev = dev;
 682
 683         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "c8sectpfe");
 684         fei->io = devm_ioremap_resource(dev, res);
 685         if (IS_ERR(fei->io))
 686                 return PTR_ERR(fei->io);
 687
 688         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 689                                         "c8sectpfe-ram");
 690         fei->sram = devm_ioremap_resource(dev, res);
 691         if (IS_ERR(fei->sram))
 692                 return PTR_ERR(fei->sram);
 693
 694         fei->sram_size = res->end - res->start;
 695
 696         fei->idle_irq = platform_get_irq_byname(pdev, "c8sectpfe-idle-irq");
 697         if (fei->idle_irq < 0) {
 698                 dev_err(dev, "Can't get c8sectpfe-idle-irq\n");
 699                 return fei->idle_irq;
 700         }
 701
 702         fei->error_irq = platform_get_irq_byname(pdev, "c8sectpfe-error-irq");
 703         if (fei->error_irq < 0) {
 704                 dev_err(dev, "Can't get c8sectpfe-error-irq\n");
 705                 return fei->error_irq;
 706         }
 707
 708         platform_set_drvdata(pdev, fei);
 709
 710         fei->c8sectpfeclk = devm_clk_get(dev, "c8sectpfe");
 711         if (IS_ERR(fei->c8sectpfeclk)) {
 712                 dev_err(dev, "c8sectpfe clk not found\n");
 713                 return PTR_ERR(fei->c8sectpfeclk);
 714         }
 715
 716         ret = clk_prepare_enable(fei->c8sectpfeclk);
 717         if (ret) {
 718                 dev_err(dev, "Failed to enable c8sectpfe clock\n");
 719                 return ret;
 720         }
 721
 722         /* to save power disable all IP's (on by default) */
 723         writel(0, fei->io + SYS_INPUT_CLKEN);
 724
 725         /* Enable memdma clock */
 726         writel(MEMDMAENABLE, fei->io + SYS_OTHER_CLKEN);
 727
 728         /* clear internal sram */
 729         memset_io(fei->sram, 0x0, fei->sram_size);
 730
 731         c8sectpfe_getconfig(fei);
 732
 733         ret = devm_request_irq(dev, fei->idle_irq, c8sectpfe_idle_irq_handler,
 734                         0, "c8sectpfe-idle-irq", fei);
 735         if (ret) {
 736                 dev_err(dev, "Can't register c8sectpfe-idle-irq IRQ.\n");
 737                 goto err_clk_disable;
 738         }
 739
 740         ret = devm_request_irq(dev, fei->error_irq,
 741                                 c8sectpfe_error_irq_handler, 0,
 742                                 "c8sectpfe-error-irq", fei);
 743         if (ret) {
 744                 dev_err(dev, "Can't register c8sectpfe-error-irq IRQ.\n");
 745                 goto err_clk_disable;
 746         }
 747
 748         fei->tsin_count = of_get_child_count(np);
 749
 750         if (fei->tsin_count > C8SECTPFE_MAX_TSIN_CHAN ||
 751                 fei->tsin_count > fei->hw_stats.num_ib) {
 752
 753                 dev_err(dev, "More tsin declared than exist on SoC!\n");
 754                 ret = -EINVAL;
 755                 goto err_clk_disable;
 756         }
 757
 758         fei->pinctrl = devm_pinctrl_get(dev);
 759
 760         if (IS_ERR(fei->pinctrl)) {
 761                 dev_err(dev, "Error getting tsin pins\n");
 762                 ret = PTR_ERR(fei->pinctrl);
 763                 goto err_clk_disable;
 764         }
 765
 766         for_each_child_of_node(np, child) {
 767                 struct device_node *i2c_bus;
 768
 769                 fei->channel_data[index] = devm_kzalloc(dev,
 770                                                 sizeof(struct channel_info),
 771                                                 GFP_KERNEL);
 772
 773                 if (!fei->channel_data[index]) {
 774                         ret = -ENOMEM;
 775                         goto err_clk_disable;
 776                 }
 777
 778                 tsin = fei->channel_data[index];
 779
 780                 tsin->fei = fei;
 781
 782                 ret = of_property_read_u32(child, "tsin-num", &tsin->tsin_id);
 783                 if (ret) {
 784                         dev_err(&pdev->dev, "No tsin_num found\n");
 785                         goto err_clk_disable;
 786                 }
 787
 788                 /* sanity check value */
 789                 if (tsin->tsin_id > fei->hw_stats.num_ib) {
 790                         dev_err(&pdev->dev,
 791                                 "tsin-num %d specified greater than number\n\tof input block hw in SoC! (%d)",
 792                                 tsin->tsin_id, fei->hw_stats.num_ib);
 793                         ret = -EINVAL;
 794                         goto err_clk_disable;
 795                 }
 796
 797                 tsin->invert_ts_clk = of_property_read_bool(child,
 798                                                         "invert-ts-clk");
 799
 800                 tsin->serial_not_parallel = of_property_read_bool(child,
 801                                                         "serial-not-parallel");
 802
 803                 tsin->async_not_sync = of_property_read_bool(child,
 804                                                         "async-not-sync");
 805
 806                 ret = of_property_read_u32(child, "dvb-card",
 807                                         &tsin->dvb_card);
 808                 if (ret) {
 809                         dev_err(&pdev->dev, "No dvb-card found\n");
 810                         goto err_clk_disable;
 811                 }
 812
 813                 i2c_bus = of_parse_phandle(child, "i2c-bus", 0);
 814                 if (!i2c_bus) {
 815                         dev_err(&pdev->dev, "No i2c-bus found\n");
 816                         ret = -ENODEV;
 817                         goto err_clk_disable;
 818                 }
 819                 tsin->i2c_adapter =
 820                         of_find_i2c_adapter_by_node(i2c_bus);
 821                 if (!tsin->i2c_adapter) {
 822                         dev_err(&pdev->dev, "No i2c adapter found\n");
 823                         of_node_put(i2c_bus);
 824                         ret = -ENODEV;
 825                         goto err_clk_disable;
 826                 }
 827                 of_node_put(i2c_bus);
 828
 829                 tsin->rst_gpio = of_get_named_gpio(child, "reset-gpios", 0);
 830
 831                 ret = gpio_is_valid(tsin->rst_gpio);
 832                 if (!ret) {
 833                         dev_err(dev,
 834                                 "reset gpio for tsin%d not valid (gpio=%d)\n",
 835                                 tsin->tsin_id, tsin->rst_gpio);
 836                         goto err_clk_disable;
 837                 }
 838
 839                 ret = devm_gpio_request_one(dev, tsin->rst_gpio,
 840                                         GPIOF_OUT_INIT_LOW, "NIM reset");
 841                 if (ret && ret != -EBUSY) {
 842                         dev_err(dev, "Can't request tsin%d reset gpio\n"
 843                                 , fei->channel_data[index]->tsin_id);
 844                         goto err_clk_disable;
 845                 }
 846
 847                 if (!ret) {
 848                         /* toggle reset lines */
 849                         gpio_direction_output(tsin->rst_gpio, 0);
 850                         usleep_range(3500, 5000);
 851                         gpio_direction_output(tsin->rst_gpio, 1);
 852                         usleep_range(3000, 5000);
 853                 }
 854
 855                 tsin->demux_mapping = index;
 856
 857                 dev_dbg(fei->dev,
 858                         "channel=%p n=%d tsin_num=%d, invert-ts-clk=%d\n\tserial-not-parallel=%d pkt-clk-valid=%d dvb-card=%d\n",
 859                         fei->channel_data[index], index,
 860                         tsin->tsin_id, tsin->invert_ts_clk,
 861                         tsin->serial_not_parallel, tsin->async_not_sync,
 862                         tsin->dvb_card);
 863
 864                 index++;
 865         }
 866
 867         /* Setup timer interrupt */
 868         setup_timer(&fei->timer, c8sectpfe_timer_interrupt,
 869                     (unsigned long)fei);
 870
 871         mutex_init(&fei->lock);
 872
 873         /* Get the configuration information about the tuners */
 874         ret = c8sectpfe_tuner_register_frontend(&fei->c8sectpfe[0],
 875                                         (void *)fei,
 876                                         c8sectpfe_start_feed,
 877                                         c8sectpfe_stop_feed);
 878         if (ret) {
 879                 dev_err(dev, "c8sectpfe_tuner_register_frontend failed (%d)\n",
 880                         ret);
 881                 goto err_clk_disable;
 882         }
 883
 884         c8sectpfe_debugfs_init(fei);
 885
 886         return 0;
 887
 888 err_clk_disable:
 889         clk_disable_unprepare(fei->c8sectpfeclk);
 890         return ret;
 891 }
 892
 893 static int c8sectpfe_remove(struct platform_device *pdev)
 894 {
 895         struct c8sectpfei *fei = platform_get_drvdata(pdev);
 896         struct channel_info *channel;
 897         int i;
 898
 899         wait_for_completion(&fei->fw_ack);
 900
 901         c8sectpfe_tuner_unregister_frontend(fei->c8sectpfe[0], fei);
 902
 903         /*
 904          * Now loop through and un-configure each of the InputBlock resources
 905          */
 906         for (i = 0; i < fei->tsin_count; i++) {
 907                 channel = fei->channel_data[i];
 908                 free_input_block(fei, channel);
 909         }
 910
 911         c8sectpfe_debugfs_exit(fei);
 912
 913         dev_info(fei->dev, "Stopping memdma SLIM core\n");
 914         if (readl(fei->io + DMA_CPU_RUN))
 915                 writel(0x0,  fei->io + DMA_CPU_RUN);
 916
 917         /* unclock all internal IP's */
 918         if (readl(fei->io + SYS_INPUT_CLKEN))
 919                 writel(0, fei->io + SYS_INPUT_CLKEN);
 920
 921         if (readl(fei->io + SYS_OTHER_CLKEN))
 922                 writel(0, fei->io + SYS_OTHER_CLKEN);
 923
 924         if (fei->c8sectpfeclk)
 925                 clk_disable_unprepare(fei->c8sectpfeclk);
 926
 927         return 0;
 928 }
 929
 930
 931 static int configure_channels(struct c8sectpfei *fei)
 932 {
 933         int index = 0, ret;
 934         struct channel_info *tsin;
 935         struct device_node *child, *np = fei->dev->of_node;
 936
 937         /* iterate round each tsin and configure memdma descriptor and IB hw */
 938         for_each_child_of_node(np, child) {
 939
 940                 tsin = fei->channel_data[index];
 941
 942                 ret = configure_memdma_and_inputblock(fei,
 943                                                 fei->channel_data[index]);
 944
 945                 if (ret) {
 946                         dev_err(fei->dev,
 947                                 "configure_memdma_and_inputblock failed\n");
 948                         goto err_unmap;
 949                 }
 950                 index++;
 951         }
 952
 953         return 0;
 954
 955 err_unmap:
 956         for (index = 0; index < fei->tsin_count; index++) {
 957                 tsin = fei->channel_data[index];
 958                 free_input_block(fei, tsin);
 959         }
 960         return ret;
 961 }
 962
 963 static int
 964 c8sectpfe_elf_sanity_check(struct c8sectpfei *fei, const struct firmware *fw)
 965 {
 966         struct elf32_hdr *ehdr;
 967         char class;
 968
 969         if (!fw) {
 970                 dev_err(fei->dev, "failed to load %s\n", FIRMWARE_MEMDMA);
 971                 return -EINVAL;
 972         }
 973
 974         if (fw->size < sizeof(struct elf32_hdr)) {
 975                 dev_err(fei->dev, "Image is too small\n");
 976                 return -EINVAL;
 977         }
 978
 979         ehdr = (struct elf32_hdr *)fw->data;
 980
 981         /* We only support ELF32 at this point */
 982         class = ehdr->e_ident[EI_CLASS];
 983         if (class != ELFCLASS32) {
 984                 dev_err(fei->dev, "Unsupported class: %d\n", class);
 985                 return -EINVAL;
 986         }
 987
 988         if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB) {
 989                 dev_err(fei->dev, "Unsupported firmware endianness\n");
 990                 return -EINVAL;
 991         }
 992
 993         if (fw->size < ehdr->e_shoff + sizeof(struct elf32_shdr)) {
 994                 dev_err(fei->dev, "Image is too small\n");
 995                 return -EINVAL;
 996         }
 997
 998         if (memcmp(ehdr->e_ident, ELFMAG, SELFMAG)) {
 999                 dev_err(fei->dev, "Image is corrupted (bad magic)\n");
1000                 return -EINVAL;
1001         }
1002
1003         /* Check ELF magic */
1004         ehdr = (Elf32_Ehdr *)fw->data;
1005         if (ehdr->e_ident[EI_MAG0] != ELFMAG0 ||
1006             ehdr->e_ident[EI_MAG1] != ELFMAG1 ||
1007             ehdr->e_ident[EI_MAG2] != ELFMAG2 ||
1008             ehdr->e_ident[EI_MAG3] != ELFMAG3) {
1009                 dev_err(fei->dev, "Invalid ELF magic\n");
1010                 return -EINVAL;
1011         }
1012
1013         if (ehdr->e_type != ET_EXEC) {
1014                 dev_err(fei->dev, "Unsupported ELF header type\n");
1015                 return -EINVAL;
1016         }
1017
1018         if (ehdr->e_phoff > fw->size) {
1019                 dev_err(fei->dev, "Firmware size is too small\n");
1020                 return -EINVAL;
1021         }
1022
1023         return 0;
1024 }
1025
1026
1027 static void load_imem_segment(struct c8sectpfei *fei, Elf32_Phdr *phdr,
1028                         const struct firmware *fw, u8 __iomem *dest,
1029                         int seg_num)
1030 {
1031         const u8 *imem_src = fw->data + phdr->p_offset;
1032         int i;
1033
1034         /*
1035          * For IMEM segments, the segment contains 24-bit
1036          * instructions which must be padded to 32-bit
1037          * instructions before being written. The written
1038          * segment is padded with NOP instructions.
1039          */
1040
1041         dev_dbg(fei->dev,
1042                 "Loading IMEM segment %d 0x%08x\n\t (0x%x bytes) -> 0x%p (0x%x bytes)\n",
1043 seg_num,
1044                 phdr->p_paddr, phdr->p_filesz,
1045                 dest, phdr->p_memsz + phdr->p_memsz / 3);
1046
1047         for (i = 0; i < phdr->p_filesz; i++) {
1048
1049                 writeb(readb((void __iomem *)imem_src), (void __iomem *)dest);
1050
1051                 /* Every 3 bytes, add an additional
1052                  * padding zero in destination */
1053                 if (i % 3 == 2) {
1054                         dest++;
1055                         writeb(0x00, (void __iomem *)dest);
1056                 }
1057
1058                 dest++;
1059                 imem_src++;
1060         }
1061 }
1062
1063 static void load_dmem_segment(struct c8sectpfei *fei, Elf32_Phdr *phdr,
1064                         const struct firmware *fw, u8 __iomem *dst, int seg_num)
1065 {
1066         /*
1067          * For DMEM segments copy the segment data from the ELF
1068          * file and pad segment with zeroes
1069          */
1070
1071         dev_dbg(fei->dev,
1072                 "Loading DMEM segment %d 0x%08x\n\t(0x%x bytes) -> 0x%p (0x%x bytes)\n",
1073                 seg_num, phdr->p_paddr, phdr->p_filesz,
1074                 dst, phdr->p_memsz);
1075
1076         memcpy((void __force *)dst, (void *)fw->data + phdr->p_offset,
1077                 phdr->p_filesz);
1078
1079         memset((void __force *)dst + phdr->p_filesz, 0,
1080                 phdr->p_memsz - phdr->p_filesz);
1081 }
1082
1083 static int load_slim_core_fw(const struct firmware *fw, struct c8sectpfei *fei)
1084 {
1085         Elf32_Ehdr *ehdr;
1086         Elf32_Phdr *phdr;
1087         u8 __iomem *dst;
1088         int err = 0, i;
1089
1090         if (!fw || !fei)
1091                 return -EINVAL;
1092
1093         ehdr = (Elf32_Ehdr *)fw->data;
1094         phdr = (Elf32_Phdr *)(fw->data + ehdr->e_phoff);
1095
1096         /* go through the available ELF segments */
1097         for (i = 0; i < ehdr->e_phnum; i++, phdr++) {
1098
1099                 /* Only consider LOAD segments */
1100                 if (phdr->p_type != PT_LOAD)
1101                         continue;
1102
1103                 /*
1104                  * Check segment is contained within the fw->data buffer
1105                  */
1106                 if (phdr->p_offset + phdr->p_filesz > fw->size) {
1107                         dev_err(fei->dev,
1108                                 "Segment %d is outside of firmware file\n", i);
1109                         err = -EINVAL;
1110                         break;
1111                 }
1112
1113                 /*
1114                  * MEMDMA IMEM has executable flag set, otherwise load
1115                  * this segment into DMEM.
1116                  *
1117                  */
1118
1119                 if (phdr->p_flags & PF_X) {
1120                         dst = (u8 __iomem *) fei->io + DMA_MEMDMA_IMEM;
1121                         /*
1122                          * The Slim ELF file uses 32-bit word addressing for
1123                          * load offsets.
1124                          */
1125                         dst += (phdr->p_paddr & 0xFFFFF) * sizeof(unsigned int);
1126                         load_imem_segment(fei, phdr, fw, dst, i);
1127                 } else {
1128                         dst = (u8 __iomem *) fei->io + DMA_MEMDMA_DMEM;
1129                         /*
1130                          * The Slim ELF file uses 32-bit word addressing for
1131                          * load offsets.
1132                          */
1133                         dst += (phdr->p_paddr & 0xFFFFF) * sizeof(unsigned int);
1134                         load_dmem_segment(fei, phdr, fw, dst, i);
1135                 }
1136         }
1137
1138         release_firmware(fw);
1139         return err;
1140 }
1141
1142 static int load_c8sectpfe_fw(struct c8sectpfei *fei)
1143 {
1144         const struct firmware *fw;
1145         int err;
1146
1147         dev_info(fei->dev, "Loading firmware: %s\n", FIRMWARE_MEMDMA);
1148
1149         err = request_firmware(&fw, FIRMWARE_MEMDMA, fei->dev);
1150         if (err)
1151                 return err;
1152
1153         err = c8sectpfe_elf_sanity_check(fei, fw);
1154         if (err) {
1155                 dev_err(fei->dev, "c8sectpfe_elf_sanity_check failed err=(%d)\n"
1156                         , err);
1157                 release_firmware(fw);
1158                 return err;
1159         }
1160
1161         err = load_slim_core_fw(fw, fei);
1162         if (err) {
1163                 dev_err(fei->dev, "load_slim_core_fw failed err=(%d)\n", err);
1164                 return err;
1165         }
1166
1167         /* now the firmware is loaded configure the input blocks */
1168         err = configure_channels(fei);
1169         if (err) {
1170                 dev_err(fei->dev, "configure_channels failed err=(%d)\n", err);
1171                 return err;
1172         }
1173
1174         /*
1175          * STBus target port can access IMEM and DMEM ports
1176          * without waiting for CPU
1177          */
1178         writel(0x1, fei->io + DMA_PER_STBUS_SYNC);
1179
1180         dev_info(fei->dev, "Boot the memdma SLIM core\n");
1181         writel(0x1,  fei->io + DMA_CPU_RUN);
1182
1183         atomic_set(&fei->fw_loaded, 1);
1184
1185         return 0;
1186 }
1187
1188 static const struct of_device_id c8sectpfe_match[] = {
1189         { .compatible = "st,stih407-c8sectpfe" },
1190         { /* sentinel */ },
1191 };
1192 MODULE_DEVICE_TABLE(of, c8sectpfe_match);
1193
1194 static struct platform_driver c8sectpfe_driver = {
1195         .driver = {
1196                 .name = "c8sectpfe",
1197                 .of_match_table = of_match_ptr(c8sectpfe_match),
1198         },
1199         .probe  = c8sectpfe_probe,
1200         .remove = c8sectpfe_remove,
1201 };
1202
1203 module_platform_driver(c8sectpfe_driver);
1204
1205 MODULE_AUTHOR("Peter Bennett <peter.bennett@st.com>");
1206 MODULE_AUTHOR("Peter Griffin <peter.griffin@linaro.org>");
1207 MODULE_DESCRIPTION("C8SECTPFE STi DVB Driver");
1208 MODULE_LICENSE("GPL");