drivers/media/platform/starfive/v4l2_driver/stf_csi_hw_ops.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * linux/drivers/media/platform/starfive/stf_csi.c
   4  *
   5  * Copyright (C) 2021 StarFive Technology Co., Ltd.
   6  *
   7  */
   8 #include "stfcamss.h"
   9 #include <linux/regmap.h>
  10
  11 #define CSI2RX_DEVICE_CFG_REG                   0x000
  12
  13 #define CSI2RX_SOFT_RESET_REG                   0x004
  14 #define CSI2RX_SOFT_RESET_PROTOCOL              BIT(1)
  15 #define CSI2RX_SOFT_RESET_FRONT                 BIT(0)
  16
  17 #define CSI2RX_DPHY_LANE_CONTROL                0x040
  18
  19 #define CSI2RX_STATIC_CFG_REG                   0x008
  20 #define CSI2RX_STATIC_CFG_DLANE_MAP(llane, plane)       \
  21                 ((plane) << (16 + (llane) * 4))
  22 #define CSI2RX_STATIC_CFG_LANES_MASK            GENMASK(11, 8)
  23
  24 #define CSI2RX_STREAM_BASE(n)           (((n) + 1) * 0x100)
  25
  26 #define CSI2RX_STREAM_CTRL_REG(n)               (CSI2RX_STREAM_BASE(n) + 0x000)
  27 #define CSI2RX_STREAM_CTRL_START                BIT(0)
  28
  29 #define CSI2RX_STREAM_DATA_CFG_REG(n)           (CSI2RX_STREAM_BASE(n) + 0x008)
  30 #define CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT     BIT(31)
  31 #define CSI2RX_STREAM_DATA_CFG_VC_SELECT(n)     BIT((n) + 16)
  32
  33 #define CSI2RX_STREAM_CFG_REG(n)                (CSI2RX_STREAM_BASE(n) + 0x00c)
  34 #define CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF   (1 << 8)
  35
  36 #define CSI2RX_LANES_MAX        4
  37 #define CSI2RX_STREAMS_MAX      4
  38
  39 static int stf_csi_power_on(struct stf_csi_dev *csi_dev, u8 on)
  40 {
  41         void __iomem *aon_syscon;
  42
  43         aon_syscon = ioremap(0x17010000, 0x4);
  44         reg_write(aon_syscon, 0x00, 0x80000000);
  45
  46         return 0;
  47 }
  48
  49 static int stf_csi_clk_enable(struct stf_csi_dev *csi_dev)
  50 {
  51         struct stfcamss *stfcamss = csi_dev->stfcamss;
  52
  53         clk_set_rate(stfcamss->sys_clk[STFCLK_MIPI_RX0_PXL].clk, 204800000);
  54         clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF0].clk);
  55         clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF1].clk);
  56         clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF2].clk);
  57         clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF3].clk);
  58
  59         reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF0].rstc);
  60         reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF1].rstc);
  61         reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF2].rstc);
  62         reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF3].rstc);
  63         reset_control_deassert(stfcamss->sys_rst[STFRST_AXIRD].rstc);
  64         reset_control_deassert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
  65
  66         return 0;
  67 }
  68
  69 static int stf_csi_clk_disable(struct stf_csi_dev *csi_dev)
  70 {
  71         struct stfcamss *stfcamss = csi_dev->stfcamss;
  72
  73         reset_control_assert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
  74         reset_control_assert(stfcamss->sys_rst[STFRST_AXIRD].rstc);
  75         reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF3].rstc);
  76         reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF2].rstc);
  77         reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF1].rstc);
  78         reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF0].rstc);
  79
  80         clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF0].clk);
  81         clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF1].clk);
  82         clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF2].clk);
  83         clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF3].clk);
  84
  85         return 0;
  86 }
  87
  88 static int stf_csi_config_set(struct stf_csi_dev *csi_dev)
  89 {
  90         struct stf_vin_dev *vin = csi_dev->stfcamss->vin;
  91         u32 mipi_channel_sel, mipi_vc = 0;
  92
  93         st_info(ST_CSI, "%s, csi_id = %d\n", __func__, csi_dev->id);
  94
  95         switch (csi_dev->s_type) {
  96         case SENSOR_VIN:
  97                 st_err(ST_CSI, "%s, %d: need todo\n", __func__, __LINE__);
  98                 break;
  99         case SENSOR_ISP0:
 100                 reg_set_bit(vin->clkgen_base,
 101                                 CLK_ISP0_MIPI_CTRL,
 102                                 BIT(24), csi_dev->id << 24);
 103
 104                 reg_set_bit(vin->clkgen_base,
 105                                 CLK_C_ISP0_CTRL,
 106                                 BIT(25) | BIT(24),
 107                                 csi_dev->id << 24);
 108
 109                 mipi_channel_sel = csi_dev->id * 4 + mipi_vc;
 110                 reg_set_bit(vin->sysctrl_base,
 111                                 SYSCTRL_VIN_SRC_CHAN_SEL,
 112                                 0xF, mipi_channel_sel);
 113                 break;
 114         case SENSOR_ISP1:
 115                 reg_set_bit(vin->clkgen_base,
 116                                 CLK_ISP1_MIPI_CTRL,
 117                                 BIT(24), csi_dev->id << 24);
 118
 119                 reg_set_bit(vin->clkgen_base,
 120                                 CLK_C_ISP1_CTRL,
 121                                 BIT(25) | BIT(24),
 122                                 csi_dev->id << 24);
 123
 124                 mipi_channel_sel = csi_dev->id * 4 + mipi_vc;
 125                 reg_set_bit(vin->sysctrl_base,
 126                                 SYSCTRL_VIN_SRC_CHAN_SEL,
 127                                 0xF << 4, mipi_channel_sel << 4);
 128         default:
 129                 break;
 130         }
 131
 132         return 0;
 133 }
 134
 135 static int stf_csi_set_format(struct stf_csi_dev *csi_dev,
 136                         u32 vsize, u8 bpp, int is_raw10)
 137 {
 138         struct stf_vin_dev *vin = csi_dev->stfcamss->vin;
 139         void *reg_base = NULL;
 140
 141         if (csi_dev->id == 0)
 142                 reg_base = vin->mipi0_base;
 143         else if (csi_dev->id == 1)
 144                 reg_base = vin->mipi1_base;
 145         else
 146                 return 0;
 147
 148         switch (csi_dev->s_type) {
 149         case SENSOR_VIN:
 150                 st_err(ST_CSI, "%s, %d: need todo\n", __func__, __LINE__);
 151                 break;
 152         case SENSOR_ISP0:
 153                 if (is_raw10)
 154                         reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
 155                                 BIT(12),
 156                                 1<<12);
 157                 break;
 158         case SENSOR_ISP1:
 159                 st_err(ST_CSI, "please check csi_dev s_type:%d\n", csi_dev->s_type);
 160         default:
 161                 break;
 162         }
 163
 164         return 0;
 165 }
 166
 167 static void csi2rx_reset(void *reg_base)
 168 {
 169         writel(CSI2RX_SOFT_RESET_PROTOCOL | CSI2RX_SOFT_RESET_FRONT,
 170                reg_base + CSI2RX_SOFT_RESET_REG);
 171
 172         udelay(10);
 173
 174         writel(0, reg_base + CSI2RX_SOFT_RESET_REG);
 175 }
 176
 177 static int csi2rx_start(struct stf_csi_dev *csi_dev, void *reg_base)
 178 {
 179         struct stfcamss *stfcamss = csi_dev->stfcamss;
 180         struct csi2phy_cfg *csiphy =
 181                 stfcamss->csiphy_dev[csi_dev->csiphy_id].csiphy;
 182         unsigned int i;
 183         unsigned long lanes_used = 0;
 184         u32 reg;
 185
 186         if (!csiphy) {
 187                 st_err(ST_CSI, "csiphy%d config not exist\n", csi_dev->csiphy_id);
 188                 return -EINVAL;
 189         }
 190
 191         csi2rx_reset(reg_base);
 192
 193         reg = csiphy->num_data_lanes << 8;
 194         for (i = 0; i < csiphy->num_data_lanes; i++) {
 195                 reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, csiphy->data_lanes[i]);
 196                 set_bit(csiphy->data_lanes[i] - 1, &lanes_used);
 197         }
 198
 199         /*
 200          * Even the unused lanes need to be mapped. In order to avoid
 201          * to map twice to the same physical lane, keep the lanes used
 202          * in the previous loop, and only map unused physical lanes to
 203          * the rest of our logical lanes.
 204          */
 205         for (i = csiphy->num_data_lanes; i < CSI2RX_LANES_MAX; i++) {
 206                 unsigned int idx = find_first_zero_bit(&lanes_used,
 207                                                        CSI2RX_LANES_MAX);
 208
 209                 set_bit(idx, &lanes_used);
 210                 reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, idx + 1);
 211         }
 212
 213         writel(reg, reg_base + CSI2RX_STATIC_CFG_REG);
 214
 215         // 0x40 DPHY_LANE_CONTROL
 216         reg = 0;
 217
 218         for (i = 0; i < csiphy->num_data_lanes; i++)
 219                 reg |= 1 << i | 1 << (i + 12);          //data_clane
 220
 221         reg |= 1 << 4 | 1 << 16;                //clk_lane
 222         writel(reg, reg_base + CSI2RX_DPHY_LANE_CONTROL);
 223
 224         /*
 225          * Create a static mapping between the CSI virtual channels
 226          * and the output stream.
 227          *
 228          * This should be enhanced, but v4l2 lacks the support for
 229          * changing that mapping dynamically.
 230          *
 231          * We also cannot enable and disable independent streams here,
 232          * hence the reference counting.
 233          */
 234         for (i = 0; i < CSI2RX_STREAMS_MAX; i++) {
 235                 writel(CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF,
 236                        reg_base + CSI2RX_STREAM_CFG_REG(i));
 237
 238                 writel(CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT |
 239                        CSI2RX_STREAM_DATA_CFG_VC_SELECT(i),
 240                        reg_base + CSI2RX_STREAM_DATA_CFG_REG(i));
 241
 242                 writel(CSI2RX_STREAM_CTRL_START,
 243                        reg_base + CSI2RX_STREAM_CTRL_REG(i));
 244         }
 245
 246         return 0;
 247 }
 248
 249 static void csi2rx_stop(struct stf_csi_dev *csi_dev, void *reg_base)
 250 {
 251         unsigned int i;
 252
 253         for (i = 0; i < CSI2RX_STREAMS_MAX; i++)
 254                 writel(0, reg_base + CSI2RX_STREAM_CTRL_REG(i));
 255 }
 256
 257 static int stf_csi_stream_set(struct stf_csi_dev *csi_dev, int on)
 258 {
 259         struct stfcamss *stfcamss = csi_dev->stfcamss;
 260         struct stf_vin_dev *vin = csi_dev->stfcamss->vin;
 261         void *reg_base = NULL;
 262
 263         if (csi_dev->id == 0)
 264                 reg_base = vin->mipi0_base;
 265         else if (csi_dev->id == 1)
 266                 reg_base = vin->mipi1_base;
 267         else
 268                 return 0;
 269
 270         switch (csi_dev->s_type) {
 271         case SENSOR_VIN:
 272                 clk_set_parent(stfcamss->sys_clk[STFCLK_AXIWR].clk,
 273                         stfcamss->sys_clk[STFCLK_MIPI_RX0_PXL].clk);
 274
 275                 reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_20,
 276                         BIT(3)|BIT(2)|BIT(1)|BIT(0),
 277                         0<<0);          //u0_vin_cnfg_axiwr0_channel_sel
 278                 reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28,
 279                         BIT(14)|BIT(13),
 280                         1<<13);         //u0_vin_cnfg_axiwr0_pix_ct
 281                 reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28,
 282                         BIT(16)|BIT(15),
 283                         0<<15);         //u0_vin_cnfg_axiwr0_pixel_high_bit_sel
 284                 reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28,
 285                         BIT(12)|BIT(11)|BIT(10)|BIT(9)|BIT(8)|BIT(7)|BIT(6)|BIT(5)|BIT(4)|BIT(3)|BIT(2),
 286                         (1920 / 4 - 1)<<2);     //u0_vin_cnfg_axiwr0_pix_cnt_end
 287                 break;
 288         case SENSOR_ISP0:
 289                 clk_set_parent(stfcamss->sys_clk[STFCLK_WRAPPER_CLK_C].clk,
 290                         stfcamss->sys_clk[STFCLK_MIPI_RX0_PXL].clk);
 291
 292                 reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
 293                         BIT(7)|BIT(6),
 294                         0<<6);          //u0_vin_cnfg_mipi_byte_en_isp0
 295                 reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
 296                         BIT(11)|BIT(10)|BIT(9)|BIT(8),
 297                         0<<8);          //u0_vin_cnfg_mipi_channel_sel0
 298                 reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
 299                         BIT(12),
 300                         1<<12);         //u0_vin_cnfg_p_i_mipi_header_en0
 301                 reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
 302                         BIT(16)|BIT(15)|BIT(14)|BIT(13),
 303                         0<<13);         //u0_vin_cnfg_pix_num
 304                 break;
 305         case SENSOR_ISP1:
 306                 st_err(ST_CSI, "please check csi_dev s_type:%d\n", csi_dev->s_type);
 307                 break;
 308         default:
 309                 break;
 310         }
 311
 312         if (on)
 313                 csi2rx_start(csi_dev, reg_base);
 314         else
 315                 csi2rx_stop(csi_dev, reg_base);
 316
 317         return 0;
 318 }
 319
 320 void dump_csi_reg(void *__iomem csibase, int id)
 321 {
 322         st_info(ST_CSI, "DUMP CSI%d register:\n", id);
 323         print_reg(ST_CSI, csibase, 0x00);
 324         print_reg(ST_CSI, csibase, 0x04);
 325         print_reg(ST_CSI, csibase, 0x08);
 326         print_reg(ST_CSI, csibase, 0x10);
 327
 328         print_reg(ST_CSI, csibase, 0x40);
 329         print_reg(ST_CSI, csibase, 0x48);
 330         print_reg(ST_CSI, csibase, 0x4c);
 331         print_reg(ST_CSI, csibase, 0x50);
 332 }
 333
 334 struct csi_hw_ops csi_ops = {
 335         .csi_power_on          = stf_csi_power_on,
 336         .csi_clk_enable        = stf_csi_clk_enable,
 337         .csi_clk_disable       = stf_csi_clk_disable,
 338         .csi_config_set        = stf_csi_config_set,
 339         .csi_set_format        = stf_csi_set_format,
 340         .csi_stream_set        = stf_csi_stream_set,
 341 };