drivers/media/platform/starfive/v4l2_driver/stf_csi_hw_ops.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * linux/drivers/media/platform/starfive/stf_csi.c
   4  *
   5  * Copyright (C) 2021 StarFive Technology Co., Ltd.
   6  *
   7  */
   8 #include "stfcamss.h"
   9 #include <linux/regmap.h>
  10
  11 #define CSI2RX_DEVICE_CFG_REG                   0x000
  12
  13 #define CSI2RX_SOFT_RESET_REG                   0x004
  14 #define CSI2RX_SOFT_RESET_PROTOCOL              BIT(1)
  15 #define CSI2RX_SOFT_RESET_FRONT                 BIT(0)
  16
  17 #define CSI2RX_DPHY_LANE_CONTROL                0x040
  18
  19 #define CSI2RX_STATIC_CFG_REG                   0x008
  20 #define CSI2RX_STATIC_CFG_DLANE_MAP(llane, plane)       \
  21                 ((plane) << (16 + (llane) * 4))
  22 #define CSI2RX_STATIC_CFG_LANES_MASK            GENMASK(11, 8)
  23
  24 #define CSI2RX_STREAM_BASE(n)           (((n) + 1) * 0x100)
  25
  26 #define CSI2RX_STREAM_CTRL_REG(n)               (CSI2RX_STREAM_BASE(n) + 0x000)
  27 #define CSI2RX_STREAM_CTRL_START                BIT(0)
  28
  29 #define CSI2RX_STREAM_DATA_CFG_REG(n)           (CSI2RX_STREAM_BASE(n) + 0x008)
  30 #define CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT     BIT(31)
  31 #define CSI2RX_STREAM_DATA_CFG_EN_DATA_TYPE_0 BIT(7)
  32 #define CSI2RX_STREAM_DATA_CFG_VC_SELECT(n)     BIT((n) + 16)
  33
  34 #define CSI2RX_STREAM_CFG_REG(n)                (CSI2RX_STREAM_BASE(n) + 0x00c)
  35 #define CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF   (1 << 8)
  36
  37 #define CSI2RX_LANES_MAX        4
  38 #define CSI2RX_STREAMS_MAX      4
  39
  40 static int stf_csi_power_on(struct stf_csi_dev *csi_dev, u8 on)
  41 {
  42         struct stfcamss *stfcamss = csi_dev->stfcamss;
  43         int ret;
  44
  45         if (on) {
  46                 ret = regulator_enable(csi_dev->mipirx_1p8);
  47                 if (ret) {
  48                         st_err(ST_CSI, "Cannot enable mipirx_1p8 regulator\n");
  49                         goto err_1p8;
  50                 }
  51
  52                 ret = regulator_enable(csi_dev->mipirx_0p9);
  53                 if (ret) {
  54                         st_err(ST_CSI, "Cannot enable mipirx_0p9 regulator\n");
  55                         goto err_0p9;
  56                 }
  57         } else {
  58                 regulator_disable(csi_dev->mipirx_1p8);
  59                 regulator_disable(csi_dev->mipirx_0p9);
  60         }
  61
  62         regmap_update_bits(stfcamss->stf_aon_syscon, stfcamss->aon_gp_reg,
  63                                 BIT(31), BIT(31));
  64
  65         return 0;
  66
  67 err_0p9:
  68         regulator_disable(csi_dev->mipirx_1p8);
  69 err_1p8:
  70         return ret;
  71
  72 }
  73
  74 static int stf_csi_clk_enable(struct stf_csi_dev *csi_dev)
  75 {
  76         struct stfcamss *stfcamss = csi_dev->stfcamss;
  77
  78         clk_set_rate(stfcamss->sys_clk[STFCLK_MIPI_RX0_PXL].clk, 204800000);
  79         clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF0].clk);
  80         clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF1].clk);
  81         clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF2].clk);
  82         clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF3].clk);
  83
  84         reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF0].rstc);
  85         reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF1].rstc);
  86         reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF2].rstc);
  87         reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF3].rstc);
  88         reset_control_deassert(stfcamss->sys_rst[STFRST_AXIRD].rstc);
  89         reset_control_deassert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
  90
  91         return 0;
  92 }
  93
  94 static int stf_csi_clk_disable(struct stf_csi_dev *csi_dev)
  95 {
  96         struct stfcamss *stfcamss = csi_dev->stfcamss;
  97
  98         reset_control_assert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
  99         reset_control_assert(stfcamss->sys_rst[STFRST_AXIRD].rstc);
 100         reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF3].rstc);
 101         reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF2].rstc);
 102         reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF1].rstc);
 103         reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF0].rstc);
 104
 105         clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF0].clk);
 106         clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF1].clk);
 107         clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF2].clk);
 108         clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF3].clk);
 109
 110         return 0;
 111 }
 112
 113 static void csi2rx_reset(void *reg_base)
 114 {
 115         writel(CSI2RX_SOFT_RESET_PROTOCOL | CSI2RX_SOFT_RESET_FRONT,
 116                reg_base + CSI2RX_SOFT_RESET_REG);
 117
 118         udelay(10);
 119
 120         writel(0, reg_base + CSI2RX_SOFT_RESET_REG);
 121 }
 122
 123 static int csi2rx_start(struct stf_csi_dev *csi_dev, void *reg_base, u32 dt)
 124 {
 125         struct stfcamss *stfcamss = csi_dev->stfcamss;
 126         struct csi2phy_cfg *csiphy =
 127                 stfcamss->csiphy_dev->csiphy;
 128         unsigned int i;
 129         unsigned long lanes_used = 0;
 130         u32 reg;
 131
 132         if (!csiphy) {
 133                 st_err(ST_CSI, "csiphy0 config not exist\n");
 134                 return -EINVAL;
 135         }
 136
 137         csi2rx_reset(reg_base);
 138
 139         reg = csiphy->num_data_lanes << 8;
 140         for (i = 0; i < csiphy->num_data_lanes; i++) {
 141 #ifndef USE_CSIDPHY_ONE_CLK_MODE
 142                 reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, csiphy->data_lanes[i]);
 143                 set_bit(csiphy->data_lanes[i] - 1, &lanes_used);
 144 #else
 145                 reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, i + 1);
 146                 set_bit(i, &lanes_used);
 147 #endif
 148         }
 149
 150         /*
 151          * Even the unused lanes need to be mapped. In order to avoid
 152          * to map twice to the same physical lane, keep the lanes used
 153          * in the previous loop, and only map unused physical lanes to
 154          * the rest of our logical lanes.
 155          */
 156         for (i = csiphy->num_data_lanes; i < CSI2RX_LANES_MAX; i++) {
 157                 unsigned int idx = find_first_zero_bit(&lanes_used,
 158                                                        CSI2RX_LANES_MAX);
 159
 160                 set_bit(idx, &lanes_used);
 161                 reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, idx + 1);
 162         }
 163
 164         writel(reg, reg_base + CSI2RX_STATIC_CFG_REG);
 165
 166         // 0x40 DPHY_LANE_CONTROL
 167         reg = 0;
 168 #ifndef USE_CSIDPHY_ONE_CLK_MODE
 169         for (i = 0; i < csiphy->num_data_lanes; i++)
 170                 reg |= 1 << (csiphy->data_lanes[i] - 1)
 171                         | 1 << (csiphy->data_lanes[i] + 11);
 172 #else
 173         for (i = 0; i < csiphy->num_data_lanes; i++)
 174                 reg |= 1 << i | 1 << (i + 12);          //data_clane
 175 #endif
 176
 177         reg |= 1 << 4 | 1 << 16;                //clk_lane
 178         writel(reg, reg_base + CSI2RX_DPHY_LANE_CONTROL);
 179
 180         /*
 181          * Create a static mapping between the CSI virtual channels
 182          * and the output stream.
 183          *
 184          * This should be enhanced, but v4l2 lacks the support for
 185          * changing that mapping dynamically.
 186          *
 187          * We also cannot enable and disable independent streams here,
 188          * hence the reference counting.
 189          */
 190         for (i = 0; i < CSI2RX_STREAMS_MAX; i++) {
 191                 writel(CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF,
 192                        reg_base + CSI2RX_STREAM_CFG_REG(i));
 193
 194                 writel(CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT |
 195                        CSI2RX_STREAM_DATA_CFG_VC_SELECT(i) |
 196                        CSI2RX_STREAM_DATA_CFG_EN_DATA_TYPE_0 | dt,
 197                        reg_base + CSI2RX_STREAM_DATA_CFG_REG(i));
 198
 199                 writel(CSI2RX_STREAM_CTRL_START,
 200                        reg_base + CSI2RX_STREAM_CTRL_REG(i));
 201         }
 202
 203         return 0;
 204 }
 205
 206 static void csi2rx_stop(struct stf_csi_dev *csi_dev, void *reg_base)
 207 {
 208         unsigned int i;
 209
 210         for (i = 0; i < CSI2RX_STREAMS_MAX; i++)
 211                 writel(0, reg_base + CSI2RX_STREAM_CTRL_REG(i));
 212 }
 213
 214 static int stf_csi_stream_set(struct stf_csi_dev *csi_dev,
 215                                         int on, u32 dt, u32 width)
 216 {
 217         struct stfcamss *stfcamss = csi_dev->stfcamss;
 218         struct stf_vin_dev *vin = csi_dev->stfcamss->vin;
 219         void __iomem *reg_base = vin->csi2rx_base;
 220
 221         switch (csi_dev->s_type) {
 222         case SENSOR_VIN:
 223                 clk_set_parent(stfcamss->sys_clk[STFCLK_AXIWR].clk,
 224                         stfcamss->sys_clk[STFCLK_MIPI_RX0_PXL].clk);
 225
 226                 reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_20,
 227                         BIT(3)|BIT(2)|BIT(1)|BIT(0),
 228                         0<<0);          //u0_vin_cnfg_axiwr0_channel_sel
 229                 reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28,
 230                         BIT(14)|BIT(13),
 231                         1<<13);         //u0_vin_cnfg_axiwr0_pix_ct
 232                 reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28,
 233                         BIT(16)|BIT(15),
 234                         0<<15);         //u0_vin_cnfg_axiwr0_pixel_high_bit_sel
 235                 reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28,
 236                         BIT(12)|BIT(11)|BIT(10)|BIT(9)|BIT(8)|BIT(7)|BIT(6)|BIT(5)|BIT(4)|BIT(3)|BIT(2),
 237                         (width / 4 - 1)<<2);    //u0_vin_cnfg_axiwr0_pix_cnt_end
 238                 break;
 239         case SENSOR_ISP:
 240                 clk_set_parent(stfcamss->sys_clk[STFCLK_WRAPPER_CLK_C].clk,
 241                         stfcamss->sys_clk[STFCLK_MIPI_RX0_PXL].clk);
 242
 243                 reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
 244                         BIT(7)|BIT(6),
 245                         0<<6);          //u0_vin_cnfg_mipi_byte_en_isp
 246                 reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
 247                         BIT(11)|BIT(10)|BIT(9)|BIT(8),
 248                         0<<8);          //u0_vin_cnfg_mipi_channel_sel0
 249                 reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
 250                         BIT(16)|BIT(15)|BIT(14)|BIT(13),
 251                         0<<13);         //u0_vin_cnfg_pix_num
 252
 253                 if (dt == 0x2b)
 254                         reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
 255                                 BIT(12),
 256                                 1<<12);         //u0_vin_cnfg_p_i_mipi_header_en0
 257                 break;
 258         default:
 259                 break;
 260         }
 261
 262         if (on)
 263                 csi2rx_start(csi_dev, reg_base, dt);
 264         else
 265                 csi2rx_stop(csi_dev, reg_base);
 266
 267         return 0;
 268 }
 269
 270 void dump_csi_reg(void *__iomem csibase)
 271 {
 272         st_info(ST_CSI, "DUMP CSI register:\n");
 273         print_reg(ST_CSI, csibase, 0x00);
 274         print_reg(ST_CSI, csibase, 0x04);
 275         print_reg(ST_CSI, csibase, 0x08);
 276         print_reg(ST_CSI, csibase, 0x10);
 277
 278         print_reg(ST_CSI, csibase, 0x40);
 279         print_reg(ST_CSI, csibase, 0x48);
 280         print_reg(ST_CSI, csibase, 0x4c);
 281         print_reg(ST_CSI, csibase, 0x50);
 282 }
 283
 284 struct csi_hw_ops csi_ops = {
 285         .csi_power_on          = stf_csi_power_on,
 286         .csi_clk_enable        = stf_csi_clk_enable,
 287         .csi_clk_disable       = stf_csi_clk_disable,
 288         .csi_stream_set        = stf_csi_stream_set,
 289 };