drivers/media/platform/starfive/v4l2_driver/stf_csi_hw_ops.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * linux/drivers/media/platform/starfive/stf_csi.c
   4  *
   5  * Copyright (C) 2021 StarFive Technology Co., Ltd.
   6  *
   7  */
   8 #include "stfcamss.h"
   9 #include <linux/regmap.h>
  10
  11 #define CSI2RX_DEVICE_CFG_REG                   0x000
  12
  13 #define CSI2RX_SOFT_RESET_REG                   0x004
  14 #define CSI2RX_SOFT_RESET_PROTOCOL              BIT(1)
  15 #define CSI2RX_SOFT_RESET_FRONT                 BIT(0)
  16
  17 #define CSI2RX_DPHY_LANE_CONTROL                0x040
  18
  19 #define CSI2RX_STATIC_CFG_REG                   0x008
  20 #define CSI2RX_STATIC_CFG_DLANE_MAP(llane, plane)       \
  21                 ((plane) << (16 + (llane) * 4))
  22 #define CSI2RX_STATIC_CFG_LANES_MASK            GENMASK(11, 8)
  23
  24 #define CSI2RX_STREAM_BASE(n)           (((n) + 1) * 0x100)
  25
  26 #define CSI2RX_STREAM_CTRL_REG(n)               (CSI2RX_STREAM_BASE(n) + 0x000)
  27 #define CSI2RX_STREAM_CTRL_START                BIT(0)
  28
  29 #define CSI2RX_STREAM_DATA_CFG_REG(n)           (CSI2RX_STREAM_BASE(n) + 0x008)
  30 #define CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT     BIT(31)
  31 #define CSI2RX_STREAM_DATA_CFG_EN_DATA_TYPE_0 BIT(7)
  32 #define CSI2RX_STREAM_DATA_CFG_VC_SELECT(n)     BIT((n) + 16)
  33
  34 #define CSI2RX_STREAM_CFG_REG(n)                (CSI2RX_STREAM_BASE(n) + 0x00c)
  35 #define CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF   (1 << 8)
  36
  37 #define CSI2RX_LANES_MAX        4
  38 #define CSI2RX_STREAMS_MAX      4
  39
  40 static int stf_csi_power_on(struct stf_csi_dev *csi_dev, u8 on)
  41 {
  42         struct stfcamss *stfcamss = csi_dev->stfcamss;
  43         int ret;
  44
  45         if (on) {
  46                 ret = regulator_enable(csi_dev->mipirx_0p9);
  47                 if (ret) {
  48                         st_err(ST_CSI, "Cannot enable mipirx_0p9 regulator\n");
  49                         return ret;
  50                 }
  51         } else
  52                 regulator_disable(csi_dev->mipirx_0p9);
  53
  54         regmap_update_bits(stfcamss->stf_aon_syscon, stfcamss->aon_gp_reg,
  55                                 BIT(31), BIT(31));
  56
  57         return 0;
  58 }
  59
  60 static int stf_csi_clk_enable(struct stf_csi_dev *csi_dev)
  61 {
  62         struct stfcamss *stfcamss = csi_dev->stfcamss;
  63
  64         clk_set_rate(stfcamss->sys_clk[STFCLK_MIPI_RX0_PXL].clk, 198000000);
  65         clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF0].clk);
  66         clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF1].clk);
  67         clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF2].clk);
  68         clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF3].clk);
  69
  70         reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF0].rstc);
  71         reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF1].rstc);
  72         reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF2].rstc);
  73         reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF3].rstc);
  74
  75         switch (csi_dev->s_type) {
  76         case SENSOR_VIN:
  77                 reset_control_deassert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
  78                 clk_set_parent(stfcamss->sys_clk[STFCLK_AXIWR].clk,
  79                         stfcamss->sys_clk[STFCLK_MIPI_RX0_PXL].clk);
  80                 break;
  81         case SENSOR_ISP:
  82                 clk_set_parent(stfcamss->sys_clk[STFCLK_WRAPPER_CLK_C].clk,
  83                         stfcamss->sys_clk[STFCLK_MIPI_RX0_PXL].clk);
  84                 break;
  85         }
  86
  87         return 0;
  88 }
  89
  90 static int stf_csi_clk_disable(struct stf_csi_dev *csi_dev)
  91 {
  92         struct stfcamss *stfcamss = csi_dev->stfcamss;
  93
  94         switch (csi_dev->s_type) {
  95         case SENSOR_VIN:
  96                 reset_control_assert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
  97                 break;
  98         case SENSOR_ISP:
  99                 break;
 100         }
 101
 102         reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF3].rstc);
 103         reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF2].rstc);
 104         reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF1].rstc);
 105         reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF0].rstc);
 106
 107         clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF3].clk);
 108         clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF2].clk);
 109         clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF1].clk);
 110         clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF0].clk);
 111
 112         return 0;
 113 }
 114
 115 static void csi2rx_reset(void *reg_base)
 116 {
 117         writel(CSI2RX_SOFT_RESET_PROTOCOL | CSI2RX_SOFT_RESET_FRONT,
 118                reg_base + CSI2RX_SOFT_RESET_REG);
 119
 120         udelay(10);
 121
 122         writel(0, reg_base + CSI2RX_SOFT_RESET_REG);
 123 }
 124
 125 static int csi2rx_start(struct stf_csi_dev *csi_dev, void *reg_base, u32 dt)
 126 {
 127         struct stfcamss *stfcamss = csi_dev->stfcamss;
 128         struct csi2phy_cfg *csiphy =
 129                 stfcamss->csiphy_dev->csiphy;
 130         unsigned int i;
 131         unsigned long lanes_used = 0;
 132         u32 reg;
 133
 134         if (!csiphy) {
 135                 st_err(ST_CSI, "csiphy0 config not exist\n");
 136                 return -EINVAL;
 137         }
 138
 139         csi2rx_reset(reg_base);
 140
 141         reg = csiphy->num_data_lanes << 8;
 142         for (i = 0; i < csiphy->num_data_lanes; i++) {
 143 #ifndef USE_CSIDPHY_ONE_CLK_MODE
 144                 reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, csiphy->data_lanes[i]);
 145                 set_bit(csiphy->data_lanes[i] - 1, &lanes_used);
 146 #else
 147                 reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, i + 1);
 148                 set_bit(i, &lanes_used);
 149 #endif
 150         }
 151
 152         /*
 153          * Even the unused lanes need to be mapped. In order to avoid
 154          * to map twice to the same physical lane, keep the lanes used
 155          * in the previous loop, and only map unused physical lanes to
 156          * the rest of our logical lanes.
 157          */
 158         for (i = csiphy->num_data_lanes; i < CSI2RX_LANES_MAX; i++) {
 159                 unsigned int idx = find_first_zero_bit(&lanes_used,
 160                                                        CSI2RX_LANES_MAX);
 161
 162                 set_bit(idx, &lanes_used);
 163                 reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, idx + 1);
 164         }
 165
 166         writel(reg, reg_base + CSI2RX_STATIC_CFG_REG);
 167
 168         // 0x40 DPHY_LANE_CONTROL
 169         reg = 0;
 170 #ifndef USE_CSIDPHY_ONE_CLK_MODE
 171         for (i = 0; i < csiphy->num_data_lanes; i++)
 172                 reg |= 1 << (csiphy->data_lanes[i] - 1)
 173                         | 1 << (csiphy->data_lanes[i] + 11);
 174 #else
 175         for (i = 0; i < csiphy->num_data_lanes; i++)
 176                 reg |= 1 << i | 1 << (i + 12);          //data_clane
 177 #endif
 178
 179         reg |= 1 << 4 | 1 << 16;                //clk_lane
 180         writel(reg, reg_base + CSI2RX_DPHY_LANE_CONTROL);
 181
 182         /*
 183          * Create a static mapping between the CSI virtual channels
 184          * and the output stream.
 185          *
 186          * This should be enhanced, but v4l2 lacks the support for
 187          * changing that mapping dynamically.
 188          *
 189          * We also cannot enable and disable independent streams here,
 190          * hence the reference counting.
 191          */
 192         for (i = 0; i < CSI2RX_STREAMS_MAX; i++) {
 193                 writel(CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF,
 194                        reg_base + CSI2RX_STREAM_CFG_REG(i));
 195
 196                 writel(CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT |
 197                        CSI2RX_STREAM_DATA_CFG_VC_SELECT(i) |
 198                        CSI2RX_STREAM_DATA_CFG_EN_DATA_TYPE_0 | dt,
 199                        reg_base + CSI2RX_STREAM_DATA_CFG_REG(i));
 200
 201                 writel(CSI2RX_STREAM_CTRL_START,
 202                        reg_base + CSI2RX_STREAM_CTRL_REG(i));
 203         }
 204
 205         return 0;
 206 }
 207
 208 static void csi2rx_stop(struct stf_csi_dev *csi_dev, void *reg_base)
 209 {
 210         unsigned int i;
 211
 212         for (i = 0; i < CSI2RX_STREAMS_MAX; i++)
 213                 writel(0, reg_base + CSI2RX_STREAM_CTRL_REG(i));
 214 }
 215
 216 static int stf_csi_stream_set(struct stf_csi_dev *csi_dev,
 217                                         int on, u32 dt, u32 width)
 218 {
 219         struct stf_vin_dev *vin = csi_dev->stfcamss->vin;
 220         void __iomem *reg_base = vin->csi2rx_base;
 221
 222         switch (csi_dev->s_type) {
 223         case SENSOR_VIN:
 224                 reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_20,
 225                         BIT(3)|BIT(2)|BIT(1)|BIT(0),
 226                         0<<0);          //u0_vin_cnfg_axiwr0_channel_sel
 227                 reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28,
 228                         BIT(14)|BIT(13),
 229                         1<<13);         //u0_vin_cnfg_axiwr0_pix_ct
 230                 reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28,
 231                         BIT(16)|BIT(15),
 232                         0<<15);         //u0_vin_cnfg_axiwr0_pixel_high_bit_sel
 233                 reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28,
 234                         BIT(12)|BIT(11)|BIT(10)|BIT(9)|BIT(8)|BIT(7)|BIT(6)|BIT(5)|BIT(4)|BIT(3)|BIT(2),
 235                         (width / 4 - 1)<<2);    //u0_vin_cnfg_axiwr0_pix_cnt_end
 236                 break;
 237         case SENSOR_ISP:
 238                 reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
 239                         BIT(7)|BIT(6),
 240                         0<<6);          //u0_vin_cnfg_mipi_byte_en_isp
 241                 reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
 242                         BIT(11)|BIT(10)|BIT(9)|BIT(8),
 243                         0<<8);          //u0_vin_cnfg_mipi_channel_sel0
 244                 reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
 245                         BIT(16)|BIT(15)|BIT(14)|BIT(13),
 246                         0<<13);         //u0_vin_cnfg_pix_num
 247
 248                 if (dt == 0x2b)
 249                         reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
 250                                 BIT(12),
 251                                 1<<12);         //u0_vin_cnfg_p_i_mipi_header_en0
 252                 break;
 253         }
 254
 255         if (on)
 256                 csi2rx_start(csi_dev, reg_base, dt);
 257         else
 258                 csi2rx_stop(csi_dev, reg_base);
 259
 260         return 0;
 261 }
 262
 263 void dump_csi_reg(void *__iomem csibase)
 264 {
 265         st_info(ST_CSI, "DUMP CSI register:\n");
 266         print_reg(ST_CSI, csibase, 0x00);
 267         print_reg(ST_CSI, csibase, 0x04);
 268         print_reg(ST_CSI, csibase, 0x08);
 269         print_reg(ST_CSI, csibase, 0x10);
 270
 271         print_reg(ST_CSI, csibase, 0x40);
 272         print_reg(ST_CSI, csibase, 0x48);
 273         print_reg(ST_CSI, csibase, 0x4c);
 274         print_reg(ST_CSI, csibase, 0x50);
 275 }
 276
 277 struct csi_hw_ops csi_ops = {
 278         .csi_power_on          = stf_csi_power_on,
 279         .csi_clk_enable        = stf_csi_clk_enable,
 280         .csi_clk_disable       = stf_csi_clk_disable,
 281         .csi_stream_set        = stf_csi_stream_set,
 282 };