drivers/media/platform/starfive/v4l2_driver/stf_csi_hw_ops.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * linux/drivers/media/platform/starfive/stf_csi.c
   4  *
   5  * Copyright (C) 2021 StarFive Technology Co., Ltd.
   6  *
   7  */
   8 #include "stfcamss.h"
   9 #include <linux/regmap.h>
  10 #include <soc/starfive/jh7110_pmic.h>
  11
  12 #define CSI2RX_DEVICE_CFG_REG                   0x000
  13
  14 #define CSI2RX_SOFT_RESET_REG                   0x004
  15 #define CSI2RX_SOFT_RESET_PROTOCOL              BIT(1)
  16 #define CSI2RX_SOFT_RESET_FRONT                 BIT(0)
  17
  18 #define CSI2RX_DPHY_LANE_CONTROL                0x040
  19
  20 #define CSI2RX_STATIC_CFG_REG                   0x008
  21 #define CSI2RX_STATIC_CFG_DLANE_MAP(llane, plane)       \
  22                 ((plane) << (16 + (llane) * 4))
  23 #define CSI2RX_STATIC_CFG_LANES_MASK            GENMASK(11, 8)
  24
  25 #define CSI2RX_STREAM_BASE(n)           (((n) + 1) * 0x100)
  26
  27 #define CSI2RX_STREAM_CTRL_REG(n)               (CSI2RX_STREAM_BASE(n) + 0x000)
  28 #define CSI2RX_STREAM_CTRL_START                BIT(0)
  29
  30 #define CSI2RX_STREAM_DATA_CFG_REG(n)           (CSI2RX_STREAM_BASE(n) + 0x008)
  31 #define CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT     BIT(31)
  32 #define CSI2RX_STREAM_DATA_CFG_VC_SELECT(n)     BIT((n) + 16)
  33
  34 #define CSI2RX_STREAM_CFG_REG(n)                (CSI2RX_STREAM_BASE(n) + 0x00c)
  35 #define CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF   (1 << 8)
  36
  37 #define CSI2RX_LANES_MAX        4
  38 #define CSI2RX_STREAMS_MAX      4
  39
  40 static int stf_csi_power_on(struct stf_csi_dev *csi_dev, u8 on)
  41 {
  42         void __iomem *aon_syscon;
  43
  44         pmic_set_domain(POWER_SW_0_REG, POWER_SW_0_VDD18_MIPIRX, on);
  45         pmic_set_domain(POWER_SW_0_REG, POWER_SW_0_VDD09_MIPIRX, on);
  46
  47         aon_syscon = ioremap(0x17010000, 0x4);
  48         reg_write(aon_syscon, 0x00, 0x80000000);
  49
  50         return 0;
  51 }
  52
  53 static int stf_csi_clk_enable(struct stf_csi_dev *csi_dev)
  54 {
  55         struct stfcamss *stfcamss = csi_dev->stfcamss;
  56
  57         clk_set_rate(stfcamss->sys_clk[STFCLK_MIPI_RX0_PXL].clk, 204800000);
  58         clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF0].clk);
  59         clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF1].clk);
  60         clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF2].clk);
  61         clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF3].clk);
  62
  63         reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF0].rstc);
  64         reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF1].rstc);
  65         reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF2].rstc);
  66         reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF3].rstc);
  67         reset_control_deassert(stfcamss->sys_rst[STFRST_AXIRD].rstc);
  68         reset_control_deassert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
  69
  70         return 0;
  71 }
  72
  73 static int stf_csi_clk_disable(struct stf_csi_dev *csi_dev)
  74 {
  75         struct stfcamss *stfcamss = csi_dev->stfcamss;
  76
  77         reset_control_assert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
  78         reset_control_assert(stfcamss->sys_rst[STFRST_AXIRD].rstc);
  79         reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF3].rstc);
  80         reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF2].rstc);
  81         reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF1].rstc);
  82         reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF0].rstc);
  83
  84         clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF0].clk);
  85         clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF1].clk);
  86         clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF2].clk);
  87         clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF3].clk);
  88
  89         return 0;
  90 }
  91
  92 static int stf_csi_config_set(struct stf_csi_dev *csi_dev)
  93 {
  94         struct stf_vin_dev *vin = csi_dev->stfcamss->vin;
  95         u32 mipi_channel_sel, mipi_vc = 0;
  96
  97         st_info(ST_CSI, "%s, csi_id = %d\n", __func__, csi_dev->id);
  98
  99         switch (csi_dev->s_type) {
 100         case SENSOR_VIN:
 101                 st_err(ST_CSI, "%s, %d: need todo\n", __func__, __LINE__);
 102                 break;
 103         case SENSOR_ISP0:
 104                 reg_set_bit(vin->clkgen_base,
 105                                 CLK_ISP0_MIPI_CTRL,
 106                                 BIT(24), csi_dev->id << 24);
 107
 108                 reg_set_bit(vin->clkgen_base,
 109                                 CLK_C_ISP0_CTRL,
 110                                 BIT(25) | BIT(24),
 111                                 csi_dev->id << 24);
 112
 113                 mipi_channel_sel = csi_dev->id * 4 + mipi_vc;
 114                 reg_set_bit(vin->sysctrl_base,
 115                                 SYSCTRL_VIN_SRC_CHAN_SEL,
 116                                 0xF, mipi_channel_sel);
 117                 break;
 118         case SENSOR_ISP1:
 119                 reg_set_bit(vin->clkgen_base,
 120                                 CLK_ISP1_MIPI_CTRL,
 121                                 BIT(24), csi_dev->id << 24);
 122
 123                 reg_set_bit(vin->clkgen_base,
 124                                 CLK_C_ISP1_CTRL,
 125                                 BIT(25) | BIT(24),
 126                                 csi_dev->id << 24);
 127
 128                 mipi_channel_sel = csi_dev->id * 4 + mipi_vc;
 129                 reg_set_bit(vin->sysctrl_base,
 130                                 SYSCTRL_VIN_SRC_CHAN_SEL,
 131                                 0xF << 4, mipi_channel_sel << 4);
 132         default:
 133                 break;
 134         }
 135
 136         return 0;
 137 }
 138
 139 static int stf_csi_set_format(struct stf_csi_dev *csi_dev,
 140                         u32 vsize, u8 bpp, int is_raw10)
 141 {
 142         struct stf_vin_dev *vin = csi_dev->stfcamss->vin;
 143         void *reg_base = NULL;
 144
 145         if (csi_dev->id == 0)
 146                 reg_base = vin->mipi0_base;
 147         else if (csi_dev->id == 1)
 148                 reg_base = vin->mipi1_base;
 149         else
 150                 return 0;
 151
 152         switch (csi_dev->s_type) {
 153         case SENSOR_VIN:
 154                 st_err(ST_CSI, "%s, %d: need todo\n", __func__, __LINE__);
 155                 break;
 156         case SENSOR_ISP0:
 157                 if (is_raw10)
 158                         reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
 159                                 BIT(12),
 160                                 1<<12);
 161                 break;
 162         case SENSOR_ISP1:
 163                 st_err(ST_CSI, "please check csi_dev s_type:%d\n", csi_dev->s_type);
 164         default:
 165                 break;
 166         }
 167
 168         return 0;
 169 }
 170
 171 static void csi2rx_reset(void *reg_base)
 172 {
 173         writel(CSI2RX_SOFT_RESET_PROTOCOL | CSI2RX_SOFT_RESET_FRONT,
 174                reg_base + CSI2RX_SOFT_RESET_REG);
 175
 176         udelay(10);
 177
 178         writel(0, reg_base + CSI2RX_SOFT_RESET_REG);
 179 }
 180
 181 static int csi2rx_start(struct stf_csi_dev *csi_dev, void *reg_base)
 182 {
 183         struct stfcamss *stfcamss = csi_dev->stfcamss;
 184         struct csi2phy_cfg *csiphy =
 185                 stfcamss->csiphy_dev[csi_dev->csiphy_id].csiphy;
 186         unsigned int i;
 187         unsigned long lanes_used = 0;
 188         u32 reg;
 189
 190         if (!csiphy) {
 191                 st_err(ST_CSI, "csiphy%d config not exist\n", csi_dev->csiphy_id);
 192                 return -EINVAL;
 193         }
 194
 195         csi2rx_reset(reg_base);
 196
 197         reg = csiphy->num_data_lanes << 8;
 198         for (i = 0; i < csiphy->num_data_lanes; i++) {
 199                 reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, csiphy->data_lanes[i]);
 200                 set_bit(csiphy->data_lanes[i] - 1, &lanes_used);
 201         }
 202
 203         /*
 204          * Even the unused lanes need to be mapped. In order to avoid
 205          * to map twice to the same physical lane, keep the lanes used
 206          * in the previous loop, and only map unused physical lanes to
 207          * the rest of our logical lanes.
 208          */
 209         for (i = csiphy->num_data_lanes; i < CSI2RX_LANES_MAX; i++) {
 210                 unsigned int idx = find_first_zero_bit(&lanes_used,
 211                                                        CSI2RX_LANES_MAX);
 212
 213                 set_bit(idx, &lanes_used);
 214                 reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, idx + 1);
 215         }
 216
 217         writel(reg, reg_base + CSI2RX_STATIC_CFG_REG);
 218
 219         // 0x40 DPHY_LANE_CONTROL
 220         reg = 0;
 221
 222         for (i = 0; i < csiphy->num_data_lanes; i++)
 223                 reg |= 1 << i | 1 << (i + 12);          //data_clane
 224
 225         reg |= 1 << 4 | 1 << 16;                //clk_lane
 226         writel(reg, reg_base + CSI2RX_DPHY_LANE_CONTROL);
 227
 228         /*
 229          * Create a static mapping between the CSI virtual channels
 230          * and the output stream.
 231          *
 232          * This should be enhanced, but v4l2 lacks the support for
 233          * changing that mapping dynamically.
 234          *
 235          * We also cannot enable and disable independent streams here,
 236          * hence the reference counting.
 237          */
 238         for (i = 0; i < CSI2RX_STREAMS_MAX; i++) {
 239                 writel(CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF,
 240                        reg_base + CSI2RX_STREAM_CFG_REG(i));
 241
 242                 writel(CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT |
 243                        CSI2RX_STREAM_DATA_CFG_VC_SELECT(i),
 244                        reg_base + CSI2RX_STREAM_DATA_CFG_REG(i));
 245
 246                 writel(CSI2RX_STREAM_CTRL_START,
 247                        reg_base + CSI2RX_STREAM_CTRL_REG(i));
 248         }
 249
 250         return 0;
 251 }
 252
 253 static void csi2rx_stop(struct stf_csi_dev *csi_dev, void *reg_base)
 254 {
 255         unsigned int i;
 256
 257         for (i = 0; i < CSI2RX_STREAMS_MAX; i++)
 258                 writel(0, reg_base + CSI2RX_STREAM_CTRL_REG(i));
 259 }
 260
 261 static int stf_csi_stream_set(struct stf_csi_dev *csi_dev, int on)
 262 {
 263         struct stfcamss *stfcamss = csi_dev->stfcamss;
 264         struct stf_vin_dev *vin = csi_dev->stfcamss->vin;
 265         void *reg_base = NULL;
 266
 267         if (csi_dev->id == 0)
 268                 reg_base = vin->mipi0_base;
 269         else if (csi_dev->id == 1)
 270                 reg_base = vin->mipi1_base;
 271         else
 272                 return 0;
 273
 274         switch (csi_dev->s_type) {
 275         case SENSOR_VIN:
 276                 clk_set_parent(stfcamss->sys_clk[STFCLK_AXIWR].clk,
 277                         stfcamss->sys_clk[STFCLK_MIPI_RX0_PXL].clk);
 278
 279                 reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_20,
 280                         BIT(3)|BIT(2)|BIT(1)|BIT(0),
 281                         0<<0);          //u0_vin_cnfg_axiwr0_channel_sel
 282                 reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28,
 283                         BIT(14)|BIT(13),
 284                         1<<13);         //u0_vin_cnfg_axiwr0_pix_ct
 285                 reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28,
 286                         BIT(16)|BIT(15),
 287                         0<<15);         //u0_vin_cnfg_axiwr0_pixel_high_bit_sel
 288                 reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28,
 289                         BIT(12)|BIT(11)|BIT(10)|BIT(9)|BIT(8)|BIT(7)|BIT(6)|BIT(5)|BIT(4)|BIT(3)|BIT(2),
 290                         (1920 / 4 - 1)<<2);     //u0_vin_cnfg_axiwr0_pix_cnt_end
 291                 break;
 292         case SENSOR_ISP0:
 293                 clk_set_parent(stfcamss->sys_clk[STFCLK_WRAPPER_CLK_C].clk,
 294                         stfcamss->sys_clk[STFCLK_MIPI_RX0_PXL].clk);
 295
 296                 reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
 297                         BIT(7)|BIT(6),
 298                         0<<6);          //u0_vin_cnfg_mipi_byte_en_isp0
 299                 reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
 300                         BIT(11)|BIT(10)|BIT(9)|BIT(8),
 301                         0<<8);          //u0_vin_cnfg_mipi_channel_sel0
 302                 reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
 303                         BIT(12),
 304                         1<<12);         //u0_vin_cnfg_p_i_mipi_header_en0
 305                 reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
 306                         BIT(16)|BIT(15)|BIT(14)|BIT(13),
 307                         0<<13);         //u0_vin_cnfg_pix_num
 308                 break;
 309         case SENSOR_ISP1:
 310                 st_err(ST_CSI, "please check csi_dev s_type:%d\n", csi_dev->s_type);
 311                 break;
 312         default:
 313                 break;
 314         }
 315
 316         if (on)
 317                 csi2rx_start(csi_dev, reg_base);
 318         else
 319                 csi2rx_stop(csi_dev, reg_base);
 320
 321         return 0;
 322 }
 323
 324 void dump_csi_reg(void *__iomem csibase, int id)
 325 {
 326         st_info(ST_CSI, "DUMP CSI%d register:\n", id);
 327         print_reg(ST_CSI, csibase, 0x00);
 328         print_reg(ST_CSI, csibase, 0x04);
 329         print_reg(ST_CSI, csibase, 0x08);
 330         print_reg(ST_CSI, csibase, 0x10);
 331
 332         print_reg(ST_CSI, csibase, 0x40);
 333         print_reg(ST_CSI, csibase, 0x48);
 334         print_reg(ST_CSI, csibase, 0x4c);
 335         print_reg(ST_CSI, csibase, 0x50);
 336 }
 337
 338 struct csi_hw_ops csi_ops = {
 339         .csi_power_on          = stf_csi_power_on,
 340         .csi_clk_enable        = stf_csi_clk_enable,
 341         .csi_clk_disable       = stf_csi_clk_disable,
 342         .csi_config_set        = stf_csi_config_set,
 343         .csi_set_format        = stf_csi_set_format,
 344         .csi_stream_set        = stf_csi_stream_set,
 345 };