1 // SPDX-License-Identifier: GPL-2.0
3 * linux/drivers/media/platform/starfive/stf_csi.c
5 * Copyright (C) 2021 StarFive Technology Co., Ltd.
9 #include <linux/regmap.h>
11 #define CSI2RX_DEVICE_CFG_REG 0x000
13 #define CSI2RX_SOFT_RESET_REG 0x004
14 #define CSI2RX_SOFT_RESET_PROTOCOL BIT(1)
15 #define CSI2RX_SOFT_RESET_FRONT BIT(0)
17 #define CSI2RX_DPHY_LANE_CONTROL 0x040
19 #define CSI2RX_STATIC_CFG_REG 0x008
20 #define CSI2RX_STATIC_CFG_DLANE_MAP(llane, plane) \
21 ((plane) << (16 + (llane) * 4))
22 #define CSI2RX_STATIC_CFG_LANES_MASK GENMASK(11, 8)
24 #define CSI2RX_STREAM_BASE(n) (((n) + 1) * 0x100)
26 #define CSI2RX_STREAM_CTRL_REG(n) (CSI2RX_STREAM_BASE(n) + 0x000)
27 #define CSI2RX_STREAM_CTRL_START BIT(0)
29 #define CSI2RX_STREAM_DATA_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x008)
30 #define CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT BIT(31)
31 #define CSI2RX_STREAM_DATA_CFG_EN_DATA_TYPE_0 BIT(7)
32 #define CSI2RX_STREAM_DATA_CFG_VC_SELECT(n) BIT((n) + 16)
34 #define CSI2RX_STREAM_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x00c)
35 #define CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF (1 << 8)
37 #define CSI2RX_LANES_MAX 4
38 #define CSI2RX_STREAMS_MAX 4
40 static int stf_csi_power_on(struct stf_csi_dev *csi_dev, u8 on)
42 struct stfcamss *stfcamss = csi_dev->stfcamss;
46 ret = regulator_enable(csi_dev->mipirx_1p8);
48 st_err(ST_CSI, "Cannot enable mipirx_1p8 regulator\n");
52 ret = regulator_enable(csi_dev->mipirx_0p9);
54 st_err(ST_CSI, "Cannot enable mipirx_0p9 regulator\n");
58 regulator_disable(csi_dev->mipirx_1p8);
59 regulator_disable(csi_dev->mipirx_0p9);
62 regmap_write(stfcamss->stf_aon_syscon, stfcamss->aon_gp_reg, 0x80000000);
67 regulator_disable(csi_dev->mipirx_1p8);
73 static int stf_csi_clk_enable(struct stf_csi_dev *csi_dev)
75 struct stfcamss *stfcamss = csi_dev->stfcamss;
77 clk_set_rate(stfcamss->sys_clk[STFCLK_MIPI_RX0_PXL].clk, 204800000);
78 clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF0].clk);
79 clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF1].clk);
80 clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF2].clk);
81 clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF3].clk);
83 reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF0].rstc);
84 reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF1].rstc);
85 reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF2].rstc);
86 reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF3].rstc);
87 reset_control_deassert(stfcamss->sys_rst[STFRST_AXIRD].rstc);
88 reset_control_deassert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
93 static int stf_csi_clk_disable(struct stf_csi_dev *csi_dev)
95 struct stfcamss *stfcamss = csi_dev->stfcamss;
97 reset_control_assert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
98 reset_control_assert(stfcamss->sys_rst[STFRST_AXIRD].rstc);
99 reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF3].rstc);
100 reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF2].rstc);
101 reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF1].rstc);
102 reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF0].rstc);
104 clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF0].clk);
105 clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF1].clk);
106 clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF2].clk);
107 clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF3].clk);
112 static void csi2rx_reset(void *reg_base)
114 writel(CSI2RX_SOFT_RESET_PROTOCOL | CSI2RX_SOFT_RESET_FRONT,
115 reg_base + CSI2RX_SOFT_RESET_REG);
119 writel(0, reg_base + CSI2RX_SOFT_RESET_REG);
122 static int csi2rx_start(struct stf_csi_dev *csi_dev, void *reg_base, u32 dt)
124 struct stfcamss *stfcamss = csi_dev->stfcamss;
125 struct csi2phy_cfg *csiphy =
126 stfcamss->csiphy_dev->csiphy;
128 unsigned long lanes_used = 0;
132 st_err(ST_CSI, "csiphy0 config not exist\n");
136 csi2rx_reset(reg_base);
138 reg = csiphy->num_data_lanes << 8;
139 for (i = 0; i < csiphy->num_data_lanes; i++) {
140 #ifndef USE_CSIDPHY_ONE_CLK_MODE
141 reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, csiphy->data_lanes[i]);
142 set_bit(csiphy->data_lanes[i] - 1, &lanes_used);
144 reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, i + 1);
145 set_bit(i, &lanes_used);
150 * Even the unused lanes need to be mapped. In order to avoid
151 * to map twice to the same physical lane, keep the lanes used
152 * in the previous loop, and only map unused physical lanes to
153 * the rest of our logical lanes.
155 for (i = csiphy->num_data_lanes; i < CSI2RX_LANES_MAX; i++) {
156 unsigned int idx = find_first_zero_bit(&lanes_used,
159 set_bit(idx, &lanes_used);
160 reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, idx + 1);
163 writel(reg, reg_base + CSI2RX_STATIC_CFG_REG);
165 // 0x40 DPHY_LANE_CONTROL
167 #ifndef USE_CSIDPHY_ONE_CLK_MODE
168 for (i = 0; i < csiphy->num_data_lanes; i++)
169 reg |= 1 << (csiphy->data_lanes[i] - 1)
170 | 1 << (csiphy->data_lanes[i] + 11);
172 for (i = 0; i < csiphy->num_data_lanes; i++)
173 reg |= 1 << i | 1 << (i + 12); //data_clane
176 reg |= 1 << 4 | 1 << 16; //clk_lane
177 writel(reg, reg_base + CSI2RX_DPHY_LANE_CONTROL);
180 * Create a static mapping between the CSI virtual channels
181 * and the output stream.
183 * This should be enhanced, but v4l2 lacks the support for
184 * changing that mapping dynamically.
186 * We also cannot enable and disable independent streams here,
187 * hence the reference counting.
189 for (i = 0; i < CSI2RX_STREAMS_MAX; i++) {
190 writel(CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF,
191 reg_base + CSI2RX_STREAM_CFG_REG(i));
193 writel(CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT |
194 CSI2RX_STREAM_DATA_CFG_VC_SELECT(i) |
195 CSI2RX_STREAM_DATA_CFG_EN_DATA_TYPE_0 | dt,
196 reg_base + CSI2RX_STREAM_DATA_CFG_REG(i));
198 writel(CSI2RX_STREAM_CTRL_START,
199 reg_base + CSI2RX_STREAM_CTRL_REG(i));
205 static void csi2rx_stop(struct stf_csi_dev *csi_dev, void *reg_base)
209 for (i = 0; i < CSI2RX_STREAMS_MAX; i++)
210 writel(0, reg_base + CSI2RX_STREAM_CTRL_REG(i));
213 static int stf_csi_stream_set(struct stf_csi_dev *csi_dev,
214 int on, u32 dt, u32 width)
216 struct stfcamss *stfcamss = csi_dev->stfcamss;
217 struct stf_vin_dev *vin = csi_dev->stfcamss->vin;
218 void __iomem *reg_base = vin->csi2rx_base;
220 switch (csi_dev->s_type) {
222 clk_set_parent(stfcamss->sys_clk[STFCLK_AXIWR].clk,
223 stfcamss->sys_clk[STFCLK_MIPI_RX0_PXL].clk);
225 reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_20,
226 BIT(3)|BIT(2)|BIT(1)|BIT(0),
227 0<<0); //u0_vin_cnfg_axiwr0_channel_sel
228 reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28,
230 1<<13); //u0_vin_cnfg_axiwr0_pix_ct
231 reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28,
233 0<<15); //u0_vin_cnfg_axiwr0_pixel_high_bit_sel
234 reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28,
235 BIT(12)|BIT(11)|BIT(10)|BIT(9)|BIT(8)|BIT(7)|BIT(6)|BIT(5)|BIT(4)|BIT(3)|BIT(2),
236 (width / 4 - 1)<<2); //u0_vin_cnfg_axiwr0_pix_cnt_end
239 clk_set_parent(stfcamss->sys_clk[STFCLK_WRAPPER_CLK_C].clk,
240 stfcamss->sys_clk[STFCLK_MIPI_RX0_PXL].clk);
242 reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_36,
244 0<<6); //u0_vin_cnfg_mipi_byte_en_isp
245 reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_36,
246 BIT(11)|BIT(10)|BIT(9)|BIT(8),
247 0<<8); //u0_vin_cnfg_mipi_channel_sel0
248 reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_36,
249 BIT(16)|BIT(15)|BIT(14)|BIT(13),
250 0<<13); //u0_vin_cnfg_pix_num
253 reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_36,
255 1<<12); //u0_vin_cnfg_p_i_mipi_header_en0
262 csi2rx_start(csi_dev, reg_base, dt);
264 csi2rx_stop(csi_dev, reg_base);
269 void dump_csi_reg(void *__iomem csibase)
271 st_info(ST_CSI, "DUMP CSI register:\n");
272 print_reg(ST_CSI, csibase, 0x00);
273 print_reg(ST_CSI, csibase, 0x04);
274 print_reg(ST_CSI, csibase, 0x08);
275 print_reg(ST_CSI, csibase, 0x10);
277 print_reg(ST_CSI, csibase, 0x40);
278 print_reg(ST_CSI, csibase, 0x48);
279 print_reg(ST_CSI, csibase, 0x4c);
280 print_reg(ST_CSI, csibase, 0x50);
283 struct csi_hw_ops csi_ops = {
284 .csi_power_on = stf_csi_power_on,
285 .csi_clk_enable = stf_csi_clk_enable,
286 .csi_clk_disable = stf_csi_clk_disable,
287 .csi_stream_set = stf_csi_stream_set,