drivers/media/platform/starfive/v4l2_driver/stf_common.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright (C) 2021 StarFive Technology Co., Ltd.
   4  */
   5 #ifndef STF_COMMON_H
   6 #define STF_COMMON_H
   7
   8 #include <linux/kern_levels.h>
   9
  10 // #define STF_DEBUG
  11
  12 #define USE_CSIDPHY_ONE_CLK_MODE 1
  13
  14 enum {
  15         ST_DVP = 0x0001,
  16         ST_CSIPHY = 0x0002,
  17         ST_CSI = 0x0004,
  18         ST_ISP = 0x0008,
  19         ST_VIN = 0x0010,
  20         ST_VIDEO = 0x0020,
  21         ST_CAMSS = 0x0040,
  22         ST_SENSOR = 0x0080,
  23 };
  24
  25 enum {
  26         ST_NONE = 0x00,
  27         ST_ERR = 0x01,
  28         ST_WARN = 0x02,
  29         ST_INFO = 0x03,
  30         ST_DEBUG = 0x04,
  31 };
  32
  33 extern unsigned int stdbg_level;
  34 extern unsigned int stdbg_mask;
  35
  36 #define ST_MODULE2STRING(__module) ({ \
  37         char *__str; \
  38         \
  39         switch (__module) { \
  40         case ST_DVP: \
  41                 __str = "st_dvp"; \
  42                 break; \
  43         case ST_CSIPHY: \
  44                 __str = "st_csiphy"; \
  45                 break; \
  46         case ST_CSI: \
  47                 __str = "st_csi"; \
  48                 break; \
  49         case ST_ISP: \
  50                 __str = "st_isp"; \
  51                 break; \
  52         case ST_VIN: \
  53                 __str = "st_vin"; \
  54                 break; \
  55         case ST_VIDEO: \
  56                 __str = "st_video"; \
  57                 break; \
  58         case ST_CAMSS: \
  59                 __str = "st_camss"; \
  60                 break; \
  61         case ST_SENSOR: \
  62                 __str = "st_sensor"; \
  63                 break; \
  64         default: \
  65                 __str = "unknow"; \
  66                 break; \
  67         } \
  68         \
  69         __str; \
  70         })
  71
  72 #define st_debug(module, __fmt, arg...) \
  73         do { \
  74                 if (stdbg_level > ST_INFO) { \
  75                         if (stdbg_mask & module)  \
  76                                 pr_err("[%s] debug: " __fmt, \
  77                                                 ST_MODULE2STRING(module), \
  78                                                 ## arg); \
  79                 } \
  80         } while (0)
  81
  82 #define st_info(module, __fmt, arg...)  \
  83         do { \
  84                 if (stdbg_level > ST_WARN) { \
  85                         if (stdbg_mask & module)  \
  86                                 pr_err("[%s] info: " __fmt, \
  87                                                 ST_MODULE2STRING(module), \
  88                                                 ## arg); \
  89                 } \
  90         } while (0)
  91
  92 #define st_warn(module, __fmt, arg...)  \
  93         do { \
  94                 if (stdbg_level > ST_ERR) { \
  95                         if (stdbg_mask & module)  \
  96                                 pr_err("[%s] warn: " __fmt, \
  97                                                 ST_MODULE2STRING(module), \
  98                                                 ## arg); \
  99                 } \
 100         } while (0)
 101
 102 #define st_err(module, __fmt, arg...)   \
 103         do { \
 104                 if (stdbg_level > ST_NONE) { \
 105                         if (stdbg_mask & module) \
 106                                 pr_err("[%s] error: " __fmt, \
 107                                                 ST_MODULE2STRING(module), \
 108                                                 ## arg); \
 109                 } \
 110         } while (0)
 111
 112 #define st_err_ratelimited(module, fmt, ...)                 \
 113         do {                                                                    \
 114                 static DEFINE_RATELIMIT_STATE(_rs,                              \
 115                                                 DEFAULT_RATELIMIT_INTERVAL,     \
 116                                                 DEFAULT_RATELIMIT_BURST);       \
 117                 if (__ratelimit(&_rs) && (stdbg_level > ST_NONE)) {             \
 118                         if (stdbg_mask & module)                                \
 119                                 pr_err("[%s] error: " fmt,                      \
 120                                                 ST_MODULE2STRING(module),       \
 121                                                 ##__VA_ARGS__);                 \
 122                 } \
 123         } while (0)
 124
 125 #define set_bits(p, v, b, m)    (((p) & ~(m)) | ((v) << (b)))
 126
 127 static inline u32 reg_read(void __iomem *base, u32 reg)
 128 {
 129         return ioread32(base + reg);
 130 }
 131
 132 static inline void reg_write(void __iomem *base, u32 reg, u32 val)
 133 {
 134         iowrite32(val, base + reg);
 135 }
 136
 137 static inline void reg_set_bit(void __iomem *base, u32 reg, u32 mask, u32 val)
 138 {
 139         u32 value;
 140
 141         value = ioread32(base + reg) & ~mask;
 142         val &= mask;
 143         val |= value;
 144         iowrite32(val, base + reg);
 145 }
 146
 147 static inline void reg_set(void __iomem *base, u32 reg, u32 mask)
 148 {
 149         iowrite32(ioread32(base + reg) | mask, base + reg);
 150 }
 151
 152 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask)
 153 {
 154         iowrite32(ioread32(base + reg) & ~mask, base + reg);
 155 }
 156
 157 static inline void reg_set_highest_bit(void __iomem *base, u32 reg)
 158 {
 159         u32 val;
 160
 161         val = ioread32(base + reg);
 162         val &= ~(0x1 << 31);
 163         val |= (0x1 & 0x1) << 31;
 164         iowrite32(val, base + reg);
 165 }
 166
 167 static inline void reg_clr_highest_bit(void __iomem *base, u32 reg)
 168 {
 169         u32 val;
 170
 171         val = ioread32(base + reg);
 172         val &= ~(0x1 << 31);
 173         val |= (0x0 & 0x1) << 31;
 174         iowrite32(val, base + reg);
 175 }
 176
 177 static inline void print_reg(unsigned int module, void __iomem *base, u32 reg)
 178 {
 179         //st_debug(module, "REG 0x%x = 0x%x\n",
 180         //              base + reg, ioread32(base + reg));
 181 }
 182
 183 #endif /* STF_COMMON_H */