drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Rockchip ISP1 Driver - ISP Subdevice
   4  *
   5  * Copyright (C) 2019 Collabora, Ltd.
   6  *
   7  * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd.
   8  * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
   9  */
  10
  11 #include <linux/iopoll.h>
  12 #include <linux/phy/phy.h>
  13 #include <linux/phy/phy-mipi-dphy.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/videodev2.h>
  16 #include <linux/vmalloc.h>
  17 #include <media/v4l2-event.h>
  18
  19 #include "rkisp1-common.h"
  20
  21 #define RKISP1_DEF_SINK_PAD_FMT MEDIA_BUS_FMT_SRGGB10_1X10
  22 #define RKISP1_DEF_SRC_PAD_FMT MEDIA_BUS_FMT_YUYV8_2X8
  23
  24 #define RKISP1_ISP_DEV_NAME     RKISP1_DRIVER_NAME "_isp"
  25
  26 /*
  27  * NOTE: MIPI controller and input MUX are also configured in this file.
  28  * This is because ISP Subdev describes not only ISP submodule (input size,
  29  * format, output size, format), but also a virtual route device.
  30  */
  31
  32 /*
  33  * There are many variables named with format/frame in below code,
  34  * please see here for their meaning.
  35  * Cropping in the sink pad defines the image region from the sensor.
  36  * Cropping in the source pad defines the region for the Image Stabilizer (IS)
  37  *
  38  * Cropping regions of ISP
  39  *
  40  * +---------------------------------------------------------+
  41  * | Sensor image                                            |
  42  * | +---------------------------------------------------+   |
  43  * | | CIF_ISP_ACQ (for black level)                     |   |
  44  * | | sink pad format                                   |   |
  45  * | | +--------------------------------------------+    |   |
  46  * | | |    CIF_ISP_OUT                             |    |   |
  47  * | | |    sink pad crop                           |    |   |
  48  * | | |    +---------------------------------+     |    |   |
  49  * | | |    |   CIF_ISP_IS                    |     |    |   |
  50  * | | |    |   source pad crop and format    |     |    |   |
  51  * | | |    +---------------------------------+     |    |   |
  52  * | | +--------------------------------------------+    |   |
  53  * | +---------------------------------------------------+   |
  54  * +---------------------------------------------------------+
  55  */
  56
  57 static const struct rkisp1_isp_mbus_info rkisp1_isp_formats[] = {
  58         {
  59                 .mbus_code      = MEDIA_BUS_FMT_YUYV8_2X8,
  60                 .pixel_enc      = V4L2_PIXEL_ENC_YUV,
  61                 .direction      = RKISP1_ISP_SD_SRC,
  62         }, {
  63                 .mbus_code      = MEDIA_BUS_FMT_SRGGB10_1X10,
  64                 .pixel_enc      = V4L2_PIXEL_ENC_BAYER,
  65                 .mipi_dt        = RKISP1_CIF_CSI2_DT_RAW10,
  66                 .bayer_pat      = RKISP1_RAW_RGGB,
  67                 .bus_width      = 10,
  68                 .direction      = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
  69         }, {
  70                 .mbus_code      = MEDIA_BUS_FMT_SBGGR10_1X10,
  71                 .pixel_enc      = V4L2_PIXEL_ENC_BAYER,
  72                 .mipi_dt        = RKISP1_CIF_CSI2_DT_RAW10,
  73                 .bayer_pat      = RKISP1_RAW_BGGR,
  74                 .bus_width      = 10,
  75                 .direction      = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
  76         }, {
  77                 .mbus_code      = MEDIA_BUS_FMT_SGBRG10_1X10,
  78                 .pixel_enc      = V4L2_PIXEL_ENC_BAYER,
  79                 .mipi_dt        = RKISP1_CIF_CSI2_DT_RAW10,
  80                 .bayer_pat      = RKISP1_RAW_GBRG,
  81                 .bus_width      = 10,
  82                 .direction      = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
  83         }, {
  84                 .mbus_code      = MEDIA_BUS_FMT_SGRBG10_1X10,
  85                 .pixel_enc      = V4L2_PIXEL_ENC_BAYER,
  86                 .mipi_dt        = RKISP1_CIF_CSI2_DT_RAW10,
  87                 .bayer_pat      = RKISP1_RAW_GRBG,
  88                 .bus_width      = 10,
  89                 .direction      = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
  90         }, {
  91                 .mbus_code      = MEDIA_BUS_FMT_SRGGB12_1X12,
  92                 .pixel_enc      = V4L2_PIXEL_ENC_BAYER,
  93                 .mipi_dt        = RKISP1_CIF_CSI2_DT_RAW12,
  94                 .bayer_pat      = RKISP1_RAW_RGGB,
  95                 .bus_width      = 12,
  96                 .direction      = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
  97         }, {
  98                 .mbus_code      = MEDIA_BUS_FMT_SBGGR12_1X12,
  99                 .pixel_enc      = V4L2_PIXEL_ENC_BAYER,
 100                 .mipi_dt        = RKISP1_CIF_CSI2_DT_RAW12,
 101                 .bayer_pat      = RKISP1_RAW_BGGR,
 102                 .bus_width      = 12,
 103                 .direction      = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
 104         }, {
 105                 .mbus_code      = MEDIA_BUS_FMT_SGBRG12_1X12,
 106                 .pixel_enc      = V4L2_PIXEL_ENC_BAYER,
 107                 .mipi_dt        = RKISP1_CIF_CSI2_DT_RAW12,
 108                 .bayer_pat      = RKISP1_RAW_GBRG,
 109                 .bus_width      = 12,
 110                 .direction      = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
 111         }, {
 112                 .mbus_code      = MEDIA_BUS_FMT_SGRBG12_1X12,
 113                 .pixel_enc      = V4L2_PIXEL_ENC_BAYER,
 114                 .mipi_dt        = RKISP1_CIF_CSI2_DT_RAW12,
 115                 .bayer_pat      = RKISP1_RAW_GRBG,
 116                 .bus_width      = 12,
 117                 .direction      = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
 118         }, {
 119                 .mbus_code      = MEDIA_BUS_FMT_SRGGB8_1X8,
 120                 .pixel_enc      = V4L2_PIXEL_ENC_BAYER,
 121                 .mipi_dt        = RKISP1_CIF_CSI2_DT_RAW8,
 122                 .bayer_pat      = RKISP1_RAW_RGGB,
 123                 .bus_width      = 8,
 124                 .direction      = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
 125         }, {
 126                 .mbus_code      = MEDIA_BUS_FMT_SBGGR8_1X8,
 127                 .pixel_enc      = V4L2_PIXEL_ENC_BAYER,
 128                 .mipi_dt        = RKISP1_CIF_CSI2_DT_RAW8,
 129                 .bayer_pat      = RKISP1_RAW_BGGR,
 130                 .bus_width      = 8,
 131                 .direction      = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
 132         }, {
 133                 .mbus_code      = MEDIA_BUS_FMT_SGBRG8_1X8,
 134                 .pixel_enc      = V4L2_PIXEL_ENC_BAYER,
 135                 .mipi_dt        = RKISP1_CIF_CSI2_DT_RAW8,
 136                 .bayer_pat      = RKISP1_RAW_GBRG,
 137                 .bus_width      = 8,
 138                 .direction      = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
 139         }, {
 140                 .mbus_code      = MEDIA_BUS_FMT_SGRBG8_1X8,
 141                 .pixel_enc      = V4L2_PIXEL_ENC_BAYER,
 142                 .mipi_dt        = RKISP1_CIF_CSI2_DT_RAW8,
 143                 .bayer_pat      = RKISP1_RAW_GRBG,
 144                 .bus_width      = 8,
 145                 .direction      = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
 146         }, {
 147                 .mbus_code      = MEDIA_BUS_FMT_YUYV8_1X16,
 148                 .pixel_enc      = V4L2_PIXEL_ENC_YUV,
 149                 .mipi_dt        = RKISP1_CIF_CSI2_DT_YUV422_8b,
 150                 .yuv_seq        = RKISP1_CIF_ISP_ACQ_PROP_YCBYCR,
 151                 .bus_width      = 16,
 152                 .direction      = RKISP1_ISP_SD_SINK,
 153         }, {
 154                 .mbus_code      = MEDIA_BUS_FMT_YVYU8_1X16,
 155                 .pixel_enc      = V4L2_PIXEL_ENC_YUV,
 156                 .mipi_dt        = RKISP1_CIF_CSI2_DT_YUV422_8b,
 157                 .yuv_seq        = RKISP1_CIF_ISP_ACQ_PROP_YCRYCB,
 158                 .bus_width      = 16,
 159                 .direction      = RKISP1_ISP_SD_SINK,
 160         }, {
 161                 .mbus_code      = MEDIA_BUS_FMT_UYVY8_1X16,
 162                 .pixel_enc      = V4L2_PIXEL_ENC_YUV,
 163                 .mipi_dt        = RKISP1_CIF_CSI2_DT_YUV422_8b,
 164                 .yuv_seq        = RKISP1_CIF_ISP_ACQ_PROP_CBYCRY,
 165                 .bus_width      = 16,
 166                 .direction      = RKISP1_ISP_SD_SINK,
 167         }, {
 168                 .mbus_code      = MEDIA_BUS_FMT_VYUY8_1X16,
 169                 .pixel_enc      = V4L2_PIXEL_ENC_YUV,
 170                 .mipi_dt        = RKISP1_CIF_CSI2_DT_YUV422_8b,
 171                 .yuv_seq        = RKISP1_CIF_ISP_ACQ_PROP_CRYCBY,
 172                 .bus_width      = 16,
 173                 .direction      = RKISP1_ISP_SD_SINK,
 174         },
 175 };
 176
 177 /* ----------------------------------------------------------------------------
 178  * Helpers
 179  */
 180
 181 const struct rkisp1_isp_mbus_info *rkisp1_isp_mbus_info_get(u32 mbus_code)
 182 {
 183         unsigned int i;
 184
 185         for (i = 0; i < ARRAY_SIZE(rkisp1_isp_formats); i++) {
 186                 const struct rkisp1_isp_mbus_info *fmt = &rkisp1_isp_formats[i];
 187
 188                 if (fmt->mbus_code == mbus_code)
 189                         return fmt;
 190         }
 191
 192         return NULL;
 193 }
 194
 195 static struct v4l2_subdev *rkisp1_get_remote_sensor(struct v4l2_subdev *sd)
 196 {
 197         struct media_pad *local, *remote;
 198         struct media_entity *sensor_me;
 199
 200         local = &sd->entity.pads[RKISP1_ISP_PAD_SINK_VIDEO];
 201         remote = media_entity_remote_pad(local);
 202         if (!remote)
 203                 return NULL;
 204
 205         sensor_me = remote->entity;
 206         return media_entity_to_v4l2_subdev(sensor_me);
 207 }
 208
 209 static struct v4l2_mbus_framefmt *
 210 rkisp1_isp_get_pad_fmt(struct rkisp1_isp *isp,
 211                        struct v4l2_subdev_state *sd_state,
 212                        unsigned int pad, u32 which)
 213 {
 214         struct v4l2_subdev_state state = {
 215                 .pads = isp->pad_cfg
 216                 };
 217         struct v4l2_subdev_state state = {
 218                 .pads = &state
 219                 };
 220         struct v4l2_subdev_state state = {
 221                 .pads = &state
 222                 };
 223         if (which == V4L2_SUBDEV_FORMAT_TRY)
 224                 return v4l2_subdev_get_try_format(&isp->sd, sd_state, pad);
 225         else
 226                 return v4l2_subdev_get_try_format(&isp->sd, &state, pad);
 227 }
 228
 229 static struct v4l2_rect *
 230 rkisp1_isp_get_pad_crop(struct rkisp1_isp *isp,
 231                         struct v4l2_subdev_state *sd_state,
 232                         unsigned int pad, u32 which)
 233 {
 234         struct v4l2_subdev_state state = {
 235                 .pads = isp->pad_cfg
 236                 };
 237         struct v4l2_subdev_state state = {
 238                 .pads = &state
 239                 };
 240         struct v4l2_subdev_state state = {
 241                 .pads = &state
 242                 };
 243         if (which == V4L2_SUBDEV_FORMAT_TRY)
 244                 return v4l2_subdev_get_try_crop(&isp->sd, sd_state, pad);
 245         else
 246                 return v4l2_subdev_get_try_crop(&isp->sd, &state, pad);
 247 }
 248
 249 /* ----------------------------------------------------------------------------
 250  * Camera Interface registers configurations
 251  */
 252
 253 /*
 254  * Image Stabilization.
 255  * This should only be called when configuring CIF
 256  * or at the frame end interrupt
 257  */
 258 static void rkisp1_config_ism(struct rkisp1_device *rkisp1)
 259 {
 260         struct v4l2_rect *src_crop =
 261                 rkisp1_isp_get_pad_crop(&rkisp1->isp, NULL,
 262                                         RKISP1_ISP_PAD_SOURCE_VIDEO,
 263                                         V4L2_SUBDEV_FORMAT_ACTIVE);
 264         u32 val;
 265
 266         rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IS_RECENTER);
 267         rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IS_MAX_DX);
 268         rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IS_MAX_DY);
 269         rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IS_DISPLACE);
 270         rkisp1_write(rkisp1, src_crop->left, RKISP1_CIF_ISP_IS_H_OFFS);
 271         rkisp1_write(rkisp1, src_crop->top, RKISP1_CIF_ISP_IS_V_OFFS);
 272         rkisp1_write(rkisp1, src_crop->width, RKISP1_CIF_ISP_IS_H_SIZE);
 273         rkisp1_write(rkisp1, src_crop->height, RKISP1_CIF_ISP_IS_V_SIZE);
 274
 275         /* IS(Image Stabilization) is always on, working as output crop */
 276         rkisp1_write(rkisp1, 1, RKISP1_CIF_ISP_IS_CTRL);
 277         val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL);
 278         val |= RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD;
 279         rkisp1_write(rkisp1, val, RKISP1_CIF_ISP_CTRL);
 280 }
 281
 282 /*
 283  * configure ISP blocks with input format, size......
 284  */
 285 static int rkisp1_config_isp(struct rkisp1_device *rkisp1)
 286 {
 287         u32 isp_ctrl = 0, irq_mask = 0, acq_mult = 0, signal = 0;
 288         const struct rkisp1_isp_mbus_info *src_fmt, *sink_fmt;
 289         struct rkisp1_sensor_async *sensor;
 290         struct v4l2_mbus_framefmt *sink_frm;
 291         struct v4l2_rect *sink_crop;
 292
 293         sensor = rkisp1->active_sensor;
 294         sink_fmt = rkisp1->isp.sink_fmt;
 295         src_fmt = rkisp1->isp.src_fmt;
 296         sink_frm = rkisp1_isp_get_pad_fmt(&rkisp1->isp, NULL,
 297                                           RKISP1_ISP_PAD_SINK_VIDEO,
 298                                           V4L2_SUBDEV_FORMAT_ACTIVE);
 299         sink_crop = rkisp1_isp_get_pad_crop(&rkisp1->isp, NULL,
 300                                             RKISP1_ISP_PAD_SINK_VIDEO,
 301                                             V4L2_SUBDEV_FORMAT_ACTIVE);
 302
 303         if (sink_fmt->pixel_enc == V4L2_PIXEL_ENC_BAYER) {
 304                 acq_mult = 1;
 305                 if (src_fmt->pixel_enc == V4L2_PIXEL_ENC_BAYER) {
 306                         if (sensor->mbus_type == V4L2_MBUS_BT656)
 307                                 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT_ITU656;
 308                         else
 309                                 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT;
 310                 } else {
 311                         rkisp1_write(rkisp1, RKISP1_CIF_ISP_DEMOSAIC_TH(0xc),
 312                                      RKISP1_CIF_ISP_DEMOSAIC);
 313
 314                         if (sensor->mbus_type == V4L2_MBUS_BT656)
 315                                 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_BAYER_ITU656;
 316                         else
 317                                 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_BAYER_ITU601;
 318                 }
 319         } else if (sink_fmt->pixel_enc == V4L2_PIXEL_ENC_YUV) {
 320                 acq_mult = 2;
 321                 if (sensor->mbus_type == V4L2_MBUS_CSI2_DPHY) {
 322                         isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU601;
 323                 } else {
 324                         if (sensor->mbus_type == V4L2_MBUS_BT656)
 325                                 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU656;
 326                         else
 327                                 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU601;
 328                 }
 329
 330                 irq_mask |= RKISP1_CIF_ISP_DATA_LOSS;
 331         }
 332
 333         /* Set up input acquisition properties */
 334         if (sensor->mbus_type == V4L2_MBUS_BT656 ||
 335             sensor->mbus_type == V4L2_MBUS_PARALLEL) {
 336                 if (sensor->mbus_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
 337                         signal = RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE;
 338         }
 339
 340         if (sensor->mbus_type == V4L2_MBUS_PARALLEL) {
 341                 if (sensor->mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
 342                         signal |= RKISP1_CIF_ISP_ACQ_PROP_VSYNC_LOW;
 343
 344                 if (sensor->mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
 345                         signal |= RKISP1_CIF_ISP_ACQ_PROP_HSYNC_LOW;
 346         }
 347
 348         rkisp1_write(rkisp1, isp_ctrl, RKISP1_CIF_ISP_CTRL);
 349         rkisp1_write(rkisp1, signal | sink_fmt->yuv_seq |
 350                      RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT(sink_fmt->bayer_pat) |
 351                      RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL,
 352                      RKISP1_CIF_ISP_ACQ_PROP);
 353         rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_ACQ_NR_FRAMES);
 354
 355         /* Acquisition Size */
 356         rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_ACQ_H_OFFS);
 357         rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_ACQ_V_OFFS);
 358         rkisp1_write(rkisp1,
 359                      acq_mult * sink_frm->width, RKISP1_CIF_ISP_ACQ_H_SIZE);
 360         rkisp1_write(rkisp1, sink_frm->height, RKISP1_CIF_ISP_ACQ_V_SIZE);
 361
 362         /* ISP Out Area */
 363         rkisp1_write(rkisp1, sink_crop->left, RKISP1_CIF_ISP_OUT_H_OFFS);
 364         rkisp1_write(rkisp1, sink_crop->top, RKISP1_CIF_ISP_OUT_V_OFFS);
 365         rkisp1_write(rkisp1, sink_crop->width, RKISP1_CIF_ISP_OUT_H_SIZE);
 366         rkisp1_write(rkisp1, sink_crop->height, RKISP1_CIF_ISP_OUT_V_SIZE);
 367
 368         irq_mask |= RKISP1_CIF_ISP_FRAME | RKISP1_CIF_ISP_V_START |
 369                     RKISP1_CIF_ISP_PIC_SIZE_ERROR;
 370         rkisp1_write(rkisp1, irq_mask, RKISP1_CIF_ISP_IMSC);
 371
 372         if (src_fmt->pixel_enc == V4L2_PIXEL_ENC_BAYER) {
 373                 rkisp1_params_disable(&rkisp1->params);
 374         } else {
 375                 struct v4l2_mbus_framefmt *src_frm;
 376
 377                 src_frm = rkisp1_isp_get_pad_fmt(&rkisp1->isp, NULL,
 378                                                  RKISP1_ISP_PAD_SINK_VIDEO,
 379                                                  V4L2_SUBDEV_FORMAT_ACTIVE);
 380                 rkisp1_params_configure(&rkisp1->params, sink_fmt->bayer_pat,
 381                                         src_frm->quantization);
 382         }
 383
 384         return 0;
 385 }
 386
 387 static int rkisp1_config_dvp(struct rkisp1_device *rkisp1)
 388 {
 389         const struct rkisp1_isp_mbus_info *sink_fmt = rkisp1->isp.sink_fmt;
 390         u32 val, input_sel;
 391
 392         switch (sink_fmt->bus_width) {
 393         case 8:
 394                 input_sel = RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_8B_ZERO;
 395                 break;
 396         case 10:
 397                 input_sel = RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_10B_ZERO;
 398                 break;
 399         case 12:
 400                 input_sel = RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B;
 401                 break;
 402         default:
 403                 dev_err(rkisp1->dev, "Invalid bus width\n");
 404                 return -EINVAL;
 405         }
 406
 407         val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_ACQ_PROP);
 408         rkisp1_write(rkisp1, val | input_sel, RKISP1_CIF_ISP_ACQ_PROP);
 409
 410         return 0;
 411 }
 412
 413 static int rkisp1_config_mipi(struct rkisp1_device *rkisp1)
 414 {
 415         const struct rkisp1_isp_mbus_info *sink_fmt = rkisp1->isp.sink_fmt;
 416         unsigned int lanes = rkisp1->active_sensor->lanes;
 417         u32 mipi_ctrl;
 418
 419         if (lanes < 1 || lanes > 4)
 420                 return -EINVAL;
 421
 422         mipi_ctrl = RKISP1_CIF_MIPI_CTRL_NUM_LANES(lanes - 1) |
 423                     RKISP1_CIF_MIPI_CTRL_SHUTDOWNLANES(0xf) |
 424                     RKISP1_CIF_MIPI_CTRL_ERR_SOT_SYNC_HS_SKIP |
 425                     RKISP1_CIF_MIPI_CTRL_CLOCKLANE_ENA;
 426
 427         rkisp1_write(rkisp1, mipi_ctrl, RKISP1_CIF_MIPI_CTRL);
 428
 429         /* Configure Data Type and Virtual Channel */
 430         rkisp1_write(rkisp1,
 431                      RKISP1_CIF_MIPI_DATA_SEL_DT(sink_fmt->mipi_dt) |
 432                      RKISP1_CIF_MIPI_DATA_SEL_VC(0),
 433                      RKISP1_CIF_MIPI_IMG_DATA_SEL);
 434
 435         /* Clear MIPI interrupts */
 436         rkisp1_write(rkisp1, ~0, RKISP1_CIF_MIPI_ICR);
 437         /*
 438          * Disable RKISP1_CIF_MIPI_ERR_DPHY interrupt here temporary for
 439          * isp bus may be dead when switch isp.
 440          */
 441         rkisp1_write(rkisp1,
 442                      RKISP1_CIF_MIPI_FRAME_END | RKISP1_CIF_MIPI_ERR_CSI |
 443                      RKISP1_CIF_MIPI_ERR_DPHY |
 444                      RKISP1_CIF_MIPI_SYNC_FIFO_OVFLW(0x03) |
 445                      RKISP1_CIF_MIPI_ADD_DATA_OVFLW,
 446                      RKISP1_CIF_MIPI_IMSC);
 447
 448         dev_dbg(rkisp1->dev, "\n  MIPI_CTRL 0x%08x\n"
 449                 "  MIPI_IMG_DATA_SEL 0x%08x\n"
 450                 "  MIPI_STATUS 0x%08x\n"
 451                 "  MIPI_IMSC 0x%08x\n",
 452                 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL),
 453                 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMG_DATA_SEL),
 454                 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_STATUS),
 455                 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC));
 456
 457         return 0;
 458 }
 459
 460 /* Configure MUX */
 461 static int rkisp1_config_path(struct rkisp1_device *rkisp1)
 462 {
 463         struct rkisp1_sensor_async *sensor = rkisp1->active_sensor;
 464         u32 dpcl = rkisp1_read(rkisp1, RKISP1_CIF_VI_DPCL);
 465         int ret = 0;
 466
 467         if (sensor->mbus_type == V4L2_MBUS_BT656 ||
 468             sensor->mbus_type == V4L2_MBUS_PARALLEL) {
 469                 ret = rkisp1_config_dvp(rkisp1);
 470                 dpcl |= RKISP1_CIF_VI_DPCL_IF_SEL_PARALLEL;
 471         } else if (sensor->mbus_type == V4L2_MBUS_CSI2_DPHY) {
 472                 ret = rkisp1_config_mipi(rkisp1);
 473                 dpcl |= RKISP1_CIF_VI_DPCL_IF_SEL_MIPI;
 474         }
 475
 476         rkisp1_write(rkisp1, dpcl, RKISP1_CIF_VI_DPCL);
 477
 478         return ret;
 479 }
 480
 481 /* Hardware configure Entry */
 482 static int rkisp1_config_cif(struct rkisp1_device *rkisp1)
 483 {
 484         u32 cif_id;
 485         int ret;
 486
 487         cif_id = rkisp1_read(rkisp1, RKISP1_CIF_VI_ID);
 488         dev_dbg(rkisp1->dev, "CIF_ID 0x%08x\n", cif_id);
 489
 490         ret = rkisp1_config_isp(rkisp1);
 491         if (ret)
 492                 return ret;
 493         ret = rkisp1_config_path(rkisp1);
 494         if (ret)
 495                 return ret;
 496         rkisp1_config_ism(rkisp1);
 497
 498         return 0;
 499 }
 500
 501 static void rkisp1_isp_stop(struct rkisp1_device *rkisp1)
 502 {
 503         u32 val;
 504
 505         /*
 506          * ISP(mi) stop in mi frame end -> Stop ISP(mipi) ->
 507          * Stop ISP(isp) ->wait for ISP isp off
 508          */
 509         /* stop and clear MI, MIPI, and ISP interrupts */
 510         rkisp1_write(rkisp1, 0, RKISP1_CIF_MIPI_IMSC);
 511         rkisp1_write(rkisp1, ~0, RKISP1_CIF_MIPI_ICR);
 512
 513         rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IMSC);
 514         rkisp1_write(rkisp1, ~0, RKISP1_CIF_ISP_ICR);
 515
 516         rkisp1_write(rkisp1, 0, RKISP1_CIF_MI_IMSC);
 517         rkisp1_write(rkisp1, ~0, RKISP1_CIF_MI_ICR);
 518         val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL);
 519         rkisp1_write(rkisp1, val & (~RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA),
 520                      RKISP1_CIF_MIPI_CTRL);
 521         /* stop ISP */
 522         val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL);
 523         val &= ~(RKISP1_CIF_ISP_CTRL_ISP_INFORM_ENABLE |
 524                  RKISP1_CIF_ISP_CTRL_ISP_ENABLE);
 525         rkisp1_write(rkisp1, val, RKISP1_CIF_ISP_CTRL);
 526
 527         val = rkisp1_read(rkisp1,       RKISP1_CIF_ISP_CTRL);
 528         rkisp1_write(rkisp1, val | RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD,
 529                      RKISP1_CIF_ISP_CTRL);
 530
 531         readx_poll_timeout(readl, rkisp1->base_addr + RKISP1_CIF_ISP_RIS,
 532                            val, val & RKISP1_CIF_ISP_OFF, 20, 100);
 533         rkisp1_write(rkisp1,
 534                      RKISP1_CIF_IRCL_MIPI_SW_RST | RKISP1_CIF_IRCL_ISP_SW_RST,
 535                      RKISP1_CIF_IRCL);
 536         rkisp1_write(rkisp1, 0x0, RKISP1_CIF_IRCL);
 537 }
 538
 539 static void rkisp1_config_clk(struct rkisp1_device *rkisp1)
 540 {
 541         u32 val = RKISP1_CIF_ICCL_ISP_CLK | RKISP1_CIF_ICCL_CP_CLK |
 542                   RKISP1_CIF_ICCL_MRSZ_CLK | RKISP1_CIF_ICCL_SRSZ_CLK |
 543                   RKISP1_CIF_ICCL_JPEG_CLK | RKISP1_CIF_ICCL_MI_CLK |
 544                   RKISP1_CIF_ICCL_IE_CLK | RKISP1_CIF_ICCL_MIPI_CLK |
 545                   RKISP1_CIF_ICCL_DCROP_CLK;
 546
 547         rkisp1_write(rkisp1, val, RKISP1_CIF_ICCL);
 548 }
 549
 550 static void rkisp1_isp_start(struct rkisp1_device *rkisp1)
 551 {
 552         struct rkisp1_sensor_async *sensor = rkisp1->active_sensor;
 553         u32 val;
 554
 555         rkisp1_config_clk(rkisp1);
 556
 557         /* Activate MIPI */
 558         if (sensor->mbus_type == V4L2_MBUS_CSI2_DPHY) {
 559                 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL);
 560                 rkisp1_write(rkisp1, val | RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA,
 561                              RKISP1_CIF_MIPI_CTRL);
 562         }
 563         /* Activate ISP */
 564         val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL);
 565         val |= RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD |
 566                RKISP1_CIF_ISP_CTRL_ISP_ENABLE |
 567                RKISP1_CIF_ISP_CTRL_ISP_INFORM_ENABLE;
 568         rkisp1_write(rkisp1, val, RKISP1_CIF_ISP_CTRL);
 569
 570         /*
 571          * CIF spec says to wait for sufficient time after enabling
 572          * the MIPI interface and before starting the sensor output.
 573          */
 574         usleep_range(1000, 1200);
 575 }
 576
 577 /* ----------------------------------------------------------------------------
 578  * Subdev pad operations
 579  */
 580
 581 static int rkisp1_isp_enum_mbus_code(struct v4l2_subdev *sd,
 582                                      struct v4l2_subdev_state *sd_state,
 583                                      struct v4l2_subdev_mbus_code_enum *code)
 584 {
 585         unsigned int i, dir;
 586         int pos = 0;
 587
 588         if (code->pad == RKISP1_ISP_PAD_SINK_VIDEO) {
 589                 dir = RKISP1_ISP_SD_SINK;
 590         } else if (code->pad == RKISP1_ISP_PAD_SOURCE_VIDEO) {
 591                 dir = RKISP1_ISP_SD_SRC;
 592         } else {
 593                 if (code->index > 0)
 594                         return -EINVAL;
 595                 code->code = MEDIA_BUS_FMT_METADATA_FIXED;
 596                 return 0;
 597         }
 598
 599         if (code->index >= ARRAY_SIZE(rkisp1_isp_formats))
 600                 return -EINVAL;
 601
 602         for (i = 0; i < ARRAY_SIZE(rkisp1_isp_formats); i++) {
 603                 const struct rkisp1_isp_mbus_info *fmt = &rkisp1_isp_formats[i];
 604
 605                 if (fmt->direction & dir)
 606                         pos++;
 607
 608                 if (code->index == pos - 1) {
 609                         code->code = fmt->mbus_code;
 610                         if (fmt->pixel_enc == V4L2_PIXEL_ENC_YUV &&
 611                             dir == RKISP1_ISP_SD_SRC)
 612                                 code->flags =
 613                                         V4L2_SUBDEV_MBUS_CODE_CSC_QUANTIZATION;
 614                         return 0;
 615                 }
 616         }
 617
 618         return -EINVAL;
 619 }
 620
 621 static int rkisp1_isp_enum_frame_size(struct v4l2_subdev *sd,
 622                                       struct v4l2_subdev_state *sd_state,
 623                                       struct v4l2_subdev_frame_size_enum *fse)
 624 {
 625         const struct rkisp1_isp_mbus_info *mbus_info;
 626
 627         if (fse->pad == RKISP1_ISP_PAD_SINK_PARAMS ||
 628             fse->pad == RKISP1_ISP_PAD_SOURCE_STATS)
 629                 return -ENOTTY;
 630
 631         if (fse->index > 0)
 632                 return -EINVAL;
 633
 634         mbus_info = rkisp1_isp_mbus_info_get(fse->code);
 635         if (!mbus_info)
 636                 return -EINVAL;
 637
 638         if (!(mbus_info->direction & RKISP1_ISP_SD_SINK) &&
 639             fse->pad == RKISP1_ISP_PAD_SINK_VIDEO)
 640                 return -EINVAL;
 641
 642         if (!(mbus_info->direction & RKISP1_ISP_SD_SRC) &&
 643             fse->pad == RKISP1_ISP_PAD_SOURCE_VIDEO)
 644                 return -EINVAL;
 645
 646         fse->min_width = RKISP1_ISP_MIN_WIDTH;
 647         fse->max_width = RKISP1_ISP_MAX_WIDTH;
 648         fse->min_height = RKISP1_ISP_MIN_HEIGHT;
 649         fse->max_height = RKISP1_ISP_MAX_HEIGHT;
 650
 651         return 0;
 652 }
 653
 654 static int rkisp1_isp_init_config(struct v4l2_subdev *sd,
 655                                   struct v4l2_subdev_state *sd_state)
 656 {
 657         struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;
 658         struct v4l2_rect *sink_crop, *src_crop;
 659
 660         sink_fmt = v4l2_subdev_get_try_format(sd, sd_state,
 661                                               RKISP1_ISP_PAD_SINK_VIDEO);
 662         sink_fmt->width = RKISP1_DEFAULT_WIDTH;
 663         sink_fmt->height = RKISP1_DEFAULT_HEIGHT;
 664         sink_fmt->field = V4L2_FIELD_NONE;
 665         sink_fmt->code = RKISP1_DEF_SINK_PAD_FMT;
 666
 667         sink_crop = v4l2_subdev_get_try_crop(sd, sd_state,
 668                                              RKISP1_ISP_PAD_SINK_VIDEO);
 669         sink_crop->width = RKISP1_DEFAULT_WIDTH;
 670         sink_crop->height = RKISP1_DEFAULT_HEIGHT;
 671         sink_crop->left = 0;
 672         sink_crop->top = 0;
 673
 674         src_fmt = v4l2_subdev_get_try_format(sd, sd_state,
 675                                              RKISP1_ISP_PAD_SOURCE_VIDEO);
 676         *src_fmt = *sink_fmt;
 677         src_fmt->code = RKISP1_DEF_SRC_PAD_FMT;
 678
 679         src_crop = v4l2_subdev_get_try_crop(sd, sd_state,
 680                                             RKISP1_ISP_PAD_SOURCE_VIDEO);
 681         *src_crop = *sink_crop;
 682
 683         sink_fmt = v4l2_subdev_get_try_format(sd, sd_state,
 684                                               RKISP1_ISP_PAD_SINK_PARAMS);
 685         src_fmt = v4l2_subdev_get_try_format(sd, sd_state,
 686                                              RKISP1_ISP_PAD_SOURCE_STATS);
 687         sink_fmt->width = 0;
 688         sink_fmt->height = 0;
 689         sink_fmt->field = V4L2_FIELD_NONE;
 690         sink_fmt->code = MEDIA_BUS_FMT_METADATA_FIXED;
 691         *src_fmt = *sink_fmt;
 692
 693         return 0;
 694 }
 695
 696 static void rkisp1_isp_set_src_fmt(struct rkisp1_isp *isp,
 697                                    struct v4l2_subdev_state *sd_state,
 698                                    struct v4l2_mbus_framefmt *format,
 699                                    unsigned int which)
 700 {
 701         const struct rkisp1_isp_mbus_info *mbus_info;
 702         struct v4l2_mbus_framefmt *src_fmt;
 703         const struct v4l2_rect *src_crop;
 704
 705         src_fmt = rkisp1_isp_get_pad_fmt(isp, sd_state,
 706                                          RKISP1_ISP_PAD_SOURCE_VIDEO, which);
 707         src_crop = rkisp1_isp_get_pad_crop(isp, sd_state,
 708                                            RKISP1_ISP_PAD_SOURCE_VIDEO, which);
 709
 710         src_fmt->code = format->code;
 711         mbus_info = rkisp1_isp_mbus_info_get(src_fmt->code);
 712         if (!mbus_info || !(mbus_info->direction & RKISP1_ISP_SD_SRC)) {
 713                 src_fmt->code = RKISP1_DEF_SRC_PAD_FMT;
 714                 mbus_info = rkisp1_isp_mbus_info_get(src_fmt->code);
 715         }
 716         if (which == V4L2_SUBDEV_FORMAT_ACTIVE)
 717                 isp->src_fmt = mbus_info;
 718         src_fmt->width  = src_crop->width;
 719         src_fmt->height = src_crop->height;
 720
 721         /*
 722          * The CSC API is used to allow userspace to force full
 723          * quantization on YUV formats.
 724          */
 725         if (format->flags & V4L2_MBUS_FRAMEFMT_SET_CSC &&
 726             format->quantization == V4L2_QUANTIZATION_FULL_RANGE &&
 727             mbus_info->pixel_enc == V4L2_PIXEL_ENC_YUV)
 728                 src_fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
 729         else if (mbus_info->pixel_enc == V4L2_PIXEL_ENC_YUV)
 730                 src_fmt->quantization = V4L2_QUANTIZATION_LIM_RANGE;
 731         else
 732                 src_fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
 733
 734         *format = *src_fmt;
 735 }
 736
 737 static void rkisp1_isp_set_src_crop(struct rkisp1_isp *isp,
 738                                     struct v4l2_subdev_state *sd_state,
 739                                     struct v4l2_rect *r, unsigned int which)
 740 {
 741         struct v4l2_mbus_framefmt *src_fmt;
 742         const struct v4l2_rect *sink_crop;
 743         struct v4l2_rect *src_crop;
 744
 745         src_crop = rkisp1_isp_get_pad_crop(isp, sd_state,
 746                                            RKISP1_ISP_PAD_SOURCE_VIDEO,
 747                                            which);
 748         sink_crop = rkisp1_isp_get_pad_crop(isp, sd_state,
 749                                             RKISP1_ISP_PAD_SINK_VIDEO,
 750                                             which);
 751
 752         src_crop->left = ALIGN(r->left, 2);
 753         src_crop->width = ALIGN(r->width, 2);
 754         src_crop->top = r->top;
 755         src_crop->height = r->height;
 756         rkisp1_sd_adjust_crop_rect(src_crop, sink_crop);
 757
 758         *r = *src_crop;
 759
 760         /* Propagate to out format */
 761         src_fmt = rkisp1_isp_get_pad_fmt(isp, sd_state,
 762                                          RKISP1_ISP_PAD_SOURCE_VIDEO, which);
 763         rkisp1_isp_set_src_fmt(isp, sd_state, src_fmt, which);
 764 }
 765
 766 static void rkisp1_isp_set_sink_crop(struct rkisp1_isp *isp,
 767                                      struct v4l2_subdev_state *sd_state,
 768                                      struct v4l2_rect *r, unsigned int which)
 769 {
 770         struct v4l2_rect *sink_crop, *src_crop;
 771         struct v4l2_mbus_framefmt *sink_fmt;
 772
 773         sink_crop = rkisp1_isp_get_pad_crop(isp, sd_state,
 774                                             RKISP1_ISP_PAD_SINK_VIDEO,
 775                                             which);
 776         sink_fmt = rkisp1_isp_get_pad_fmt(isp, sd_state,
 777                                           RKISP1_ISP_PAD_SINK_VIDEO,
 778                                           which);
 779
 780         sink_crop->left = ALIGN(r->left, 2);
 781         sink_crop->width = ALIGN(r->width, 2);
 782         sink_crop->top = r->top;
 783         sink_crop->height = r->height;
 784         rkisp1_sd_adjust_crop(sink_crop, sink_fmt);
 785
 786         *r = *sink_crop;
 787
 788         /* Propagate to out crop */
 789         src_crop = rkisp1_isp_get_pad_crop(isp, sd_state,
 790                                            RKISP1_ISP_PAD_SOURCE_VIDEO, which);
 791         rkisp1_isp_set_src_crop(isp, sd_state, src_crop, which);
 792 }
 793
 794 static void rkisp1_isp_set_sink_fmt(struct rkisp1_isp *isp,
 795                                     struct v4l2_subdev_state *sd_state,
 796                                     struct v4l2_mbus_framefmt *format,
 797                                     unsigned int which)
 798 {
 799         const struct rkisp1_isp_mbus_info *mbus_info;
 800         struct v4l2_mbus_framefmt *sink_fmt;
 801         struct v4l2_rect *sink_crop;
 802
 803         sink_fmt = rkisp1_isp_get_pad_fmt(isp, sd_state,
 804                                           RKISP1_ISP_PAD_SINK_VIDEO,
 805                                           which);
 806         sink_fmt->code = format->code;
 807         mbus_info = rkisp1_isp_mbus_info_get(sink_fmt->code);
 808         if (!mbus_info || !(mbus_info->direction & RKISP1_ISP_SD_SINK)) {
 809                 sink_fmt->code = RKISP1_DEF_SINK_PAD_FMT;
 810                 mbus_info = rkisp1_isp_mbus_info_get(sink_fmt->code);
 811         }
 812         if (which == V4L2_SUBDEV_FORMAT_ACTIVE)
 813                 isp->sink_fmt = mbus_info;
 814
 815         sink_fmt->width = clamp_t(u32, format->width,
 816                                   RKISP1_ISP_MIN_WIDTH,
 817                                   RKISP1_ISP_MAX_WIDTH);
 818         sink_fmt->height = clamp_t(u32, format->height,
 819                                    RKISP1_ISP_MIN_HEIGHT,
 820                                    RKISP1_ISP_MAX_HEIGHT);
 821
 822         *format = *sink_fmt;
 823
 824         /* Propagate to in crop */
 825         sink_crop = rkisp1_isp_get_pad_crop(isp, sd_state,
 826                                             RKISP1_ISP_PAD_SINK_VIDEO,
 827                                             which);
 828         rkisp1_isp_set_sink_crop(isp, sd_state, sink_crop, which);
 829 }
 830
 831 static int rkisp1_isp_get_fmt(struct v4l2_subdev *sd,
 832                               struct v4l2_subdev_state *sd_state,
 833                               struct v4l2_subdev_format *fmt)
 834 {
 835         struct rkisp1_isp *isp = container_of(sd, struct rkisp1_isp, sd);
 836
 837         mutex_lock(&isp->ops_lock);
 838         fmt->format = *rkisp1_isp_get_pad_fmt(isp, sd_state, fmt->pad,
 839                                               fmt->which);
 840         mutex_unlock(&isp->ops_lock);
 841         return 0;
 842 }
 843
 844 static int rkisp1_isp_set_fmt(struct v4l2_subdev *sd,
 845                               struct v4l2_subdev_state *sd_state,
 846                               struct v4l2_subdev_format *fmt)
 847 {
 848         struct rkisp1_isp *isp = container_of(sd, struct rkisp1_isp, sd);
 849
 850         mutex_lock(&isp->ops_lock);
 851         if (fmt->pad == RKISP1_ISP_PAD_SINK_VIDEO)
 852                 rkisp1_isp_set_sink_fmt(isp, sd_state, &fmt->format,
 853                                         fmt->which);
 854         else if (fmt->pad == RKISP1_ISP_PAD_SOURCE_VIDEO)
 855                 rkisp1_isp_set_src_fmt(isp, sd_state, &fmt->format,
 856                                        fmt->which);
 857         else
 858                 fmt->format = *rkisp1_isp_get_pad_fmt(isp, sd_state, fmt->pad,
 859                                                       fmt->which);
 860
 861         mutex_unlock(&isp->ops_lock);
 862         return 0;
 863 }
 864
 865 static int rkisp1_isp_get_selection(struct v4l2_subdev *sd,
 866                                     struct v4l2_subdev_state *sd_state,
 867                                     struct v4l2_subdev_selection *sel)
 868 {
 869         struct rkisp1_isp *isp = container_of(sd, struct rkisp1_isp, sd);
 870         int ret = 0;
 871
 872         if (sel->pad != RKISP1_ISP_PAD_SOURCE_VIDEO &&
 873             sel->pad != RKISP1_ISP_PAD_SINK_VIDEO)
 874                 return -EINVAL;
 875
 876         mutex_lock(&isp->ops_lock);
 877         switch (sel->target) {
 878         case V4L2_SEL_TGT_CROP_BOUNDS:
 879                 if (sel->pad == RKISP1_ISP_PAD_SINK_VIDEO) {
 880                         struct v4l2_mbus_framefmt *fmt;
 881
 882                         fmt = rkisp1_isp_get_pad_fmt(isp, sd_state, sel->pad,
 883                                                      sel->which);
 884                         sel->r.height = fmt->height;
 885                         sel->r.width = fmt->width;
 886                         sel->r.left = 0;
 887                         sel->r.top = 0;
 888                 } else {
 889                         sel->r = *rkisp1_isp_get_pad_crop(isp, sd_state,
 890                                                           RKISP1_ISP_PAD_SINK_VIDEO,
 891                                                           sel->which);
 892                 }
 893                 break;
 894         case V4L2_SEL_TGT_CROP:
 895                 sel->r = *rkisp1_isp_get_pad_crop(isp, sd_state, sel->pad,
 896                                                   sel->which);
 897                 break;
 898         default:
 899                 ret = -EINVAL;
 900         }
 901         mutex_unlock(&isp->ops_lock);
 902         return ret;
 903 }
 904
 905 static int rkisp1_isp_set_selection(struct v4l2_subdev *sd,
 906                                     struct v4l2_subdev_state *sd_state,
 907                                     struct v4l2_subdev_selection *sel)
 908 {
 909         struct rkisp1_device *rkisp1 =
 910                 container_of(sd->v4l2_dev, struct rkisp1_device, v4l2_dev);
 911         struct rkisp1_isp *isp = container_of(sd, struct rkisp1_isp, sd);
 912         int ret = 0;
 913
 914         if (sel->target != V4L2_SEL_TGT_CROP)
 915                 return -EINVAL;
 916
 917         dev_dbg(rkisp1->dev, "%s: pad: %d sel(%d,%d)/%dx%d\n", __func__,
 918                 sel->pad, sel->r.left, sel->r.top, sel->r.width, sel->r.height);
 919         mutex_lock(&isp->ops_lock);
 920         if (sel->pad == RKISP1_ISP_PAD_SINK_VIDEO)
 921                 rkisp1_isp_set_sink_crop(isp, sd_state, &sel->r, sel->which);
 922         else if (sel->pad == RKISP1_ISP_PAD_SOURCE_VIDEO)
 923                 rkisp1_isp_set_src_crop(isp, sd_state, &sel->r, sel->which);
 924         else
 925                 ret = -EINVAL;
 926
 927         mutex_unlock(&isp->ops_lock);
 928         return ret;
 929 }
 930
 931 static int rkisp1_subdev_link_validate(struct media_link *link)
 932 {
 933         if (link->sink->index == RKISP1_ISP_PAD_SINK_PARAMS)
 934                 return 0;
 935
 936         return v4l2_subdev_link_validate(link);
 937 }
 938
 939 static const struct v4l2_subdev_pad_ops rkisp1_isp_pad_ops = {
 940         .enum_mbus_code = rkisp1_isp_enum_mbus_code,
 941         .enum_frame_size = rkisp1_isp_enum_frame_size,
 942         .get_selection = rkisp1_isp_get_selection,
 943         .set_selection = rkisp1_isp_set_selection,
 944         .init_cfg = rkisp1_isp_init_config,
 945         .get_fmt = rkisp1_isp_get_fmt,
 946         .set_fmt = rkisp1_isp_set_fmt,
 947         .link_validate = v4l2_subdev_link_validate_default,
 948 };
 949
 950 /* ----------------------------------------------------------------------------
 951  * Stream operations
 952  */
 953
 954 static int rkisp1_mipi_csi2_start(struct rkisp1_isp *isp,
 955                                   struct rkisp1_sensor_async *sensor)
 956 {
 957         struct rkisp1_device *rkisp1 =
 958                 container_of(isp->sd.v4l2_dev, struct rkisp1_device, v4l2_dev);
 959         union phy_configure_opts opts;
 960         struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy;
 961         s64 pixel_clock;
 962
 963         if (!sensor->pixel_rate_ctrl) {
 964                 dev_warn(rkisp1->dev, "No pixel rate control in sensor subdev\n");
 965                 return -EPIPE;
 966         }
 967
 968         pixel_clock = v4l2_ctrl_g_ctrl_int64(sensor->pixel_rate_ctrl);
 969         if (!pixel_clock) {
 970                 dev_err(rkisp1->dev, "Invalid pixel rate value\n");
 971                 return -EINVAL;
 972         }
 973
 974         phy_mipi_dphy_get_default_config(pixel_clock, isp->sink_fmt->bus_width,
 975                                          sensor->lanes, cfg);
 976         phy_set_mode(sensor->dphy, PHY_MODE_MIPI_DPHY);
 977         phy_configure(sensor->dphy, &opts);
 978         phy_power_on(sensor->dphy);
 979
 980         return 0;
 981 }
 982
 983 static void rkisp1_mipi_csi2_stop(struct rkisp1_sensor_async *sensor)
 984 {
 985         phy_power_off(sensor->dphy);
 986 }
 987
 988 static int rkisp1_isp_s_stream(struct v4l2_subdev *sd, int enable)
 989 {
 990         struct rkisp1_device *rkisp1 =
 991                 container_of(sd->v4l2_dev, struct rkisp1_device, v4l2_dev);
 992         struct rkisp1_isp *isp = &rkisp1->isp;
 993         struct v4l2_subdev *sensor_sd;
 994         int ret = 0;
 995
 996         if (!enable) {
 997                 rkisp1_isp_stop(rkisp1);
 998                 rkisp1_mipi_csi2_stop(rkisp1->active_sensor);
 999                 return 0;
1000         }
1001
1002         sensor_sd = rkisp1_get_remote_sensor(sd);
1003         if (!sensor_sd) {
1004                 dev_warn(rkisp1->dev, "No link between isp and sensor\n");
1005                 return -ENODEV;
1006         }
1007
1008         rkisp1->active_sensor = container_of(sensor_sd->asd,
1009                                              struct rkisp1_sensor_async, asd);
1010
1011         if (rkisp1->active_sensor->mbus_type != V4L2_MBUS_CSI2_DPHY)
1012                 return -EINVAL;
1013
1014         rkisp1->isp.frame_sequence = -1;
1015         mutex_lock(&isp->ops_lock);
1016         ret = rkisp1_config_cif(rkisp1);
1017         if (ret)
1018                 goto mutex_unlock;
1019
1020         ret = rkisp1_mipi_csi2_start(&rkisp1->isp, rkisp1->active_sensor);
1021         if (ret)
1022                 goto mutex_unlock;
1023
1024         rkisp1_isp_start(rkisp1);
1025
1026 mutex_unlock:
1027         mutex_unlock(&isp->ops_lock);
1028         return ret;
1029 }
1030
1031 static int rkisp1_isp_subs_evt(struct v4l2_subdev *sd, struct v4l2_fh *fh,
1032                                struct v4l2_event_subscription *sub)
1033 {
1034         if (sub->type != V4L2_EVENT_FRAME_SYNC)
1035                 return -EINVAL;
1036
1037         /* V4L2_EVENT_FRAME_SYNC doesn't require an id, so zero should be set */
1038         if (sub->id != 0)
1039                 return -EINVAL;
1040
1041         return v4l2_event_subscribe(fh, sub, 0, NULL);
1042 }
1043
1044 static const struct media_entity_operations rkisp1_isp_media_ops = {
1045         .link_validate = rkisp1_subdev_link_validate,
1046 };
1047
1048 static const struct v4l2_subdev_video_ops rkisp1_isp_video_ops = {
1049         .s_stream = rkisp1_isp_s_stream,
1050 };
1051
1052 static const struct v4l2_subdev_core_ops rkisp1_isp_core_ops = {
1053         .subscribe_event = rkisp1_isp_subs_evt,
1054         .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1055 };
1056
1057 static const struct v4l2_subdev_ops rkisp1_isp_ops = {
1058         .core = &rkisp1_isp_core_ops,
1059         .video = &rkisp1_isp_video_ops,
1060         .pad = &rkisp1_isp_pad_ops,
1061 };
1062
1063 int rkisp1_isp_register(struct rkisp1_device *rkisp1)
1064 {
1065         struct v4l2_subdev_state state = {
1066                 .pads = rkisp1->isp.pad_cfg
1067                 };
1068         struct v4l2_subdev_state state = {
1069                 .pads = &state
1070                 };
1071         struct v4l2_subdev_state state = {
1072                 .pads = &state
1073                 };
1074         struct rkisp1_isp *isp = &rkisp1->isp;
1075         struct media_pad *pads = isp->pads;
1076         struct v4l2_subdev *sd = &isp->sd;
1077         int ret;
1078
1079         v4l2_subdev_init(sd, &rkisp1_isp_ops);
1080         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1081         sd->entity.ops = &rkisp1_isp_media_ops;
1082         sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
1083         sd->owner = THIS_MODULE;
1084         strscpy(sd->name, RKISP1_ISP_DEV_NAME, sizeof(sd->name));
1085
1086         pads[RKISP1_ISP_PAD_SINK_VIDEO].flags = MEDIA_PAD_FL_SINK |
1087                                                 MEDIA_PAD_FL_MUST_CONNECT;
1088         pads[RKISP1_ISP_PAD_SINK_PARAMS].flags = MEDIA_PAD_FL_SINK;
1089         pads[RKISP1_ISP_PAD_SOURCE_VIDEO].flags = MEDIA_PAD_FL_SOURCE;
1090         pads[RKISP1_ISP_PAD_SOURCE_STATS].flags = MEDIA_PAD_FL_SOURCE;
1091
1092         isp->sink_fmt = rkisp1_isp_mbus_info_get(RKISP1_DEF_SINK_PAD_FMT);
1093         isp->src_fmt = rkisp1_isp_mbus_info_get(RKISP1_DEF_SRC_PAD_FMT);
1094
1095         mutex_init(&isp->ops_lock);
1096         ret = media_entity_pads_init(&sd->entity, RKISP1_ISP_PAD_MAX, pads);
1097         if (ret)
1098                 return ret;
1099
1100         ret = v4l2_device_register_subdev(&rkisp1->v4l2_dev, sd);
1101         if (ret) {
1102                 dev_err(rkisp1->dev, "Failed to register isp subdev\n");
1103                 goto err_cleanup_media_entity;
1104         }
1105
1106         rkisp1_isp_init_config(sd, &state);
1107         return 0;
1108
1109 err_cleanup_media_entity:
1110         media_entity_cleanup(&sd->entity);
1111
1112         return ret;
1113 }
1114
1115 void rkisp1_isp_unregister(struct rkisp1_device *rkisp1)
1116 {
1117         struct v4l2_subdev *sd = &rkisp1->isp.sd;
1118
1119         v4l2_device_unregister_subdev(sd);
1120         media_entity_cleanup(&sd->entity);
1121 }
1122
1123 /* ----------------------------------------------------------------------------
1124  * Interrupt handlers
1125  */
1126
1127 void rkisp1_mipi_isr(struct rkisp1_device *rkisp1)
1128 {
1129         u32 val, status;
1130
1131         status = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_MIS);
1132         if (!status)
1133                 return;
1134
1135         rkisp1_write(rkisp1, status, RKISP1_CIF_MIPI_ICR);
1136
1137         /*
1138          * Disable DPHY errctrl interrupt, because this dphy
1139          * erctrl signal is asserted until the next changes
1140          * of line state. This time is may be too long and cpu
1141          * is hold in this interrupt.
1142          */
1143         if (status & RKISP1_CIF_MIPI_ERR_CTRL(0x0f)) {
1144                 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC);
1145                 rkisp1_write(rkisp1, val & ~RKISP1_CIF_MIPI_ERR_CTRL(0x0f),
1146                              RKISP1_CIF_MIPI_IMSC);
1147                 rkisp1->isp.is_dphy_errctrl_disabled = true;
1148         }
1149
1150         /*
1151          * Enable DPHY errctrl interrupt again, if mipi have receive
1152          * the whole frame without any error.
1153          */
1154         if (status == RKISP1_CIF_MIPI_FRAME_END) {
1155                 /*
1156                  * Enable DPHY errctrl interrupt again, if mipi have receive
1157                  * the whole frame without any error.
1158                  */
1159                 if (rkisp1->isp.is_dphy_errctrl_disabled) {
1160                         val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC);
1161                         val |= RKISP1_CIF_MIPI_ERR_CTRL(0x0f);
1162                         rkisp1_write(rkisp1, val, RKISP1_CIF_MIPI_IMSC);
1163                         rkisp1->isp.is_dphy_errctrl_disabled = false;
1164                 }
1165         } else {
1166                 rkisp1->debug.mipi_error++;
1167         }
1168 }
1169
1170 static void rkisp1_isp_queue_event_sof(struct rkisp1_isp *isp)
1171 {
1172         struct v4l2_event event = {
1173                 .type = V4L2_EVENT_FRAME_SYNC,
1174         };
1175         event.u.frame_sync.frame_sequence = isp->frame_sequence;
1176
1177         v4l2_event_queue(isp->sd.devnode, &event);
1178 }
1179
1180 void rkisp1_isp_isr(struct rkisp1_device *rkisp1)
1181 {
1182         u32 status, isp_err;
1183
1184         status = rkisp1_read(rkisp1, RKISP1_CIF_ISP_MIS);
1185         if (!status)
1186                 return;
1187
1188         rkisp1_write(rkisp1, status, RKISP1_CIF_ISP_ICR);
1189
1190         /* Vertical sync signal, starting generating new frame */
1191         if (status & RKISP1_CIF_ISP_V_START) {
1192                 rkisp1->isp.frame_sequence++;
1193                 rkisp1_isp_queue_event_sof(&rkisp1->isp);
1194                 if (status & RKISP1_CIF_ISP_FRAME) {
1195                         WARN_ONCE(1, "irq delay is too long, buffers might not be in sync\n");
1196                         rkisp1->debug.irq_delay++;
1197                 }
1198         }
1199         if (status & RKISP1_CIF_ISP_PIC_SIZE_ERROR) {
1200                 /* Clear pic_size_error */
1201                 isp_err = rkisp1_read(rkisp1, RKISP1_CIF_ISP_ERR);
1202                 if (isp_err & RKISP1_CIF_ISP_ERR_INFORM_SIZE)
1203                         rkisp1->debug.inform_size_error++;
1204                 if (isp_err & RKISP1_CIF_ISP_ERR_IS_SIZE)
1205                         rkisp1->debug.img_stabilization_size_error++;
1206                 if (isp_err & RKISP1_CIF_ISP_ERR_OUTFORM_SIZE)
1207                         rkisp1->debug.outform_size_error++;
1208                 rkisp1_write(rkisp1, isp_err, RKISP1_CIF_ISP_ERR_CLR);
1209         } else if (status & RKISP1_CIF_ISP_DATA_LOSS) {
1210                 /* keep track of data_loss in debugfs */
1211                 rkisp1->debug.data_loss++;
1212         }
1213
1214         if (status & RKISP1_CIF_ISP_FRAME) {
1215                 u32 isp_ris;
1216
1217                 /* New frame from the sensor received */
1218                 isp_ris = rkisp1_read(rkisp1, RKISP1_CIF_ISP_RIS);
1219                 if (isp_ris & RKISP1_STATS_MEAS_MASK)
1220                         rkisp1_stats_isr(&rkisp1->stats, isp_ris);
1221                 /*
1222                  * Then update changed configs. Some of them involve
1223                  * lot of register writes. Do those only one per frame.
1224                  * Do the updates in the order of the processing flow.
1225                  */
1226                 rkisp1_params_isr(rkisp1);
1227         }
1228 }