1 // SPDX-License-Identifier: GPL-2.0
3 * PiSP Front End driver.
4 * Copyright (c) 2021 Raspberry Pi Ltd.
8 #include <linux/bitops.h>
9 #include <linux/delay.h>
10 #include <linux/moduleparam.h>
11 #include <linux/pm_runtime.h>
12 #include <linux/seq_file.h>
14 #include <media/videobuf2-dma-contig.h>
19 #define FE_VERSION 0x000
20 #define FE_CONTROL 0x004
21 #define FE_STATUS 0x008
22 #define FE_FRAME_STATUS 0x00c
23 #define FE_ERROR_STATUS 0x010
24 #define FE_OUTPUT_STATUS 0x014
25 #define FE_INT_EN 0x018
26 #define FE_INT_STATUS 0x01c
29 #define FE_CONTROL_QUEUE BIT(0)
30 #define FE_CONTROL_ABORT BIT(1)
31 #define FE_CONTROL_RESET BIT(2)
32 #define FE_CONTROL_LATCH_REGS BIT(3)
34 /* INT_EN / INT_STATUS */
35 #define FE_INT_EOF BIT(0)
36 #define FE_INT_SOF BIT(1)
37 #define FE_INT_LINES0 BIT(8)
38 #define FE_INT_LINES1 BIT(9)
39 #define FE_INT_STATS BIT(16)
40 #define FE_INT_QREADY BIT(24)
43 #define FE_STATUS_QUEUED BIT(0)
44 #define FE_STATUS_WAITING BIT(1)
45 #define FE_STATUS_ACTIVE BIT(2)
47 #define PISP_FE_CONFIG_BASE_OFFSET 0x0040
49 #define PISP_FE_ENABLE_STATS_CLUSTER \
50 (PISP_FE_ENABLE_STATS_CROP | PISP_FE_ENABLE_DECIMATE | \
51 PISP_FE_ENABLE_BLC | PISP_FE_ENABLE_CDAF_STATS | \
52 PISP_FE_ENABLE_AWB_STATS | PISP_FE_ENABLE_RGBY | \
53 PISP_FE_ENABLE_LSC | PISP_FE_ENABLE_AGC_STATS)
55 #define PISP_FE_ENABLE_OUTPUT_CLUSTER(i) \
56 ((PISP_FE_ENABLE_CROP0 | PISP_FE_ENABLE_DOWNSCALE0 | \
57 PISP_FE_ENABLE_COMPRESS0 | PISP_FE_ENABLE_OUTPUT0) << (4 * (i)))
59 struct pisp_fe_config_param {
61 u32 dirty_flags_extra;
66 static const struct pisp_fe_config_param pisp_fe_config_map[] = {
67 /* *_dirty_flag_extra types */
68 { 0, PISP_FE_DIRTY_GLOBAL, offsetof(struct pisp_fe_config, global),
69 sizeof(struct pisp_fe_global_config) },
70 { 0, PISP_FE_DIRTY_FLOATING, offsetof(struct pisp_fe_config, floating_stats),
71 sizeof(struct pisp_fe_floating_stats_config) },
72 { 0, PISP_FE_DIRTY_OUTPUT_AXI, offsetof(struct pisp_fe_config, output_axi),
73 sizeof(struct pisp_fe_output_axi_config) },
74 /* *_dirty_flag types */
75 { PISP_FE_ENABLE_INPUT, 0, offsetof(struct pisp_fe_config, input),
76 sizeof(struct pisp_fe_input_config) },
77 { PISP_FE_ENABLE_DECOMPRESS, 0, offsetof(struct pisp_fe_config, decompress),
78 sizeof(struct pisp_decompress_config) },
79 { PISP_FE_ENABLE_DECOMPAND, 0, offsetof(struct pisp_fe_config, decompand),
80 sizeof(struct pisp_fe_decompand_config) },
81 { PISP_FE_ENABLE_BLA, 0, offsetof(struct pisp_fe_config, bla),
82 sizeof(struct pisp_bla_config) },
83 { PISP_FE_ENABLE_DPC, 0, offsetof(struct pisp_fe_config, dpc),
84 sizeof(struct pisp_fe_dpc_config) },
85 { PISP_FE_ENABLE_STATS_CROP, 0, offsetof(struct pisp_fe_config, stats_crop),
86 sizeof(struct pisp_fe_crop_config) },
87 { PISP_FE_ENABLE_BLC, 0, offsetof(struct pisp_fe_config, blc),
88 sizeof(struct pisp_bla_config) },
89 { PISP_FE_ENABLE_CDAF_STATS, 0, offsetof(struct pisp_fe_config, cdaf_stats),
90 sizeof(struct pisp_fe_cdaf_stats_config) },
91 { PISP_FE_ENABLE_AWB_STATS, 0, offsetof(struct pisp_fe_config, awb_stats),
92 sizeof(struct pisp_fe_awb_stats_config) },
93 { PISP_FE_ENABLE_RGBY, 0, offsetof(struct pisp_fe_config, rgby),
94 sizeof(struct pisp_fe_rgby_config) },
95 { PISP_FE_ENABLE_LSC, 0, offsetof(struct pisp_fe_config, lsc),
96 sizeof(struct pisp_fe_lsc_config) },
97 { PISP_FE_ENABLE_AGC_STATS, 0, offsetof(struct pisp_fe_config, agc_stats),
98 sizeof(struct pisp_agc_statistics) },
99 { PISP_FE_ENABLE_CROP0, 0, offsetof(struct pisp_fe_config, ch[0].crop),
100 sizeof(struct pisp_fe_crop_config) },
101 { PISP_FE_ENABLE_DOWNSCALE0, 0, offsetof(struct pisp_fe_config, ch[0].downscale),
102 sizeof(struct pisp_fe_downscale_config) },
103 { PISP_FE_ENABLE_COMPRESS0, 0, offsetof(struct pisp_fe_config, ch[0].compress),
104 sizeof(struct pisp_compress_config) },
105 { PISP_FE_ENABLE_OUTPUT0, 0, offsetof(struct pisp_fe_config, ch[0].output),
106 sizeof(struct pisp_fe_output_config) },
107 { PISP_FE_ENABLE_CROP1, 0, offsetof(struct pisp_fe_config, ch[1].crop),
108 sizeof(struct pisp_fe_crop_config) },
109 { PISP_FE_ENABLE_DOWNSCALE1, 0, offsetof(struct pisp_fe_config, ch[1].downscale),
110 sizeof(struct pisp_fe_downscale_config) },
111 { PISP_FE_ENABLE_COMPRESS1, 0, offsetof(struct pisp_fe_config, ch[1].compress),
112 sizeof(struct pisp_compress_config) },
113 { PISP_FE_ENABLE_OUTPUT1, 0, offsetof(struct pisp_fe_config, ch[1].output),
114 sizeof(struct pisp_fe_output_config) },
117 #define pisp_fe_dbg_verbose(fmt, arg...) \
119 if (cfe_debug_verbose) \
120 dev_dbg(fe->v4l2_dev->dev, fmt, ##arg); \
122 #define pisp_fe_dbg(fmt, arg...) dev_dbg(fe->v4l2_dev->dev, fmt, ##arg)
123 #define pisp_fe_info(fmt, arg...) dev_info(fe->v4l2_dev->dev, fmt, ##arg)
124 #define pisp_fe_err(fmt, arg...) dev_err(fe->v4l2_dev->dev, fmt, ##arg)
126 static inline u32 pisp_fe_reg_read(struct pisp_fe_device *fe, u32 offset)
128 return readl(fe->base + offset);
131 static inline void pisp_fe_reg_write(struct pisp_fe_device *fe, u32 offset,
134 writel(val, fe->base + offset);
137 static inline void pisp_fe_reg_write_relaxed(struct pisp_fe_device *fe, u32 offset,
140 writel_relaxed(val, fe->base + offset);
143 static int pisp_regs_show(struct seq_file *s, void *data)
145 struct pisp_fe_device *fe = s->private;
148 ret = pm_runtime_resume_and_get(fe->v4l2_dev->dev);
152 pisp_fe_reg_write(fe, FE_CONTROL, FE_CONTROL_LATCH_REGS);
154 #define DUMP(reg) seq_printf(s, #reg " \t0x%08x\n", pisp_fe_reg_read(fe, reg))
158 DUMP(FE_FRAME_STATUS);
159 DUMP(FE_ERROR_STATUS);
160 DUMP(FE_OUTPUT_STATUS);
165 pm_runtime_put(fe->v4l2_dev->dev);
170 DEFINE_SHOW_ATTRIBUTE(pisp_regs);
172 static void pisp_config_write(struct pisp_fe_device *fe,
173 struct pisp_fe_config *config,
174 unsigned int start_offset,
177 const unsigned int max_offset =
178 offsetof(struct pisp_fe_config, ch[PISP_FE_NUM_OUTPUTS]);
179 unsigned int i, end_offset;
180 u32 *cfg = (u32 *)config;
182 start_offset = min(start_offset, max_offset);
183 end_offset = min(start_offset + size, max_offset);
185 cfg += start_offset >> 2;
186 for (i = start_offset; i < end_offset; i += 4, cfg++)
187 pisp_fe_reg_write_relaxed(fe, PISP_FE_CONFIG_BASE_OFFSET + i,
191 void pisp_fe_isr(struct pisp_fe_device *fe, bool *sof, bool *eof)
193 u32 status, int_status, out_status, frame_status, error_status;
196 pisp_fe_reg_write(fe, FE_CONTROL, FE_CONTROL_LATCH_REGS);
197 status = pisp_fe_reg_read(fe, FE_STATUS);
198 out_status = pisp_fe_reg_read(fe, FE_OUTPUT_STATUS);
199 frame_status = pisp_fe_reg_read(fe, FE_FRAME_STATUS);
200 error_status = pisp_fe_reg_read(fe, FE_ERROR_STATUS);
202 int_status = pisp_fe_reg_read(fe, FE_INT_STATUS);
203 pisp_fe_reg_write(fe, FE_INT_STATUS, int_status);
205 pisp_fe_dbg_verbose("%s: status 0x%x out 0x%x frame 0x%x error 0x%x int 0x%x\n",
206 __func__, status, out_status, frame_status, error_status,
209 /* We do not report interrupts for the input/stream pad. */
210 for (i = 0; i < FE_NUM_PADS - 1; i++) {
211 sof[i] = !!(int_status & FE_INT_SOF);
212 eof[i] = !!(int_status & FE_INT_EOF);
216 static bool pisp_fe_validate_output(struct pisp_fe_config const *cfg,
217 unsigned int c, struct v4l2_format const *f)
221 wbytes = cfg->ch[c].output.format.width;
222 if (cfg->ch[c].output.format.format & PISP_IMAGE_FORMAT_BPS_MASK)
225 /* Check output image dimensions are nonzero and not too big */
226 if (cfg->ch[c].output.format.width < 2 ||
227 cfg->ch[c].output.format.height < 2 ||
228 cfg->ch[c].output.format.height > f->fmt.pix.height ||
229 cfg->ch[c].output.format.stride > f->fmt.pix.bytesperline ||
230 wbytes > f->fmt.pix.bytesperline)
233 /* Check for zero-sized crops, which could cause lockup */
234 if ((cfg->global.enables & PISP_FE_ENABLE_CROP(c)) &&
235 ((cfg->ch[c].crop.offset_x >= (cfg->input.format.width & ~1) ||
236 cfg->ch[c].crop.offset_y >= cfg->input.format.height ||
237 cfg->ch[c].crop.width < 2 ||
238 cfg->ch[c].crop.height < 2)))
241 if ((cfg->global.enables & PISP_FE_ENABLE_DOWNSCALE(c)) &&
242 (cfg->ch[c].downscale.output_width < 2 ||
243 cfg->ch[c].downscale.output_height < 2))
249 static bool pisp_fe_validate_stats(struct pisp_fe_config const *cfg)
251 /* Check for zero-sized crop, which could cause lockup */
252 return (!(cfg->global.enables & PISP_FE_ENABLE_STATS_CROP) ||
253 (cfg->stats_crop.offset_x < (cfg->input.format.width & ~1) &&
254 cfg->stats_crop.offset_y < cfg->input.format.height &&
255 cfg->stats_crop.width >= 2 &&
256 cfg->stats_crop.height >= 2));
259 int pisp_fe_validate_config(struct pisp_fe_device *fe,
260 struct pisp_fe_config *cfg,
261 struct v4l2_format const *f0,
262 struct v4l2_format const *f1)
267 * Check the input is enabled, streaming and has nonzero size;
268 * to avoid cases where the hardware might lock up or try to
269 * read inputs from memory (which this driver doesn't support).
271 if (!(cfg->global.enables & PISP_FE_ENABLE_INPUT) ||
272 cfg->input.streaming != 1 || cfg->input.format.width < 2 ||
273 cfg->input.format.height < 2) {
274 pisp_fe_err("%s: Input config not valid", __func__);
278 for (i = 0; i < PISP_FE_NUM_OUTPUTS; i++) {
279 if (!(cfg->global.enables & PISP_FE_ENABLE_OUTPUT(i))) {
280 if (cfg->global.enables &
281 PISP_FE_ENABLE_OUTPUT_CLUSTER(i)) {
282 pisp_fe_err("%s: Output %u not valid",
289 if (!pisp_fe_validate_output(cfg, i, i ? f1 : f0))
293 if ((cfg->global.enables & PISP_FE_ENABLE_STATS_CLUSTER) &&
294 !pisp_fe_validate_stats(cfg)) {
295 pisp_fe_err("%s: Stats config not valid", __func__);
302 void pisp_fe_submit_job(struct pisp_fe_device *fe, struct vb2_buffer **vb2_bufs,
303 struct pisp_fe_config *cfg)
310 * Check output buffers exist and outputs are correctly configured.
311 * If valid, set the buffer's DMA address; otherwise disable.
313 for (i = 0; i < PISP_FE_NUM_OUTPUTS; i++) {
314 struct vb2_buffer *buf = vb2_bufs[FE_OUTPUT0_PAD + i];
316 if (!(cfg->global.enables & PISP_FE_ENABLE_OUTPUT(i)))
319 addr = vb2_dma_contig_plane_dma_addr(buf, 0);
320 cfg->output_buffer[i].addr_lo = addr & 0xffffffff;
321 cfg->output_buffer[i].addr_hi = addr >> 32;
324 if (vb2_bufs[FE_STATS_PAD]) {
325 addr = vb2_dma_contig_plane_dma_addr(vb2_bufs[FE_STATS_PAD], 0);
326 cfg->stats_buffer.addr_lo = addr & 0xffffffff;
327 cfg->stats_buffer.addr_hi = addr >> 32;
330 /* Set up ILINES interrupts 3/4 of the way down each output */
331 cfg->ch[0].output.ilines =
332 max(0x80u, (3u * cfg->ch[0].output.format.height) >> 2);
333 cfg->ch[1].output.ilines =
334 max(0x80u, (3u * cfg->ch[1].output.format.height) >> 2);
337 * The hardware must have consumed the previous config by now.
338 * This read of status also serves as a memory barrier before the
339 * sequence of relaxed writes which follow.
341 status = pisp_fe_reg_read(fe, FE_STATUS);
342 pisp_fe_dbg_verbose("%s: status = 0x%x\n", __func__, status);
343 if (WARN_ON(status & FE_STATUS_QUEUED))
347 * Unconditionally write buffers, global and input parameters.
348 * Write cropping and output parameters whenever they are enabled.
349 * Selectively write other parameters that have been marked as
350 * changed through the dirty flags.
352 pisp_config_write(fe, cfg, 0,
353 offsetof(struct pisp_fe_config, decompress));
354 cfg->dirty_flags_extra &= ~PISP_FE_DIRTY_GLOBAL;
355 cfg->dirty_flags &= ~PISP_FE_ENABLE_INPUT;
356 cfg->dirty_flags |= (cfg->global.enables &
357 (PISP_FE_ENABLE_STATS_CROP |
358 PISP_FE_ENABLE_OUTPUT_CLUSTER(0) |
359 PISP_FE_ENABLE_OUTPUT_CLUSTER(1)));
360 for (i = 0; i < ARRAY_SIZE(pisp_fe_config_map); i++) {
361 const struct pisp_fe_config_param *p = &pisp_fe_config_map[i];
363 if (cfg->dirty_flags & p->dirty_flags ||
364 cfg->dirty_flags_extra & p->dirty_flags_extra)
365 pisp_config_write(fe, cfg, p->offset, p->size);
368 /* This final non-relaxed write serves as a memory barrier */
369 pisp_fe_reg_write(fe, FE_CONTROL, FE_CONTROL_QUEUE);
372 void pisp_fe_start(struct pisp_fe_device *fe)
374 pisp_fe_reg_write(fe, FE_CONTROL, FE_CONTROL_RESET);
375 pisp_fe_reg_write(fe, FE_INT_STATUS, ~0);
376 pisp_fe_reg_write(fe, FE_INT_EN, FE_INT_EOF | FE_INT_SOF | FE_INT_LINES0 | FE_INT_LINES1);
377 fe->inframe_count = 0;
380 void pisp_fe_stop(struct pisp_fe_device *fe)
382 pisp_fe_reg_write(fe, FE_INT_EN, 0);
383 pisp_fe_reg_write(fe, FE_CONTROL, FE_CONTROL_ABORT);
384 usleep_range(1000, 2000);
385 WARN_ON(pisp_fe_reg_read(fe, FE_STATUS));
386 pisp_fe_reg_write(fe, FE_INT_STATUS, ~0);
389 static struct pisp_fe_device *to_pisp_fe_device(struct v4l2_subdev *subdev)
391 return container_of(subdev, struct pisp_fe_device, sd);
394 static int pisp_fe_init_cfg(struct v4l2_subdev *sd,
395 struct v4l2_subdev_state *state)
397 struct v4l2_mbus_framefmt *fmt;
399 fmt = v4l2_subdev_get_pad_format(sd, state, FE_STREAM_PAD);
400 *fmt = cfe_default_format;
401 fmt->code = MEDIA_BUS_FMT_SRGGB16_1X16;
403 fmt = v4l2_subdev_get_pad_format(sd, state, FE_CONFIG_PAD);
404 *fmt = cfe_default_meta_format;
405 fmt->code = MEDIA_BUS_FMT_PISP_FE_CONFIG;
407 fmt = v4l2_subdev_get_pad_format(sd, state, FE_OUTPUT0_PAD);
408 *fmt = cfe_default_format;
409 fmt->code = MEDIA_BUS_FMT_SRGGB16_1X16;
411 fmt = v4l2_subdev_get_pad_format(sd, state, FE_OUTPUT1_PAD);
412 *fmt = cfe_default_format;
413 fmt->code = MEDIA_BUS_FMT_SRGGB16_1X16;
415 fmt = v4l2_subdev_get_pad_format(sd, state, FE_STATS_PAD);
416 *fmt = cfe_default_meta_format;
417 fmt->code = MEDIA_BUS_FMT_PISP_FE_STATS;
422 static int pisp_fe_pad_set_fmt(struct v4l2_subdev *sd,
423 struct v4l2_subdev_state *state,
424 struct v4l2_subdev_format *format)
426 struct v4l2_mbus_framefmt *fmt;
427 const struct cfe_fmt *cfe_fmt;
429 /* TODO: format propagation to source pads */
430 /* TODO: format validation */
432 switch (format->pad) {
436 cfe_fmt = find_format_by_code(format->format.code);
437 if (!cfe_fmt || !(cfe_fmt->flags & CFE_FORMAT_FLAG_FE_OUT))
438 cfe_fmt = find_format_by_code(MEDIA_BUS_FMT_SBGGR10_1X10);
440 format->format.code = cfe_fmt->code;
445 format->format.code = MEDIA_BUS_FMT_PISP_FE_CONFIG;
449 format->format.code = MEDIA_BUS_FMT_PISP_FE_STATS;
453 fmt = v4l2_subdev_get_pad_format(sd, state, format->pad);
454 *fmt = format->format;
459 static int pisp_fe_link_validate(struct v4l2_subdev *sd,
460 struct media_link *link,
461 struct v4l2_subdev_format *source_fmt,
462 struct v4l2_subdev_format *sink_fmt)
464 struct pisp_fe_device *fe = to_pisp_fe_device(sd);
466 pisp_fe_dbg("%s: link \"%s\":%u -> \"%s\":%u\n", __func__,
467 link->source->entity->name, link->source->index,
468 link->sink->entity->name, link->sink->index);
470 /* The width, height and code must match. */
471 if (source_fmt->format.width != sink_fmt->format.width ||
472 source_fmt->format.width != sink_fmt->format.width ||
473 source_fmt->format.code != sink_fmt->format.code) {
474 pisp_fe_err("%s: format does not match (source %ux%u 0x%x, sink %ux%u 0x%x)\n",
476 source_fmt->format.width,
477 source_fmt->format.height,
478 source_fmt->format.code,
479 sink_fmt->format.width,
480 sink_fmt->format.height,
481 sink_fmt->format.code);
488 static const struct v4l2_subdev_pad_ops pisp_fe_subdev_pad_ops = {
489 .init_cfg = pisp_fe_init_cfg,
490 .get_fmt = v4l2_subdev_get_fmt,
491 .set_fmt = pisp_fe_pad_set_fmt,
492 .link_validate = pisp_fe_link_validate,
495 static const struct media_entity_operations pisp_fe_entity_ops = {
496 .link_validate = v4l2_subdev_link_validate,
499 static const struct v4l2_subdev_ops pisp_fe_subdev_ops = {
500 .pad = &pisp_fe_subdev_pad_ops,
503 int pisp_fe_init(struct pisp_fe_device *fe, struct dentry *debugfs)
507 debugfs_create_file("pisp_regs", 0444, debugfs, fe, &pisp_regs_fops);
509 fe->hw_revision = pisp_fe_reg_read(fe, FE_VERSION);
510 pisp_fe_info("PiSP FE HW v%u.%u\n",
511 (fe->hw_revision >> 24) & 0xff,
512 (fe->hw_revision >> 20) & 0x0f);
514 fe->pad[FE_STREAM_PAD].flags =
515 MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
516 fe->pad[FE_CONFIG_PAD].flags = MEDIA_PAD_FL_SINK;
517 fe->pad[FE_OUTPUT0_PAD].flags = MEDIA_PAD_FL_SOURCE;
518 fe->pad[FE_OUTPUT1_PAD].flags = MEDIA_PAD_FL_SOURCE;
519 fe->pad[FE_STATS_PAD].flags = MEDIA_PAD_FL_SOURCE;
521 ret = media_entity_pads_init(&fe->sd.entity, ARRAY_SIZE(fe->pad),
526 /* Initialize subdev */
527 v4l2_subdev_init(&fe->sd, &pisp_fe_subdev_ops);
528 fe->sd.entity.function = MEDIA_ENT_F_PROC_VIDEO_SCALER;
529 fe->sd.entity.ops = &pisp_fe_entity_ops;
530 fe->sd.entity.name = "pisp-fe";
531 fe->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
532 fe->sd.owner = THIS_MODULE;
533 snprintf(fe->sd.name, sizeof(fe->sd.name), "pisp-fe");
535 ret = v4l2_subdev_init_finalize(&fe->sd);
537 goto err_entity_cleanup;
539 ret = v4l2_device_register_subdev(fe->v4l2_dev, &fe->sd);
541 pisp_fe_err("Failed register pisp fe subdev (%d)\n", ret);
542 goto err_subdev_cleanup;
545 /* Must be in IDLE state (STATUS == 0) here. */
546 WARN_ON(pisp_fe_reg_read(fe, FE_STATUS));
551 v4l2_subdev_cleanup(&fe->sd);
553 media_entity_cleanup(&fe->sd.entity);
558 void pisp_fe_uninit(struct pisp_fe_device *fe)
560 v4l2_device_unregister_subdev(&fe->sd);
561 v4l2_subdev_cleanup(&fe->sd);
562 media_entity_cleanup(&fe->sd.entity);