drivers/media/platform/raspberrypi/rp1_cfe/csi2.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * RP1 CSI-2 Driver
   4  *
   5  * Copyright (C) 2021 - Raspberry Pi Ltd.
   6  *
   7  */
   8
   9 #include <linux/delay.h>
  10 #include <linux/moduleparam.h>
  11 #include <linux/pm_runtime.h>
  12 #include <linux/seq_file.h>
  13
  14 #include <media/videobuf2-dma-contig.h>
  15
  16 #include "csi2.h"
  17 #include "cfe.h"
  18
  19 #define csi2_dbg_verbose(fmt, arg...)                             \
  20         do {                                                      \
  21                 if (cfe_debug_verbose)                            \
  22                         dev_dbg(csi2->v4l2_dev->dev, fmt, ##arg); \
  23         } while (0)
  24 #define csi2_dbg(fmt, arg...) dev_dbg(csi2->v4l2_dev->dev, fmt, ##arg)
  25 #define csi2_info(fmt, arg...) dev_info(csi2->v4l2_dev->dev, fmt, ##arg)
  26 #define csi2_err(fmt, arg...) dev_err(csi2->v4l2_dev->dev, fmt, ##arg)
  27
  28 /* CSI2-DMA registers */
  29 #define CSI2_STATUS             0x000
  30 #define CSI2_QOS                0x004
  31 #define CSI2_DISCARDS_OVERFLOW  0x008
  32 #define CSI2_DISCARDS_INACTIVE  0x00c
  33 #define CSI2_DISCARDS_UNMATCHED 0x010
  34 #define CSI2_DISCARDS_LEN_LIMIT 0x014
  35 #define CSI2_LLEV_PANICS        0x018
  36 #define CSI2_ULEV_PANICS        0x01c
  37 #define CSI2_IRQ_MASK           0x020
  38 #define CSI2_CTRL               0x024
  39 #define CSI2_CH_CTRL(x)         ((x) * 0x40 + 0x28)
  40 #define CSI2_CH_ADDR0(x)        ((x) * 0x40 + 0x2c)
  41 #define CSI2_CH_ADDR1(x)        ((x) * 0x40 + 0x3c)
  42 #define CSI2_CH_STRIDE(x)       ((x) * 0x40 + 0x30)
  43 #define CSI2_CH_LENGTH(x)       ((x) * 0x40 + 0x34)
  44 #define CSI2_CH_DEBUG(x)        ((x) * 0x40 + 0x38)
  45 #define CSI2_CH_FRAME_SIZE(x)   ((x) * 0x40 + 0x40)
  46 #define CSI2_CH_COMP_CTRL(x)    ((x) * 0x40 + 0x44)
  47 #define CSI2_CH_FE_FRAME_ID(x)  ((x) * 0x40 + 0x48)
  48
  49 /* CSI2_STATUS */
  50 #define IRQ_FS(x)               (BIT(0) << (x))
  51 #define IRQ_FE(x)               (BIT(4) << (x))
  52 #define IRQ_FE_ACK(x)           (BIT(8) << (x))
  53 #define IRQ_LE(x)               (BIT(12) << (x))
  54 #define IRQ_LE_ACK(x)           (BIT(16) << (x))
  55 #define IRQ_CH_MASK(x)          (IRQ_FS(x) | IRQ_FE(x) | IRQ_FE_ACK(x) | IRQ_LE(x) | IRQ_LE_ACK(x))
  56 #define IRQ_OVERFLOW            BIT(20)
  57 #define IRQ_DISCARD_OVERFLOW    BIT(21)
  58 #define IRQ_DISCARD_LEN_LIMIT   BIT(22)
  59 #define IRQ_DISCARD_UNMATCHED   BIT(23)
  60 #define IRQ_DISCARD_INACTIVE    BIT(24)
  61
  62 /* CSI2_CTRL */
  63 #define EOP_IS_EOL              BIT(0)
  64
  65 /* CSI2_CH_CTRL */
  66 #define DMA_EN                  BIT(0)
  67 #define FORCE                   BIT(3)
  68 #define AUTO_ARM                BIT(4)
  69 #define IRQ_EN_FS               BIT(13)
  70 #define IRQ_EN_FE               BIT(14)
  71 #define IRQ_EN_FE_ACK           BIT(15)
  72 #define IRQ_EN_LE               BIT(16)
  73 #define IRQ_EN_LE_ACK           BIT(17)
  74 #define FLUSH_FE                BIT(28)
  75 #define PACK_LINE               BIT(29)
  76 #define PACK_BYTES              BIT(30)
  77 #define CH_MODE_MASK            GENMASK(2, 1)
  78 #define VC_MASK                 GENMASK(6, 5)
  79 #define DT_MASK                 GENMASK(12, 7)
  80 #define LC_MASK                 GENMASK(27, 18)
  81
  82 /* CHx_COMPRESSION_CONTROL */
  83 #define COMP_OFFSET_MASK        GENMASK(15, 0)
  84 #define COMP_SHIFT_MASK         GENMASK(19, 16)
  85 #define COMP_MODE_MASK          GENMASK(25, 24)
  86
  87 static inline u32 csi2_reg_read(struct csi2_device *csi2, u32 offset)
  88 {
  89         return readl(csi2->base + offset);
  90 }
  91
  92 static inline void csi2_reg_write(struct csi2_device *csi2, u32 offset, u32 val)
  93 {
  94         writel(val, csi2->base + offset);
  95 }
  96
  97 static inline void set_field(u32 *valp, u32 field, u32 mask)
  98 {
  99         u32 val = *valp;
 100
 101         val &= ~mask;
 102         val |= (field << __ffs(mask)) & mask;
 103         *valp = val;
 104 }
 105
 106 static int csi2_regs_show(struct seq_file *s, void *data)
 107 {
 108         struct csi2_device *csi2 = s->private;
 109         unsigned int i;
 110         int ret;
 111
 112         ret = pm_runtime_resume_and_get(csi2->v4l2_dev->dev);
 113         if (ret)
 114                 return ret;
 115
 116 #define DUMP(reg) seq_printf(s, #reg " \t0x%08x\n", csi2_reg_read(csi2, reg))
 117 #define DUMP_CH(idx, reg) seq_printf(s, #reg "(%u) \t0x%08x\n", idx, csi2_reg_read(csi2, reg(idx)))
 118
 119         DUMP(CSI2_STATUS);
 120         DUMP(CSI2_DISCARDS_OVERFLOW);
 121         DUMP(CSI2_DISCARDS_INACTIVE);
 122         DUMP(CSI2_DISCARDS_UNMATCHED);
 123         DUMP(CSI2_DISCARDS_LEN_LIMIT);
 124         DUMP(CSI2_LLEV_PANICS);
 125         DUMP(CSI2_ULEV_PANICS);
 126         DUMP(CSI2_IRQ_MASK);
 127         DUMP(CSI2_CTRL);
 128
 129         for (i = 0; i < CSI2_NUM_CHANNELS; ++i) {
 130                 DUMP_CH(i, CSI2_CH_CTRL);
 131                 DUMP_CH(i, CSI2_CH_ADDR0);
 132                 DUMP_CH(i, CSI2_CH_ADDR1);
 133                 DUMP_CH(i, CSI2_CH_STRIDE);
 134                 DUMP_CH(i, CSI2_CH_LENGTH);
 135                 DUMP_CH(i, CSI2_CH_DEBUG);
 136                 DUMP_CH(i, CSI2_CH_FRAME_SIZE);
 137                 DUMP_CH(i, CSI2_CH_COMP_CTRL);
 138                 DUMP_CH(i, CSI2_CH_FE_FRAME_ID);
 139         }
 140
 141 #undef DUMP
 142 #undef DUMP_CH
 143
 144         pm_runtime_put(csi2->v4l2_dev->dev);
 145
 146         return 0;
 147 }
 148
 149 DEFINE_SHOW_ATTRIBUTE(csi2_regs);
 150
 151 void csi2_isr(struct csi2_device *csi2, bool *sof, bool *eof, bool *lci)
 152 {
 153         unsigned int i;
 154         u32 status;
 155
 156         status = csi2_reg_read(csi2, CSI2_STATUS);
 157         csi2_dbg_verbose("ISR: STA: 0x%x\n", status);
 158
 159         /* Write value back to clear the interrupts */
 160         csi2_reg_write(csi2, CSI2_STATUS, status);
 161
 162         for (i = 0; i < CSI2_NUM_CHANNELS; i++) {
 163                 u32 dbg;
 164
 165                 if ((status & IRQ_CH_MASK(i)) == 0)
 166                         continue;
 167
 168                 dbg = csi2_reg_read(csi2, CSI2_CH_DEBUG(i));
 169
 170                 csi2_dbg_verbose("ISR: [%u], %s%s%s%s%s frame: %u line: %u\n",
 171                                  i, (status & IRQ_FS(i)) ? "FS " : "",
 172                                  (status & IRQ_FE(i)) ? "FE " : "",
 173                                  (status & IRQ_FE_ACK(i)) ? "FE_ACK " : "",
 174                                  (status & IRQ_LE(i)) ? "LE " : "",
 175                                  (status & IRQ_LE_ACK(i)) ? "LE_ACK " : "",
 176                                  dbg >> 16,
 177                                  csi2->num_lines[i] ?
 178                                          ((dbg & 0xffff) % csi2->num_lines[i]) :
 179                                          0);
 180
 181                 sof[i] = !!(status & IRQ_FS(i));
 182                 eof[i] = !!(status & IRQ_FE_ACK(i));
 183                 lci[i] = !!(status & IRQ_LE_ACK(i));
 184         }
 185 }
 186
 187 void csi2_set_buffer(struct csi2_device *csi2, unsigned int channel,
 188                      dma_addr_t dmaaddr, unsigned int stride, unsigned int size)
 189 {
 190         u64 addr = dmaaddr;
 191         /*
 192          * ADDRESS0 must be written last as it triggers the double buffering
 193          * mechanism for all buffer registers within the hardware.
 194          */
 195         addr >>= 4;
 196         csi2_reg_write(csi2, CSI2_CH_LENGTH(channel), size >> 4);
 197         csi2_reg_write(csi2, CSI2_CH_STRIDE(channel), stride >> 4);
 198         csi2_reg_write(csi2, CSI2_CH_ADDR1(channel), addr >> 32);
 199         csi2_reg_write(csi2, CSI2_CH_ADDR0(channel), addr & 0xffffffff);
 200 }
 201
 202 void csi2_set_compression(struct csi2_device *csi2, unsigned int channel,
 203                           enum csi2_compression_mode mode, unsigned int shift,
 204                           unsigned int offset)
 205 {
 206         u32 compression = 0;
 207
 208         set_field(&compression, COMP_OFFSET_MASK, offset);
 209         set_field(&compression, COMP_SHIFT_MASK, shift);
 210         set_field(&compression, COMP_MODE_MASK, mode);
 211         csi2_reg_write(csi2, CSI2_CH_COMP_CTRL(channel), compression);
 212 }
 213
 214 void csi2_start_channel(struct csi2_device *csi2, unsigned int channel,
 215                         u16 dt, enum csi2_mode mode, bool auto_arm,
 216                         bool pack_bytes, unsigned int width,
 217                         unsigned int height)
 218 {
 219         u32 ctrl;
 220
 221         csi2_dbg("%s [%u]\n", __func__, channel);
 222
 223         /*
 224          * Disable the channel, but ensure N != 0!  Otherwise we end up with a
 225          * spurious LE + LE_ACK interrupt when re-enabling the channel.
 226          */
 227         csi2_reg_write(csi2, CSI2_CH_CTRL(channel), 0x100 << __ffs(LC_MASK));
 228         csi2_reg_write(csi2, CSI2_CH_DEBUG(channel), 0);
 229         csi2_reg_write(csi2, CSI2_STATUS, IRQ_CH_MASK(channel));
 230
 231         /* Enable channel and FS/FE/LE interrupts. */
 232         ctrl = DMA_EN | IRQ_EN_FS | IRQ_EN_FE_ACK | IRQ_EN_LE_ACK | PACK_LINE;
 233         /* PACK_BYTES ensures no striding for embedded data. */
 234         if (pack_bytes)
 235                 ctrl |= PACK_BYTES;
 236
 237         if (auto_arm)
 238                 ctrl |= AUTO_ARM;
 239
 240         if (width && height) {
 241                 int line_int_freq = height >> 2;
 242
 243                 line_int_freq = min(max(0x80, line_int_freq), 0x3ff);
 244                 set_field(&ctrl, line_int_freq, LC_MASK);
 245                 set_field(&ctrl, mode, CH_MODE_MASK);
 246                 csi2_reg_write(csi2, CSI2_CH_FRAME_SIZE(channel),
 247                                (height << 16) | width);
 248         } else {
 249                 /*
 250                  * Do not disable line interrupts for the embedded data channel,
 251                  * set it to the maximum value.  This avoids spamming the ISR
 252                  * with spurious line interrupts.
 253                  */
 254                 set_field(&ctrl, 0x3ff, LC_MASK);
 255                 set_field(&ctrl, 0x00, CH_MODE_MASK);
 256                 csi2_reg_write(csi2, CSI2_CH_FRAME_SIZE(channel), 0);
 257         }
 258
 259         set_field(&ctrl, dt, DT_MASK);
 260         csi2_reg_write(csi2, CSI2_CH_CTRL(channel), ctrl);
 261         csi2->num_lines[channel] = height;
 262 }
 263
 264 void csi2_stop_channel(struct csi2_device *csi2, unsigned int channel)
 265 {
 266         csi2_dbg("%s [%u]\n", __func__, channel);
 267
 268         /* Channel disable.  Use FORCE to allow stopping mid-frame. */
 269         csi2_reg_write(csi2, CSI2_CH_CTRL(channel),
 270                        (0x100 << __ffs(LC_MASK)) | FORCE);
 271         /* Latch the above change by writing to the ADDR0 register. */
 272         csi2_reg_write(csi2, CSI2_CH_ADDR0(channel), 0);
 273         /* Write this again, the HW needs it! */
 274         csi2_reg_write(csi2, CSI2_CH_ADDR0(channel), 0);
 275 }
 276
 277 void csi2_open_rx(struct csi2_device *csi2)
 278 {
 279         dphy_start(&csi2->dphy);
 280
 281         csi2_reg_write(csi2, CSI2_CTRL,
 282                        csi2->multipacket_line ? 0 : EOP_IS_EOL);
 283 }
 284
 285 void csi2_close_rx(struct csi2_device *csi2)
 286 {
 287         dphy_stop(&csi2->dphy);
 288 }
 289
 290 static struct csi2_device *to_csi2_device(struct v4l2_subdev *subdev)
 291 {
 292         return container_of(subdev, struct csi2_device, sd);
 293 }
 294
 295 static int csi2_init_cfg(struct v4l2_subdev *sd,
 296                          struct v4l2_subdev_state *state)
 297 {
 298         struct v4l2_mbus_framefmt *fmt;
 299
 300         for (unsigned int i = 0; i < CSI2_NUM_CHANNELS; ++i) {
 301                 const struct v4l2_mbus_framefmt *def_fmt;
 302
 303                 /* CSI2_CH1_EMBEDDED */
 304                 if (i == 1)
 305                         def_fmt = &cfe_default_meta_format;
 306                 else
 307                         def_fmt = &cfe_default_format;
 308
 309                 fmt = v4l2_subdev_get_pad_format(sd, state, i);
 310                 *fmt = *def_fmt;
 311
 312                 fmt = v4l2_subdev_get_pad_format(sd, state, i + CSI2_NUM_CHANNELS);
 313                 *fmt = *def_fmt;
 314         }
 315
 316         return 0;
 317 }
 318
 319 static int csi2_pad_set_fmt(struct v4l2_subdev *sd,
 320                             struct v4l2_subdev_state *state,
 321                             struct v4l2_subdev_format *format)
 322 {
 323         struct v4l2_mbus_framefmt *fmt;
 324         const struct cfe_fmt *cfe_fmt;
 325
 326         /* TODO: format validation */
 327
 328         cfe_fmt = find_format_by_code(format->format.code);
 329         if (!cfe_fmt)
 330                 cfe_fmt = find_format_by_code(MEDIA_BUS_FMT_SBGGR10_1X10);
 331
 332         format->format.code = cfe_fmt->code;
 333
 334         fmt = v4l2_subdev_get_pad_format(sd, state, format->pad);
 335         *fmt = format->format;
 336
 337         if (format->pad < CSI2_NUM_CHANNELS) {
 338                 /* Propagate to the source pad */
 339                 fmt = v4l2_subdev_get_pad_format(sd, state,
 340                                                  format->pad + CSI2_NUM_CHANNELS);
 341                 *fmt = format->format;
 342         }
 343
 344         return 0;
 345 }
 346
 347 static int csi2_link_validate(struct v4l2_subdev *sd, struct media_link *link,
 348                               struct v4l2_subdev_format *source_fmt,
 349                               struct v4l2_subdev_format *sink_fmt)
 350 {
 351         struct csi2_device *csi2 = to_csi2_device(sd);
 352
 353         csi2_dbg("%s: link \"%s\":%u -> \"%s\":%u\n", __func__,
 354                  link->source->entity->name, link->source->index,
 355                  link->sink->entity->name, link->sink->index);
 356
 357         if ((link->source->entity == &csi2->sd.entity &&
 358              link->source->index == 1) ||
 359             (link->sink->entity == &csi2->sd.entity &&
 360              link->sink->index == 1)) {
 361                 csi2_dbg("Ignore metadata pad for now\n");
 362                 return 0;
 363         }
 364
 365         /* The width, height and code must match. */
 366         if (source_fmt->format.width != sink_fmt->format.width ||
 367             source_fmt->format.width != sink_fmt->format.width ||
 368             source_fmt->format.code != sink_fmt->format.code) {
 369                 csi2_err("%s: format does not match (source %ux%u 0x%x, sink %ux%u 0x%x)\n",
 370                          __func__,
 371                          source_fmt->format.width, source_fmt->format.height,
 372                          source_fmt->format.code,
 373                          sink_fmt->format.width, sink_fmt->format.height,
 374                          sink_fmt->format.code);
 375                 return -EPIPE;
 376         }
 377
 378         return 0;
 379 }
 380
 381 static const struct v4l2_subdev_pad_ops csi2_subdev_pad_ops = {
 382         .init_cfg = csi2_init_cfg,
 383         .get_fmt = v4l2_subdev_get_fmt,
 384         .set_fmt = csi2_pad_set_fmt,
 385         .link_validate = csi2_link_validate,
 386 };
 387
 388 static const struct media_entity_operations csi2_entity_ops = {
 389         .link_validate = v4l2_subdev_link_validate,
 390 };
 391
 392 static const struct v4l2_subdev_ops csi2_subdev_ops = {
 393         .pad = &csi2_subdev_pad_ops,
 394 };
 395
 396 int csi2_init(struct csi2_device *csi2, struct dentry *debugfs)
 397 {
 398         unsigned int i, ret;
 399
 400         csi2->dphy.dev = csi2->v4l2_dev->dev;
 401         dphy_probe(&csi2->dphy);
 402
 403         debugfs_create_file("csi2_regs", 0444, debugfs, csi2, &csi2_regs_fops);
 404
 405         for (i = 0; i < CSI2_NUM_CHANNELS * 2; i++)
 406                 csi2->pad[i].flags = i < CSI2_NUM_CHANNELS ?
 407                                      MEDIA_PAD_FL_SINK : MEDIA_PAD_FL_SOURCE;
 408
 409         ret = media_entity_pads_init(&csi2->sd.entity, ARRAY_SIZE(csi2->pad),
 410                                      csi2->pad);
 411         if (ret)
 412                 return ret;
 413
 414         /* Initialize subdev */
 415         v4l2_subdev_init(&csi2->sd, &csi2_subdev_ops);
 416         csi2->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
 417         csi2->sd.entity.ops = &csi2_entity_ops;
 418         csi2->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
 419         csi2->sd.owner = THIS_MODULE;
 420         snprintf(csi2->sd.name, sizeof(csi2->sd.name), "csi2");
 421
 422         ret = v4l2_subdev_init_finalize(&csi2->sd);
 423         if (ret)
 424                 goto err_entity_cleanup;
 425
 426         ret = v4l2_device_register_subdev(csi2->v4l2_dev, &csi2->sd);
 427         if (ret) {
 428                 csi2_err("Failed register csi2 subdev (%d)\n", ret);
 429                 goto err_subdev_cleanup;
 430         }
 431
 432         return 0;
 433
 434 err_subdev_cleanup:
 435         v4l2_subdev_cleanup(&csi2->sd);
 436 err_entity_cleanup:
 437         media_entity_cleanup(&csi2->sd.entity);
 438
 439         return ret;
 440 }
 441
 442 void csi2_uninit(struct csi2_device *csi2)
 443 {
 444         v4l2_device_unregister_subdev(&csi2->sd);
 445         v4l2_subdev_cleanup(&csi2->sd);
 446         media_entity_cleanup(&csi2->sd.entity);
 447 }