1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Qualcomm MSM Camera Subsystem - CSIPHY Module
7 * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
8 * Copyright (C) 2016-2018 Linaro Ltd.
10 #ifndef QC_MSM_CAMSS_CSIPHY_H
11 #define QC_MSM_CAMSS_CSIPHY_H
13 #include <linux/clk.h>
14 #include <linux/interrupt.h>
15 #include <media/media-entity.h>
16 #include <media/v4l2-device.h>
17 #include <media/v4l2-mediabus.h>
18 #include <media/v4l2-subdev.h>
20 #define MSM_CSIPHY_PAD_SINK 0
21 #define MSM_CSIPHY_PAD_SRC 1
22 #define MSM_CSIPHY_PADS_NUM 2
29 struct csiphy_lanes_cfg {
31 struct csiphy_lane *data;
32 struct csiphy_lane clk;
35 struct csiphy_csi2_cfg {
36 struct csiphy_lanes_cfg lane_cfg;
39 struct csiphy_config {
42 struct csiphy_csi2_cfg *csi2;
47 struct csiphy_hw_ops {
49 * csiphy_get_lane_mask - Calculate CSI2 lane mask configuration parameter
50 * @lane_cfg - CSI2 lane configuration
54 u8 (*get_lane_mask)(struct csiphy_lanes_cfg *lane_cfg);
55 void (*hw_version_read)(struct csiphy_device *csiphy,
57 void (*reset)(struct csiphy_device *csiphy);
58 void (*lanes_enable)(struct csiphy_device *csiphy,
59 struct csiphy_config *cfg,
60 s64 link_freq, u8 lane_mask);
61 void (*lanes_disable)(struct csiphy_device *csiphy,
62 struct csiphy_config *cfg);
63 irqreturn_t (*isr)(int irq, void *dev);
66 struct csiphy_device {
69 struct v4l2_subdev subdev;
70 struct media_pad pads[MSM_CSIPHY_PADS_NUM];
72 void __iomem *base_clk_mux;
75 struct camss_clock *clock;
79 struct csiphy_config cfg;
80 struct v4l2_mbus_framefmt fmt[MSM_CSIPHY_PADS_NUM];
81 const struct csiphy_hw_ops *ops;
82 const struct csiphy_format *formats;
83 unsigned int nformats;
88 int msm_csiphy_subdev_init(struct camss *camss,
89 struct csiphy_device *csiphy,
90 const struct resources *res, u8 id);
92 int msm_csiphy_register_entity(struct csiphy_device *csiphy,
93 struct v4l2_device *v4l2_dev);
95 void msm_csiphy_unregister_entity(struct csiphy_device *csiphy);
97 extern const struct csiphy_hw_ops csiphy_ops_2ph_1_0;
98 extern const struct csiphy_hw_ops csiphy_ops_3ph_1_0;
100 #endif /* QC_MSM_CAMSS_CSIPHY_H */