1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2023 MediaTek Inc.
4 * Author: Yunfei Dong <yunfei.dong@mediatek.com>
7 #ifndef _MTK_VCODEC_DEC_DRV_H_
8 #define _MTK_VCODEC_DEC_DRV_H_
10 #include "mtk_vcodec_cmn_drv.h"
11 #include "mtk_vcodec_dbgfs.h"
12 #include "mtk_vcodec_fw_priv.h"
13 #include "mtk_vcodec_util.h"
14 #include "vdec_msg_queue.h"
16 #define MTK_VCODEC_DEC_NAME "mtk-vcodec-dec"
18 #define IS_VDEC_LAT_ARCH(hw_arch) ((hw_arch) >= MTK_VDEC_LAT_SINGLE_CORE)
19 #define IS_VDEC_INNER_RACING(capability) ((capability) & MTK_VCODEC_INNER_RACING)
22 * struct mtk_vdec_format_types - Structure used to get supported
23 * format types according to decoder capability
25 enum mtk_vdec_format_types {
26 MTK_VDEC_FORMAT_MM21 = 0x20,
27 MTK_VDEC_FORMAT_MT21C = 0x40,
28 MTK_VDEC_FORMAT_H264_SLICE = 0x100,
29 MTK_VDEC_FORMAT_VP8_FRAME = 0x200,
30 MTK_VDEC_FORMAT_VP9_FRAME = 0x400,
31 MTK_VDEC_FORMAT_AV1_FRAME = 0x800,
32 MTK_VDEC_FORMAT_HEVC_FRAME = 0x1000,
33 MTK_VCODEC_INNER_RACING = 0x20000,
37 * enum mtk_vdec_hw_count - Supported hardware count
39 enum mtk_vdec_hw_count {
42 MTK_VDEC_ONE_LAT_ONE_CORE,
43 MTK_VDEC_MAX_HW_COUNT,
47 * enum mtk_vdec_hw_arch - Used to separate different hardware architecture
49 enum mtk_vdec_hw_arch {
50 MTK_VDEC_PURE_SINGLE_CORE,
51 MTK_VDEC_LAT_SINGLE_CORE,
55 * struct vdec_pic_info - picture size information
56 * @pic_w: picture width
57 * @pic_h: picture height
58 * @buf_w: picture buffer width (64 aligned up from pic_w)
59 * @buf_h: picture buffer heiht (64 aligned up from pic_h)
60 * @fb_sz: bitstream size of each plane
61 * E.g. suppose picture size is 176x144,
62 * buffer size will be aligned to 176x160.
63 * @cap_fourcc: fourcc number(may changed when resolution change)
64 * @reserved: align struct to 64-bit in order to adjust 32-bit and 64-bit os.
66 struct vdec_pic_info {
71 unsigned int fb_sz[VIDEO_MAX_PLANES];
72 unsigned int cap_fourcc;
73 unsigned int reserved;
77 * struct mtk_vcodec_dec_pdata - compatible data for each IC
78 * @init_vdec_params: init vdec params
79 * @ctrls_setup: init vcodec dec ctrls
80 * @worker: worker to start a decode job
81 * @flush_decoder: function that flushes the decoder
82 * @get_cap_buffer: get capture buffer from capture queue
83 * @cap_to_disp: put capture buffer to disp list for lat and core arch
84 * @vdec_vb2_ops: struct vb2_ops
86 * @vdec_formats: supported video decoder formats
87 * @num_formats: count of video decoder formats
88 * @default_out_fmt: default output buffer format
89 * @default_cap_fmt: default capture buffer format
91 * @hw_arch: hardware arch is used to separate pure_sin_core and lat_sin_core
93 * @is_subdev_supported: whether support parent-node architecture(subdev)
94 * @uses_stateless_api: whether the decoder uses the stateless API with requests
96 struct mtk_vcodec_dec_pdata {
97 void (*init_vdec_params)(struct mtk_vcodec_dec_ctx *ctx);
98 int (*ctrls_setup)(struct mtk_vcodec_dec_ctx *ctx);
99 void (*worker)(struct work_struct *work);
100 int (*flush_decoder)(struct mtk_vcodec_dec_ctx *ctx);
101 struct vdec_fb *(*get_cap_buffer)(struct mtk_vcodec_dec_ctx *ctx);
102 void (*cap_to_disp)(struct mtk_vcodec_dec_ctx *ctx, int error,
103 struct media_request *src_buf_req);
105 const struct vb2_ops *vdec_vb2_ops;
107 const struct mtk_video_fmt *vdec_formats;
108 const int *num_formats;
109 const struct mtk_video_fmt *default_out_fmt;
110 const struct mtk_video_fmt *default_cap_fmt;
112 enum mtk_vdec_hw_arch hw_arch;
114 bool is_subdev_supported;
115 bool uses_stateless_api;
119 * struct mtk_vcodec_dec_ctx - Context (instance) private data.
121 * @type: type of decoder instance
122 * @dev: pointer to the mtk_vcodec_dec_dev of the device
123 * @list: link to ctx_list of mtk_vcodec_dec_dev
125 * @fh: struct v4l2_fh
126 * @m2m_ctx: pointer to the v4l2_m2m_ctx of the context
127 * @q_data: store information of input and output queue of the context
128 * @id: index of the context that this structure describes
129 * @state: state of the context
131 * @dec_if: hooked decoder driver interface
132 * @drv_handle: driver handle for specific decode/encode instance
134 * @picinfo: store picture info after header parsing
135 * @dpb_size: store dpb count after header parsing
137 * @int_cond: variable used by the waitqueue
138 * @int_type: type of the last interrupt
139 * @queue: waitqueue that can be used to wait for this context to finish
140 * @irq_status: irq status
142 * @ctrl_hdl: handler for v4l2 framework
143 * @decode_work: worker for the decoding
144 * @last_decoded_picinfo: pic information get from latest decode
145 * @empty_flush_buf: a fake size-0 capture buffer that indicates flush. Used
146 * for stateful decoder.
147 * @is_flushing: set to true if flushing is in progress.
149 * @current_codec: current set input codec, in V4L2 pixel format
150 * @capture_fourcc: capture queue type in V4L2 pixel format
152 * @colorspace: enum v4l2_colorspace; supplemental to pixelformat
153 * @ycbcr_enc: enum v4l2_ycbcr_encoding, Y'CbCr encoding
154 * @quantization: enum v4l2_quantization, colorspace quantization
155 * @xfer_func: enum v4l2_xfer_func, colorspace transfer function
157 * @decoded_frame_cnt: number of decoded frames
158 * @lock: protect variables accessed by V4L2 threads and worker thread such as
160 * @hw_id: hardware index used to identify different hardware.
162 * @msg_queue: msg queue used to store lat buffer information.
164 struct mtk_vcodec_dec_ctx {
165 enum mtk_instance_type type;
166 struct mtk_vcodec_dec_dev *dev;
167 struct list_head list;
170 struct v4l2_m2m_ctx *m2m_ctx;
171 struct mtk_q_data q_data[2];
173 enum mtk_instance_state state;
175 const struct vdec_common_if *dec_if;
178 struct vdec_pic_info picinfo;
181 int int_cond[MTK_VDEC_HW_MAX];
182 int int_type[MTK_VDEC_HW_MAX];
183 wait_queue_head_t queue[MTK_VDEC_HW_MAX];
184 unsigned int irq_status;
186 struct v4l2_ctrl_handler ctrl_hdl;
187 struct work_struct decode_work;
188 struct vdec_pic_info last_decoded_picinfo;
189 struct v4l2_m2m_buffer empty_flush_buf;
195 enum v4l2_colorspace colorspace;
196 enum v4l2_ycbcr_encoding ycbcr_enc;
197 enum v4l2_quantization quantization;
198 enum v4l2_xfer_func xfer_func;
200 int decoded_frame_cnt;
204 struct vdec_msg_queue msg_queue;
208 * struct mtk_vcodec_dec_dev - driver data
209 * @v4l2_dev: V4L2 device to register video devices for.
210 * @vfd_dec: Video device for decoder
211 * @mdev_dec: Media device for decoder
213 * @m2m_dev_dec: m2m device for decoder
214 * @plat_dev: platform device
215 * @ctx_list: list of struct mtk_vcodec_ctx
216 * @curr_ctx: The context that is waiting for codec hardware
218 * @reg_base: Mapped address of MTK Vcodec registers.
219 * @vdec_pdata: decoder IC-specific data
220 * @vdecsys_regmap: VDEC_SYS register space passed through syscon
222 * @fw_handler: used to communicate with the firmware.
223 * @id_counter: used to identify current opened instance
225 * @dec_mutex: decoder hardware lock
226 * @dev_mutex: video_device lock
227 * @decode_workqueue: decode work queue
229 * @irqlock: protect data access by irq handler and work thread
230 * @dec_irq: decoder irq resource
232 * @pm: power management control
233 * @dec_capability: used to identify decode capability, ex: 4k
235 * @core_workqueue: queue used for core hardware decode
237 * @subdev_dev: subdev hardware device
238 * @subdev_prob_done: check whether all used hw device is prob done
239 * @subdev_bitmap: used to record hardware is ready or not
241 * @dec_active_cnt: used to mark whether need to record register value
242 * @vdec_racing_info: record register value
243 * @dec_racing_info_mutex: mutex lock used for inner racing mode
244 * @dbgfs: debug log related information
246 struct mtk_vcodec_dec_dev {
247 struct v4l2_device v4l2_dev;
248 struct video_device *vfd_dec;
249 struct media_device mdev_dec;
251 struct v4l2_m2m_dev *m2m_dev_dec;
252 struct platform_device *plat_dev;
253 struct list_head ctx_list;
254 struct mtk_vcodec_dec_ctx *curr_ctx;
256 void __iomem *reg_base[NUM_MAX_VCODEC_REG_BASE];
257 const struct mtk_vcodec_dec_pdata *vdec_pdata;
258 struct regmap *vdecsys_regmap;
260 struct mtk_vcodec_fw *fw_handler;
261 unsigned long id_counter;
263 /* decoder hardware mutex lock */
264 struct mutex dec_mutex[MTK_VDEC_HW_MAX];
265 struct mutex dev_mutex;
266 struct workqueue_struct *decode_workqueue;
271 struct mtk_vcodec_pm pm;
272 unsigned int dec_capability;
274 struct workqueue_struct *core_workqueue;
276 void *subdev_dev[MTK_VDEC_HW_MAX];
277 int (*subdev_prob_done)(struct mtk_vcodec_dec_dev *vdec_dev);
278 DECLARE_BITMAP(subdev_bitmap, MTK_VDEC_HW_MAX);
280 atomic_t dec_active_cnt;
281 u32 vdec_racing_info[132];
282 /* Protects access to vdec_racing_info data */
283 struct mutex dec_racing_info_mutex;
284 struct mtk_vcodec_dbgfs dbgfs;
287 static inline struct mtk_vcodec_dec_ctx *fh_to_dec_ctx(struct v4l2_fh *fh)
289 return container_of(fh, struct mtk_vcodec_dec_ctx, fh);
292 static inline struct mtk_vcodec_dec_ctx *ctrl_to_dec_ctx(struct v4l2_ctrl *ctrl)
294 return container_of(ctrl->handler, struct mtk_vcodec_dec_ctx, ctrl_hdl);
297 /* Wake up context wait_queue */
299 wake_up_dec_ctx(struct mtk_vcodec_dec_ctx *ctx, unsigned int reason, unsigned int hw_id)
301 ctx->int_cond[hw_id] = 1;
302 ctx->int_type[hw_id] = reason;
303 wake_up_interruptible(&ctx->queue[hw_id]);
306 #endif /* _MTK_VCODEC_DEC_DRV_H_ */