2 * Samsung S5P/EXYNOS SoC series MIPI-CSI receiver driver
4 * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd.
5 * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/errno.h>
16 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/kernel.h>
20 #include <linux/memory.h>
21 #include <linux/module.h>
23 #include <linux/phy/phy.h>
24 #include <linux/platform_data/mipi-csis.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/slab.h>
29 #include <linux/spinlock.h>
30 #include <linux/videodev2.h>
31 #include <media/s5p_fimc.h>
32 #include <media/v4l2-of.h>
33 #include <media/v4l2-subdev.h>
35 #include "mipi-csis.h"
38 module_param(debug, int, 0644);
39 MODULE_PARM_DESC(debug, "Debug level (0-2)");
41 /* Register map definition */
43 /* CSIS global control */
44 #define S5PCSIS_CTRL 0x00
45 #define S5PCSIS_CTRL_DPDN_DEFAULT (0 << 31)
46 #define S5PCSIS_CTRL_DPDN_SWAP (1 << 31)
47 #define S5PCSIS_CTRL_ALIGN_32BIT (1 << 20)
48 #define S5PCSIS_CTRL_UPDATE_SHADOW (1 << 16)
49 #define S5PCSIS_CTRL_WCLK_EXTCLK (1 << 8)
50 #define S5PCSIS_CTRL_RESET (1 << 4)
51 #define S5PCSIS_CTRL_ENABLE (1 << 0)
54 #define S5PCSIS_DPHYCTRL 0x04
55 #define S5PCSIS_DPHYCTRL_HSS_MASK (0x1f << 27)
56 #define S5PCSIS_DPHYCTRL_ENABLE (0x1f << 0)
58 #define S5PCSIS_CONFIG 0x08
59 #define S5PCSIS_CFG_FMT_YCBCR422_8BIT (0x1e << 2)
60 #define S5PCSIS_CFG_FMT_RAW8 (0x2a << 2)
61 #define S5PCSIS_CFG_FMT_RAW10 (0x2b << 2)
62 #define S5PCSIS_CFG_FMT_RAW12 (0x2c << 2)
63 /* User defined formats, x = 1...4 */
64 #define S5PCSIS_CFG_FMT_USER(x) ((0x30 + x - 1) << 2)
65 #define S5PCSIS_CFG_FMT_MASK (0x3f << 2)
66 #define S5PCSIS_CFG_NR_LANE_MASK 3
69 #define S5PCSIS_INTMSK 0x10
70 #define S5PCSIS_INTMSK_EVEN_BEFORE (1 << 31)
71 #define S5PCSIS_INTMSK_EVEN_AFTER (1 << 30)
72 #define S5PCSIS_INTMSK_ODD_BEFORE (1 << 29)
73 #define S5PCSIS_INTMSK_ODD_AFTER (1 << 28)
74 #define S5PCSIS_INTMSK_FRAME_START (1 << 27)
75 #define S5PCSIS_INTMSK_FRAME_END (1 << 26)
76 #define S5PCSIS_INTMSK_ERR_SOT_HS (1 << 12)
77 #define S5PCSIS_INTMSK_ERR_LOST_FS (1 << 5)
78 #define S5PCSIS_INTMSK_ERR_LOST_FE (1 << 4)
79 #define S5PCSIS_INTMSK_ERR_OVER (1 << 3)
80 #define S5PCSIS_INTMSK_ERR_ECC (1 << 2)
81 #define S5PCSIS_INTMSK_ERR_CRC (1 << 1)
82 #define S5PCSIS_INTMSK_ERR_UNKNOWN (1 << 0)
83 #define S5PCSIS_INTMSK_EXYNOS4_EN_ALL 0xf000103f
84 #define S5PCSIS_INTMSK_EXYNOS5_EN_ALL 0xfc00103f
86 /* Interrupt source */
87 #define S5PCSIS_INTSRC 0x14
88 #define S5PCSIS_INTSRC_EVEN_BEFORE (1 << 31)
89 #define S5PCSIS_INTSRC_EVEN_AFTER (1 << 30)
90 #define S5PCSIS_INTSRC_EVEN (0x3 << 30)
91 #define S5PCSIS_INTSRC_ODD_BEFORE (1 << 29)
92 #define S5PCSIS_INTSRC_ODD_AFTER (1 << 28)
93 #define S5PCSIS_INTSRC_ODD (0x3 << 28)
94 #define S5PCSIS_INTSRC_NON_IMAGE_DATA (0xf << 28)
95 #define S5PCSIS_INTSRC_FRAME_START (1 << 27)
96 #define S5PCSIS_INTSRC_FRAME_END (1 << 26)
97 #define S5PCSIS_INTSRC_ERR_SOT_HS (0xf << 12)
98 #define S5PCSIS_INTSRC_ERR_LOST_FS (1 << 5)
99 #define S5PCSIS_INTSRC_ERR_LOST_FE (1 << 4)
100 #define S5PCSIS_INTSRC_ERR_OVER (1 << 3)
101 #define S5PCSIS_INTSRC_ERR_ECC (1 << 2)
102 #define S5PCSIS_INTSRC_ERR_CRC (1 << 1)
103 #define S5PCSIS_INTSRC_ERR_UNKNOWN (1 << 0)
104 #define S5PCSIS_INTSRC_ERRORS 0xf03f
106 /* Pixel resolution */
107 #define S5PCSIS_RESOL 0x2c
108 #define CSIS_MAX_PIX_WIDTH 0xffff
109 #define CSIS_MAX_PIX_HEIGHT 0xffff
111 /* Non-image packet data buffers */
112 #define S5PCSIS_PKTDATA_ODD 0x2000
113 #define S5PCSIS_PKTDATA_EVEN 0x3000
114 #define S5PCSIS_PKTDATA_SIZE SZ_4K
121 static char *csi_clock_name[] = {
122 [CSIS_CLK_MUX] = "sclk_csis",
123 [CSIS_CLK_GATE] = "csis",
125 #define NUM_CSIS_CLOCKS ARRAY_SIZE(csi_clock_name)
126 #define DEFAULT_SCLK_CSIS_FREQ 166000000UL
128 static const char * const csis_supply_name[] = {
129 "vddcore", /* CSIS Core (1.0V, 1.1V or 1.2V) suppply */
130 "vddio", /* CSIS I/O and PLL (1.8V) supply */
132 #define CSIS_NUM_SUPPLIES ARRAY_SIZE(csis_supply_name)
140 struct s5pcsis_event {
142 const char * const name;
143 unsigned int counter;
146 static const struct s5pcsis_event s5pcsis_events[] = {
148 { S5PCSIS_INTSRC_ERR_SOT_HS, "SOT Error" },
149 { S5PCSIS_INTSRC_ERR_LOST_FS, "Lost Frame Start Error" },
150 { S5PCSIS_INTSRC_ERR_LOST_FE, "Lost Frame End Error" },
151 { S5PCSIS_INTSRC_ERR_OVER, "FIFO Overflow Error" },
152 { S5PCSIS_INTSRC_ERR_ECC, "ECC Error" },
153 { S5PCSIS_INTSRC_ERR_CRC, "CRC Error" },
154 { S5PCSIS_INTSRC_ERR_UNKNOWN, "Unknown Error" },
155 /* Non-image data receive events */
156 { S5PCSIS_INTSRC_EVEN_BEFORE, "Non-image data before even frame" },
157 { S5PCSIS_INTSRC_EVEN_AFTER, "Non-image data after even frame" },
158 { S5PCSIS_INTSRC_ODD_BEFORE, "Non-image data before odd frame" },
159 { S5PCSIS_INTSRC_ODD_AFTER, "Non-image data after odd frame" },
160 /* Frame start/end */
161 { S5PCSIS_INTSRC_FRAME_START, "Frame Start" },
162 { S5PCSIS_INTSRC_FRAME_END, "Frame End" },
164 #define S5PCSIS_NUM_EVENTS ARRAY_SIZE(s5pcsis_events)
171 struct csis_drvdata {
172 /* Mask of all used interrupts in S5PCSIS_INTMSK register */
177 * struct csis_state - the driver's internal state data structure
178 * @lock: mutex serializing the subdev and power management operations,
179 * protecting @format and @flags members
180 * @pads: CSIS pads array
181 * @sd: v4l2_subdev associated with CSIS device instance
182 * @index: the hardware instance index
183 * @pdev: CSIS platform device
184 * @phy: pointer to the CSIS generic PHY
185 * @regs: mmaped I/O registers memory
186 * @supplies: CSIS regulator supplies
187 * @clock: CSIS clocks
188 * @irq: requested s5p-mipi-csis irq number
189 * @interrupt_mask: interrupt mask of the all used interrupts
190 * @flags: the state variable for power and streaming control
191 * @clock_frequency: device bus clock frequency
192 * @hs_settle: HS-RX settle time
193 * @num_lanes: number of MIPI-CSI data lanes used
194 * @max_num_lanes: maximum number of MIPI-CSI data lanes supported
195 * @wclk_ext: CSI wrapper clock: 0 - bus clock, 1 - external SCLK_CAM
196 * @csis_fmt: current CSIS pixel format
197 * @format: common media bus format for the source and sink pad
198 * @slock: spinlock protecting structure members below
199 * @pkt_buf: the frame embedded (non-image) data buffer
200 * @events: MIPI-CSIS event (error) counters
204 struct media_pad pads[CSIS_PADS_NUM];
205 struct v4l2_subdev sd;
207 struct platform_device *pdev;
210 struct regulator_bulk_data supplies[CSIS_NUM_SUPPLIES];
211 struct clk *clock[NUM_CSIS_CLOCKS];
222 const struct csis_pix_format *csis_fmt;
223 struct v4l2_mbus_framefmt format;
226 struct csis_pktbuf pkt_buf;
227 struct s5pcsis_event events[S5PCSIS_NUM_EVENTS];
231 * struct csis_pix_format - CSIS pixel format description
232 * @pix_width_alignment: horizontal pixel alignment, width will be
233 * multiple of 2^pix_width_alignment
234 * @code: corresponding media bus code
235 * @fmt_reg: S5PCSIS_CONFIG register value
236 * @data_alignment: MIPI-CSI data alignment in bits
238 struct csis_pix_format {
239 unsigned int pix_width_alignment;
240 enum v4l2_mbus_pixelcode code;
245 static const struct csis_pix_format s5pcsis_formats[] = {
247 .code = V4L2_MBUS_FMT_VYUY8_2X8,
248 .fmt_reg = S5PCSIS_CFG_FMT_YCBCR422_8BIT,
249 .data_alignment = 32,
251 .code = V4L2_MBUS_FMT_JPEG_1X8,
252 .fmt_reg = S5PCSIS_CFG_FMT_USER(1),
253 .data_alignment = 32,
255 .code = V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8,
256 .fmt_reg = S5PCSIS_CFG_FMT_USER(1),
257 .data_alignment = 32,
259 .code = V4L2_MBUS_FMT_SGRBG8_1X8,
260 .fmt_reg = S5PCSIS_CFG_FMT_RAW8,
261 .data_alignment = 24,
263 .code = V4L2_MBUS_FMT_SGRBG10_1X10,
264 .fmt_reg = S5PCSIS_CFG_FMT_RAW10,
265 .data_alignment = 24,
267 .code = V4L2_MBUS_FMT_SGRBG12_1X12,
268 .fmt_reg = S5PCSIS_CFG_FMT_RAW12,
269 .data_alignment = 24,
273 #define s5pcsis_write(__csis, __r, __v) writel(__v, __csis->regs + __r)
274 #define s5pcsis_read(__csis, __r) readl(__csis->regs + __r)
276 static struct csis_state *sd_to_csis_state(struct v4l2_subdev *sdev)
278 return container_of(sdev, struct csis_state, sd);
281 static const struct csis_pix_format *find_csis_format(
282 struct v4l2_mbus_framefmt *mf)
286 for (i = 0; i < ARRAY_SIZE(s5pcsis_formats); i++)
287 if (mf->code == s5pcsis_formats[i].code)
288 return &s5pcsis_formats[i];
292 static void s5pcsis_enable_interrupts(struct csis_state *state, bool on)
294 u32 val = s5pcsis_read(state, S5PCSIS_INTMSK);
296 val |= state->interrupt_mask;
298 val &= ~state->interrupt_mask;
299 s5pcsis_write(state, S5PCSIS_INTMSK, val);
302 static void s5pcsis_reset(struct csis_state *state)
304 u32 val = s5pcsis_read(state, S5PCSIS_CTRL);
306 s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_RESET);
310 static void s5pcsis_system_enable(struct csis_state *state, int on)
314 val = s5pcsis_read(state, S5PCSIS_CTRL);
316 val |= S5PCSIS_CTRL_ENABLE;
318 val &= ~S5PCSIS_CTRL_ENABLE;
319 s5pcsis_write(state, S5PCSIS_CTRL, val);
321 val = s5pcsis_read(state, S5PCSIS_DPHYCTRL);
322 val &= ~S5PCSIS_DPHYCTRL_ENABLE;
324 mask = (1 << (state->num_lanes + 1)) - 1;
325 val |= (mask & S5PCSIS_DPHYCTRL_ENABLE);
327 s5pcsis_write(state, S5PCSIS_DPHYCTRL, val);
330 /* Called with the state.lock mutex held */
331 static void __s5pcsis_set_format(struct csis_state *state)
333 struct v4l2_mbus_framefmt *mf = &state->format;
336 v4l2_dbg(1, debug, &state->sd, "fmt: %#x, %d x %d\n",
337 mf->code, mf->width, mf->height);
340 val = s5pcsis_read(state, S5PCSIS_CONFIG);
341 val = (val & ~S5PCSIS_CFG_FMT_MASK) | state->csis_fmt->fmt_reg;
342 s5pcsis_write(state, S5PCSIS_CONFIG, val);
344 /* Pixel resolution */
345 val = (mf->width << 16) | mf->height;
346 s5pcsis_write(state, S5PCSIS_RESOL, val);
349 static void s5pcsis_set_hsync_settle(struct csis_state *state, int settle)
351 u32 val = s5pcsis_read(state, S5PCSIS_DPHYCTRL);
353 val = (val & ~S5PCSIS_DPHYCTRL_HSS_MASK) | (settle << 27);
354 s5pcsis_write(state, S5PCSIS_DPHYCTRL, val);
357 static void s5pcsis_set_params(struct csis_state *state)
361 val = s5pcsis_read(state, S5PCSIS_CONFIG);
362 val = (val & ~S5PCSIS_CFG_NR_LANE_MASK) | (state->num_lanes - 1);
363 s5pcsis_write(state, S5PCSIS_CONFIG, val);
365 __s5pcsis_set_format(state);
366 s5pcsis_set_hsync_settle(state, state->hs_settle);
368 val = s5pcsis_read(state, S5PCSIS_CTRL);
369 if (state->csis_fmt->data_alignment == 32)
370 val |= S5PCSIS_CTRL_ALIGN_32BIT;
372 val &= ~S5PCSIS_CTRL_ALIGN_32BIT;
374 val &= ~S5PCSIS_CTRL_WCLK_EXTCLK;
376 val |= S5PCSIS_CTRL_WCLK_EXTCLK;
377 s5pcsis_write(state, S5PCSIS_CTRL, val);
379 /* Update the shadow register. */
380 val = s5pcsis_read(state, S5PCSIS_CTRL);
381 s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_UPDATE_SHADOW);
384 static void s5pcsis_clk_put(struct csis_state *state)
388 for (i = 0; i < NUM_CSIS_CLOCKS; i++) {
389 if (IS_ERR(state->clock[i]))
391 clk_unprepare(state->clock[i]);
392 clk_put(state->clock[i]);
393 state->clock[i] = ERR_PTR(-EINVAL);
397 static int s5pcsis_clk_get(struct csis_state *state)
399 struct device *dev = &state->pdev->dev;
402 for (i = 0; i < NUM_CSIS_CLOCKS; i++)
403 state->clock[i] = ERR_PTR(-EINVAL);
405 for (i = 0; i < NUM_CSIS_CLOCKS; i++) {
406 state->clock[i] = clk_get(dev, csi_clock_name[i]);
407 if (IS_ERR(state->clock[i])) {
408 ret = PTR_ERR(state->clock[i]);
411 ret = clk_prepare(state->clock[i]);
413 clk_put(state->clock[i]);
414 state->clock[i] = ERR_PTR(-EINVAL);
420 s5pcsis_clk_put(state);
421 dev_err(dev, "failed to get clock: %s\n", csi_clock_name[i]);
425 static void dump_regs(struct csis_state *state, const char *label)
429 const char * const name;
432 { 0x04, "DPHYCTRL" },
437 { 0x38, "SDW_CONFIG" },
441 v4l2_info(&state->sd, "--- %s ---\n", label);
443 for (i = 0; i < ARRAY_SIZE(registers); i++) {
444 u32 cfg = s5pcsis_read(state, registers[i].offset);
445 v4l2_info(&state->sd, "%10s: 0x%08x\n", registers[i].name, cfg);
449 static void s5pcsis_start_stream(struct csis_state *state)
451 s5pcsis_reset(state);
452 s5pcsis_set_params(state);
453 s5pcsis_system_enable(state, true);
454 s5pcsis_enable_interrupts(state, true);
457 static void s5pcsis_stop_stream(struct csis_state *state)
459 s5pcsis_enable_interrupts(state, false);
460 s5pcsis_system_enable(state, false);
463 static void s5pcsis_clear_counters(struct csis_state *state)
468 spin_lock_irqsave(&state->slock, flags);
469 for (i = 0; i < S5PCSIS_NUM_EVENTS; i++)
470 state->events[i].counter = 0;
471 spin_unlock_irqrestore(&state->slock, flags);
474 static void s5pcsis_log_counters(struct csis_state *state, bool non_errors)
476 int i = non_errors ? S5PCSIS_NUM_EVENTS : S5PCSIS_NUM_EVENTS - 4;
479 spin_lock_irqsave(&state->slock, flags);
481 for (i--; i >= 0; i--) {
482 if (state->events[i].counter > 0 || debug)
483 v4l2_info(&state->sd, "%s events: %d\n",
484 state->events[i].name,
485 state->events[i].counter);
487 spin_unlock_irqrestore(&state->slock, flags);
491 * V4L2 subdev operations
493 static int s5pcsis_s_power(struct v4l2_subdev *sd, int on)
495 struct csis_state *state = sd_to_csis_state(sd);
496 struct device *dev = &state->pdev->dev;
499 return pm_runtime_get_sync(dev);
501 return pm_runtime_put_sync(dev);
504 static int s5pcsis_s_stream(struct v4l2_subdev *sd, int enable)
506 struct csis_state *state = sd_to_csis_state(sd);
509 v4l2_dbg(1, debug, sd, "%s: %d, state: 0x%x\n",
510 __func__, enable, state->flags);
513 s5pcsis_clear_counters(state);
514 ret = pm_runtime_get_sync(&state->pdev->dev);
519 mutex_lock(&state->lock);
521 if (state->flags & ST_SUSPENDED) {
525 s5pcsis_start_stream(state);
526 state->flags |= ST_STREAMING;
528 s5pcsis_stop_stream(state);
529 state->flags &= ~ST_STREAMING;
531 s5pcsis_log_counters(state, true);
534 mutex_unlock(&state->lock);
536 pm_runtime_put(&state->pdev->dev);
538 return ret == 1 ? 0 : ret;
541 static int s5pcsis_enum_mbus_code(struct v4l2_subdev *sd,
542 struct v4l2_subdev_fh *fh,
543 struct v4l2_subdev_mbus_code_enum *code)
545 if (code->index >= ARRAY_SIZE(s5pcsis_formats))
548 code->code = s5pcsis_formats[code->index].code;
552 static struct csis_pix_format const *s5pcsis_try_format(
553 struct v4l2_mbus_framefmt *mf)
555 struct csis_pix_format const *csis_fmt;
557 csis_fmt = find_csis_format(mf);
558 if (csis_fmt == NULL)
559 csis_fmt = &s5pcsis_formats[0];
561 mf->code = csis_fmt->code;
562 v4l_bound_align_image(&mf->width, 1, CSIS_MAX_PIX_WIDTH,
563 csis_fmt->pix_width_alignment,
564 &mf->height, 1, CSIS_MAX_PIX_HEIGHT, 1,
569 static struct v4l2_mbus_framefmt *__s5pcsis_get_format(
570 struct csis_state *state, struct v4l2_subdev_fh *fh,
571 enum v4l2_subdev_format_whence which)
573 if (which == V4L2_SUBDEV_FORMAT_TRY)
574 return fh ? v4l2_subdev_get_try_format(fh, 0) : NULL;
576 return &state->format;
579 static int s5pcsis_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
580 struct v4l2_subdev_format *fmt)
582 struct csis_state *state = sd_to_csis_state(sd);
583 struct csis_pix_format const *csis_fmt;
584 struct v4l2_mbus_framefmt *mf;
586 mf = __s5pcsis_get_format(state, fh, fmt->which);
588 if (fmt->pad == CSIS_PAD_SOURCE) {
590 mutex_lock(&state->lock);
592 mutex_unlock(&state->lock);
596 csis_fmt = s5pcsis_try_format(&fmt->format);
598 mutex_lock(&state->lock);
600 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
601 state->csis_fmt = csis_fmt;
602 mutex_unlock(&state->lock);
607 static int s5pcsis_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
608 struct v4l2_subdev_format *fmt)
610 struct csis_state *state = sd_to_csis_state(sd);
611 struct v4l2_mbus_framefmt *mf;
613 mf = __s5pcsis_get_format(state, fh, fmt->which);
617 mutex_lock(&state->lock);
619 mutex_unlock(&state->lock);
623 static int s5pcsis_s_rx_buffer(struct v4l2_subdev *sd, void *buf,
626 struct csis_state *state = sd_to_csis_state(sd);
629 *size = min_t(unsigned int, *size, S5PCSIS_PKTDATA_SIZE);
631 spin_lock_irqsave(&state->slock, flags);
632 state->pkt_buf.data = buf;
633 state->pkt_buf.len = *size;
634 spin_unlock_irqrestore(&state->slock, flags);
639 static int s5pcsis_log_status(struct v4l2_subdev *sd)
641 struct csis_state *state = sd_to_csis_state(sd);
643 mutex_lock(&state->lock);
644 s5pcsis_log_counters(state, true);
645 if (debug && (state->flags & ST_POWERED))
646 dump_regs(state, __func__);
647 mutex_unlock(&state->lock);
651 static int s5pcsis_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
653 struct v4l2_mbus_framefmt *format = v4l2_subdev_get_try_format(fh, 0);
655 format->colorspace = V4L2_COLORSPACE_JPEG;
656 format->code = s5pcsis_formats[0].code;
657 format->width = S5PCSIS_DEF_PIX_WIDTH;
658 format->height = S5PCSIS_DEF_PIX_HEIGHT;
659 format->field = V4L2_FIELD_NONE;
664 static const struct v4l2_subdev_internal_ops s5pcsis_sd_internal_ops = {
665 .open = s5pcsis_open,
668 static struct v4l2_subdev_core_ops s5pcsis_core_ops = {
669 .s_power = s5pcsis_s_power,
670 .log_status = s5pcsis_log_status,
673 static struct v4l2_subdev_pad_ops s5pcsis_pad_ops = {
674 .enum_mbus_code = s5pcsis_enum_mbus_code,
675 .get_fmt = s5pcsis_get_fmt,
676 .set_fmt = s5pcsis_set_fmt,
679 static struct v4l2_subdev_video_ops s5pcsis_video_ops = {
680 .s_rx_buffer = s5pcsis_s_rx_buffer,
681 .s_stream = s5pcsis_s_stream,
684 static struct v4l2_subdev_ops s5pcsis_subdev_ops = {
685 .core = &s5pcsis_core_ops,
686 .pad = &s5pcsis_pad_ops,
687 .video = &s5pcsis_video_ops,
690 static irqreturn_t s5pcsis_irq_handler(int irq, void *dev_id)
692 struct csis_state *state = dev_id;
693 struct csis_pktbuf *pktbuf = &state->pkt_buf;
697 status = s5pcsis_read(state, S5PCSIS_INTSRC);
698 spin_lock_irqsave(&state->slock, flags);
700 if ((status & S5PCSIS_INTSRC_NON_IMAGE_DATA) && pktbuf->data) {
703 if (status & S5PCSIS_INTSRC_EVEN)
704 offset = S5PCSIS_PKTDATA_EVEN;
706 offset = S5PCSIS_PKTDATA_ODD;
708 memcpy(pktbuf->data, state->regs + offset, pktbuf->len);
713 /* Update the event/error counters */
714 if ((status & S5PCSIS_INTSRC_ERRORS) || debug) {
716 for (i = 0; i < S5PCSIS_NUM_EVENTS; i++) {
717 if (!(status & state->events[i].mask))
719 state->events[i].counter++;
720 v4l2_dbg(2, debug, &state->sd, "%s: %d\n",
721 state->events[i].name,
722 state->events[i].counter);
724 v4l2_dbg(2, debug, &state->sd, "status: %08x\n", status);
726 spin_unlock_irqrestore(&state->slock, flags);
728 s5pcsis_write(state, S5PCSIS_INTSRC, status);
732 static int s5pcsis_get_platform_data(struct platform_device *pdev,
733 struct csis_state *state)
735 struct s5p_platform_mipi_csis *pdata = pdev->dev.platform_data;
738 dev_err(&pdev->dev, "Platform data not specified\n");
742 state->clk_frequency = pdata->clk_rate;
743 state->num_lanes = pdata->lanes;
744 state->hs_settle = pdata->hs_settle;
745 state->index = max(0, pdev->id);
746 state->max_num_lanes = state->index ? CSIS1_MAX_LANES :
752 static int s5pcsis_parse_dt(struct platform_device *pdev,
753 struct csis_state *state)
755 struct device_node *node = pdev->dev.of_node;
756 struct v4l2_of_endpoint endpoint;
758 if (of_property_read_u32(node, "clock-frequency",
759 &state->clk_frequency))
760 state->clk_frequency = DEFAULT_SCLK_CSIS_FREQ;
761 if (of_property_read_u32(node, "bus-width",
762 &state->max_num_lanes))
765 node = v4l2_of_get_next_endpoint(node, NULL);
767 dev_err(&pdev->dev, "No port node at %s\n",
768 pdev->dev.of_node->full_name);
771 /* Get port node and validate MIPI-CSI channel id. */
772 v4l2_of_parse_endpoint(node, &endpoint);
774 state->index = endpoint.port - FIMC_INPUT_MIPI_CSI2_0;
775 if (state->index < 0 || state->index >= CSIS_MAX_ENTITIES)
778 /* Get MIPI CSI-2 bus configration from the endpoint node. */
779 of_property_read_u32(node, "samsung,csis-hs-settle",
781 state->wclk_ext = of_property_read_bool(node,
782 "samsung,csis-wclk");
784 state->num_lanes = endpoint.bus.mipi_csi2.num_data_lanes;
790 #define s5pcsis_parse_dt(pdev, state) (-ENOSYS)
793 static int s5pcsis_pm_resume(struct device *dev, bool runtime);
794 static const struct of_device_id s5pcsis_of_match[];
796 static int s5pcsis_probe(struct platform_device *pdev)
798 const struct of_device_id *of_id;
799 const struct csis_drvdata *drv_data;
800 struct device *dev = &pdev->dev;
801 struct resource *mem_res;
802 struct csis_state *state;
806 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
810 mutex_init(&state->lock);
811 spin_lock_init(&state->slock);
815 of_id = of_match_node(s5pcsis_of_match, dev->of_node);
816 if (WARN_ON(of_id == NULL))
819 drv_data = of_id->data;
820 state->interrupt_mask = drv_data->interrupt_mask;
822 ret = s5pcsis_parse_dt(pdev, state);
824 ret = s5pcsis_get_platform_data(pdev, state);
830 if (state->num_lanes == 0 || state->num_lanes > state->max_num_lanes) {
831 dev_err(dev, "Unsupported number of data lanes: %d (max. %d)\n",
832 state->num_lanes, state->max_num_lanes);
836 state->phy = devm_phy_get(dev, "csis");
837 if (IS_ERR(state->phy))
838 return PTR_ERR(state->phy);
840 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
841 state->regs = devm_ioremap_resource(dev, mem_res);
842 if (IS_ERR(state->regs))
843 return PTR_ERR(state->regs);
845 state->irq = platform_get_irq(pdev, 0);
846 if (state->irq < 0) {
847 dev_err(dev, "Failed to get irq\n");
851 for (i = 0; i < CSIS_NUM_SUPPLIES; i++)
852 state->supplies[i].supply = csis_supply_name[i];
854 ret = devm_regulator_bulk_get(dev, CSIS_NUM_SUPPLIES,
859 ret = s5pcsis_clk_get(state);
863 if (state->clk_frequency)
864 ret = clk_set_rate(state->clock[CSIS_CLK_MUX],
865 state->clk_frequency);
867 dev_WARN(dev, "No clock frequency specified!\n");
871 ret = clk_enable(state->clock[CSIS_CLK_MUX]);
875 ret = devm_request_irq(dev, state->irq, s5pcsis_irq_handler,
876 0, dev_name(dev), state);
878 dev_err(dev, "Interrupt request failed\n");
882 v4l2_subdev_init(&state->sd, &s5pcsis_subdev_ops);
883 state->sd.owner = THIS_MODULE;
884 snprintf(state->sd.name, sizeof(state->sd.name), "%s.%d",
885 CSIS_SUBDEV_NAME, state->index);
886 state->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
887 state->csis_fmt = &s5pcsis_formats[0];
889 state->format.code = s5pcsis_formats[0].code;
890 state->format.width = S5PCSIS_DEF_PIX_WIDTH;
891 state->format.height = S5PCSIS_DEF_PIX_HEIGHT;
893 state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
894 state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
895 ret = media_entity_init(&state->sd.entity,
896 CSIS_PADS_NUM, state->pads, 0);
900 /* This allows to retrieve the platform device id by the host driver */
901 v4l2_set_subdevdata(&state->sd, pdev);
903 /* .. and a pointer to the subdev. */
904 platform_set_drvdata(pdev, &state->sd);
905 memcpy(state->events, s5pcsis_events, sizeof(state->events));
907 pm_runtime_enable(dev);
908 if (!pm_runtime_enabled(dev)) {
909 ret = s5pcsis_pm_resume(dev, true);
914 dev_info(&pdev->dev, "lanes: %d, hs_settle: %d, wclk: %d, freq: %u\n",
915 state->num_lanes, state->hs_settle, state->wclk_ext,
916 state->clk_frequency);
920 media_entity_cleanup(&state->sd.entity);
922 clk_disable(state->clock[CSIS_CLK_MUX]);
924 s5pcsis_clk_put(state);
928 static int s5pcsis_pm_suspend(struct device *dev, bool runtime)
930 struct platform_device *pdev = to_platform_device(dev);
931 struct v4l2_subdev *sd = platform_get_drvdata(pdev);
932 struct csis_state *state = sd_to_csis_state(sd);
935 v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n",
936 __func__, state->flags);
938 mutex_lock(&state->lock);
939 if (state->flags & ST_POWERED) {
940 s5pcsis_stop_stream(state);
941 ret = phy_power_off(state->phy);
944 ret = regulator_bulk_disable(CSIS_NUM_SUPPLIES,
948 clk_disable(state->clock[CSIS_CLK_GATE]);
949 state->flags &= ~ST_POWERED;
951 state->flags |= ST_SUSPENDED;
954 mutex_unlock(&state->lock);
955 return ret ? -EAGAIN : 0;
958 static int s5pcsis_pm_resume(struct device *dev, bool runtime)
960 struct platform_device *pdev = to_platform_device(dev);
961 struct v4l2_subdev *sd = platform_get_drvdata(pdev);
962 struct csis_state *state = sd_to_csis_state(sd);
965 v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n",
966 __func__, state->flags);
968 mutex_lock(&state->lock);
969 if (!runtime && !(state->flags & ST_SUSPENDED))
972 if (!(state->flags & ST_POWERED)) {
973 ret = regulator_bulk_enable(CSIS_NUM_SUPPLIES,
977 ret = phy_power_on(state->phy);
979 state->flags |= ST_POWERED;
981 regulator_bulk_disable(CSIS_NUM_SUPPLIES,
985 clk_enable(state->clock[CSIS_CLK_GATE]);
987 if (state->flags & ST_STREAMING)
988 s5pcsis_start_stream(state);
990 state->flags &= ~ST_SUSPENDED;
992 mutex_unlock(&state->lock);
993 return ret ? -EAGAIN : 0;
996 #ifdef CONFIG_PM_SLEEP
997 static int s5pcsis_suspend(struct device *dev)
999 return s5pcsis_pm_suspend(dev, false);
1002 static int s5pcsis_resume(struct device *dev)
1004 return s5pcsis_pm_resume(dev, false);
1008 #ifdef CONFIG_PM_RUNTIME
1009 static int s5pcsis_runtime_suspend(struct device *dev)
1011 return s5pcsis_pm_suspend(dev, true);
1014 static int s5pcsis_runtime_resume(struct device *dev)
1016 return s5pcsis_pm_resume(dev, true);
1020 static int s5pcsis_remove(struct platform_device *pdev)
1022 struct v4l2_subdev *sd = platform_get_drvdata(pdev);
1023 struct csis_state *state = sd_to_csis_state(sd);
1025 pm_runtime_disable(&pdev->dev);
1026 s5pcsis_pm_suspend(&pdev->dev, true);
1027 clk_disable(state->clock[CSIS_CLK_MUX]);
1028 pm_runtime_set_suspended(&pdev->dev);
1029 s5pcsis_clk_put(state);
1031 media_entity_cleanup(&state->sd.entity);
1036 static const struct dev_pm_ops s5pcsis_pm_ops = {
1037 SET_RUNTIME_PM_OPS(s5pcsis_runtime_suspend, s5pcsis_runtime_resume,
1039 SET_SYSTEM_SLEEP_PM_OPS(s5pcsis_suspend, s5pcsis_resume)
1042 static const struct csis_drvdata exynos4_csis_drvdata = {
1043 .interrupt_mask = S5PCSIS_INTMSK_EXYNOS4_EN_ALL,
1046 static const struct csis_drvdata exynos5_csis_drvdata = {
1047 .interrupt_mask = S5PCSIS_INTMSK_EXYNOS5_EN_ALL,
1050 static const struct of_device_id s5pcsis_of_match[] = {
1052 .compatible = "samsung,s5pv210-csis",
1053 .data = &exynos4_csis_drvdata,
1055 .compatible = "samsung,exynos4210-csis",
1056 .data = &exynos4_csis_drvdata,
1058 .compatible = "samsung,exynos5250-csis",
1059 .data = &exynos5_csis_drvdata,
1063 MODULE_DEVICE_TABLE(of, s5pcsis_of_match);
1065 static struct platform_driver s5pcsis_driver = {
1066 .probe = s5pcsis_probe,
1067 .remove = s5pcsis_remove,
1069 .of_match_table = s5pcsis_of_match,
1070 .name = CSIS_DRIVER_NAME,
1071 .owner = THIS_MODULE,
1072 .pm = &s5pcsis_pm_ops,
1076 module_platform_driver(s5pcsis_driver);
1078 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
1079 MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC MIPI-CSI2 receiver driver");
1080 MODULE_LICENSE("GPL");