1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
7 * Authors: Younghwan Joo <yhwan.joo@samsung.com>
8 * Sylwester Nawrocki <s.nawrocki@samsung.com>
13 #include <asm/barrier.h>
14 #include <linux/clk.h>
15 #include <linux/device.h>
16 #include <linux/kernel.h>
17 #include <linux/pinctrl/consumer.h>
18 #include <linux/platform_device.h>
19 #include <linux/sizes.h>
20 #include <linux/spinlock.h>
21 #include <linux/types.h>
22 #include <media/videobuf2-v4l2.h>
23 #include <media/v4l2-ctrls.h>
26 #include "fimc-is-command.h"
27 #include "fimc-is-sensor.h"
28 #include "fimc-is-param.h"
29 #include "fimc-is-regs.h"
31 #define FIMC_IS_DRV_NAME "exynos4-fimc-is"
33 #define FIMC_IS_FW_FILENAME "exynos4_fimc_is_fw.bin"
34 #define FIMC_IS_SETFILE_6A3 "exynos4_s5k6a3_setfile.bin"
36 #define FIMC_IS_FW_LOAD_TIMEOUT 1000 /* ms */
37 #define FIMC_IS_POWER_ON_TIMEOUT 1000 /* us */
39 #define FIMC_IS_SENSORS_NUM 2
41 /* Memory definitions */
42 #define FIMC_IS_CPU_MEM_SIZE (0xa00000)
43 #define FIMC_IS_CPU_BASE_MASK ((1 << 26) - 1)
44 #define FIMC_IS_REGION_SIZE 0x5000
46 #define FIMC_IS_DEBUG_REGION_OFFSET 0x0084b000
47 #define FIMC_IS_SHARED_REGION_OFFSET 0x008c0000
48 #define FIMC_IS_FW_INFO_LEN 31
49 #define FIMC_IS_FW_VER_LEN 7
50 #define FIMC_IS_FW_DESC_LEN (FIMC_IS_FW_INFO_LEN + \
52 #define FIMC_IS_SETFILE_INFO_LEN 39
54 #define FIMC_IS_EXTRA_MEM_SIZE (FIMC_IS_EXTRA_FW_SIZE + \
55 FIMC_IS_EXTRA_SETFILE_SIZE + 0x1000)
56 #define FIMC_IS_EXTRA_FW_SIZE 0x180000
57 #define FIMC_IS_EXTRA_SETFILE_SIZE 0x4b000
60 #define FIMC_IS_FW_ADDR_MASK ((1 << 26) - 1)
61 #define FIMC_IS_FW_SIZE_MAX (SZ_4M)
62 #define FIMC_IS_FW_SIZE_MIN (SZ_32K)
64 #define ATCLK_MCUISP_FREQUENCY 100000000UL
65 #define ACLK_AXI_FREQUENCY 100000000UL
82 ISS_CLK_ISP_DIV0 = ISS_GATE_CLKS_MAX,
88 ISS_CLK_ACLK400MCUISP,
89 ISS_CLK_ACLK400MCUISP_DIV,
93 /* The driver's internal state flags */
100 IS_ST_SETFILE_LOADED,
105 IS_ST_BLOCK_CMD_CLEARED,
113 FIMC_IS_AF_SETCONFIG = 1,
114 FIMC_IS_AF_RUNNING = 2,
116 FIMC_IS_AF_ABORT = 4,
117 FIMC_IS_AF_FAILED = 5,
121 FIMC_IS_AF_UNLOCKED = 0,
122 FIMC_IS_AF_LOCKED = 2
126 FIMC_IS_AE_UNLOCKED = 0,
127 FIMC_IS_AE_LOCKED = 1
130 enum awb_lock_state {
131 FIMC_IS_AWB_UNLOCKED = 0,
132 FIMC_IS_AWB_LOCKED = 1
136 IS_METERING_CONFIG_CMD,
137 IS_METERING_CONFIG_WIN_POS_X,
138 IS_METERING_CONFIG_WIN_POS_Y,
139 IS_METERING_CONFIG_WIN_WIDTH,
140 IS_METERING_CONFIG_WIN_HEIGHT,
141 IS_METERING_CONFIG_MAX
145 const struct firmware *info;
152 struct is_fd_result_header {
174 struct fimc_is_firmware {
175 const struct firmware *f_w;
181 char info[FIMC_IS_FW_INFO_LEN + 1];
182 char version[FIMC_IS_FW_VER_LEN + 1];
183 char setfile_info[FIMC_IS_SETFILE_INFO_LEN + 1];
187 struct fimc_is_memory {
188 /* physical base address */
190 /* virtual base address */
196 #define FIMC_IS_I2H_MAX_ARGS 12
202 u32 args[FIMC_IS_I2H_MAX_ARGS];
210 #define FIMC_IS_DEBUG_MSG 0x3f
211 #define FIMC_IS_DEBUG_LEVEL 3
213 struct fimc_is_setfile {
214 const struct firmware *info;
221 struct chain_config {
222 struct global_param global;
223 struct sensor_param sensor;
224 struct isp_param isp;
225 struct drc_param drc;
228 unsigned long p_region_index[2];
232 * struct fimc_is - fimc-is data structure
233 * @pdev: pointer to FIMC-IS platform device
234 * @pctrl: pointer to pinctrl structure for this device
235 * @v4l2_dev: pointer to top the level v4l2_device
236 * @lock: mutex serializing video device and the subdev operations
237 * @slock: spinlock protecting this data structure and the hw registers
238 * @clocks: FIMC-LITE gate clock
239 * @regs: MCUCTL mmapped registers region
240 * @pmu_regs: PMU ISP mmapped registers region
241 * @irq_queue: interrupt handling waitqueue
242 * @lpm: low power mode flag
243 * @state: internal driver's state flags
246 struct platform_device *pdev;
247 struct pinctrl *pctrl;
248 struct v4l2_device *v4l2_dev;
250 struct fimc_is_firmware fw;
251 struct fimc_is_memory memory;
252 struct firmware *f_w;
255 struct fimc_is_sensor sensor[FIMC_IS_SENSORS_NUM];
256 struct fimc_is_setfile setfile;
258 struct v4l2_ctrl_handler ctrl_handler;
263 struct clk *clocks[ISS_CLKS_MAX];
265 void __iomem *pmu_regs;
267 wait_queue_head_t irq_queue;
271 unsigned int sensor_index;
273 struct i2h_cmd i2h_cmd;
274 struct h2i_cmd h2i_cmd;
275 struct is_fd_result_header fd_header;
277 struct chain_config config[IS_SC_MAX];
278 unsigned config_index;
280 struct is_region *is_p_region;
281 dma_addr_t is_dma_p_region;
282 struct is_share_region *is_shared_region;
283 struct is_af_info af;
285 struct dentry *debugfs_entry;
288 static inline struct fimc_is *fimc_isp_to_is(struct fimc_isp *isp)
290 return container_of(isp, struct fimc_is, isp);
293 static inline struct chain_config *__get_curr_is_config(struct fimc_is *is)
295 return &is->config[is->config_index];
298 static inline void fimc_is_mem_barrier(void)
303 static inline void fimc_is_set_param_bit(struct fimc_is *is, int num)
305 struct chain_config *cfg = &is->config[is->config_index];
307 set_bit(num, &cfg->p_region_index[0]);
310 static inline void fimc_is_set_param_ctrl_cmd(struct fimc_is *is, int cmd)
312 is->is_p_region->parameter.isp.control.cmd = cmd;
315 static inline void mcuctl_write(u32 v, struct fimc_is *is, unsigned int offset)
317 writel(v, is->regs + offset);
320 static inline u32 mcuctl_read(struct fimc_is *is, unsigned int offset)
322 return readl(is->regs + offset);
325 static inline void pmuisp_write(u32 v, struct fimc_is *is, unsigned int offset)
327 writel(v, is->pmu_regs + offset);
330 static inline u32 pmuisp_read(struct fimc_is *is, unsigned int offset)
332 return readl(is->pmu_regs + offset);
335 int fimc_is_wait_event(struct fimc_is *is, unsigned long bit,
336 unsigned int state, unsigned int timeout);
337 int fimc_is_cpu_set_power(struct fimc_is *is, int on);
338 int fimc_is_start_firmware(struct fimc_is *is);
339 int fimc_is_hw_initialize(struct fimc_is *is);
340 void fimc_is_log_dump(const char *level, const void *buf, size_t len);
342 #endif /* FIMC_IS_H_ */