drivers/media/platform/exynos4-is/fimc-core.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Samsung S5P/EXYNOS4 SoC series FIMC (CAMIF) driver
   4  *
   5  * Copyright (C) 2010-2012 Samsung Electronics Co., Ltd.
   6  * Sylwester Nawrocki <s.nawrocki@samsung.com>
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/kernel.h>
  11 #include <linux/types.h>
  12 #include <linux/errno.h>
  13 #include <linux/bug.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/device.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/list.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/io.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include <linux/slab.h>
  24 #include <linux/clk.h>
  25 #include <media/v4l2-ioctl.h>
  26 #include <media/videobuf2-v4l2.h>
  27 #include <media/videobuf2-dma-contig.h>
  28
  29 #include "fimc-core.h"
  30 #include "fimc-reg.h"
  31 #include "media-dev.h"
  32
  33 static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
  34         "sclk_fimc", "fimc"
  35 };
  36
  37 static struct fimc_fmt fimc_formats[] = {
  38         {
  39                 .fourcc         = V4L2_PIX_FMT_RGB565,
  40                 .depth          = { 16 },
  41                 .color          = FIMC_FMT_RGB565,
  42                 .memplanes      = 1,
  43                 .colplanes      = 1,
  44                 .flags          = FMT_FLAGS_M2M,
  45         }, {
  46                 .fourcc         = V4L2_PIX_FMT_BGR666,
  47                 .depth          = { 32 },
  48                 .color          = FIMC_FMT_RGB666,
  49                 .memplanes      = 1,
  50                 .colplanes      = 1,
  51                 .flags          = FMT_FLAGS_M2M,
  52         }, {
  53                 .fourcc         = V4L2_PIX_FMT_BGR32,
  54                 .depth          = { 32 },
  55                 .color          = FIMC_FMT_RGB888,
  56                 .memplanes      = 1,
  57                 .colplanes      = 1,
  58                 .flags          = FMT_FLAGS_M2M | FMT_HAS_ALPHA,
  59         }, {
  60                 .fourcc         = V4L2_PIX_FMT_RGB555,
  61                 .depth          = { 16 },
  62                 .color          = FIMC_FMT_RGB555,
  63                 .memplanes      = 1,
  64                 .colplanes      = 1,
  65                 .flags          = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA,
  66         }, {
  67                 .fourcc         = V4L2_PIX_FMT_RGB444,
  68                 .depth          = { 16 },
  69                 .color          = FIMC_FMT_RGB444,
  70                 .memplanes      = 1,
  71                 .colplanes      = 1,
  72                 .flags          = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA,
  73         }, {
  74                 .mbus_code      = MEDIA_BUS_FMT_YUV10_1X30,
  75                 .flags          = FMT_FLAGS_WRITEBACK,
  76         }, {
  77                 .fourcc         = V4L2_PIX_FMT_YUYV,
  78                 .depth          = { 16 },
  79                 .color          = FIMC_FMT_YCBYCR422,
  80                 .memplanes      = 1,
  81                 .colplanes      = 1,
  82                 .mbus_code      = MEDIA_BUS_FMT_YUYV8_2X8,
  83                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  84         }, {
  85                 .fourcc         = V4L2_PIX_FMT_UYVY,
  86                 .depth          = { 16 },
  87                 .color          = FIMC_FMT_CBYCRY422,
  88                 .memplanes      = 1,
  89                 .colplanes      = 1,
  90                 .mbus_code      = MEDIA_BUS_FMT_UYVY8_2X8,
  91                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  92         }, {
  93                 .fourcc         = V4L2_PIX_FMT_VYUY,
  94                 .depth          = { 16 },
  95                 .color          = FIMC_FMT_CRYCBY422,
  96                 .memplanes      = 1,
  97                 .colplanes      = 1,
  98                 .mbus_code      = MEDIA_BUS_FMT_VYUY8_2X8,
  99                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
 100         }, {
 101                 .fourcc         = V4L2_PIX_FMT_YVYU,
 102                 .depth          = { 16 },
 103                 .color          = FIMC_FMT_YCRYCB422,
 104                 .memplanes      = 1,
 105                 .colplanes      = 1,
 106                 .mbus_code      = MEDIA_BUS_FMT_YVYU8_2X8,
 107                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
 108         }, {
 109                 .fourcc         = V4L2_PIX_FMT_YUV422P,
 110                 .depth          = { 16 },
 111                 .color          = FIMC_FMT_YCBYCR422,
 112                 .memplanes      = 1,
 113                 .colplanes      = 3,
 114                 .flags          = FMT_FLAGS_M2M,
 115         }, {
 116                 .fourcc         = V4L2_PIX_FMT_NV16,
 117                 .depth          = { 16 },
 118                 .color          = FIMC_FMT_YCBYCR422,
 119                 .memplanes      = 1,
 120                 .colplanes      = 2,
 121                 .flags          = FMT_FLAGS_M2M,
 122         }, {
 123                 .fourcc         = V4L2_PIX_FMT_NV61,
 124                 .depth          = { 16 },
 125                 .color          = FIMC_FMT_YCRYCB422,
 126                 .memplanes      = 1,
 127                 .colplanes      = 2,
 128                 .flags          = FMT_FLAGS_M2M,
 129         }, {
 130                 .fourcc         = V4L2_PIX_FMT_YUV420,
 131                 .depth          = { 12 },
 132                 .color          = FIMC_FMT_YCBCR420,
 133                 .memplanes      = 1,
 134                 .colplanes      = 3,
 135                 .flags          = FMT_FLAGS_M2M,
 136         }, {
 137                 .fourcc         = V4L2_PIX_FMT_NV12,
 138                 .depth          = { 12 },
 139                 .color          = FIMC_FMT_YCBCR420,
 140                 .memplanes      = 1,
 141                 .colplanes      = 2,
 142                 .flags          = FMT_FLAGS_M2M,
 143         }, {
 144                 .fourcc         = V4L2_PIX_FMT_NV12M,
 145                 .color          = FIMC_FMT_YCBCR420,
 146                 .depth          = { 8, 4 },
 147                 .memplanes      = 2,
 148                 .colplanes      = 2,
 149                 .flags          = FMT_FLAGS_M2M,
 150         }, {
 151                 .fourcc         = V4L2_PIX_FMT_YUV420M,
 152                 .color          = FIMC_FMT_YCBCR420,
 153                 .depth          = { 8, 2, 2 },
 154                 .memplanes      = 3,
 155                 .colplanes      = 3,
 156                 .flags          = FMT_FLAGS_M2M,
 157         }, {
 158                 .fourcc         = V4L2_PIX_FMT_NV12MT,
 159                 .color          = FIMC_FMT_YCBCR420,
 160                 .depth          = { 8, 4 },
 161                 .memplanes      = 2,
 162                 .colplanes      = 2,
 163                 .flags          = FMT_FLAGS_M2M,
 164         }, {
 165                 .fourcc         = V4L2_PIX_FMT_JPEG,
 166                 .color          = FIMC_FMT_JPEG,
 167                 .depth          = { 8 },
 168                 .memplanes      = 1,
 169                 .colplanes      = 1,
 170                 .mbus_code      = MEDIA_BUS_FMT_JPEG_1X8,
 171                 .flags          = FMT_FLAGS_CAM | FMT_FLAGS_COMPRESSED,
 172         }, {
 173                 .fourcc         = V4L2_PIX_FMT_S5C_UYVY_JPG,
 174                 .color          = FIMC_FMT_YUYV_JPEG,
 175                 .depth          = { 8 },
 176                 .memplanes      = 2,
 177                 .colplanes      = 1,
 178                 .mdataplanes    = 0x2, /* plane 1 holds frame meta data */
 179                 .mbus_code      = MEDIA_BUS_FMT_S5C_UYVY_JPEG_1X8,
 180                 .flags          = FMT_FLAGS_CAM | FMT_FLAGS_COMPRESSED,
 181         },
 182 };
 183
 184 struct fimc_fmt *fimc_get_format(unsigned int index)
 185 {
 186         if (index >= ARRAY_SIZE(fimc_formats))
 187                 return NULL;
 188
 189         return &fimc_formats[index];
 190 }
 191
 192 int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
 193                             int dw, int dh, int rotation)
 194 {
 195         if (rotation == 90 || rotation == 270)
 196                 swap(dw, dh);
 197
 198         if (!ctx->scaler.enabled)
 199                 return (sw == dw && sh == dh) ? 0 : -EINVAL;
 200
 201         if ((sw >= SCALER_MAX_HRATIO * dw) || (sh >= SCALER_MAX_VRATIO * dh))
 202                 return -EINVAL;
 203
 204         return 0;
 205 }
 206
 207 static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
 208 {
 209         u32 sh = 6;
 210
 211         if (src >= 64 * tar)
 212                 return -EINVAL;
 213
 214         while (sh--) {
 215                 u32 tmp = 1 << sh;
 216                 if (src >= tar * tmp) {
 217                         *shift = sh;
 218                         *ratio = tmp;
 219                         return 0;
 220                 }
 221         }
 222         *shift = 0;
 223         *ratio = 1;
 224         return 0;
 225 }
 226
 227 int fimc_set_scaler_info(struct fimc_ctx *ctx)
 228 {
 229         const struct fimc_variant *variant = ctx->fimc_dev->variant;
 230         struct device *dev = &ctx->fimc_dev->pdev->dev;
 231         struct fimc_scaler *sc = &ctx->scaler;
 232         struct fimc_frame *s_frame = &ctx->s_frame;
 233         struct fimc_frame *d_frame = &ctx->d_frame;
 234         int tx, ty, sx, sy;
 235         int ret;
 236
 237         if (ctx->rotation == 90 || ctx->rotation == 270) {
 238                 ty = d_frame->width;
 239                 tx = d_frame->height;
 240         } else {
 241                 tx = d_frame->width;
 242                 ty = d_frame->height;
 243         }
 244         if (tx <= 0 || ty <= 0) {
 245                 dev_err(dev, "Invalid target size: %dx%d\n", tx, ty);
 246                 return -EINVAL;
 247         }
 248
 249         sx = s_frame->width;
 250         sy = s_frame->height;
 251         if (sx <= 0 || sy <= 0) {
 252                 dev_err(dev, "Invalid source size: %dx%d\n", sx, sy);
 253                 return -EINVAL;
 254         }
 255         sc->real_width = sx;
 256         sc->real_height = sy;
 257
 258         ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
 259         if (ret)
 260                 return ret;
 261
 262         ret = fimc_get_scaler_factor(sy, ty,  &sc->pre_vratio, &sc->vfactor);
 263         if (ret)
 264                 return ret;
 265
 266         sc->pre_dst_width = sx / sc->pre_hratio;
 267         sc->pre_dst_height = sy / sc->pre_vratio;
 268
 269         if (variant->has_mainscaler_ext) {
 270                 sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
 271                 sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
 272         } else {
 273                 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
 274                 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
 275
 276         }
 277
 278         sc->scaleup_h = (tx >= sx) ? 1 : 0;
 279         sc->scaleup_v = (ty >= sy) ? 1 : 0;
 280
 281         /* check to see if input and output size/format differ */
 282         if (s_frame->fmt->color == d_frame->fmt->color
 283                 && s_frame->width == d_frame->width
 284                 && s_frame->height == d_frame->height)
 285                 sc->copy_mode = 1;
 286         else
 287                 sc->copy_mode = 0;
 288
 289         return 0;
 290 }
 291
 292 static irqreturn_t fimc_irq_handler(int irq, void *priv)
 293 {
 294         struct fimc_dev *fimc = priv;
 295         struct fimc_ctx *ctx;
 296
 297         fimc_hw_clear_irq(fimc);
 298
 299         spin_lock(&fimc->slock);
 300
 301         if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
 302                 if (test_and_clear_bit(ST_M2M_SUSPENDING, &fimc->state)) {
 303                         set_bit(ST_M2M_SUSPENDED, &fimc->state);
 304                         wake_up(&fimc->irq_queue);
 305                         goto out;
 306                 }
 307                 ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
 308                 if (ctx != NULL) {
 309                         spin_unlock(&fimc->slock);
 310                         fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
 311
 312                         if (ctx->state & FIMC_CTX_SHUT) {
 313                                 ctx->state &= ~FIMC_CTX_SHUT;
 314                                 wake_up(&fimc->irq_queue);
 315                         }
 316                         return IRQ_HANDLED;
 317                 }
 318         } else if (test_bit(ST_CAPT_PEND, &fimc->state)) {
 319                 int last_buf = test_bit(ST_CAPT_JPEG, &fimc->state) &&
 320                                 fimc->vid_cap.reqbufs_count == 1;
 321                 fimc_capture_irq_handler(fimc, !last_buf);
 322         }
 323 out:
 324         spin_unlock(&fimc->slock);
 325         return IRQ_HANDLED;
 326 }
 327
 328 /* The color format (colplanes, memplanes) must be already configured. */
 329 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
 330                       struct fimc_frame *frame, struct fimc_addr *paddr)
 331 {
 332         int ret = 0;
 333         u32 pix_size;
 334
 335         if (vb == NULL || frame == NULL)
 336                 return -EINVAL;
 337
 338         pix_size = frame->width * frame->height;
 339
 340         dbg("memplanes= %d, colplanes= %d, pix_size= %d",
 341                 frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
 342
 343         paddr->y = vb2_dma_contig_plane_dma_addr(vb, 0);
 344
 345         if (frame->fmt->memplanes == 1) {
 346                 switch (frame->fmt->colplanes) {
 347                 case 1:
 348                         paddr->cb = 0;
 349                         paddr->cr = 0;
 350                         break;
 351                 case 2:
 352                         /* decompose Y into Y/Cb */
 353                         paddr->cb = (u32)(paddr->y + pix_size);
 354                         paddr->cr = 0;
 355                         break;
 356                 case 3:
 357                         paddr->cb = (u32)(paddr->y + pix_size);
 358                         /* decompose Y into Y/Cb/Cr */
 359                         if (FIMC_FMT_YCBCR420 == frame->fmt->color)
 360                                 paddr->cr = (u32)(paddr->cb
 361                                                 + (pix_size >> 2));
 362                         else /* 422 */
 363                                 paddr->cr = (u32)(paddr->cb
 364                                                 + (pix_size >> 1));
 365                         break;
 366                 default:
 367                         return -EINVAL;
 368                 }
 369         } else if (!frame->fmt->mdataplanes) {
 370                 if (frame->fmt->memplanes >= 2)
 371                         paddr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
 372
 373                 if (frame->fmt->memplanes == 3)
 374                         paddr->cr = vb2_dma_contig_plane_dma_addr(vb, 2);
 375         }
 376
 377         dbg("PHYS_ADDR: y= 0x%X  cb= 0x%X cr= 0x%X ret= %d",
 378             paddr->y, paddr->cb, paddr->cr, ret);
 379
 380         return ret;
 381 }
 382
 383 /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
 384 void fimc_set_yuv_order(struct fimc_ctx *ctx)
 385 {
 386         /* The one only mode supported in SoC. */
 387         ctx->in_order_2p = FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB;
 388         ctx->out_order_2p = FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB;
 389
 390         /* Set order for 1 plane input formats. */
 391         switch (ctx->s_frame.fmt->color) {
 392         case FIMC_FMT_YCRYCB422:
 393                 ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCRYCB;
 394                 break;
 395         case FIMC_FMT_CBYCRY422:
 396                 ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CBYCRY;
 397                 break;
 398         case FIMC_FMT_CRYCBY422:
 399                 ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CRYCBY;
 400                 break;
 401         case FIMC_FMT_YCBYCR422:
 402         default:
 403                 ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCBYCR;
 404                 break;
 405         }
 406         dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
 407
 408         switch (ctx->d_frame.fmt->color) {
 409         case FIMC_FMT_YCRYCB422:
 410                 ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCRYCB;
 411                 break;
 412         case FIMC_FMT_CBYCRY422:
 413                 ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CBYCRY;
 414                 break;
 415         case FIMC_FMT_CRYCBY422:
 416                 ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CRYCBY;
 417                 break;
 418         case FIMC_FMT_YCBYCR422:
 419         default:
 420                 ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCBYCR;
 421                 break;
 422         }
 423         dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
 424 }
 425
 426 void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
 427 {
 428         bool pix_hoff = ctx->fimc_dev->drv_data->dma_pix_hoff;
 429         u32 i, depth = 0;
 430
 431         for (i = 0; i < f->fmt->memplanes; i++)
 432                 depth += f->fmt->depth[i];
 433
 434         f->dma_offset.y_h = f->offs_h;
 435         if (!pix_hoff)
 436                 f->dma_offset.y_h *= (depth >> 3);
 437
 438         f->dma_offset.y_v = f->offs_v;
 439
 440         f->dma_offset.cb_h = f->offs_h;
 441         f->dma_offset.cb_v = f->offs_v;
 442
 443         f->dma_offset.cr_h = f->offs_h;
 444         f->dma_offset.cr_v = f->offs_v;
 445
 446         if (!pix_hoff) {
 447                 if (f->fmt->colplanes == 3) {
 448                         f->dma_offset.cb_h >>= 1;
 449                         f->dma_offset.cr_h >>= 1;
 450                 }
 451                 if (f->fmt->color == FIMC_FMT_YCBCR420) {
 452                         f->dma_offset.cb_v >>= 1;
 453                         f->dma_offset.cr_v >>= 1;
 454                 }
 455         }
 456
 457         dbg("in_offset: color= %d, y_h= %d, y_v= %d",
 458             f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
 459 }
 460
 461 static int fimc_set_color_effect(struct fimc_ctx *ctx, enum v4l2_colorfx colorfx)
 462 {
 463         struct fimc_effect *effect = &ctx->effect;
 464
 465         switch (colorfx) {
 466         case V4L2_COLORFX_NONE:
 467                 effect->type = FIMC_REG_CIIMGEFF_FIN_BYPASS;
 468                 break;
 469         case V4L2_COLORFX_BW:
 470                 effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY;
 471                 effect->pat_cb = 128;
 472                 effect->pat_cr = 128;
 473                 break;
 474         case V4L2_COLORFX_SEPIA:
 475                 effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY;
 476                 effect->pat_cb = 115;
 477                 effect->pat_cr = 145;
 478                 break;
 479         case V4L2_COLORFX_NEGATIVE:
 480                 effect->type = FIMC_REG_CIIMGEFF_FIN_NEGATIVE;
 481                 break;
 482         case V4L2_COLORFX_EMBOSS:
 483                 effect->type = FIMC_REG_CIIMGEFF_FIN_EMBOSSING;
 484                 break;
 485         case V4L2_COLORFX_ART_FREEZE:
 486                 effect->type = FIMC_REG_CIIMGEFF_FIN_ARTFREEZE;
 487                 break;
 488         case V4L2_COLORFX_SILHOUETTE:
 489                 effect->type = FIMC_REG_CIIMGEFF_FIN_SILHOUETTE;
 490                 break;
 491         case V4L2_COLORFX_SET_CBCR:
 492                 effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY;
 493                 effect->pat_cb = ctx->ctrls.colorfx_cbcr->val >> 8;
 494                 effect->pat_cr = ctx->ctrls.colorfx_cbcr->val & 0xff;
 495                 break;
 496         default:
 497                 return -EINVAL;
 498         }
 499
 500         return 0;
 501 }
 502
 503 /*
 504  * V4L2 controls handling
 505  */
 506 #define ctrl_to_ctx(__ctrl) \
 507         container_of((__ctrl)->handler, struct fimc_ctx, ctrls.handler)
 508
 509 static int __fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_ctrl *ctrl)
 510 {
 511         struct fimc_dev *fimc = ctx->fimc_dev;
 512         const struct fimc_variant *variant = fimc->variant;
 513         int ret = 0;
 514
 515         if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
 516                 return 0;
 517
 518         switch (ctrl->id) {
 519         case V4L2_CID_HFLIP:
 520                 ctx->hflip = ctrl->val;
 521                 break;
 522
 523         case V4L2_CID_VFLIP:
 524                 ctx->vflip = ctrl->val;
 525                 break;
 526
 527         case V4L2_CID_ROTATE:
 528                 if (fimc_capture_pending(fimc)) {
 529                         ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width,
 530                                         ctx->s_frame.height, ctx->d_frame.width,
 531                                         ctx->d_frame.height, ctrl->val);
 532                         if (ret)
 533                                 return -EINVAL;
 534                 }
 535                 if ((ctrl->val == 90 || ctrl->val == 270) &&
 536                     !variant->has_out_rot)
 537                         return -EINVAL;
 538
 539                 ctx->rotation = ctrl->val;
 540                 break;
 541
 542         case V4L2_CID_ALPHA_COMPONENT:
 543                 ctx->d_frame.alpha = ctrl->val;
 544                 break;
 545
 546         case V4L2_CID_COLORFX:
 547                 ret = fimc_set_color_effect(ctx, ctrl->val);
 548                 if (ret)
 549                         return ret;
 550                 break;
 551         }
 552
 553         ctx->state |= FIMC_PARAMS;
 554         set_bit(ST_CAPT_APPLY_CFG, &fimc->state);
 555         return 0;
 556 }
 557
 558 static int fimc_s_ctrl(struct v4l2_ctrl *ctrl)
 559 {
 560         struct fimc_ctx *ctx = ctrl_to_ctx(ctrl);
 561         unsigned long flags;
 562         int ret;
 563
 564         spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
 565         ret = __fimc_s_ctrl(ctx, ctrl);
 566         spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
 567
 568         return ret;
 569 }
 570
 571 static const struct v4l2_ctrl_ops fimc_ctrl_ops = {
 572         .s_ctrl = fimc_s_ctrl,
 573 };
 574
 575 int fimc_ctrls_create(struct fimc_ctx *ctx)
 576 {
 577         unsigned int max_alpha = fimc_get_alpha_mask(ctx->d_frame.fmt);
 578         struct fimc_ctrls *ctrls = &ctx->ctrls;
 579         struct v4l2_ctrl_handler *handler = &ctrls->handler;
 580
 581         if (ctx->ctrls.ready)
 582                 return 0;
 583
 584         v4l2_ctrl_handler_init(handler, 6);
 585
 586         ctrls->rotate = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 587                                         V4L2_CID_ROTATE, 0, 270, 90, 0);
 588         ctrls->hflip = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 589                                         V4L2_CID_HFLIP, 0, 1, 1, 0);
 590         ctrls->vflip = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 591                                         V4L2_CID_VFLIP, 0, 1, 1, 0);
 592
 593         if (ctx->fimc_dev->drv_data->alpha_color)
 594                 ctrls->alpha = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 595                                         V4L2_CID_ALPHA_COMPONENT,
 596                                         0, max_alpha, 1, 0);
 597         else
 598                 ctrls->alpha = NULL;
 599
 600         ctrls->colorfx = v4l2_ctrl_new_std_menu(handler, &fimc_ctrl_ops,
 601                                 V4L2_CID_COLORFX, V4L2_COLORFX_SET_CBCR,
 602                                 ~0x983f, V4L2_COLORFX_NONE);
 603
 604         ctrls->colorfx_cbcr = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 605                                 V4L2_CID_COLORFX_CBCR, 0, 0xffff, 1, 0);
 606
 607         ctx->effect.type = FIMC_REG_CIIMGEFF_FIN_BYPASS;
 608
 609         if (!handler->error) {
 610                 v4l2_ctrl_cluster(2, &ctrls->colorfx);
 611                 ctrls->ready = true;
 612         }
 613
 614         return handler->error;
 615 }
 616
 617 void fimc_ctrls_delete(struct fimc_ctx *ctx)
 618 {
 619         struct fimc_ctrls *ctrls = &ctx->ctrls;
 620
 621         if (ctrls->ready) {
 622                 v4l2_ctrl_handler_free(&ctrls->handler);
 623                 ctrls->ready = false;
 624                 ctrls->alpha = NULL;
 625         }
 626 }
 627
 628 void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active)
 629 {
 630         unsigned int has_alpha = ctx->d_frame.fmt->flags & FMT_HAS_ALPHA;
 631         struct fimc_ctrls *ctrls = &ctx->ctrls;
 632
 633         if (!ctrls->ready)
 634                 return;
 635
 636         mutex_lock(ctrls->handler.lock);
 637         v4l2_ctrl_activate(ctrls->rotate, active);
 638         v4l2_ctrl_activate(ctrls->hflip, active);
 639         v4l2_ctrl_activate(ctrls->vflip, active);
 640         v4l2_ctrl_activate(ctrls->colorfx, active);
 641         if (ctrls->alpha)
 642                 v4l2_ctrl_activate(ctrls->alpha, active && has_alpha);
 643
 644         if (active) {
 645                 fimc_set_color_effect(ctx, ctrls->colorfx->cur.val);
 646                 ctx->rotation = ctrls->rotate->val;
 647                 ctx->hflip    = ctrls->hflip->val;
 648                 ctx->vflip    = ctrls->vflip->val;
 649         } else {
 650                 ctx->effect.type = FIMC_REG_CIIMGEFF_FIN_BYPASS;
 651                 ctx->rotation = 0;
 652                 ctx->hflip    = 0;
 653                 ctx->vflip    = 0;
 654         }
 655         mutex_unlock(ctrls->handler.lock);
 656 }
 657
 658 /* Update maximum value of the alpha color control */
 659 void fimc_alpha_ctrl_update(struct fimc_ctx *ctx)
 660 {
 661         struct fimc_dev *fimc = ctx->fimc_dev;
 662         struct v4l2_ctrl *ctrl = ctx->ctrls.alpha;
 663
 664         if (ctrl == NULL || !fimc->drv_data->alpha_color)
 665                 return;
 666
 667         v4l2_ctrl_lock(ctrl);
 668         ctrl->maximum = fimc_get_alpha_mask(ctx->d_frame.fmt);
 669
 670         if (ctrl->cur.val > ctrl->maximum)
 671                 ctrl->cur.val = ctrl->maximum;
 672
 673         v4l2_ctrl_unlock(ctrl);
 674 }
 675
 676 void __fimc_get_format(struct fimc_frame *frame, struct v4l2_format *f)
 677 {
 678         struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
 679         int i;
 680
 681         pixm->width = frame->o_width;
 682         pixm->height = frame->o_height;
 683         pixm->field = V4L2_FIELD_NONE;
 684         pixm->pixelformat = frame->fmt->fourcc;
 685         pixm->colorspace = V4L2_COLORSPACE_JPEG;
 686         pixm->num_planes = frame->fmt->memplanes;
 687
 688         for (i = 0; i < pixm->num_planes; ++i) {
 689                 pixm->plane_fmt[i].bytesperline = frame->bytesperline[i];
 690                 pixm->plane_fmt[i].sizeimage = frame->payload[i];
 691         }
 692 }
 693
 694 /**
 695  * fimc_adjust_mplane_format - adjust bytesperline/sizeimage for each plane
 696  * @fmt: fimc pixel format description (input)
 697  * @width: requested pixel width
 698  * @height: requested pixel height
 699  * @pix: multi-plane format to adjust
 700  */
 701 void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
 702                                struct v4l2_pix_format_mplane *pix)
 703 {
 704         u32 bytesperline = 0;
 705         int i;
 706
 707         pix->colorspace = V4L2_COLORSPACE_JPEG;
 708         pix->field = V4L2_FIELD_NONE;
 709         pix->num_planes = fmt->memplanes;
 710         pix->pixelformat = fmt->fourcc;
 711         pix->height = height;
 712         pix->width = width;
 713
 714         for (i = 0; i < pix->num_planes; ++i) {
 715                 struct v4l2_plane_pix_format *plane_fmt = &pix->plane_fmt[i];
 716                 u32 bpl = plane_fmt->bytesperline;
 717                 u32 sizeimage;
 718
 719                 if (fmt->colplanes > 1 && (bpl == 0 || bpl < pix->width))
 720                         bpl = pix->width; /* Planar */
 721
 722                 if (fmt->colplanes == 1 && /* Packed */
 723                     (bpl == 0 || ((bpl * 8) / fmt->depth[i]) < pix->width))
 724                         bpl = (pix->width * fmt->depth[0]) / 8;
 725                 /*
 726                  * Currently bytesperline for each plane is same, except
 727                  * V4L2_PIX_FMT_YUV420M format. This calculation may need
 728                  * to be changed when other multi-planar formats are added
 729                  * to the fimc_formats[] array.
 730                  */
 731                 if (i == 0)
 732                         bytesperline = bpl;
 733                 else if (i == 1 && fmt->memplanes == 3)
 734                         bytesperline /= 2;
 735
 736                 plane_fmt->bytesperline = bytesperline;
 737                 sizeimage = pix->width * pix->height * fmt->depth[i] / 8;
 738
 739                 /* Ensure full last row for tiled formats */
 740                 if (tiled_fmt(fmt)) {
 741                         /* 64 * 32 * plane_fmt->bytesperline / 64 */
 742                         u32 row_size = plane_fmt->bytesperline * 32;
 743
 744                         sizeimage = roundup(sizeimage, row_size);
 745                 }
 746
 747                 plane_fmt->sizeimage = max(sizeimage, plane_fmt->sizeimage);
 748         }
 749 }
 750
 751 /**
 752  * fimc_find_format - lookup fimc color format by fourcc or media bus format
 753  * @pixelformat: fourcc to match, ignored if null
 754  * @mbus_code: media bus code to match, ignored if null
 755  * @mask: the color flags to match
 756  * @index: offset in the fimc_formats array, ignored if negative
 757  */
 758 struct fimc_fmt *fimc_find_format(const u32 *pixelformat, const u32 *mbus_code,
 759                                   unsigned int mask, int index)
 760 {
 761         struct fimc_fmt *fmt, *def_fmt = NULL;
 762         unsigned int i;
 763         int id = 0;
 764
 765         if (index >= (int)ARRAY_SIZE(fimc_formats))
 766                 return NULL;
 767
 768         for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
 769                 fmt = &fimc_formats[i];
 770                 if (!(fmt->flags & mask))
 771                         continue;
 772                 if (pixelformat && fmt->fourcc == *pixelformat)
 773                         return fmt;
 774                 if (mbus_code && fmt->mbus_code == *mbus_code)
 775                         return fmt;
 776                 if (index == id)
 777                         def_fmt = fmt;
 778                 id++;
 779         }
 780         return def_fmt;
 781 }
 782
 783 static void fimc_clk_put(struct fimc_dev *fimc)
 784 {
 785         int i;
 786         for (i = 0; i < MAX_FIMC_CLOCKS; i++) {
 787                 if (IS_ERR(fimc->clock[i]))
 788                         continue;
 789                 clk_unprepare(fimc->clock[i]);
 790                 clk_put(fimc->clock[i]);
 791                 fimc->clock[i] = ERR_PTR(-EINVAL);
 792         }
 793 }
 794
 795 static int fimc_clk_get(struct fimc_dev *fimc)
 796 {
 797         int i, ret;
 798
 799         for (i = 0; i < MAX_FIMC_CLOCKS; i++)
 800                 fimc->clock[i] = ERR_PTR(-EINVAL);
 801
 802         for (i = 0; i < MAX_FIMC_CLOCKS; i++) {
 803                 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
 804                 if (IS_ERR(fimc->clock[i])) {
 805                         ret = PTR_ERR(fimc->clock[i]);
 806                         goto err;
 807                 }
 808                 ret = clk_prepare(fimc->clock[i]);
 809                 if (ret < 0) {
 810                         clk_put(fimc->clock[i]);
 811                         fimc->clock[i] = ERR_PTR(-EINVAL);
 812                         goto err;
 813                 }
 814         }
 815         return 0;
 816 err:
 817         fimc_clk_put(fimc);
 818         dev_err(&fimc->pdev->dev, "failed to get clock: %s\n",
 819                 fimc_clocks[i]);
 820         return -ENXIO;
 821 }
 822
 823 #ifdef CONFIG_PM
 824 static int fimc_m2m_suspend(struct fimc_dev *fimc)
 825 {
 826         unsigned long flags;
 827         int timeout;
 828
 829         spin_lock_irqsave(&fimc->slock, flags);
 830         if (!fimc_m2m_pending(fimc)) {
 831                 spin_unlock_irqrestore(&fimc->slock, flags);
 832                 return 0;
 833         }
 834         clear_bit(ST_M2M_SUSPENDED, &fimc->state);
 835         set_bit(ST_M2M_SUSPENDING, &fimc->state);
 836         spin_unlock_irqrestore(&fimc->slock, flags);
 837
 838         timeout = wait_event_timeout(fimc->irq_queue,
 839                              test_bit(ST_M2M_SUSPENDED, &fimc->state),
 840                              FIMC_SHUTDOWN_TIMEOUT);
 841
 842         clear_bit(ST_M2M_SUSPENDING, &fimc->state);
 843         return timeout == 0 ? -EAGAIN : 0;
 844 }
 845
 846 static int fimc_m2m_resume(struct fimc_dev *fimc)
 847 {
 848         struct fimc_ctx *ctx;
 849         unsigned long flags;
 850
 851         spin_lock_irqsave(&fimc->slock, flags);
 852         /* Clear for full H/W setup in first run after resume */
 853         ctx = fimc->m2m.ctx;
 854         fimc->m2m.ctx = NULL;
 855         spin_unlock_irqrestore(&fimc->slock, flags);
 856
 857         if (test_and_clear_bit(ST_M2M_SUSPENDED, &fimc->state))
 858                 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR);
 859
 860         return 0;
 861 }
 862 #endif /* CONFIG_PM */
 863
 864 static const struct of_device_id fimc_of_match[];
 865
 866 static int fimc_parse_dt(struct fimc_dev *fimc, u32 *clk_freq)
 867 {
 868         struct device *dev = &fimc->pdev->dev;
 869         struct device_node *node = dev->of_node;
 870         const struct of_device_id *of_id;
 871         struct fimc_variant *v;
 872         struct fimc_pix_limit *lim;
 873         u32 args[FIMC_PIX_LIMITS_MAX];
 874         int ret;
 875
 876         if (of_property_read_bool(node, "samsung,lcd-wb"))
 877                 return -ENODEV;
 878
 879         v = devm_kzalloc(dev, sizeof(*v) + sizeof(*lim), GFP_KERNEL);
 880         if (!v)
 881                 return -ENOMEM;
 882
 883         of_id = of_match_node(fimc_of_match, node);
 884         if (!of_id)
 885                 return -EINVAL;
 886         fimc->drv_data = of_id->data;
 887         ret = of_property_read_u32_array(node, "samsung,pix-limits",
 888                                          args, FIMC_PIX_LIMITS_MAX);
 889         if (ret < 0)
 890                 return ret;
 891
 892         lim = (struct fimc_pix_limit *)&v[1];
 893
 894         lim->scaler_en_w = args[0];
 895         lim->scaler_dis_w = args[1];
 896         lim->out_rot_en_w = args[2];
 897         lim->out_rot_dis_w = args[3];
 898         v->pix_limit = lim;
 899
 900         ret = of_property_read_u32_array(node, "samsung,min-pix-sizes",
 901                                                                 args, 2);
 902         v->min_inp_pixsize = ret ? FIMC_DEF_MIN_SIZE : args[0];
 903         v->min_out_pixsize = ret ? FIMC_DEF_MIN_SIZE : args[1];
 904         ret = of_property_read_u32_array(node, "samsung,min-pix-alignment",
 905                                                                 args, 2);
 906         v->min_vsize_align = ret ? FIMC_DEF_HEIGHT_ALIGN : args[0];
 907         v->hor_offs_align = ret ? FIMC_DEF_HOR_OFFS_ALIGN : args[1];
 908
 909         ret = of_property_read_u32(node, "samsung,rotators", &args[1]);
 910         v->has_inp_rot = ret ? 1 : args[1] & 0x01;
 911         v->has_out_rot = ret ? 1 : args[1] & 0x10;
 912         v->has_mainscaler_ext = of_property_read_bool(node,
 913                                         "samsung,mainscaler-ext");
 914
 915         v->has_isp_wb = of_property_read_bool(node, "samsung,isp-wb");
 916         v->has_cam_if = of_property_read_bool(node, "samsung,cam-if");
 917         of_property_read_u32(node, "clock-frequency", clk_freq);
 918         fimc->id = of_alias_get_id(node, "fimc");
 919
 920         fimc->variant = v;
 921         return 0;
 922 }
 923
 924 static int fimc_probe(struct platform_device *pdev)
 925 {
 926         struct device *dev = &pdev->dev;
 927         u32 lclk_freq = 0;
 928         struct fimc_dev *fimc;
 929         struct resource *res;
 930         int ret = 0;
 931
 932         fimc = devm_kzalloc(dev, sizeof(*fimc), GFP_KERNEL);
 933         if (!fimc)
 934                 return -ENOMEM;
 935
 936         fimc->pdev = pdev;
 937
 938         if (dev->of_node) {
 939                 ret = fimc_parse_dt(fimc, &lclk_freq);
 940                 if (ret < 0)
 941                         return ret;
 942         } else {
 943                 fimc->drv_data = fimc_get_drvdata(pdev);
 944                 fimc->id = pdev->id;
 945         }
 946         if (!fimc->drv_data || fimc->id >= fimc->drv_data->num_entities ||
 947             fimc->id < 0) {
 948                 dev_err(dev, "Invalid driver data or device id (%d)\n",
 949                         fimc->id);
 950                 return -EINVAL;
 951         }
 952         if (!dev->of_node)
 953                 fimc->variant = fimc->drv_data->variant[fimc->id];
 954
 955         init_waitqueue_head(&fimc->irq_queue);
 956         spin_lock_init(&fimc->slock);
 957         mutex_init(&fimc->lock);
 958
 959         if (fimc->variant->has_isp_wb) {
 960                 fimc->sysreg = fimc_get_sysreg_regmap(dev->of_node);
 961                 if (IS_ERR(fimc->sysreg))
 962                         return PTR_ERR(fimc->sysreg);
 963         }
 964
 965         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 966         fimc->regs = devm_ioremap_resource(dev, res);
 967         if (IS_ERR(fimc->regs))
 968                 return PTR_ERR(fimc->regs);
 969
 970         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 971         if (res == NULL) {
 972                 dev_err(dev, "Failed to get IRQ resource\n");
 973                 return -ENXIO;
 974         }
 975
 976         ret = fimc_clk_get(fimc);
 977         if (ret)
 978                 return ret;
 979
 980         if (lclk_freq == 0)
 981                 lclk_freq = fimc->drv_data->lclk_frequency;
 982
 983         ret = clk_set_rate(fimc->clock[CLK_BUS], lclk_freq);
 984         if (ret < 0)
 985                 return ret;
 986
 987         ret = clk_enable(fimc->clock[CLK_BUS]);
 988         if (ret < 0)
 989                 return ret;
 990
 991         ret = devm_request_irq(dev, res->start, fimc_irq_handler,
 992                                0, dev_name(dev), fimc);
 993         if (ret < 0) {
 994                 dev_err(dev, "failed to install irq (%d)\n", ret);
 995                 goto err_sclk;
 996         }
 997
 998         ret = fimc_initialize_capture_subdev(fimc);
 999         if (ret < 0)
1000                 goto err_sclk;
1001
1002         platform_set_drvdata(pdev, fimc);
1003         pm_runtime_enable(dev);
1004
1005         if (!pm_runtime_enabled(dev)) {
1006                 ret = clk_enable(fimc->clock[CLK_GATE]);
1007                 if (ret < 0)
1008                         goto err_sd;
1009         }
1010
1011         vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32));
1012
1013         dev_dbg(dev, "FIMC.%d registered successfully\n", fimc->id);
1014         return 0;
1015
1016 err_sd:
1017         fimc_unregister_capture_subdev(fimc);
1018 err_sclk:
1019         clk_disable(fimc->clock[CLK_BUS]);
1020         fimc_clk_put(fimc);
1021         return ret;
1022 }
1023
1024 #ifdef CONFIG_PM
1025 static int fimc_runtime_resume(struct device *dev)
1026 {
1027         struct fimc_dev *fimc = dev_get_drvdata(dev);
1028
1029         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1030
1031         /* Enable clocks and perform basic initialization */
1032         clk_enable(fimc->clock[CLK_GATE]);
1033         fimc_hw_reset(fimc);
1034
1035         /* Resume the capture or mem-to-mem device */
1036         if (fimc_capture_busy(fimc))
1037                 return fimc_capture_resume(fimc);
1038
1039         return fimc_m2m_resume(fimc);
1040 }
1041
1042 static int fimc_runtime_suspend(struct device *dev)
1043 {
1044         struct fimc_dev *fimc = dev_get_drvdata(dev);
1045         int ret = 0;
1046
1047         if (fimc_capture_busy(fimc))
1048                 ret = fimc_capture_suspend(fimc);
1049         else
1050                 ret = fimc_m2m_suspend(fimc);
1051         if (!ret)
1052                 clk_disable(fimc->clock[CLK_GATE]);
1053
1054         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1055         return ret;
1056 }
1057 #endif
1058
1059 #ifdef CONFIG_PM_SLEEP
1060 static int fimc_resume(struct device *dev)
1061 {
1062         struct fimc_dev *fimc = dev_get_drvdata(dev);
1063         unsigned long flags;
1064
1065         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1066
1067         /* Do not resume if the device was idle before system suspend */
1068         spin_lock_irqsave(&fimc->slock, flags);
1069         if (!test_and_clear_bit(ST_LPM, &fimc->state) ||
1070             (!fimc_m2m_active(fimc) && !fimc_capture_busy(fimc))) {
1071                 spin_unlock_irqrestore(&fimc->slock, flags);
1072                 return 0;
1073         }
1074         fimc_hw_reset(fimc);
1075         spin_unlock_irqrestore(&fimc->slock, flags);
1076
1077         if (fimc_capture_busy(fimc))
1078                 return fimc_capture_resume(fimc);
1079
1080         return fimc_m2m_resume(fimc);
1081 }
1082
1083 static int fimc_suspend(struct device *dev)
1084 {
1085         struct fimc_dev *fimc = dev_get_drvdata(dev);
1086
1087         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1088
1089         if (test_and_set_bit(ST_LPM, &fimc->state))
1090                 return 0;
1091         if (fimc_capture_busy(fimc))
1092                 return fimc_capture_suspend(fimc);
1093
1094         return fimc_m2m_suspend(fimc);
1095 }
1096 #endif /* CONFIG_PM_SLEEP */
1097
1098 static int fimc_remove(struct platform_device *pdev)
1099 {
1100         struct fimc_dev *fimc = platform_get_drvdata(pdev);
1101
1102         pm_runtime_disable(&pdev->dev);
1103         if (!pm_runtime_status_suspended(&pdev->dev))
1104                 clk_disable(fimc->clock[CLK_GATE]);
1105         pm_runtime_set_suspended(&pdev->dev);
1106
1107         fimc_unregister_capture_subdev(fimc);
1108         vb2_dma_contig_clear_max_seg_size(&pdev->dev);
1109
1110         clk_disable(fimc->clock[CLK_BUS]);
1111         fimc_clk_put(fimc);
1112
1113         dev_info(&pdev->dev, "driver unloaded\n");
1114         return 0;
1115 }
1116
1117 /* S5PV210, S5PC110 */
1118 static const struct fimc_drvdata fimc_drvdata_s5pv210 = {
1119         .num_entities   = 3,
1120         .lclk_frequency = 166000000UL,
1121         .out_buf_count  = 4,
1122         .dma_pix_hoff   = 1,
1123 };
1124
1125 /* EXYNOS4210, S5PV310, S5PC210 */
1126 static const struct fimc_drvdata fimc_drvdata_exynos4210 = {
1127         .num_entities   = 4,
1128         .lclk_frequency = 166000000UL,
1129         .dma_pix_hoff   = 1,
1130         .cistatus2      = 1,
1131         .alpha_color    = 1,
1132         .out_buf_count  = 32,
1133 };
1134
1135 /* EXYNOS4412 */
1136 static const struct fimc_drvdata fimc_drvdata_exynos4x12 = {
1137         .num_entities   = 4,
1138         .lclk_frequency = 166000000UL,
1139         .dma_pix_hoff   = 1,
1140         .cistatus2      = 1,
1141         .alpha_color    = 1,
1142         .out_buf_count  = 32,
1143 };
1144
1145 static const struct of_device_id fimc_of_match[] = {
1146         {
1147                 .compatible = "samsung,s5pv210-fimc",
1148                 .data = &fimc_drvdata_s5pv210,
1149         }, {
1150                 .compatible = "samsung,exynos4210-fimc",
1151                 .data = &fimc_drvdata_exynos4210,
1152         }, {
1153                 .compatible = "samsung,exynos4212-fimc",
1154                 .data = &fimc_drvdata_exynos4x12,
1155         },
1156         { /* sentinel */ },
1157 };
1158
1159 static const struct dev_pm_ops fimc_pm_ops = {
1160         SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
1161         SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
1162 };
1163
1164 static struct platform_driver fimc_driver = {
1165         .probe          = fimc_probe,
1166         .remove         = fimc_remove,
1167         .driver = {
1168                 .of_match_table = fimc_of_match,
1169                 .name           = FIMC_DRIVER_NAME,
1170                 .pm             = &fimc_pm_ops,
1171         }
1172 };
1173
1174 int __init fimc_register_driver(void)
1175 {
1176         return platform_driver_register(&fimc_driver);
1177 }
1178
1179 void __exit fimc_unregister_driver(void)
1180 {
1181         platform_driver_unregister(&fimc_driver);
1182 }