drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
   2 /*
   3  * Wave5 series multi-standard codec IP - decoder interface
   4  *
   5  * Copyright (C) 2021 CHIPS&MEDIA INC
   6  */
   7
   8 #include "wave5-helper.h"
   9
  10 #define VPU_DEC_DEV_NAME "C&M Wave5 VPU decoder"
  11 #define VPU_DEC_DRV_NAME "wave5-dec"
  12 #define V4L2_CID_VPU_THUMBNAIL_MODE (V4L2_CID_USER_BASE + 0x1001)
  13
  14 static const struct vpu_format dec_fmt_list[FMT_TYPES][MAX_FMTS] = {
  15         [VPU_FMT_TYPE_CODEC] = {
  16                 {
  17                         .v4l2_pix_fmt = V4L2_PIX_FMT_HEVC,
  18                         .max_width = 8192,
  19                         .min_width = 8,
  20                         .max_height = 4320,
  21                         .min_height = 8,
  22                 },
  23                 {
  24                         .v4l2_pix_fmt = V4L2_PIX_FMT_H264,
  25                         .max_width = 8192,
  26                         .min_width = 32,
  27                         .max_height = 4320,
  28                         .min_height = 32,
  29                 },
  30         },
  31         [VPU_FMT_TYPE_RAW] = {
  32                 /*{
  33                         .v4l2_pix_fmt = V4L2_PIX_FMT_YUV420,
  34                         .max_width = 8192,
  35                         .min_width = 8,
  36                         .max_height = 4320,
  37                         .min_height = 8,
  38                 },
  39                 {
  40                         .v4l2_pix_fmt = V4L2_PIX_FMT_NV12,
  41                         .max_width = 8192,
  42                         .min_width = 8,
  43                         .max_height = 4320,
  44                         .min_height = 8,
  45                 },
  46                 {
  47                         .v4l2_pix_fmt = V4L2_PIX_FMT_NV21,
  48                         .max_width = 8192,
  49                         .min_width = 8,
  50                         .max_height = 4320,
  51                         .min_height = 8,
  52                 },*/
  53                 {
  54                         .v4l2_pix_fmt = V4L2_PIX_FMT_YUV420M,
  55                         .max_width = 8192,
  56                         .min_width = 8,
  57                         .max_height = 4320,
  58                         .min_height = 8,
  59                 },
  60                 {
  61                         .v4l2_pix_fmt = V4L2_PIX_FMT_NV12M,
  62                         .max_width = 8192,
  63                         .min_width = 8,
  64                         .max_height = 4320,
  65                         .min_height = 8,
  66                 },
  67                 {
  68                         .v4l2_pix_fmt = V4L2_PIX_FMT_NV21M,
  69                         .max_width = 8192,
  70                         .min_width = 8,
  71                         .max_height = 4320,
  72                         .min_height = 8,
  73                 },
  74         }
  75 };
  76
  77 static enum wave_std wave5_to_vpu_codstd(unsigned int v4l2_pix_fmt)
  78 {
  79         switch (v4l2_pix_fmt) {
  80         case V4L2_PIX_FMT_H264:
  81                 return W_AVC_DEC;
  82         case V4L2_PIX_FMT_HEVC:
  83                 return W_HEVC_DEC;
  84         default:
  85                 return STD_UNKNOWN;
  86         }
  87 }
  88
  89 static void wave5_handle_bitstream_buffer(struct vpu_instance *inst)
  90 {
  91         struct v4l2_m2m_buffer *buf, *n;
  92         int ret;
  93
  94         v4l2_m2m_for_each_src_buf_safe(inst->v4l2_fh.m2m_ctx, buf, n) {
  95                 struct vb2_v4l2_buffer *vbuf = &buf->vb;
  96                 struct vpu_buffer *vpu_buf = wave5_to_vpu_buf(vbuf);
  97                 size_t src_size = vb2_get_plane_payload(&vbuf->vb2_buf, 0);
  98                 void *src_buf = vb2_plane_vaddr(&vbuf->vb2_buf, 0);
  99                 dma_addr_t rd_ptr = 0;
 100                 dma_addr_t wr_ptr = 0;
 101                 size_t remain_size = 0;
 102                 size_t offset;
 103
 104                 if (src_size == vb2_plane_size(&vbuf->vb2_buf, 0))
 105                         src_size = 0;
 106
 107                 if (vpu_buf->consumed) {
 108                         dev_dbg(inst->dev->dev, "already consumed src buf (%u)\n",
 109                                 vbuf->vb2_buf.index);
 110                         continue;
 111                 }
 112
 113                 if (!src_buf) {
 114                         dev_dbg(inst->dev->dev,
 115                                 "%s: Acquiring kernel pointer to src buf (%u), fail\n",
 116                                 __func__, vbuf->vb2_buf.index);
 117                         break;
 118                 }
 119
 120                 ret = wave5_vpu_dec_get_bitstream_buffer(inst, &rd_ptr, &wr_ptr, &remain_size);
 121                 if (ret) {
 122                         dev_err(inst->dev->dev, "Getting the bitstream buffer, fail: %d\n",
 123                                 ret);
 124                         return;
 125                 }
 126
 127                 if (remain_size < src_size) {
 128                         dev_dbg(inst->dev->dev,
 129                                 "%s: remaining size: %zu < source size: %zu for src buf (%u)\n",
 130                                 __func__, remain_size, src_size, vbuf->vb2_buf.index);
 131                         break;
 132                 }
 133
 134                 offset = wr_ptr - inst->bitstream_vbuf.daddr;
 135                 if (wr_ptr + src_size > inst->bitstream_vbuf.daddr + inst->bitstream_vbuf.size) {
 136                         size_t size;
 137
 138                         size = inst->bitstream_vbuf.daddr + inst->bitstream_vbuf.size - wr_ptr;
 139                         ret = wave5_vdi_write_memory(inst->dev, &inst->bitstream_vbuf, offset,
 140                                                      (u8 *)src_buf, size, VDI_128BIT_LITTLE_ENDIAN);
 141                         if (ret < 0) {
 142                                 dev_dbg(inst->dev->dev,
 143                                         "%s: 1/2 write src buf (%u) into bitstream buf, fail: %d\n",
 144                                         __func__, vbuf->vb2_buf.index, ret);
 145                                 break;
 146                         }
 147                         ret = wave5_vdi_write_memory(inst->dev, &inst->bitstream_vbuf, 0,
 148                                                      (u8 *)src_buf + size, src_size - size,
 149                                                      VDI_128BIT_LITTLE_ENDIAN);
 150                         if (ret < 0) {
 151                                 dev_dbg(inst->dev->dev,
 152                                         "%s: 2/2 write src buf (%u) into bitstream buf, fail: %d\n",
 153                                         __func__, vbuf->vb2_buf.index, ret);
 154                                 break;
 155                         }
 156                 } else {
 157                         ret = wave5_vdi_write_memory(inst->dev, &inst->bitstream_vbuf, offset,
 158                                                      (u8 *)src_buf, src_size,
 159                                                      VDI_128BIT_LITTLE_ENDIAN);
 160                         if (ret < 0) {
 161                                 dev_dbg(inst->dev->dev,
 162                                         "%s: write src buf (%u) into bitstream buf, fail: %d",
 163                                         __func__, vbuf->vb2_buf.index, ret);
 164                                 break;
 165                         }
 166                 }
 167
 168                 ret = wave5_vpu_dec_update_bitstream_buffer(inst, src_size);
 169                 if (ret) {
 170                         dev_dbg(inst->dev->dev,
 171                                 "vpu_dec_update_bitstream_buffer fail: %d for src buf (%u)\n",
 172                                 ret, vbuf->vb2_buf.index);
 173                         break;
 174                 }
 175
 176                 vpu_buf->consumed = true;
 177         }
 178 }
 179
 180 static void wave5_handle_src_buffer(struct vpu_instance *inst)
 181 {
 182         struct vb2_v4l2_buffer *src_buf;
 183
 184         src_buf = v4l2_m2m_next_src_buf(inst->v4l2_fh.m2m_ctx);
 185         if (src_buf) {
 186                 struct vpu_buffer *vpu_buf = wave5_to_vpu_buf(src_buf);
 187
 188                 if (vpu_buf->consumed) {
 189                         dev_dbg(inst->dev->dev, "%s: already consumed buffer\n", __func__);
 190                         src_buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx);
 191                         inst->timestamp = src_buf->vb2_buf.timestamp;
 192                         v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
 193                 }
 194         }
 195 }
 196
 197 static void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *pix_mp, unsigned int width,
 198                                  unsigned int height)
 199 {
 200         switch (pix_mp->pixelformat) {
 201         case V4L2_PIX_FMT_YUV420:
 202         case V4L2_PIX_FMT_NV12:
 203         case V4L2_PIX_FMT_NV21:
 204                 pix_mp->width = round_up(width, 32);
 205                 pix_mp->height = round_up(height, 16);
 206                 pix_mp->plane_fmt[0].bytesperline = round_up(width, 32);
 207                 pix_mp->plane_fmt[0].sizeimage = width * height * 3 / 2;
 208                 break;
 209         case V4L2_PIX_FMT_YUV420M:
 210                 pix_mp->width = round_up(width, 32);
 211                 pix_mp->height = round_up(height, 16);
 212                 pix_mp->plane_fmt[0].bytesperline = round_up(width, 32);
 213                 pix_mp->plane_fmt[0].sizeimage = width * height;
 214                 pix_mp->plane_fmt[1].bytesperline = round_up(width, 32) / 2;
 215                 pix_mp->plane_fmt[1].sizeimage = width * height / 4;
 216                 pix_mp->plane_fmt[2].bytesperline = round_up(width, 32) / 2;
 217                 pix_mp->plane_fmt[2].sizeimage = width * height / 4;
 218                 break;
 219         case V4L2_PIX_FMT_NV12M:
 220         case V4L2_PIX_FMT_NV21M:
 221                 pix_mp->width = round_up(width, 32);
 222                 pix_mp->height = round_up(height, 16);
 223                 pix_mp->plane_fmt[0].bytesperline = round_up(width, 32);
 224                 pix_mp->plane_fmt[0].sizeimage = width * height;
 225                 pix_mp->plane_fmt[1].bytesperline = round_up(width, 32);
 226                 pix_mp->plane_fmt[1].sizeimage = width * height / 2;
 227                 break;
 228         default:
 229                 pix_mp->width = width;
 230                 pix_mp->height = height;
 231                 pix_mp->plane_fmt[0].bytesperline = 0;
 232                 pix_mp->plane_fmt[0].sizeimage = width * height;
 233                 break;
 234         }
 235 }
 236
 237 static void wave5_update_pix_fmt_r8(struct v4l2_pix_format_mplane *pix_mp, unsigned int width,
 238                                  unsigned int height)
 239 {
 240         switch (pix_mp->pixelformat) {
 241         case V4L2_PIX_FMT_YUV420:
 242         case V4L2_PIX_FMT_NV12:
 243         case V4L2_PIX_FMT_NV21:
 244                 pix_mp->width = round_up(width, 32);
 245                 pix_mp->height = round_up(height, 8);
 246                 pix_mp->plane_fmt[0].bytesperline = round_up(width, 32);
 247                 pix_mp->plane_fmt[0].sizeimage = width * height * 3 / 2;
 248                 break;
 249         case V4L2_PIX_FMT_YUV420M:
 250                 pix_mp->width = round_up(width, 32);
 251                 pix_mp->height = round_up(height, 8);
 252                 pix_mp->plane_fmt[0].bytesperline = round_up(width, 32);
 253                 pix_mp->plane_fmt[0].sizeimage = width * height;
 254                 pix_mp->plane_fmt[1].bytesperline = round_up(width, 32) / 2;
 255                 pix_mp->plane_fmt[1].sizeimage = width * height / 4;
 256                 pix_mp->plane_fmt[2].bytesperline = round_up(width, 32) / 2;
 257                 pix_mp->plane_fmt[2].sizeimage = width * height / 4;
 258                 break;
 259         case V4L2_PIX_FMT_NV12M:
 260         case V4L2_PIX_FMT_NV21M:
 261                 pix_mp->width = round_up(width, 32);
 262                 pix_mp->height = round_up(height, 8);
 263                 pix_mp->plane_fmt[0].bytesperline = round_up(width, 32);
 264                 pix_mp->plane_fmt[0].sizeimage = width * height;
 265                 pix_mp->plane_fmt[1].bytesperline = round_up(width, 32);
 266                 pix_mp->plane_fmt[1].sizeimage = width * height / 2;
 267                 break;
 268         default:
 269                 pix_mp->width = width;
 270                 pix_mp->height = height;
 271                 pix_mp->plane_fmt[0].bytesperline = 0;
 272                 pix_mp->plane_fmt[0].sizeimage = width * height;
 273                 break;
 274         }
 275 }
 276
 277 static void wave5_vpu_dec_start_decode(struct vpu_instance *inst)
 278 {
 279         struct dec_param pic_param;
 280         int ret;
 281         u32 fail_res = 0;
 282
 283         memset(&pic_param, 0, sizeof(struct dec_param));
 284
 285         if (inst->state == VPU_INST_STATE_INIT_SEQ) {
 286                 u32 non_linear_num = inst->dst_buf_count;
 287                 u32 linear_num = inst->dst_buf_count;
 288                 u32 stride = inst->dst_fmt.width;
 289
 290                 ret = wave5_vpu_dec_register_frame_buffer_ex(inst, non_linear_num, linear_num,
 291                                                              stride, inst->dst_fmt.height,
 292                                                              COMPRESSED_FRAME_MAP);
 293                 if (ret)
 294                         dev_dbg(inst->dev->dev, "%s: vpu_dec_register_frame_buffer_ex fail: %d",
 295                                 __func__, ret);
 296         }
 297
 298         ret = wave5_vpu_dec_start_one_frame(inst, &pic_param, &fail_res);
 299         if (ret && fail_res != WAVE5_SYSERR_QUEUEING_FAIL) {
 300                 struct vb2_v4l2_buffer *src_buf;
 301
 302                 src_buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx);
 303                 inst->state = VPU_INST_STATE_STOP;
 304                 //printk("%d wave5 state = %d\n",__LINE__, inst->state);
 305                 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR);
 306         }
 307 }
 308
 309 static void wave5_vpu_dec_stop_decode(struct vpu_instance *inst)
 310 {
 311         unsigned int i;
 312         int ret;
 313
 314         inst->state = VPU_INST_STATE_STOP;
 315         //printk("%d wave5 state = %d\n",__LINE__, inst->state);
 316
 317         ret = wave5_vpu_dec_update_bitstream_buffer(inst, 0);
 318         if (ret) {
 319                 dev_warn(inst->dev->dev,
 320                          "Setting EOS for the bitstream, fail: %d\n", ret);
 321         }
 322
 323         for (i = 0; i < inst->dst_buf_count; i++) {
 324                 ret = wave5_vpu_dec_clr_disp_flag(inst, i);
 325                 if (ret) {
 326                         dev_dbg(inst->dev->dev,
 327                                 "%s: Clearing the display flag of buffer index: %u, fail: %d\n",
 328                                 __func__, i, ret);
 329                 }
 330         }
 331
 332         v4l2_m2m_job_finish(inst->v4l2_m2m_dev, inst->v4l2_fh.m2m_ctx);
 333 }
 334
 335 static void wave5_vpu_dec_finish_decode(struct vpu_instance *inst)
 336 {
 337         struct dec_output_info dec_output_info;
 338         int ret;
 339         u32 irq_status;
 340
 341         if (kfifo_out(&inst->irq_status, &irq_status, sizeof(int)))
 342                 wave5_vpu_clear_interrupt_ex(inst, irq_status);
 343
 344         ret = wave5_vpu_dec_get_output_info(inst, &dec_output_info);
 345         if (ret) {
 346                 v4l2_m2m_job_finish(inst->v4l2_m2m_dev, inst->v4l2_fh.m2m_ctx);
 347                 return;
 348         }
 349         if (dec_output_info.index_frame_decoded == DECODED_IDX_FLAG_NO_FB &&
 350             dec_output_info.index_frame_display == DISPLAY_IDX_FLAG_NO_FB) {
 351                 dev_dbg(inst->dev->dev, "%s: no more frame buffer\n", __func__);
 352         } else {
 353                 wave5_handle_src_buffer(inst);
 354
 355                 if (dec_output_info.index_frame_display >= 0) {
 356                         struct vb2_v4l2_buffer *dst_buf =
 357                                 v4l2_m2m_dst_buf_remove_by_idx(inst->v4l2_fh.m2m_ctx,
 358                                                                dec_output_info.index_frame_display);
 359
 360                         int stride = inst->display_fmt.width;
 361                         int height  =inst->display_fmt.height;
 362                         dev_dbg(inst->dev->dev, "%s %d disp_pic_height %u rc_display.bottom %u\n",
 363                                 __func__, __LINE__, dec_output_info.disp_pic_height, dec_output_info.rc_display.bottom);
 364                         dev_dbg(inst->dev->dev, "%s %d stride %u height %u num %d\n", __func__, __LINE__, stride, height,inst->dst_fmt.num_planes);
 365
 366                         if (inst->dst_fmt.num_planes == 1) {
 367                                 vb2_set_plane_payload(&dst_buf->vb2_buf, 0,
 368                                                       (stride * height * 3 / 2));
 369                         } else if (inst->dst_fmt.num_planes == 2) {
 370                                 vb2_set_plane_payload(&dst_buf->vb2_buf, 0,
 371                                                       (stride * height));
 372                                 vb2_set_plane_payload(&dst_buf->vb2_buf, 1,
 373                                                       ((stride / 2) * height));
 374                         } else if (inst->dst_fmt.num_planes == 3) {
 375                                 vb2_set_plane_payload(&dst_buf->vb2_buf, 0,
 376                                                       (stride * height));
 377                                 vb2_set_plane_payload(&dst_buf->vb2_buf, 1,
 378                                                       ((stride / 2) * (height / 2)));
 379                                 vb2_set_plane_payload(&dst_buf->vb2_buf, 2,
 380                                                       ((stride / 2) * (height / 2)));
 381                         }
 382
 383                         if (inst->timestamp) {
 384                                 dst_buf->vb2_buf.timestamp = inst->timestamp;
 385                         } else {
 386                                 dst_buf->vb2_buf.timestamp = inst->timestamp_cnt++ * inst->codec_info->dec_info.initial_info.ns_per_frame;
 387                         }
 388
 389                         dst_buf->field = V4L2_FIELD_NONE;
 390                         v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
 391
 392                         dev_dbg(inst->dev->dev, "%s: frame_cycle %8u\n",
 393                                 __func__, dec_output_info.frame_cycle);
 394                 } else if (dec_output_info.index_frame_display == DISPLAY_IDX_FLAG_SEQ_END &&
 395                            !inst->eos) {
 396                         static const struct v4l2_event vpu_event_eos = {
 397                                 .type = V4L2_EVENT_EOS
 398                         };
 399                         struct vb2_v4l2_buffer *dst_buf =
 400                                 v4l2_m2m_dst_buf_remove(inst->v4l2_fh.m2m_ctx);
 401
 402                         if (!dst_buf)
 403                                 return;
 404
 405                         if (inst->dst_fmt.num_planes == 1) {
 406                                 vb2_set_plane_payload(&dst_buf->vb2_buf, 0,
 407                                                       vb2_plane_size(&dst_buf->vb2_buf, 0));
 408                         } else if (inst->dst_fmt.num_planes == 2) {
 409                                 vb2_set_plane_payload(&dst_buf->vb2_buf, 0,
 410                                                       vb2_plane_size(&dst_buf->vb2_buf, 0));
 411                                 vb2_set_plane_payload(&dst_buf->vb2_buf, 1,
 412                                                       vb2_plane_size(&dst_buf->vb2_buf, 1));
 413                         } else if (inst->dst_fmt.num_planes == 3) {
 414                                 vb2_set_plane_payload(&dst_buf->vb2_buf, 0,
 415                                                       vb2_plane_size(&dst_buf->vb2_buf, 0));
 416                                 vb2_set_plane_payload(&dst_buf->vb2_buf, 1,
 417                                                       vb2_plane_size(&dst_buf->vb2_buf, 1));
 418                                 vb2_set_plane_payload(&dst_buf->vb2_buf, 2,
 419                                                       vb2_plane_size(&dst_buf->vb2_buf, 2));
 420                         }
 421
 422                         dst_buf->vb2_buf.timestamp = inst->timestamp;
 423                         dst_buf->flags |= V4L2_BUF_FLAG_LAST;
 424                         dst_buf->field = V4L2_FIELD_NONE;
 425                         v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
 426
 427                         inst->eos = TRUE;
 428                         //pr_err("wave5 queue event type: %d id: %d\n",vpu_event_eos.type, vpu_event_eos.id);
 429                         v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_eos);
 430
 431                         v4l2_m2m_job_finish(inst->v4l2_m2m_dev, inst->v4l2_fh.m2m_ctx);
 432                 }
 433         }
 434 }
 435
 436 static int wave5_vpu_dec_querycap(struct file *file, void *fh, struct v4l2_capability *cap)
 437 {
 438         strscpy(cap->driver, VPU_DEC_DRV_NAME, sizeof(cap->driver));
 439         strscpy(cap->card, VPU_DEC_DRV_NAME, sizeof(cap->card));
 440         strscpy(cap->bus_info, "platform:" VPU_DEC_DRV_NAME, sizeof(cap->bus_info));
 441
 442         return 0;
 443 }
 444
 445 static int wave5_vpu_dec_enum_framesizes(struct file *f, void *fh, struct v4l2_frmsizeenum *fsize)
 446 {
 447         const struct vpu_format *vpu_fmt;
 448
 449         if (fsize->index)
 450                 return -EINVAL;
 451
 452         vpu_fmt = wave5_find_vpu_fmt(fsize->pixel_format, dec_fmt_list[VPU_FMT_TYPE_CODEC]);
 453         if (!vpu_fmt) {
 454                 vpu_fmt = wave5_find_vpu_fmt(fsize->pixel_format, dec_fmt_list[VPU_FMT_TYPE_RAW]);
 455                 if (!vpu_fmt)
 456                         return -EINVAL;
 457         }
 458
 459         fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
 460         fsize->stepwise.min_width = vpu_fmt->min_width;
 461         fsize->stepwise.max_width = vpu_fmt->max_width;
 462         fsize->stepwise.step_width = 1;
 463         fsize->stepwise.min_height = vpu_fmt->min_height;
 464         fsize->stepwise.max_height = vpu_fmt->max_height;
 465         fsize->stepwise.step_height = 1;
 466
 467         return 0;
 468 }
 469
 470 static int wave5_vpu_dec_enum_fmt_cap(struct file *file, void *fh, struct v4l2_fmtdesc *f)
 471 {
 472         const struct vpu_format *vpu_fmt;
 473
 474         vpu_fmt = wave5_find_vpu_fmt_by_idx(f->index, dec_fmt_list[VPU_FMT_TYPE_RAW]);
 475         if (!vpu_fmt)
 476                 return -EINVAL;
 477
 478         f->pixelformat = vpu_fmt->v4l2_pix_fmt;
 479         f->flags = 0;
 480
 481         return 0;
 482 }
 483
 484 static int wave5_vpu_dec_try_fmt_cap(struct file *file, void *fh, struct v4l2_format *f)
 485 {
 486         struct vpu_instance *inst = wave5_to_vpu_inst(fh);
 487         const struct vpu_format *vpu_fmt;
 488
 489         dev_dbg(inst->dev->dev,
 490                 "%s: fourcc: %u width: %u height: %u nm planes: %u colorspace: %u field: %u\n",
 491                 __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height,
 492                 f->fmt.pix_mp.num_planes, f->fmt.pix_mp.colorspace, f->fmt.pix_mp.field);
 493
 494         if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
 495                 return -EINVAL;
 496
 497         vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, dec_fmt_list[VPU_FMT_TYPE_RAW]);
 498         if (!vpu_fmt) {
 499                 f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat;
 500                 f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes;
 501                 wave5_update_pix_fmt_r8(&f->fmt.pix_mp, inst->dst_fmt.width, inst->dst_fmt.height);
 502         } else {
 503                 int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width);
 504                 int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height);
 505                 const struct v4l2_format_info *info = v4l2_format_info(vpu_fmt->v4l2_pix_fmt);
 506
 507                 f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt;
 508                 f->fmt.pix_mp.num_planes = info->mem_planes;
 509                 wave5_update_pix_fmt_r8(&f->fmt.pix_mp, width, height);
 510         }
 511
 512         f->fmt.pix_mp.flags = 0;
 513         f->fmt.pix_mp.field = V4L2_FIELD_NONE;
 514         f->fmt.pix_mp.colorspace = inst->colorspace;
 515         f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc;
 516         f->fmt.pix_mp.hsv_enc = inst->hsv_enc;
 517         f->fmt.pix_mp.quantization = inst->quantization;
 518         f->fmt.pix_mp.xfer_func = inst->xfer_func;
 519         memset(&f->fmt.pix_mp.reserved, 0, sizeof(f->fmt.pix_mp.reserved));
 520
 521         return 0;
 522 }
 523
 524 static int wave5_vpu_dec_s_fmt_cap(struct file *file, void *fh, struct v4l2_format *f)
 525 {
 526         struct vpu_instance *inst = wave5_to_vpu_inst(fh);
 527         int i, ret;
 528         unsigned int scalew, scaleh;
 529
 530         dev_dbg(inst->dev->dev,
 531                 "%s: fourcc: %u width: %u height: %u num_planes: %u colorspace: %u field: %u\n",
 532                 __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height,
 533                 f->fmt.pix_mp.num_planes, f->fmt.pix_mp.colorspace, f->fmt.pix_mp.field);
 534
 535         ret = wave5_vpu_dec_try_fmt_cap(file, fh, f);
 536
 537         if (ret)
 538                 return ret;
 539
 540         scalew = inst->src_fmt.width / f->fmt.pix_mp.width;
 541         scaleh = inst->src_fmt.height / f->fmt.pix_mp.height;
 542
 543         //if (scalew > 8 || scaleh > 8 || scalew < 1 || scaleh < 1) {
 544         //      dev_err(inst->dev->dev,"Scaling should be 1 to 1/8 (down-scaling only)! Use input parameter. \n");
 545         //      return -EINVAL;
 546         //}
 547
 548         inst->display_fmt.width = f->fmt.pix_mp.width;
 549         inst->display_fmt.height = f->fmt.pix_mp.height;
 550         inst->display_fmt.pixelformat = f->fmt.pix_mp.pixelformat;
 551         inst->display_fmt.field = f->fmt.pix_mp.field;
 552         inst->display_fmt.flags = f->fmt.pix_mp.flags;
 553         inst->display_fmt.num_planes = f->fmt.pix_mp.num_planes;
 554         inst->dst_fmt.pixelformat = f->fmt.pix_mp.pixelformat;
 555         inst->dst_fmt.num_planes = f->fmt.pix_mp.num_planes;
 556         for (i = 0; i < inst->display_fmt.num_planes; i++) {
 557                 inst->display_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline;
 558                 inst->display_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage;
 559         }
 560
 561         if (inst->display_fmt.pixelformat == V4L2_PIX_FMT_NV12 ||
 562             inst->display_fmt.pixelformat == V4L2_PIX_FMT_NV12M) {
 563                 inst->cbcr_interleave = true;
 564                 inst->nv21 = false;
 565         } else if (inst->display_fmt.pixelformat == V4L2_PIX_FMT_NV21 ||
 566                    inst->display_fmt.pixelformat == V4L2_PIX_FMT_NV21M) {
 567                 inst->cbcr_interleave = true;
 568                 inst->nv21 = true;
 569         } else {
 570                 inst->cbcr_interleave = false;
 571                 inst->nv21 = false;
 572         }
 573
 574         return 0;
 575 }
 576
 577 static int wave5_vpu_dec_g_fmt_cap(struct file *file, void *fh, struct v4l2_format *f)
 578 {
 579         struct vpu_instance *inst = wave5_to_vpu_inst(fh);
 580         int i;
 581
 582         f->fmt.pix_mp.width = inst->display_fmt.width;
 583         f->fmt.pix_mp.height = inst->display_fmt.height;
 584         f->fmt.pix_mp.pixelformat = inst->display_fmt.pixelformat;
 585         f->fmt.pix_mp.field = inst->display_fmt.field;
 586         f->fmt.pix_mp.flags = inst->display_fmt.flags;
 587         f->fmt.pix_mp.num_planes = inst->display_fmt.num_planes;
 588         for (i = 0; i < f->fmt.pix_mp.num_planes; i++) {
 589                 f->fmt.pix_mp.plane_fmt[i].bytesperline = inst->display_fmt.plane_fmt[i].bytesperline;
 590                 f->fmt.pix_mp.plane_fmt[i].sizeimage = inst->display_fmt.plane_fmt[i].sizeimage;
 591         }
 592
 593         f->fmt.pix_mp.colorspace = inst->colorspace;
 594         f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc;
 595         f->fmt.pix_mp.hsv_enc = inst->hsv_enc;
 596         f->fmt.pix_mp.quantization = inst->quantization;
 597         f->fmt.pix_mp.xfer_func = inst->xfer_func;
 598
 599         return 0;
 600 }
 601
 602 static int wave5_vpu_dec_enum_fmt_out(struct file *file, void *fh, struct v4l2_fmtdesc *f)
 603 {
 604         struct vpu_instance *inst = wave5_to_vpu_inst(fh);
 605         const struct vpu_format *vpu_fmt;
 606
 607         dev_dbg(inst->dev->dev, "%s: index: %u\n", __func__, f->index);
 608
 609         vpu_fmt = wave5_find_vpu_fmt_by_idx(f->index, dec_fmt_list[VPU_FMT_TYPE_CODEC]);
 610         if (!vpu_fmt)
 611                 return -EINVAL;
 612
 613         f->pixelformat = vpu_fmt->v4l2_pix_fmt;
 614         f->flags = 0;
 615
 616         return 0;
 617 }
 618
 619 static int wave5_vpu_dec_try_fmt_out(struct file *file, void *fh, struct v4l2_format *f)
 620 {
 621         struct vpu_instance *inst = wave5_to_vpu_inst(fh);
 622         const struct vpu_format *vpu_fmt;
 623
 624         dev_dbg(inst->dev->dev,
 625                 "%s: fourcc: %u width: %u height: %u num_planes: %u colorspace: %u field: %u\n",
 626                 __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height,
 627                 f->fmt.pix_mp.num_planes, f->fmt.pix_mp.colorspace, f->fmt.pix_mp.field);
 628
 629         if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
 630                 return -EINVAL;
 631
 632         vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, dec_fmt_list[VPU_FMT_TYPE_CODEC]);
 633         if (!vpu_fmt) {
 634                 f->fmt.pix_mp.pixelformat = inst->src_fmt.pixelformat;
 635                 f->fmt.pix_mp.num_planes = inst->src_fmt.num_planes;
 636                 wave5_update_pix_fmt(&f->fmt.pix_mp, inst->src_fmt.width, inst->src_fmt.height);
 637         } else {
 638                 int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width);
 639                 int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height);
 640
 641                 f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt;
 642                 f->fmt.pix_mp.num_planes = 1;
 643                 wave5_update_pix_fmt(&f->fmt.pix_mp, width, height);
 644         }
 645
 646         f->fmt.pix_mp.flags = 0;
 647         f->fmt.pix_mp.field = V4L2_FIELD_NONE;
 648         memset(&f->fmt.pix_mp.reserved, 0, sizeof(f->fmt.pix_mp.reserved));
 649
 650         return 0;
 651 }
 652
 653 static int wave5_vpu_dec_s_fmt_out(struct file *file, void *fh, struct v4l2_format *f)
 654 {
 655         struct vpu_instance *inst = wave5_to_vpu_inst(fh);
 656         int i, ret;
 657
 658         dev_dbg(inst->dev->dev,
 659                 "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n",
 660                 __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height,
 661                 f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field);
 662
 663
 664         ret = wave5_vpu_dec_try_fmt_out(file, fh, f);
 665         if (ret)
 666                 return ret;
 667
 668         inst->src_fmt.width = f->fmt.pix_mp.width;
 669         inst->src_fmt.height = f->fmt.pix_mp.height;
 670         inst->src_fmt.pixelformat = f->fmt.pix_mp.pixelformat;
 671         inst->src_fmt.field = f->fmt.pix_mp.field;
 672         inst->src_fmt.flags = f->fmt.pix_mp.flags;
 673         inst->src_fmt.num_planes = f->fmt.pix_mp.num_planes;
 674         for (i = 0; i < inst->src_fmt.num_planes; i++) {
 675                 inst->src_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline;
 676                 inst->src_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage;
 677         }
 678
 679         inst->colorspace = f->fmt.pix_mp.colorspace;
 680         inst->ycbcr_enc = f->fmt.pix_mp.ycbcr_enc;
 681         inst->hsv_enc = f->fmt.pix_mp.hsv_enc;
 682         inst->quantization = f->fmt.pix_mp.quantization;
 683         inst->xfer_func = f->fmt.pix_mp.xfer_func;
 684
 685
 686         wave5_update_pix_fmt_r8(&inst->dst_fmt, f->fmt.pix_mp.width, f->fmt.pix_mp.height);
 687         wave5_update_pix_fmt_r8(&inst->display_fmt, f->fmt.pix_mp.width, f->fmt.pix_mp.height);
 688
 689         return 0;
 690 }
 691
 692 static int wave5_vpu_dec_g_selection(struct file *file, void *fh, struct v4l2_selection *s)
 693 {
 694         struct vpu_instance *inst = wave5_to_vpu_inst(fh);
 695
 696         dev_dbg(inst->dev->dev, "%s: type: %u | target: %u\n", __func__, s->type, s->target);
 697
 698         if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
 699                 return -EINVAL;
 700         switch (s->target) {
 701         case V4L2_SEL_TGT_COMPOSE_BOUNDS:
 702         case V4L2_SEL_TGT_COMPOSE_PADDED:
 703                 s->r.left = 0;
 704                 s->r.top = 0;
 705                 s->r.width = inst->dst_fmt.width;
 706                 s->r.height = inst->dst_fmt.height;
 707                 break;
 708         case V4L2_SEL_TGT_COMPOSE:
 709         case V4L2_SEL_TGT_COMPOSE_DEFAULT:
 710                 s->r.left = 0;
 711                 s->r.top = 0;
 712                 if (inst->state > VPU_INST_STATE_OPEN) {
 713                         s->r.width = inst->conf_win_width;
 714                         s->r.height = inst->conf_win_height;
 715                 } else {
 716                         s->r.width = inst->src_fmt.width;
 717                         s->r.height = inst->src_fmt.height;
 718                 }
 719                 break;
 720         default:
 721                 return -EINVAL;
 722         }
 723
 724         return 0;
 725 }
 726
 727 static int wave5_vpu_dec_s_selection(struct file *file, void *fh, struct v4l2_selection *s)
 728 {
 729         struct vpu_instance *inst = wave5_to_vpu_inst(fh);
 730
 731         if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
 732                 return -EINVAL;
 733
 734         if (s->target != V4L2_SEL_TGT_COMPOSE)
 735                 return -EINVAL;
 736
 737         dev_dbg(inst->dev->dev, "V4L2_SEL_TGT_COMPOSE w: %u h: %u\n",
 738                 s->r.width, s->r.height);
 739
 740         s->r.left = 0;
 741         s->r.top = 0;
 742         s->r.width = inst->dst_fmt.width;
 743         s->r.height = inst->dst_fmt.height;
 744
 745         return 0;
 746 }
 747
 748 static int wave5_vpu_dec_decoder_cmd(struct file *file, void *fh, struct v4l2_decoder_cmd *dc)
 749 {
 750         struct vpu_instance *inst = wave5_to_vpu_inst(fh);
 751         int ret;
 752
 753         dev_dbg(inst->dev->dev, "decoder command: %u\n", dc->cmd);
 754
 755         ret = v4l2_m2m_ioctl_try_decoder_cmd(file, fh, dc);
 756         if (ret)
 757                 return ret;
 758
 759         if (!wave5_vpu_both_queues_are_streaming(inst))
 760                 return 0;
 761
 762         switch (dc->cmd) {
 763         case V4L2_DEC_CMD_STOP:
 764                 wave5_handle_bitstream_buffer(inst);
 765                 inst->ops->start_process(inst);
 766                 inst->state = VPU_INST_STATE_STOP;
 767                 //printk("%d wave5 state = %d\n",__LINE__, inst->state);
 768
 769                 ret = wave5_vpu_dec_update_bitstream_buffer(inst, 0);
 770                 if (ret) {
 771                         dev_err(inst->dev->dev,
 772                                 "Setting EOS for the bitstream, fail: %d\n", ret);
 773                         return ret;
 774                 }
 775                 break;
 776         case V4L2_DEC_CMD_START:
 777                 break;
 778         default:
 779                 return -EINVAL;
 780         }
 781
 782         return 0;
 783 }
 784
 785 static const struct v4l2_ioctl_ops wave5_vpu_dec_ioctl_ops = {
 786         .vidioc_querycap = wave5_vpu_dec_querycap,
 787         .vidioc_enum_framesizes = wave5_vpu_dec_enum_framesizes,
 788
 789         .vidioc_enum_fmt_vid_cap        = wave5_vpu_dec_enum_fmt_cap,
 790         .vidioc_s_fmt_vid_cap_mplane = wave5_vpu_dec_s_fmt_cap,
 791         .vidioc_g_fmt_vid_cap_mplane = wave5_vpu_dec_g_fmt_cap,
 792         .vidioc_try_fmt_vid_cap_mplane = wave5_vpu_dec_try_fmt_cap,
 793
 794         .vidioc_enum_fmt_vid_out        = wave5_vpu_dec_enum_fmt_out,
 795         .vidioc_s_fmt_vid_out_mplane = wave5_vpu_dec_s_fmt_out,
 796         .vidioc_g_fmt_vid_out_mplane = wave5_vpu_g_fmt_out,
 797         .vidioc_try_fmt_vid_out_mplane = wave5_vpu_dec_try_fmt_out,
 798
 799         .vidioc_g_selection = wave5_vpu_dec_g_selection,
 800         .vidioc_s_selection = wave5_vpu_dec_s_selection,
 801
 802         .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
 803         .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
 804         .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
 805         .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
 806         .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
 807         .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
 808         .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
 809         .vidioc_streamon = v4l2_m2m_ioctl_streamon,
 810         .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
 811
 812         .vidioc_try_decoder_cmd = v4l2_m2m_ioctl_try_decoder_cmd,
 813         .vidioc_decoder_cmd = wave5_vpu_dec_decoder_cmd,
 814
 815         .vidioc_subscribe_event = wave5_vpu_subscribe_event,
 816         .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
 817 };
 818
 819 static int wave5_vpu_dec_s_ctrl(struct v4l2_ctrl *ctrl)
 820 {
 821         struct vpu_instance *inst = wave5_ctrl_to_vpu_inst(ctrl);
 822
 823         dev_dbg(inst->dev->dev, "%s: name: %s | value: %d\n",
 824                 __func__, ctrl->name, ctrl->val);
 825
 826         switch (ctrl->id) {
 827         case V4L2_CID_VPU_THUMBNAIL_MODE:
 828                 inst->thumbnail_mode = ctrl->val;
 829                 break;
 830         case V4L2_CID_MIN_BUFFERS_FOR_CAPTURE:
 831                 break;
 832         default:
 833                 return -EINVAL;
 834         }
 835
 836         return 0;
 837 }
 838
 839 static const struct v4l2_ctrl_ops wave5_vpu_dec_ctrl_ops = {
 840         .s_ctrl = wave5_vpu_dec_s_ctrl,
 841 };
 842
 843 static const struct v4l2_ctrl_config wave5_vpu_thumbnail_mode = {
 844         .ops = &wave5_vpu_dec_ctrl_ops,
 845         .id = V4L2_CID_VPU_THUMBNAIL_MODE,
 846         .name = "thumbnail mode",
 847         .type = V4L2_CTRL_TYPE_BOOLEAN,
 848         .def = 0,
 849         .min = 0,
 850         .max = 1,
 851         .step = 1,
 852         .flags = V4L2_CTRL_FLAG_WRITE_ONLY,
 853 };
 854
 855 static void wave5_set_default_dec_openparam(struct dec_open_param *open_param)
 856 {
 857         open_param->bitstream_mode = BS_MODE_INTERRUPT;
 858         open_param->stream_endian = VPU_STREAM_ENDIAN;
 859         open_param->frame_endian = VPU_FRAME_ENDIAN;
 860 }
 861
 862 static int wave5_vpu_dec_queue_setup(struct vb2_queue *q, unsigned int *num_buffers,
 863                                      unsigned int *num_planes, unsigned int sizes[],
 864                                      struct device *alloc_devs[])
 865 {
 866         struct vpu_instance *inst = vb2_get_drv_priv(q);
 867         struct v4l2_pix_format_mplane inst_format =
 868                 (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ? inst->src_fmt : inst->display_fmt;
 869         unsigned int i;
 870         int ret;
 871
 872         dev_dbg(inst->dev->dev, "%s: num_buffers: %u | num_planes: %u | type: %u\n", __func__,
 873                 *num_buffers, *num_planes, q->type);
 874
 875         if (*num_planes) {
 876                 if (inst_format.num_planes != *num_planes)
 877                         return -EINVAL;
 878
 879                 for (i = 0; i < *num_planes; i++) {
 880                         if (sizes[i] < inst_format.plane_fmt[i].sizeimage)
 881                                 return -EINVAL;
 882                 }
 883         } else {
 884                 *num_planes = inst_format.num_planes;
 885
 886                 if (*num_planes == 1) {
 887                         sizes[0] = inst_format.width * inst_format.height * 3 / 2;
 888                         if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
 889                                 sizes[0] = inst_format.plane_fmt[0].sizeimage;
 890                         dev_dbg(inst->dev->dev, "%s: size[0]: %u\n", __func__, sizes[0]);
 891                 } else if (*num_planes == 2) {
 892                         sizes[0] = inst_format.width * inst_format.height;
 893                         sizes[1] = inst_format.width * inst_format.height / 2;
 894                         dev_dbg(inst->dev->dev, "%s: size[0]: %u | size[1]: %u\n",
 895                                 __func__, sizes[0], sizes[1]);
 896                 } else if (*num_planes == 3) {
 897                         sizes[0] = inst_format.width * inst_format.height;
 898                         sizes[1] = inst_format.width * inst_format.height / 4;
 899                         sizes[2] = inst_format.width * inst_format.height / 4;
 900                         dev_dbg(inst->dev->dev, "%s: size[0]: %u | size[1]: %u | size[2]: %u\n",
 901                                 __func__, sizes[0], sizes[1], sizes[2]);
 902                 }
 903         }
 904
 905         if (inst->state == VPU_INST_STATE_NONE && q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
 906                 struct dec_open_param open_param;
 907
 908                 *num_buffers = 4;
 909
 910                 memset(&open_param, 0, sizeof(struct dec_open_param));
 911                 wave5_set_default_dec_openparam(&open_param);
 912
 913                 inst->bitstream_vbuf.size = ALIGN(inst->src_fmt.plane_fmt[0].sizeimage, 1024) * 4;
 914                 ret = wave5_vdi_allocate_dma_memory(inst->dev, &inst->bitstream_vbuf);
 915                 if (ret) {
 916                         dev_dbg(inst->dev->dev, "%s: alloc bitstream of size %zu fail: %d\n",
 917                                 __func__, inst->bitstream_vbuf.size, ret);
 918                         return ret;
 919                 }
 920
 921                 inst->std = wave5_to_vpu_codstd(inst->src_fmt.pixelformat);
 922                 if (inst->std == STD_UNKNOWN) {
 923                         dev_warn(inst->dev->dev, "unsupported pixelformat: %.4s\n",
 924                                  (char *)&inst->src_fmt.pixelformat);
 925                         ret = -EINVAL;
 926                         goto free_bitstream_vbuf;
 927                 }
 928                 open_param.bitstream_buffer = inst->bitstream_vbuf.daddr;
 929                 open_param.bitstream_buffer_size = inst->bitstream_vbuf.size;
 930
 931                 ret = wave5_vpu_dec_open(inst, &open_param);
 932                 if (ret) {
 933                         dev_dbg(inst->dev->dev, "%s: wave5_vpu_dec_open, fail: %d\n",
 934                                 __func__, ret);
 935                         goto free_bitstream_vbuf;
 936                 }
 937
 938                 inst->state = VPU_INST_STATE_OPEN;
 939                 //printk("wave5 state = %d\n",inst->state);
 940
 941                 if (inst->thumbnail_mode)
 942                         wave5_vpu_dec_give_command(inst, ENABLE_DEC_THUMBNAIL_MODE, NULL);
 943
 944         } else if (inst->state == VPU_INST_STATE_INIT_SEQ &&
 945                    q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
 946                 u32 non_linear_num;
 947                 u32 fb_stride, fb_height;
 948                 u32 luma_size, chroma_size;
 949
 950                 //if (*num_buffers > inst->min_dst_buf_count &&
 951                 //    *num_buffers < WAVE5_MAX_FBS)
 952                 //      inst->dst_buf_count = *num_buffers;
 953
 954                 *num_buffers = inst->dst_buf_count;
 955                 non_linear_num = inst->dst_buf_count;
 956
 957                 for (i = 0; i < non_linear_num; i++) {
 958                         struct frame_buffer *frame = &inst->frame_buf[i];
 959                         struct vpu_buf *vframe = &inst->frame_vbuf[i];
 960
 961                         if (inst->codec_info->dec_info.initial_info.luma_bitdepth > 8 ||
 962                                 inst->codec_info->dec_info.initial_info.chroma_bitdepth > 8) {
 963                                 fb_stride = ALIGN(ALIGN(inst->dst_fmt.width, 16) * 5, 32) / 4;
 964                                 fb_stride = ALIGN(fb_stride, 32);
 965                         } else {
 966                                 fb_stride = inst->dst_fmt.width;
 967                         }
 968
 969                         fb_height = ALIGN(inst->dst_fmt.height, 32);
 970                         luma_size = fb_stride * fb_height;
 971                         chroma_size = ALIGN(fb_stride / 2, 16) * fb_height;
 972
 973                         vframe->size = luma_size + chroma_size;
 974                         ret = wave5_vdi_allocate_dma_memory(inst->dev, vframe);
 975                         if (ret) {
 976                                 dev_dbg(inst->dev->dev,
 977                                         "%s: Allocating FBC buf of size %zu, fail: %d\n",
 978                                         __func__, vframe->size, ret);
 979                                 return ret;
 980                         }
 981
 982                         frame->buf_y = vframe->daddr;
 983                         frame->buf_cb = vframe->daddr + luma_size;
 984                         frame->buf_cr = (dma_addr_t)-1;
 985                         frame->size = vframe->size;
 986                         frame->width = inst->src_fmt.width;
 987                         frame->stride = fb_stride;
 988                         frame->map_type = COMPRESSED_FRAME_MAP;
 989                         frame->update_fb_info = true;
 990                         dev_dbg(inst->dev->dev, "no linear framebuf y 0x%llx cb 0x%llx cr 0x%llx\n",
 991                                                                                                 frame->buf_y, frame->buf_cb, frame->buf_cr);
 992                 }
 993         } else if (inst->state == VPU_INST_STATE_STOP &&
 994                    q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
 995                 *num_buffers = 0;
 996         }
 997
 998         return 0;
 999
1000 free_bitstream_vbuf:
1001         wave5_vdi_free_dma_memory(inst->dev, &inst->bitstream_vbuf);
1002         return ret;
1003 }
1004
1005 static int wave5_vpu_dec_start_streaming_open(struct vpu_instance *inst)
1006 {
1007         struct dec_initial_info initial_info;
1008         unsigned int scalew, scaleh;
1009         int ret = 0;
1010
1011         memset(&initial_info, 0, sizeof(struct dec_initial_info));
1012
1013         ret = wave5_vpu_dec_issue_seq_init(inst);
1014         if (ret) {
1015                 dev_err(inst->dev->dev, "%s: wave5_vpu_dec_issue_seq_init, fail: %d\n",
1016                         __func__, ret);
1017                 return ret;
1018         }
1019
1020         if (wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT) < 0)
1021                 dev_err(inst->dev->dev, "%s: failed to call vpu_wait_interrupt()\n", __func__);
1022
1023         ret = wave5_vpu_dec_complete_seq_init(inst, &initial_info);
1024         if (ret) {
1025                 dev_err(inst->dev->dev, "%s: vpu_dec_complete_seq_init, fail: %d, reason: %u\n",
1026                         __func__, ret, initial_info.seq_init_err_reason);
1027         } else {
1028                 static const struct v4l2_event vpu_event_src_ch = {
1029                         .type = V4L2_EVENT_SOURCE_CHANGE,
1030                         .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
1031                 };
1032                 struct v4l2_ctrl *ctrl;
1033
1034                 dev_dbg(inst->dev->dev, "%s: width: %u height: %u profile: %u | minbuffer: %u\n",
1035                         __func__, initial_info.pic_width, initial_info.pic_height,
1036                         initial_info.profile, initial_info.min_frame_buffer_count);
1037
1038                 inst->state = VPU_INST_STATE_INIT_SEQ;
1039                 //printk("wave5 state = %d\n",inst->state);
1040                 inst->min_dst_buf_count = initial_info.min_frame_buffer_count + 1;
1041                 inst->dst_buf_count = inst->min_dst_buf_count;
1042
1043                 inst->conf_win_width = initial_info.pic_width - initial_info.pic_crop_rect.right;
1044                 inst->conf_win_height = initial_info.pic_height - initial_info.pic_crop_rect.bottom;
1045
1046                 ctrl = v4l2_ctrl_find(&inst->v4l2_ctrl_hdl,
1047                                       V4L2_CID_MIN_BUFFERS_FOR_CAPTURE);
1048                 if (ctrl)
1049                         v4l2_ctrl_s_ctrl(ctrl, inst->min_dst_buf_count);
1050
1051                 if (initial_info.pic_width != inst->src_fmt.width ||
1052                     initial_info.pic_height != inst->src_fmt.height) {
1053                         if (inst->std == W_AVC_DEC) {
1054                                 wave5_update_pix_fmt(&inst->src_fmt, initial_info.pic_width,
1055                                                         initial_info.pic_height);
1056                                 wave5_update_pix_fmt(&inst->dst_fmt, initial_info.pic_width,
1057                                                         initial_info.pic_height);
1058                         } else { //HEVC
1059                                 wave5_update_pix_fmt_r8(&inst->src_fmt, initial_info.pic_width,
1060                                                         initial_info.pic_height);
1061                                 wave5_update_pix_fmt_r8(&inst->dst_fmt, initial_info.pic_width,
1062                                                         initial_info.pic_height);
1063                         }
1064                 }
1065                 inst->crop_rect.right = initial_info.pic_crop_rect.right;
1066                 inst->crop_rect.bottom = initial_info.pic_crop_rect.bottom;
1067
1068                 scalew = inst->dst_fmt.width / inst->display_fmt.width;
1069                 scaleh = inst->dst_fmt.height / inst->display_fmt.height;
1070
1071                 if (scalew > 8 || scaleh > 8 || scalew < 1 || scaleh < 1) {
1072                         wave5_update_pix_fmt(&inst->display_fmt, inst->dst_fmt.width,
1073                                                 inst->dst_fmt.height);
1074                 }
1075
1076                 dev_dbg(inst->dev->dev, "wave5 queue event type: %d id: %d\n",vpu_event_src_ch.type, vpu_event_src_ch.id);
1077                 v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_src_ch);
1078
1079                 wave5_handle_src_buffer(inst);
1080         }
1081
1082         return ret;
1083 }
1084
1085 static int wave5_vpu_dec_start_streaming_seek(struct vpu_instance *inst)
1086 {
1087         struct dec_initial_info initial_info;
1088         struct dec_param pic_param;
1089         struct dec_output_info dec_output_info;
1090         unsigned int scalew, scaleh;
1091         int ret = 0;
1092         u32 fail_res = 0;
1093
1094         memset(&pic_param, 0, sizeof(struct dec_param));
1095
1096         ret = wave5_vpu_dec_start_one_frame(inst, &pic_param, &fail_res);
1097         if (ret && fail_res != WAVE5_SYSERR_QUEUEING_FAIL) {
1098                 struct vb2_v4l2_buffer *src_buf;
1099
1100                 src_buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx);
1101                 inst->state = VPU_INST_STATE_STOP;
1102                 //printk("%d wave5 state = %d\n",__LINE__, inst->state);
1103                 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR);
1104                 dev_dbg(inst->dev->dev, "%s: wave5_vpu_dec_start_one_frame\n", __func__);
1105                 return ret;
1106         }
1107
1108         if (wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT) < 0)
1109                 dev_dbg(inst->dev->dev, "%s: failed to call vpu_wait_interrupt()\n", __func__);
1110
1111         ret = wave5_vpu_dec_get_output_info(inst, &dec_output_info);
1112         if (ret) {
1113                 dev_dbg(inst->dev->dev, "%s: wave5_vpu_dec_get_output_info, fail: %d\n",
1114                         __func__, ret);
1115                 return ret;
1116         }
1117
1118         if (dec_output_info.sequence_changed) {
1119                 static const struct v4l2_event vpu_event_src_ch = {
1120                         .type = V4L2_EVENT_SOURCE_CHANGE,
1121                         .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
1122                 };
1123                 struct v4l2_ctrl *ctrl;
1124
1125                 wave5_vpu_dec_give_command(inst, DEC_RESET_FRAMEBUF_INFO, NULL);
1126                 wave5_vpu_dec_give_command(inst, DEC_GET_SEQ_INFO, &initial_info);
1127
1128                 dev_dbg(inst->dev->dev, "%s: width: %u height: %u profile: %u | minbuffer: %u\n",
1129                         __func__, initial_info.pic_width, initial_info.pic_height,
1130                         initial_info.profile, initial_info.min_frame_buffer_count);
1131
1132                 inst->min_dst_buf_count = initial_info.min_frame_buffer_count + 1;
1133                 inst->dst_buf_count = inst->min_dst_buf_count;
1134
1135                 inst->conf_win_width = initial_info.pic_width - initial_info.pic_crop_rect.right;
1136                 inst->conf_win_height = initial_info.pic_height - initial_info.pic_crop_rect.bottom;
1137
1138                 ctrl = v4l2_ctrl_find(&inst->v4l2_ctrl_hdl,
1139                                       V4L2_CID_MIN_BUFFERS_FOR_CAPTURE);
1140                 if (ctrl)
1141                         v4l2_ctrl_s_ctrl(ctrl, inst->min_dst_buf_count);
1142
1143                 if (initial_info.pic_width != inst->src_fmt.width ||
1144                     initial_info.pic_height != inst->src_fmt.height) {
1145                         if (inst->std == W_AVC_DEC) {
1146                                 wave5_update_pix_fmt(&inst->src_fmt, initial_info.pic_width,
1147                                                         initial_info.pic_height);
1148                                 wave5_update_pix_fmt(&inst->dst_fmt, initial_info.pic_width,
1149                                                         initial_info.pic_height);
1150                         } else { //HEVC
1151                                 wave5_update_pix_fmt_r8(&inst->src_fmt, initial_info.pic_width,
1152                                                         initial_info.pic_height);
1153                                 wave5_update_pix_fmt_r8(&inst->dst_fmt, initial_info.pic_width,
1154                                                         initial_info.pic_height);
1155                         }
1156                 }
1157                 inst->crop_rect.right = initial_info.pic_crop_rect.right;
1158                 inst->crop_rect.bottom = initial_info.pic_crop_rect.bottom;
1159
1160                 scalew = inst->dst_fmt.width / inst->display_fmt.width;
1161                 scaleh = inst->dst_fmt.height / inst->display_fmt.height;
1162
1163                 if (scalew > 8 || scaleh > 8 || scalew < 1 || scaleh < 1) {
1164                         wave5_update_pix_fmt(&inst->display_fmt, inst->dst_fmt.width,
1165                                                 inst->dst_fmt.height);
1166                 }
1167
1168                 v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_src_ch);
1169
1170                 wave5_handle_src_buffer(inst);
1171         }
1172
1173         return ret;
1174 }
1175
1176 static void wave5_vpu_dec_buf_queue_src(struct vb2_buffer *vb)
1177 {
1178         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1179         struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue);
1180         struct vpu_buffer *vpu_buf = wave5_to_vpu_buf(vbuf);
1181
1182         vpu_buf->consumed = false;
1183         vbuf->sequence = inst->queued_src_buf_num++;
1184
1185         if (inst->state == VPU_INST_STATE_PIC_RUN) {
1186                 wave5_handle_bitstream_buffer(inst);
1187                 inst->ops->start_process(inst);
1188         }
1189 }
1190
1191 static void wave5_vpu_dec_buf_queue_dst(struct vb2_buffer *vb)
1192 {
1193         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1194         struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue);
1195         int ret;
1196
1197         vbuf->sequence = inst->queued_dst_buf_num++;
1198         ret = wave5_vpu_dec_clr_disp_flag(inst, vb->index);
1199         if (ret) {
1200                 dev_dbg(inst->dev->dev,
1201                         "%s: Clearing the display flag of buffer index: %u, fail: %d\n",
1202                         __func__, vb->index, ret);
1203         }
1204
1205         if (inst->state == VPU_INST_STATE_INIT_SEQ) {
1206                 dma_addr_t buf_addr_y = 0, buf_addr_cb = 0, buf_addr_cr = 0;
1207                 u32 buf_size = 0;
1208                 u32 non_linear_num = inst->dst_buf_count;
1209                 u32 fb_stride = inst->display_fmt.width;
1210                 u32 luma_size = fb_stride * inst->display_fmt.height;
1211                 u32 chroma_size = (fb_stride / 2) * (inst->display_fmt.height / 2);
1212
1213                 if (inst->display_fmt.num_planes == 1) {
1214                         buf_size = vb2_plane_size(&vbuf->vb2_buf, 0);
1215                         buf_addr_y = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0);
1216                         buf_addr_cb = buf_addr_y + luma_size;
1217                         buf_addr_cr = buf_addr_cb + chroma_size;
1218                 } else if (inst->display_fmt.num_planes == 2) {
1219                         buf_size = vb2_plane_size(&vbuf->vb2_buf, 0) +
1220                                 vb2_plane_size(&vbuf->vb2_buf, 1);
1221                         buf_addr_y = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0);
1222                         buf_addr_cb = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 1);
1223                         buf_addr_cr = buf_addr_cb + chroma_size;
1224                 } else if (inst->display_fmt.num_planes == 3) {
1225                         buf_size = vb2_plane_size(&vbuf->vb2_buf, 0) +
1226                                 vb2_plane_size(&vbuf->vb2_buf, 1) +
1227                                 vb2_plane_size(&vbuf->vb2_buf, 2);
1228                         buf_addr_y = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0);
1229                         buf_addr_cb = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 1);
1230                         buf_addr_cr = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 2);
1231                 }
1232                 inst->frame_buf[vb->index + non_linear_num].buf_y = buf_addr_y;
1233                 inst->frame_buf[vb->index + non_linear_num].buf_cb = buf_addr_cb;
1234                 inst->frame_buf[vb->index + non_linear_num].buf_cr = buf_addr_cr;
1235                 inst->frame_buf[vb->index + non_linear_num].size = buf_size;
1236                 inst->frame_buf[vb->index + non_linear_num].width = inst->display_fmt.width;
1237                 inst->frame_buf[vb->index + non_linear_num].stride = fb_stride;
1238                 inst->frame_buf[vb->index + non_linear_num].map_type = LINEAR_FRAME_MAP;
1239                 inst->frame_buf[vb->index + non_linear_num].update_fb_info = true;
1240                 dev_dbg(inst->dev->dev, "linear framebuf y 0x%llx cb 0x%llx cr 0x%llx\n",buf_addr_y, buf_addr_cb, buf_addr_cr);
1241         }
1242
1243         if (!vb2_is_streaming(vb->vb2_queue))
1244                 return;
1245
1246         if (inst->state == VPU_INST_STATE_STOP && inst->eos == FALSE)
1247                 inst->ops->start_process(inst);
1248 }
1249
1250 static void wave5_vpu_dec_buf_queue(struct vb2_buffer *vb)
1251 {
1252         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1253         struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue);
1254
1255         dev_dbg(inst->dev->dev, "%s: type: %4u index: %4u size: ([0]=%4lu, [1]=%4lu, [2]=%4lu)\n",
1256                 __func__, vb->type, vb->index, vb2_get_plane_payload(&vbuf->vb2_buf, 0),
1257                 vb2_get_plane_payload(&vbuf->vb2_buf, 1), vb2_get_plane_payload(&vbuf->vb2_buf, 2));
1258
1259         v4l2_m2m_buf_queue(inst->v4l2_fh.m2m_ctx, vbuf);
1260
1261         if (vb->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1262                 wave5_vpu_dec_buf_queue_src(vb);
1263         else if (vb->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1264                 wave5_vpu_dec_buf_queue_dst(vb);
1265 }
1266
1267 static int wave5_vpu_dec_start_streaming(struct vb2_queue *q, unsigned int count)
1268 {
1269         struct vpu_instance *inst = vb2_get_drv_priv(q);
1270         int ret = 0;
1271
1272         dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type);
1273
1274         if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1275                 wave5_handle_bitstream_buffer(inst);
1276                 if (inst->state == VPU_INST_STATE_OPEN)
1277                         ret = wave5_vpu_dec_start_streaming_open(inst);
1278                 else if (inst->state == VPU_INST_STATE_INIT_SEQ)
1279                         ret = wave5_vpu_dec_start_streaming_seek(inst);
1280
1281                 if (ret) {
1282                         struct vb2_v4l2_buffer *buf;
1283
1284                         while ((buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx))) {
1285                                 dev_dbg(inst->dev->dev, "%s: (Multiplanar) buf type %4d | index %4d\n",
1286                                             __func__, buf->vb2_buf.type, buf->vb2_buf.index);
1287                                 v4l2_m2m_buf_done(buf, VB2_BUF_STATE_QUEUED);
1288                         }
1289                 }
1290         }
1291
1292         return ret;
1293 }
1294
1295 static void wave5_vpu_dec_stop_streaming(struct vb2_queue *q)
1296 {
1297         struct vpu_instance *inst = vb2_get_drv_priv(q);
1298         struct vb2_v4l2_buffer *buf;
1299         int try_cnt = 0;
1300         bool check_cmd = TRUE;
1301
1302         dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type);
1303
1304         while (check_cmd) {
1305                 struct queue_status_info q_status;
1306                 struct dec_output_info dec_output_info;
1307
1308                 wave5_vpu_dec_give_command(inst, DEC_GET_QUEUE_STATUS, &q_status);
1309
1310                 if (q_status.instance_queue_count + q_status.report_queue_count == 0)
1311                         break;
1312
1313                 if (wave5_vpu_wait_interrupt(inst, 600) < 0){
1314                         try_cnt++;
1315                         if (try_cnt >= 10)
1316                                 break;
1317                         continue;
1318                 }
1319
1320                 if (wave5_vpu_dec_get_output_info(inst, &dec_output_info))
1321                         dev_dbg(inst->dev->dev, "Getting decoding results from fw, fail\n");
1322         }
1323
1324         if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1325                 while ((buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx))) {
1326                         dev_dbg(inst->dev->dev, "%s: (Multiplanar) buf type %4u | index %4u\n",
1327                                 __func__, buf->vb2_buf.type, buf->vb2_buf.index);
1328                         v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR);
1329                 }
1330                 inst->queued_src_buf_num = 0;
1331         } else {
1332                 unsigned int i;
1333                 int ret;
1334                 dma_addr_t rd_ptr, wr_ptr;
1335
1336                 while ((buf = v4l2_m2m_dst_buf_remove(inst->v4l2_fh.m2m_ctx))) {
1337                         u32 plane;
1338
1339                         dev_dbg(inst->dev->dev, "%s: buf type %4u | index %4u\n",
1340                                 __func__, buf->vb2_buf.type, buf->vb2_buf.index);
1341
1342                         for (plane = 0; plane < inst->dst_fmt.num_planes; plane++)
1343                                 vb2_set_plane_payload(&buf->vb2_buf, plane, 0);
1344
1345                         v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR);
1346                 }
1347
1348                 for (i = 0; i < inst->dst_buf_count; i++) {
1349                         ret = wave5_vpu_dec_set_disp_flag(inst, i);
1350                         if (ret) {
1351                                 dev_dbg(inst->dev->dev,
1352                                         "%s: Setting display flag of buf index: %u, fail: %d\n",
1353                                         __func__, i, ret);
1354                         }
1355                 }
1356
1357                 ret = wave5_vpu_dec_get_bitstream_buffer(inst, &rd_ptr, &wr_ptr, NULL);
1358                 if (ret) {
1359                         dev_err(inst->dev->dev,
1360                                 "Getting bitstream buf, fail: %d\n", ret);
1361                         return;
1362                 }
1363                 ret = wave5_vpu_dec_set_rd_ptr(inst, wr_ptr, TRUE);
1364                 if (ret) {
1365                         dev_err(inst->dev->dev,
1366                                 "Setting read pointer for the decoder, fail: %d\n", ret);
1367                         return;
1368                 }
1369                 if (inst->eos) {
1370                         inst->eos = FALSE;
1371                         inst->state = VPU_INST_STATE_INIT_SEQ;
1372                         //printk("wave5 state = %d\n",inst->state);
1373                 }
1374                 inst->queued_dst_buf_num = 0;
1375         }
1376 }
1377
1378 static const struct vb2_ops wave5_vpu_dec_vb2_ops = {
1379         .queue_setup = wave5_vpu_dec_queue_setup,
1380         .wait_prepare = vb2_ops_wait_prepare,
1381         .wait_finish = vb2_ops_wait_finish,
1382         .buf_queue = wave5_vpu_dec_buf_queue,
1383         .start_streaming = wave5_vpu_dec_start_streaming,
1384         .stop_streaming = wave5_vpu_dec_stop_streaming,
1385 };
1386
1387 static void wave5_set_default_format(struct v4l2_pix_format_mplane *src_fmt,
1388                                      struct v4l2_pix_format_mplane *dst_fmt)
1389 {
1390         unsigned int dst_pix_fmt = dec_fmt_list[VPU_FMT_TYPE_RAW][0].v4l2_pix_fmt;
1391         const struct v4l2_format_info *dst_fmt_info = v4l2_format_info(dst_pix_fmt);
1392
1393         src_fmt->pixelformat = dec_fmt_list[VPU_FMT_TYPE_CODEC][0].v4l2_pix_fmt;
1394         src_fmt->field = V4L2_FIELD_NONE;
1395         src_fmt->flags = 0;
1396         src_fmt->num_planes = 1;
1397         wave5_update_pix_fmt(src_fmt, 720, 480);
1398
1399         dst_fmt->pixelformat = dst_pix_fmt;
1400         dst_fmt->field = V4L2_FIELD_NONE;
1401         dst_fmt->flags = 0;
1402         dst_fmt->num_planes = dst_fmt_info->mem_planes;
1403         wave5_update_pix_fmt(dst_fmt, 736, 480);
1404 }
1405
1406 static int wave5_vpu_dec_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)
1407 {
1408         return wave5_vpu_queue_init(priv, src_vq, dst_vq, &wave5_vpu_dec_vb2_ops);
1409 }
1410
1411 static const struct vpu_instance_ops wave5_vpu_dec_inst_ops = {
1412         .start_process = wave5_vpu_dec_start_decode,
1413         .stop_process = wave5_vpu_dec_stop_decode,
1414         .finish_process = wave5_vpu_dec_finish_decode,
1415 };
1416
1417 static void wave5_vpu_dec_device_run(void *priv)
1418 {
1419         struct vpu_instance *inst = priv;
1420
1421         wave5_handle_bitstream_buffer(inst);
1422         inst->ops->start_process(inst);
1423
1424         inst->state = VPU_INST_STATE_PIC_RUN;
1425         //printk("wave5 state = %d\n",inst->state);
1426 }
1427
1428 static void wave5_vpu_dec_job_abort(void *priv)
1429 {
1430         struct vpu_instance *inst = priv;
1431
1432         inst->ops->stop_process(inst);
1433 }
1434
1435 static const struct v4l2_m2m_ops wave5_vpu_dec_m2m_ops = {
1436         .device_run = wave5_vpu_dec_device_run,
1437         .job_abort = wave5_vpu_dec_job_abort,
1438 };
1439
1440 static int wave5_vpu_open_dec(struct file *filp)
1441 {
1442         struct video_device *vdev = video_devdata(filp);
1443         struct vpu_device *dev = video_drvdata(filp);
1444         struct vpu_instance *inst = NULL;
1445         int ret = 0;
1446
1447         inst = kzalloc(sizeof(*inst), GFP_KERNEL);
1448         if (!inst)
1449                 return -ENOMEM;
1450
1451         inst->dev = dev;
1452         inst->type = VPU_INST_TYPE_DEC;
1453         inst->ops = &wave5_vpu_dec_inst_ops;
1454
1455         v4l2_fh_init(&inst->v4l2_fh, vdev);
1456         filp->private_data = &inst->v4l2_fh;
1457         v4l2_fh_add(&inst->v4l2_fh);
1458
1459         INIT_LIST_HEAD(&inst->list);
1460         list_add_tail(&inst->list, &dev->instances);
1461
1462         inst->v4l2_m2m_dev = v4l2_m2m_init(&wave5_vpu_dec_m2m_ops);
1463         if (IS_ERR(inst->v4l2_m2m_dev)) {
1464                 ret = PTR_ERR(inst->v4l2_m2m_dev);
1465                 dev_err(inst->dev->dev, "v4l2_m2m_init, fail: %d\n", ret);
1466                 goto cleanup_inst;
1467         }
1468
1469         inst->v4l2_fh.m2m_ctx =
1470                 v4l2_m2m_ctx_init(inst->v4l2_m2m_dev, inst, wave5_vpu_dec_queue_init);
1471         if (IS_ERR(inst->v4l2_fh.m2m_ctx)) {
1472                 ret = PTR_ERR(inst->v4l2_fh.m2m_ctx);
1473                 goto cleanup_inst;
1474         }
1475
1476         v4l2_ctrl_handler_init(&inst->v4l2_ctrl_hdl, 10);
1477         v4l2_ctrl_new_custom(&inst->v4l2_ctrl_hdl, &wave5_vpu_thumbnail_mode, NULL);
1478         v4l2_ctrl_new_std(&inst->v4l2_ctrl_hdl, &wave5_vpu_dec_ctrl_ops,
1479                           V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 32, 1, 1);
1480
1481         if (inst->v4l2_ctrl_hdl.error) {
1482                 ret = -ENODEV;
1483                 goto cleanup_inst;
1484         }
1485
1486         inst->v4l2_fh.ctrl_handler = &inst->v4l2_ctrl_hdl;
1487         v4l2_ctrl_handler_setup(&inst->v4l2_ctrl_hdl);
1488
1489         wave5_set_default_format(&inst->src_fmt, &inst->dst_fmt);
1490         memcpy((void *)&inst->display_fmt, (void *)&inst->dst_fmt, sizeof(struct v4l2_pix_format_mplane));
1491         inst->colorspace = V4L2_COLORSPACE_REC709;
1492         inst->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
1493         inst->hsv_enc = 0;
1494         inst->quantization = V4L2_QUANTIZATION_DEFAULT;
1495         inst->xfer_func = V4L2_XFER_FUNC_DEFAULT;
1496
1497         init_completion(&inst->irq_done);
1498         ret = kfifo_alloc(&inst->irq_status, 16 * sizeof(int), GFP_KERNEL);
1499         if (ret) {
1500                 dev_err(inst->dev->dev, "failed to allocate fifo\n");
1501                 goto cleanup_inst;
1502         }
1503
1504         inst->id = ida_alloc(&inst->dev->inst_ida, GFP_KERNEL);
1505         if (inst->id < 0) {
1506                 dev_warn(inst->dev->dev, "Allocating instance ID, fail: %d\n", inst->id);
1507                 ret = inst->id;
1508                 goto cleanup_inst;
1509         }
1510
1511         return 0;
1512
1513 cleanup_inst:
1514         wave5_cleanup_instance(inst);
1515         return ret;
1516 }
1517
1518 static int wave5_vpu_dec_release(struct file *filp)
1519 {
1520         return wave5_vpu_release_device(filp, wave5_vpu_dec_close, "decoder");
1521 }
1522
1523 static const struct v4l2_file_operations wave5_vpu_dec_fops = {
1524         .owner = THIS_MODULE,
1525         .open = wave5_vpu_open_dec,
1526         .release = wave5_vpu_dec_release,
1527         .unlocked_ioctl = video_ioctl2,
1528         .poll = v4l2_m2m_fop_poll,
1529         .mmap = v4l2_m2m_fop_mmap,
1530 };
1531
1532 int wave5_vpu_dec_register_device(struct vpu_device *dev)
1533 {
1534         struct video_device *vdev_dec;
1535         int ret;
1536
1537         vdev_dec = devm_kzalloc(dev->v4l2_dev.dev, sizeof(*vdev_dec), GFP_KERNEL);
1538         if (!vdev_dec)
1539                 return -ENOMEM;
1540
1541         dev->video_dev_dec = vdev_dec;
1542
1543         strscpy(vdev_dec->name, VPU_DEC_DEV_NAME, sizeof(vdev_dec->name));
1544         vdev_dec->fops = &wave5_vpu_dec_fops;
1545         vdev_dec->ioctl_ops = &wave5_vpu_dec_ioctl_ops;
1546         vdev_dec->release = video_device_release_empty;
1547         vdev_dec->v4l2_dev = &dev->v4l2_dev;
1548         vdev_dec->vfl_dir = VFL_DIR_M2M;
1549         vdev_dec->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;
1550         vdev_dec->lock = &dev->dev_lock;
1551
1552         ret = video_register_device(vdev_dec, VFL_TYPE_VIDEO, -1);
1553         if (ret)
1554                 return ret;
1555
1556         video_set_drvdata(vdev_dec, dev);
1557
1558         return 0;
1559 }
1560
1561 void wave5_vpu_dec_unregister_device(struct vpu_device *dev)
1562 {
1563         video_unregister_device(dev->video_dev_dec);
1564 }