1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Microchip Image Sensor Controller (ISC) driver header file
5 * Copyright (C) 2016-2019 Microchip Technology, Inc.
8 * Author: Eugen Hristev <eugen.hristev@microchip.com>
13 #include <linux/clk-provider.h>
14 #include <linux/platform_device.h>
16 #include <media/v4l2-ctrls.h>
17 #include <media/v4l2-device.h>
18 #include <media/videobuf2-dma-contig.h>
20 #define ISC_CLK_MAX_DIV 255
30 struct regmap *regmap;
31 spinlock_t lock; /* serialize access to clock registers */
38 #define to_isc_clk(v) container_of(v, struct isc_clk, hw)
41 struct vb2_v4l2_buffer vb;
42 struct list_head list;
45 struct isc_subdev_entity {
46 struct v4l2_subdev *sd;
47 struct v4l2_async_subdev *asd;
48 struct device_node *epn;
49 struct v4l2_async_notifier notifier;
53 struct list_head list;
57 * struct isc_format - ISC media bus format information
58 This structure represents the interface between the ISC
59 and the sensor. It's the input format received by
61 * @fourcc: Fourcc code for this format
62 * @mbus_code: V4L2 media bus format code.
63 * @cfa_baycfg: If this format is RAW BAYER, indicate the type of bayer.
64 this is either BGBG, RGRG, etc.
65 * @pfe_cfg0_bps: Number of hardware data lines connected to the ISC
78 #define DPC_DPCENABLE BIT(0)
79 #define DPC_GDCENABLE BIT(1)
80 #define DPC_BLCENABLE BIT(2)
81 #define WB_ENABLE BIT(3)
82 #define CFA_ENABLE BIT(4)
83 #define CC_ENABLE BIT(5)
84 #define GAM_ENABLE BIT(6)
85 #define GAM_BENABLE BIT(7)
86 #define GAM_GENABLE BIT(8)
87 #define GAM_RENABLE BIT(9)
88 #define VHXS_ENABLE BIT(10)
89 #define CSC_ENABLE BIT(11)
90 #define CBC_ENABLE BIT(12)
91 #define SUB422_ENABLE BIT(13)
92 #define SUB420_ENABLE BIT(14)
94 #define GAM_ENABLES (GAM_RENABLE | GAM_GENABLE | GAM_BENABLE | GAM_ENABLE)
97 * struct fmt_config - ISC format configuration and internal pipeline
98 This structure represents the internal configuration
100 It also holds the format that ISC will present to v4l2.
101 * @sd_format: Pointer to an isc_format struct that holds the sensor
103 * @fourcc: Fourcc code for this format.
104 * @bpp: Bytes per pixel in the current format.
105 * @bpp_v4l2: Bytes per pixel in the current format, for v4l2.
106 This differs from 'bpp' in the sense that in planar
107 formats, it refers only to the first plane.
108 * @rlp_cfg_mode: Configuration of the RLP (rounding, limiting packaging)
109 * @dcfg_imode: Configuration of the input of the DMA module
110 * @dctrl_dview: Configuration of the output of the DMA module
111 * @bits_pipeline: Configuration of the pipeline, which modules are enabled
114 struct isc_format *sd_format;
127 #define HIST_ENTRIES 512
128 #define HIST_BAYER (ISC_HIS_CFG_MODE_B + 1)
137 struct v4l2_ctrl_handler handler;
142 #define ISC_WB_NONE 0
143 #define ISC_WB_AUTO 1
144 #define ISC_WB_ONETIME 2
147 /* one for each component : GR, R, GB, B */
148 u32 gain[HIST_BAYER];
149 s32 offset[HIST_BAYER];
151 u32 hist_entry[HIST_ENTRIES];
152 u32 hist_count[HIST_BAYER];
155 #define HIST_MIN_INDEX 0
156 #define HIST_MAX_INDEX 1
157 u32 hist_minmax[HIST_BAYER][2];
160 #define ISC_PIPE_LINE_NODE_NUM 15
163 * struct isc_reg_offsets - ISC device register offsets
164 * @csc: Offset for the CSC register
165 * @cbc: Offset for the CBC register
166 * @sub422: Offset for the SUB422 register
167 * @sub420: Offset for the SUB420 register
168 * @rlp: Offset for the RLP register
169 * @his: Offset for the HIS related registers
170 * @dma: Offset for the DMA related registers
171 * @version: Offset for the version register
172 * @his_entry: Offset for the HIS entries registers
174 struct isc_reg_offsets {
187 * struct isc_device - ISC device driver data/config struct
188 * @regmap: Register map
189 * @hclock: Hclock clock input (refer datasheet)
190 * @ispck: iscpck clock (refer datasheet)
191 * @isc_clks: ISC clocks
192 * @ispck_required: ISC requires ISP Clock initialization
193 * @dcfg: DMA master configuration, architecture dependent
195 * @dev: Registered device driver
196 * @v4l2_dev: v4l2 registered device
197 * @video_dev: registered video device
199 * @vb2_vidq: video buffer 2 video queue
200 * @dma_queue_lock: lock to serialize the dma buffer queue
201 * @dma_queue: the queue for dma buffers
202 * @cur_frm: current isc frame/buffer
203 * @sequence: current frame number
204 * @stop: true if isc is not streaming, false if streaming
205 * @comp: completion reference that signals frame completion
207 * @fmt: current v42l format
208 * @user_formats: list of formats that are supported and agreed with sd
209 * @num_user_formats: how many formats are in user_formats
211 * @config: current ISC format configuration
212 * @try_config: the current ISC try format , not yet activated
214 * @ctrls: holds information about ISC controls
215 * @do_wb_ctrl: control regarding the DO_WHITE_BALANCE button
216 * @awb_work: workqueue reference for autowhitebalance histogram
219 * @lock: lock for serializing userspace file operations
220 * with ISC operations
221 * @awb_lock: lock for serializing awb work queue operations
222 * with DMA/buffer operations
224 * @pipeline: configuration of the ISC pipeline
226 * @current_subdev: current subdevice: the sensor
227 * @subdev_entities: list of subdevice entitites
229 * @gamma_table: pointer to the table with gamma values, has
230 * gamma_max sets of GAMMA_ENTRIES entries each
231 * @gamma_max: maximum number of sets of inside the gamma_table
233 * @max_width: maximum frame width, dependent on the internal RAM
234 * @max_height: maximum frame height, dependent on the internal RAM
236 * @config_dpc: pointer to a function that initializes product
237 * specific DPC module
238 * @config_csc: pointer to a function that initializes product
239 * specific CSC module
240 * @config_cbc: pointer to a function that initializes product
241 * specific CBC module
242 * @config_cc: pointer to a function that initializes product
244 * @config_gam: pointer to a function that initializes product
245 * specific GAMMA module
246 * @config_rlp: pointer to a function that initializes product
247 * specific RLP module
248 * @config_ctrls: pointer to a functoin that initializes product
249 * specific v4l2 controls.
251 * @adapt_pipeline: pointer to a function that adapts the pipeline bits
252 * to the product specific pipeline
254 * @offsets: struct holding the product specific register offsets
255 * @controller_formats: pointer to the array of possible formats that the
256 * controller can output
257 * @formats_list: pointer to the array of possible formats that can
258 * be used as an input to the controller
259 * @controller_formats_size: size of controller_formats array
260 * @formats_list_size: size of formats_list array
263 struct regmap *regmap;
266 struct isc_clk isc_clks[2];
271 struct v4l2_device v4l2_dev;
272 struct video_device video_dev;
274 struct vb2_queue vb2_vidq;
275 spinlock_t dma_queue_lock;
276 struct list_head dma_queue;
277 struct isc_buffer *cur_frm;
278 unsigned int sequence;
280 struct completion comp;
282 struct v4l2_format fmt;
283 struct isc_format **user_formats;
284 unsigned int num_user_formats;
286 struct fmt_config config;
287 struct fmt_config try_config;
289 struct isc_ctrls ctrls;
290 struct work_struct awb_work;
295 struct regmap_field *pipeline[ISC_PIPE_LINE_NODE_NUM];
297 struct isc_subdev_entity *current_subdev;
298 struct list_head subdev_entities;
301 #define ISC_CTRL_DO_WB 1
302 #define ISC_CTRL_R_GAIN 2
303 #define ISC_CTRL_B_GAIN 3
304 #define ISC_CTRL_GR_GAIN 4
305 #define ISC_CTRL_GB_GAIN 5
306 #define ISC_CTRL_R_OFF 6
307 #define ISC_CTRL_B_OFF 7
308 #define ISC_CTRL_GR_OFF 8
309 #define ISC_CTRL_GB_OFF 9
310 struct v4l2_ctrl *awb_ctrl;
311 struct v4l2_ctrl *do_wb_ctrl;
312 struct v4l2_ctrl *r_gain_ctrl;
313 struct v4l2_ctrl *b_gain_ctrl;
314 struct v4l2_ctrl *gr_gain_ctrl;
315 struct v4l2_ctrl *gb_gain_ctrl;
316 struct v4l2_ctrl *r_off_ctrl;
317 struct v4l2_ctrl *b_off_ctrl;
318 struct v4l2_ctrl *gr_off_ctrl;
319 struct v4l2_ctrl *gb_off_ctrl;
322 #define GAMMA_ENTRIES 64
323 /* pointer to the defined gamma table */
324 const u32 (*gamma_table)[GAMMA_ENTRIES];
331 void (*config_dpc)(struct isc_device *isc);
332 void (*config_csc)(struct isc_device *isc);
333 void (*config_cbc)(struct isc_device *isc);
334 void (*config_cc)(struct isc_device *isc);
335 void (*config_gam)(struct isc_device *isc);
336 void (*config_rlp)(struct isc_device *isc);
338 void (*config_ctrls)(struct isc_device *isc,
339 const struct v4l2_ctrl_ops *ops);
341 void (*adapt_pipeline)(struct isc_device *isc);
344 struct isc_reg_offsets offsets;
345 const struct isc_format *controller_formats;
346 struct isc_format *formats_list;
347 u32 controller_formats_size;
348 u32 formats_list_size;
351 extern const struct regmap_config isc_regmap_config;
352 extern const struct v4l2_async_notifier_operations isc_async_ops;
354 irqreturn_t isc_interrupt(int irq, void *dev_id);
355 int isc_pipeline_init(struct isc_device *isc);
356 int isc_clk_init(struct isc_device *isc);
357 void isc_subdev_cleanup(struct isc_device *isc);
358 void isc_clk_cleanup(struct isc_device *isc);