drivers/media/platform/atmel/atmel-isc-base.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Microchip Image Sensor Controller (ISC) common driver base
   4  *
   5  * Copyright (C) 2016-2019 Microchip Technology, Inc.
   6  *
   7  * Author: Songjun Wu
   8  * Author: Eugen Hristev <eugen.hristev@microchip.com>
   9  *
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clkdev.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/delay.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/math64.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_graph.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/regmap.h>
  24 #include <linux/videodev2.h>
  25 #include <linux/atmel-isc-media.h>
  26
  27 #include <media/v4l2-ctrls.h>
  28 #include <media/v4l2-device.h>
  29 #include <media/v4l2-event.h>
  30 #include <media/v4l2-image-sizes.h>
  31 #include <media/v4l2-ioctl.h>
  32 #include <media/v4l2-fwnode.h>
  33 #include <media/v4l2-subdev.h>
  34 #include <media/videobuf2-dma-contig.h>
  35
  36 #include "atmel-isc-regs.h"
  37 #include "atmel-isc.h"
  38
  39 static unsigned int debug;
  40 module_param(debug, int, 0644);
  41 MODULE_PARM_DESC(debug, "debug level (0-2)");
  42
  43 static unsigned int sensor_preferred = 1;
  44 module_param(sensor_preferred, uint, 0644);
  45 MODULE_PARM_DESC(sensor_preferred,
  46                  "Sensor is preferred to output the specified format (1-on 0-off), default 1");
  47
  48 /* This is a list of the formats that the ISC can *output* */
  49 const struct isc_format controller_formats[] = {
  50         {
  51                 .fourcc         = V4L2_PIX_FMT_ARGB444,
  52         },
  53         {
  54                 .fourcc         = V4L2_PIX_FMT_ARGB555,
  55         },
  56         {
  57                 .fourcc         = V4L2_PIX_FMT_RGB565,
  58         },
  59         {
  60                 .fourcc         = V4L2_PIX_FMT_ABGR32,
  61         },
  62         {
  63                 .fourcc         = V4L2_PIX_FMT_XBGR32,
  64         },
  65         {
  66                 .fourcc         = V4L2_PIX_FMT_YUV420,
  67         },
  68         {
  69                 .fourcc         = V4L2_PIX_FMT_YUYV,
  70         },
  71         {
  72                 .fourcc         = V4L2_PIX_FMT_YUV422P,
  73         },
  74         {
  75                 .fourcc         = V4L2_PIX_FMT_GREY,
  76         },
  77         {
  78                 .fourcc         = V4L2_PIX_FMT_Y10,
  79         },
  80 };
  81
  82 /* This is a list of formats that the ISC can receive as *input* */
  83 struct isc_format formats_list[] = {
  84         {
  85                 .fourcc         = V4L2_PIX_FMT_SBGGR8,
  86                 .mbus_code      = MEDIA_BUS_FMT_SBGGR8_1X8,
  87                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
  88                 .cfa_baycfg     = ISC_BAY_CFG_BGBG,
  89         },
  90         {
  91                 .fourcc         = V4L2_PIX_FMT_SGBRG8,
  92                 .mbus_code      = MEDIA_BUS_FMT_SGBRG8_1X8,
  93                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
  94                 .cfa_baycfg     = ISC_BAY_CFG_GBGB,
  95         },
  96         {
  97                 .fourcc         = V4L2_PIX_FMT_SGRBG8,
  98                 .mbus_code      = MEDIA_BUS_FMT_SGRBG8_1X8,
  99                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
 100                 .cfa_baycfg     = ISC_BAY_CFG_GRGR,
 101         },
 102         {
 103                 .fourcc         = V4L2_PIX_FMT_SRGGB8,
 104                 .mbus_code      = MEDIA_BUS_FMT_SRGGB8_1X8,
 105                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
 106                 .cfa_baycfg     = ISC_BAY_CFG_RGRG,
 107         },
 108         {
 109                 .fourcc         = V4L2_PIX_FMT_SBGGR10,
 110                 .mbus_code      = MEDIA_BUS_FMT_SBGGR10_1X10,
 111                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TEN,
 112                 .cfa_baycfg     = ISC_BAY_CFG_RGRG,
 113         },
 114         {
 115                 .fourcc         = V4L2_PIX_FMT_SGBRG10,
 116                 .mbus_code      = MEDIA_BUS_FMT_SGBRG10_1X10,
 117                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TEN,
 118                 .cfa_baycfg     = ISC_BAY_CFG_GBGB,
 119         },
 120         {
 121                 .fourcc         = V4L2_PIX_FMT_SGRBG10,
 122                 .mbus_code      = MEDIA_BUS_FMT_SGRBG10_1X10,
 123                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TEN,
 124                 .cfa_baycfg     = ISC_BAY_CFG_GRGR,
 125         },
 126         {
 127                 .fourcc         = V4L2_PIX_FMT_SRGGB10,
 128                 .mbus_code      = MEDIA_BUS_FMT_SRGGB10_1X10,
 129                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TEN,
 130                 .cfa_baycfg     = ISC_BAY_CFG_RGRG,
 131         },
 132         {
 133                 .fourcc         = V4L2_PIX_FMT_SBGGR12,
 134                 .mbus_code      = MEDIA_BUS_FMT_SBGGR12_1X12,
 135                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TWELVE,
 136                 .cfa_baycfg     = ISC_BAY_CFG_BGBG,
 137         },
 138         {
 139                 .fourcc         = V4L2_PIX_FMT_SGBRG12,
 140                 .mbus_code      = MEDIA_BUS_FMT_SGBRG12_1X12,
 141                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TWELVE,
 142                 .cfa_baycfg     = ISC_BAY_CFG_GBGB,
 143         },
 144         {
 145                 .fourcc         = V4L2_PIX_FMT_SGRBG12,
 146                 .mbus_code      = MEDIA_BUS_FMT_SGRBG12_1X12,
 147                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TWELVE,
 148                 .cfa_baycfg     = ISC_BAY_CFG_GRGR,
 149         },
 150         {
 151                 .fourcc         = V4L2_PIX_FMT_SRGGB12,
 152                 .mbus_code      = MEDIA_BUS_FMT_SRGGB12_1X12,
 153                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TWELVE,
 154                 .cfa_baycfg     = ISC_BAY_CFG_RGRG,
 155         },
 156         {
 157                 .fourcc         = V4L2_PIX_FMT_GREY,
 158                 .mbus_code      = MEDIA_BUS_FMT_Y8_1X8,
 159                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
 160         },
 161         {
 162                 .fourcc         = V4L2_PIX_FMT_YUYV,
 163                 .mbus_code      = MEDIA_BUS_FMT_YUYV8_2X8,
 164                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
 165         },
 166         {
 167                 .fourcc         = V4L2_PIX_FMT_RGB565,
 168                 .mbus_code      = MEDIA_BUS_FMT_RGB565_2X8_LE,
 169                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
 170         },
 171         {
 172                 .fourcc         = V4L2_PIX_FMT_Y10,
 173                 .mbus_code      = MEDIA_BUS_FMT_Y10_1X10,
 174                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TEN,
 175         },
 176
 177 };
 178
 179 #define ISC_IS_FORMAT_RAW(mbus_code) \
 180         (((mbus_code) & 0xf000) == 0x3000)
 181
 182 #define ISC_IS_FORMAT_GREY(mbus_code) \
 183         (((mbus_code) == MEDIA_BUS_FMT_Y10_1X10) | \
 184         (((mbus_code) == MEDIA_BUS_FMT_Y8_1X8)))
 185
 186 static inline void isc_update_v4l2_ctrls(struct isc_device *isc)
 187 {
 188         struct isc_ctrls *ctrls = &isc->ctrls;
 189
 190         /* In here we set the v4l2 controls w.r.t. our pipeline config */
 191         v4l2_ctrl_s_ctrl(isc->r_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_R]);
 192         v4l2_ctrl_s_ctrl(isc->b_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_B]);
 193         v4l2_ctrl_s_ctrl(isc->gr_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GR]);
 194         v4l2_ctrl_s_ctrl(isc->gb_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GB]);
 195
 196         v4l2_ctrl_s_ctrl(isc->r_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_R]);
 197         v4l2_ctrl_s_ctrl(isc->b_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_B]);
 198         v4l2_ctrl_s_ctrl(isc->gr_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GR]);
 199         v4l2_ctrl_s_ctrl(isc->gb_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GB]);
 200 }
 201
 202 static inline void isc_update_awb_ctrls(struct isc_device *isc)
 203 {
 204         struct isc_ctrls *ctrls = &isc->ctrls;
 205
 206         /* In here we set our actual hw pipeline config */
 207
 208         regmap_write(isc->regmap, ISC_WB_O_RGR,
 209                      ((ctrls->offset[ISC_HIS_CFG_MODE_R])) |
 210                      ((ctrls->offset[ISC_HIS_CFG_MODE_GR]) << 16));
 211         regmap_write(isc->regmap, ISC_WB_O_BGB,
 212                      ((ctrls->offset[ISC_HIS_CFG_MODE_B])) |
 213                      ((ctrls->offset[ISC_HIS_CFG_MODE_GB]) << 16));
 214         regmap_write(isc->regmap, ISC_WB_G_RGR,
 215                      ctrls->gain[ISC_HIS_CFG_MODE_R] |
 216                      (ctrls->gain[ISC_HIS_CFG_MODE_GR] << 16));
 217         regmap_write(isc->regmap, ISC_WB_G_BGB,
 218                      ctrls->gain[ISC_HIS_CFG_MODE_B] |
 219                      (ctrls->gain[ISC_HIS_CFG_MODE_GB] << 16));
 220 }
 221
 222 static inline void isc_reset_awb_ctrls(struct isc_device *isc)
 223 {
 224         unsigned int c;
 225
 226         for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) {
 227                 /* gains have a fixed point at 9 decimals */
 228                 isc->ctrls.gain[c] = 1 << 9;
 229                 /* offsets are in 2's complements */
 230                 isc->ctrls.offset[c] = 0;
 231         }
 232 }
 233
 234 static int isc_wait_clk_stable(struct clk_hw *hw)
 235 {
 236         struct isc_clk *isc_clk = to_isc_clk(hw);
 237         struct regmap *regmap = isc_clk->regmap;
 238         unsigned long timeout = jiffies + usecs_to_jiffies(1000);
 239         unsigned int status;
 240
 241         while (time_before(jiffies, timeout)) {
 242                 regmap_read(regmap, ISC_CLKSR, &status);
 243                 if (!(status & ISC_CLKSR_SIP))
 244                         return 0;
 245
 246                 usleep_range(10, 250);
 247         }
 248
 249         return -ETIMEDOUT;
 250 }
 251
 252 static int isc_clk_prepare(struct clk_hw *hw)
 253 {
 254         struct isc_clk *isc_clk = to_isc_clk(hw);
 255         int ret;
 256
 257         if (isc_clk->id == ISC_ISPCK) {
 258                 ret = pm_runtime_resume_and_get(isc_clk->dev);
 259                 if (ret < 0)
 260                         return ret;
 261         }
 262
 263         return isc_wait_clk_stable(hw);
 264 }
 265
 266 static void isc_clk_unprepare(struct clk_hw *hw)
 267 {
 268         struct isc_clk *isc_clk = to_isc_clk(hw);
 269
 270         isc_wait_clk_stable(hw);
 271
 272         if (isc_clk->id == ISC_ISPCK)
 273                 pm_runtime_put_sync(isc_clk->dev);
 274 }
 275
 276 static int isc_clk_enable(struct clk_hw *hw)
 277 {
 278         struct isc_clk *isc_clk = to_isc_clk(hw);
 279         u32 id = isc_clk->id;
 280         struct regmap *regmap = isc_clk->regmap;
 281         unsigned long flags;
 282         unsigned int status;
 283
 284         dev_dbg(isc_clk->dev, "ISC CLK: %s, id = %d, div = %d, parent id = %d\n",
 285                 __func__, id, isc_clk->div, isc_clk->parent_id);
 286
 287         spin_lock_irqsave(&isc_clk->lock, flags);
 288         regmap_update_bits(regmap, ISC_CLKCFG,
 289                            ISC_CLKCFG_DIV_MASK(id) | ISC_CLKCFG_SEL_MASK(id),
 290                            (isc_clk->div << ISC_CLKCFG_DIV_SHIFT(id)) |
 291                            (isc_clk->parent_id << ISC_CLKCFG_SEL_SHIFT(id)));
 292
 293         regmap_write(regmap, ISC_CLKEN, ISC_CLK(id));
 294         spin_unlock_irqrestore(&isc_clk->lock, flags);
 295
 296         regmap_read(regmap, ISC_CLKSR, &status);
 297         if (status & ISC_CLK(id))
 298                 return 0;
 299         else
 300                 return -EINVAL;
 301 }
 302
 303 static void isc_clk_disable(struct clk_hw *hw)
 304 {
 305         struct isc_clk *isc_clk = to_isc_clk(hw);
 306         u32 id = isc_clk->id;
 307         unsigned long flags;
 308
 309         spin_lock_irqsave(&isc_clk->lock, flags);
 310         regmap_write(isc_clk->regmap, ISC_CLKDIS, ISC_CLK(id));
 311         spin_unlock_irqrestore(&isc_clk->lock, flags);
 312 }
 313
 314 static int isc_clk_is_enabled(struct clk_hw *hw)
 315 {
 316         struct isc_clk *isc_clk = to_isc_clk(hw);
 317         u32 status;
 318         int ret;
 319
 320         if (isc_clk->id == ISC_ISPCK) {
 321                 ret = pm_runtime_resume_and_get(isc_clk->dev);
 322                 if (ret < 0)
 323                         return 0;
 324         }
 325
 326         regmap_read(isc_clk->regmap, ISC_CLKSR, &status);
 327
 328         if (isc_clk->id == ISC_ISPCK)
 329                 pm_runtime_put_sync(isc_clk->dev);
 330
 331         return status & ISC_CLK(isc_clk->id) ? 1 : 0;
 332 }
 333
 334 static unsigned long
 335 isc_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 336 {
 337         struct isc_clk *isc_clk = to_isc_clk(hw);
 338
 339         return DIV_ROUND_CLOSEST(parent_rate, isc_clk->div + 1);
 340 }
 341
 342 static int isc_clk_determine_rate(struct clk_hw *hw,
 343                                    struct clk_rate_request *req)
 344 {
 345         struct isc_clk *isc_clk = to_isc_clk(hw);
 346         long best_rate = -EINVAL;
 347         int best_diff = -1;
 348         unsigned int i, div;
 349
 350         for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
 351                 struct clk_hw *parent;
 352                 unsigned long parent_rate;
 353
 354                 parent = clk_hw_get_parent_by_index(hw, i);
 355                 if (!parent)
 356                         continue;
 357
 358                 parent_rate = clk_hw_get_rate(parent);
 359                 if (!parent_rate)
 360                         continue;
 361
 362                 for (div = 1; div < ISC_CLK_MAX_DIV + 2; div++) {
 363                         unsigned long rate;
 364                         int diff;
 365
 366                         rate = DIV_ROUND_CLOSEST(parent_rate, div);
 367                         diff = abs(req->rate - rate);
 368
 369                         if (best_diff < 0 || best_diff > diff) {
 370                                 best_rate = rate;
 371                                 best_diff = diff;
 372                                 req->best_parent_rate = parent_rate;
 373                                 req->best_parent_hw = parent;
 374                         }
 375
 376                         if (!best_diff || rate < req->rate)
 377                                 break;
 378                 }
 379
 380                 if (!best_diff)
 381                         break;
 382         }
 383
 384         dev_dbg(isc_clk->dev,
 385                 "ISC CLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
 386                 __func__, best_rate,
 387                 __clk_get_name((req->best_parent_hw)->clk),
 388                 req->best_parent_rate);
 389
 390         if (best_rate < 0)
 391                 return best_rate;
 392
 393         req->rate = best_rate;
 394
 395         return 0;
 396 }
 397
 398 static int isc_clk_set_parent(struct clk_hw *hw, u8 index)
 399 {
 400         struct isc_clk *isc_clk = to_isc_clk(hw);
 401
 402         if (index >= clk_hw_get_num_parents(hw))
 403                 return -EINVAL;
 404
 405         isc_clk->parent_id = index;
 406
 407         return 0;
 408 }
 409
 410 static u8 isc_clk_get_parent(struct clk_hw *hw)
 411 {
 412         struct isc_clk *isc_clk = to_isc_clk(hw);
 413
 414         return isc_clk->parent_id;
 415 }
 416
 417 static int isc_clk_set_rate(struct clk_hw *hw,
 418                              unsigned long rate,
 419                              unsigned long parent_rate)
 420 {
 421         struct isc_clk *isc_clk = to_isc_clk(hw);
 422         u32 div;
 423
 424         if (!rate)
 425                 return -EINVAL;
 426
 427         div = DIV_ROUND_CLOSEST(parent_rate, rate);
 428         if (div > (ISC_CLK_MAX_DIV + 1) || !div)
 429                 return -EINVAL;
 430
 431         isc_clk->div = div - 1;
 432
 433         return 0;
 434 }
 435
 436 static const struct clk_ops isc_clk_ops = {
 437         .prepare        = isc_clk_prepare,
 438         .unprepare      = isc_clk_unprepare,
 439         .enable         = isc_clk_enable,
 440         .disable        = isc_clk_disable,
 441         .is_enabled     = isc_clk_is_enabled,
 442         .recalc_rate    = isc_clk_recalc_rate,
 443         .determine_rate = isc_clk_determine_rate,
 444         .set_parent     = isc_clk_set_parent,
 445         .get_parent     = isc_clk_get_parent,
 446         .set_rate       = isc_clk_set_rate,
 447 };
 448
 449 static int isc_clk_register(struct isc_device *isc, unsigned int id)
 450 {
 451         struct regmap *regmap = isc->regmap;
 452         struct device_node *np = isc->dev->of_node;
 453         struct isc_clk *isc_clk;
 454         struct clk_init_data init;
 455         const char *clk_name = np->name;
 456         const char *parent_names[3];
 457         int num_parents;
 458
 459         num_parents = of_clk_get_parent_count(np);
 460         if (num_parents < 1 || num_parents > 3)
 461                 return -EINVAL;
 462
 463         if (num_parents > 2 && id == ISC_ISPCK)
 464                 num_parents = 2;
 465
 466         of_clk_parent_fill(np, parent_names, num_parents);
 467
 468         if (id == ISC_MCK)
 469                 of_property_read_string(np, "clock-output-names", &clk_name);
 470         else
 471                 clk_name = "isc-ispck";
 472
 473         init.parent_names       = parent_names;
 474         init.num_parents        = num_parents;
 475         init.name               = clk_name;
 476         init.ops                = &isc_clk_ops;
 477         init.flags              = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
 478
 479         isc_clk = &isc->isc_clks[id];
 480         isc_clk->hw.init        = &init;
 481         isc_clk->regmap         = regmap;
 482         isc_clk->id             = id;
 483         isc_clk->dev            = isc->dev;
 484         spin_lock_init(&isc_clk->lock);
 485
 486         isc_clk->clk = clk_register(isc->dev, &isc_clk->hw);
 487         if (IS_ERR(isc_clk->clk)) {
 488                 dev_err(isc->dev, "%s: clock register fail\n", clk_name);
 489                 return PTR_ERR(isc_clk->clk);
 490         } else if (id == ISC_MCK)
 491                 of_clk_add_provider(np, of_clk_src_simple_get, isc_clk->clk);
 492
 493         return 0;
 494 }
 495
 496 int isc_clk_init(struct isc_device *isc)
 497 {
 498         unsigned int i;
 499         int ret;
 500
 501         for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++)
 502                 isc->isc_clks[i].clk = ERR_PTR(-EINVAL);
 503
 504         for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) {
 505                 ret = isc_clk_register(isc, i);
 506                 if (ret)
 507                         return ret;
 508         }
 509
 510         return 0;
 511 }
 512
 513 void isc_clk_cleanup(struct isc_device *isc)
 514 {
 515         unsigned int i;
 516
 517         of_clk_del_provider(isc->dev->of_node);
 518
 519         for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) {
 520                 struct isc_clk *isc_clk = &isc->isc_clks[i];
 521
 522                 if (!IS_ERR(isc_clk->clk))
 523                         clk_unregister(isc_clk->clk);
 524         }
 525 }
 526
 527 static int isc_queue_setup(struct vb2_queue *vq,
 528                             unsigned int *nbuffers, unsigned int *nplanes,
 529                             unsigned int sizes[], struct device *alloc_devs[])
 530 {
 531         struct isc_device *isc = vb2_get_drv_priv(vq);
 532         unsigned int size = isc->fmt.fmt.pix.sizeimage;
 533
 534         if (*nplanes)
 535                 return sizes[0] < size ? -EINVAL : 0;
 536
 537         *nplanes = 1;
 538         sizes[0] = size;
 539
 540         return 0;
 541 }
 542
 543 static int isc_buffer_prepare(struct vb2_buffer *vb)
 544 {
 545         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 546         struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
 547         unsigned long size = isc->fmt.fmt.pix.sizeimage;
 548
 549         if (vb2_plane_size(vb, 0) < size) {
 550                 v4l2_err(&isc->v4l2_dev, "buffer too small (%lu < %lu)\n",
 551                          vb2_plane_size(vb, 0), size);
 552                 return -EINVAL;
 553         }
 554
 555         vb2_set_plane_payload(vb, 0, size);
 556
 557         vbuf->field = isc->fmt.fmt.pix.field;
 558
 559         return 0;
 560 }
 561
 562 static void isc_start_dma(struct isc_device *isc)
 563 {
 564         struct regmap *regmap = isc->regmap;
 565         u32 sizeimage = isc->fmt.fmt.pix.sizeimage;
 566         u32 dctrl_dview;
 567         dma_addr_t addr0;
 568         u32 h, w;
 569
 570         h = isc->fmt.fmt.pix.height;
 571         w = isc->fmt.fmt.pix.width;
 572
 573         /*
 574          * In case the sensor is not RAW, it will output a pixel (12-16 bits)
 575          * with two samples on the ISC Data bus (which is 8-12)
 576          * ISC will count each sample, so, we need to multiply these values
 577          * by two, to get the real number of samples for the required pixels.
 578          */
 579         if (!ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) {
 580                 h <<= 1;
 581                 w <<= 1;
 582         }
 583
 584         /*
 585          * We limit the column/row count that the ISC will output according
 586          * to the configured resolution that we want.
 587          * This will avoid the situation where the sensor is misconfigured,
 588          * sending more data, and the ISC will just take it and DMA to memory,
 589          * causing corruption.
 590          */
 591         regmap_write(regmap, ISC_PFE_CFG1,
 592                      (ISC_PFE_CFG1_COLMIN(0) & ISC_PFE_CFG1_COLMIN_MASK) |
 593                      (ISC_PFE_CFG1_COLMAX(w - 1) & ISC_PFE_CFG1_COLMAX_MASK));
 594
 595         regmap_write(regmap, ISC_PFE_CFG2,
 596                      (ISC_PFE_CFG2_ROWMIN(0) & ISC_PFE_CFG2_ROWMIN_MASK) |
 597                      (ISC_PFE_CFG2_ROWMAX(h - 1) & ISC_PFE_CFG2_ROWMAX_MASK));
 598
 599         regmap_update_bits(regmap, ISC_PFE_CFG0,
 600                            ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN,
 601                            ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN);
 602
 603         addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0);
 604         regmap_write(regmap, ISC_DAD0 + isc->offsets.dma, addr0);
 605
 606         switch (isc->config.fourcc) {
 607         case V4L2_PIX_FMT_YUV420:
 608                 regmap_write(regmap, ISC_DAD1 + isc->offsets.dma,
 609                              addr0 + (sizeimage * 2) / 3);
 610                 regmap_write(regmap, ISC_DAD2 + isc->offsets.dma,
 611                              addr0 + (sizeimage * 5) / 6);
 612                 break;
 613         case V4L2_PIX_FMT_YUV422P:
 614                 regmap_write(regmap, ISC_DAD1 + isc->offsets.dma,
 615                              addr0 + sizeimage / 2);
 616                 regmap_write(regmap, ISC_DAD2 + isc->offsets.dma,
 617                              addr0 + (sizeimage * 3) / 4);
 618                 break;
 619         default:
 620                 break;
 621         }
 622
 623         dctrl_dview = isc->config.dctrl_dview;
 624
 625         regmap_write(regmap, ISC_DCTRL + isc->offsets.dma,
 626                      dctrl_dview | ISC_DCTRL_IE_IS);
 627         spin_lock(&isc->awb_lock);
 628         regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE);
 629         spin_unlock(&isc->awb_lock);
 630 }
 631
 632 static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)
 633 {
 634         struct regmap *regmap = isc->regmap;
 635         struct isc_ctrls *ctrls = &isc->ctrls;
 636         u32 val, bay_cfg;
 637         const u32 *gamma;
 638         unsigned int i;
 639
 640         /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */
 641         for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
 642                 val = pipeline & BIT(i) ? 1 : 0;
 643                 regmap_field_write(isc->pipeline[i], val);
 644         }
 645
 646         if (!pipeline)
 647                 return;
 648
 649         bay_cfg = isc->config.sd_format->cfa_baycfg;
 650
 651         regmap_write(regmap, ISC_WB_CFG, bay_cfg);
 652         isc_update_awb_ctrls(isc);
 653         isc_update_v4l2_ctrls(isc);
 654
 655         regmap_write(regmap, ISC_CFA_CFG, bay_cfg | ISC_CFA_CFG_EITPOL);
 656
 657         gamma = &isc->gamma_table[ctrls->gamma_index][0];
 658         regmap_bulk_write(regmap, ISC_GAM_BENTRY, gamma, GAMMA_ENTRIES);
 659         regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES);
 660         regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);
 661
 662         isc->config_dpc(isc);
 663         isc->config_csc(isc);
 664         isc->config_cbc(isc);
 665         isc->config_cc(isc);
 666 }
 667
 668 static int isc_update_profile(struct isc_device *isc)
 669 {
 670         struct regmap *regmap = isc->regmap;
 671         u32 sr;
 672         int counter = 100;
 673
 674         regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_UPPRO);
 675
 676         regmap_read(regmap, ISC_CTRLSR, &sr);
 677         while ((sr & ISC_CTRL_UPPRO) && counter--) {
 678                 usleep_range(1000, 2000);
 679                 regmap_read(regmap, ISC_CTRLSR, &sr);
 680         }
 681
 682         if (counter < 0) {
 683                 v4l2_warn(&isc->v4l2_dev, "Time out to update profile\n");
 684                 return -ETIMEDOUT;
 685         }
 686
 687         return 0;
 688 }
 689
 690 static void isc_set_histogram(struct isc_device *isc, bool enable)
 691 {
 692         struct regmap *regmap = isc->regmap;
 693         struct isc_ctrls *ctrls = &isc->ctrls;
 694
 695         if (enable) {
 696                 regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his,
 697                              ISC_HIS_CFG_MODE_GR |
 698                              (isc->config.sd_format->cfa_baycfg
 699                                         << ISC_HIS_CFG_BAYSEL_SHIFT) |
 700                                         ISC_HIS_CFG_RAR);
 701                 regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his,
 702                              ISC_HIS_CTRL_EN);
 703                 regmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE);
 704                 ctrls->hist_id = ISC_HIS_CFG_MODE_GR;
 705                 isc_update_profile(isc);
 706                 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ);
 707
 708                 ctrls->hist_stat = HIST_ENABLED;
 709         } else {
 710                 regmap_write(regmap, ISC_INTDIS, ISC_INT_HISDONE);
 711                 regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his,
 712                              ISC_HIS_CTRL_DIS);
 713
 714                 ctrls->hist_stat = HIST_DISABLED;
 715         }
 716 }
 717
 718 static int isc_configure(struct isc_device *isc)
 719 {
 720         struct regmap *regmap = isc->regmap;
 721         u32 pfe_cfg0, rlp_mode, dcfg, mask, pipeline;
 722         struct isc_subdev_entity *subdev = isc->current_subdev;
 723
 724         pfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps;
 725         rlp_mode = isc->config.rlp_cfg_mode;
 726         pipeline = isc->config.bits_pipeline;
 727
 728         dcfg = isc->config.dcfg_imode | isc->dcfg;
 729
 730         pfe_cfg0  |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE;
 731         mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW |
 732                ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW |
 733                ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC |
 734                    ISC_PFE_CFG0_CCIR656;
 735
 736         regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);
 737
 738         regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,
 739                            ISC_RLP_CFG_MODE_MASK, rlp_mode);
 740
 741         regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg);
 742
 743         /* Set the pipeline */
 744         isc_set_pipeline(isc, pipeline);
 745
 746         /*
 747          * The current implemented histogram is available for RAW R, B, GB, GR
 748          * channels. We need to check if sensor is outputting RAW BAYER
 749          */
 750         if (isc->ctrls.awb &&
 751             ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
 752                 isc_set_histogram(isc, true);
 753         else
 754                 isc_set_histogram(isc, false);
 755
 756         /* Update profile */
 757         return isc_update_profile(isc);
 758 }
 759
 760 static int isc_start_streaming(struct vb2_queue *vq, unsigned int count)
 761 {
 762         struct isc_device *isc = vb2_get_drv_priv(vq);
 763         struct regmap *regmap = isc->regmap;
 764         struct isc_buffer *buf;
 765         unsigned long flags;
 766         int ret;
 767
 768         /* Enable stream on the sub device */
 769         ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 1);
 770         if (ret && ret != -ENOIOCTLCMD) {
 771                 v4l2_err(&isc->v4l2_dev, "stream on failed in subdev %d\n",
 772                          ret);
 773                 goto err_start_stream;
 774         }
 775
 776         ret = pm_runtime_resume_and_get(isc->dev);
 777         if (ret < 0) {
 778                 v4l2_err(&isc->v4l2_dev, "RPM resume failed in subdev %d\n",
 779                          ret);
 780                 goto err_pm_get;
 781         }
 782
 783         ret = isc_configure(isc);
 784         if (unlikely(ret))
 785                 goto err_configure;
 786
 787         /* Enable DMA interrupt */
 788         regmap_write(regmap, ISC_INTEN, ISC_INT_DDONE);
 789
 790         spin_lock_irqsave(&isc->dma_queue_lock, flags);
 791
 792         isc->sequence = 0;
 793         isc->stop = false;
 794         reinit_completion(&isc->comp);
 795
 796         isc->cur_frm = list_first_entry(&isc->dma_queue,
 797                                         struct isc_buffer, list);
 798         list_del(&isc->cur_frm->list);
 799
 800         isc_start_dma(isc);
 801
 802         spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
 803
 804         /* if we streaming from RAW, we can do one-shot white balance adj */
 805         if (ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
 806                 v4l2_ctrl_activate(isc->do_wb_ctrl, true);
 807
 808         return 0;
 809
 810 err_configure:
 811         pm_runtime_put_sync(isc->dev);
 812 err_pm_get:
 813         v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
 814
 815 err_start_stream:
 816         spin_lock_irqsave(&isc->dma_queue_lock, flags);
 817         list_for_each_entry(buf, &isc->dma_queue, list)
 818                 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
 819         INIT_LIST_HEAD(&isc->dma_queue);
 820         spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
 821
 822         return ret;
 823 }
 824
 825 static void isc_stop_streaming(struct vb2_queue *vq)
 826 {
 827         struct isc_device *isc = vb2_get_drv_priv(vq);
 828         unsigned long flags;
 829         struct isc_buffer *buf;
 830         int ret;
 831
 832         v4l2_ctrl_activate(isc->do_wb_ctrl, false);
 833
 834         isc->stop = true;
 835
 836         /* Wait until the end of the current frame */
 837         if (isc->cur_frm && !wait_for_completion_timeout(&isc->comp, 5 * HZ))
 838                 v4l2_err(&isc->v4l2_dev,
 839                          "Timeout waiting for end of the capture\n");
 840
 841         /* Disable DMA interrupt */
 842         regmap_write(isc->regmap, ISC_INTDIS, ISC_INT_DDONE);
 843
 844         pm_runtime_put_sync(isc->dev);
 845
 846         /* Disable stream on the sub device */
 847         ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
 848         if (ret && ret != -ENOIOCTLCMD)
 849                 v4l2_err(&isc->v4l2_dev, "stream off failed in subdev\n");
 850
 851         /* Release all active buffers */
 852         spin_lock_irqsave(&isc->dma_queue_lock, flags);
 853         if (unlikely(isc->cur_frm)) {
 854                 vb2_buffer_done(&isc->cur_frm->vb.vb2_buf,
 855                                 VB2_BUF_STATE_ERROR);
 856                 isc->cur_frm = NULL;
 857         }
 858         list_for_each_entry(buf, &isc->dma_queue, list)
 859                 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
 860         INIT_LIST_HEAD(&isc->dma_queue);
 861         spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
 862 }
 863
 864 static void isc_buffer_queue(struct vb2_buffer *vb)
 865 {
 866         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 867         struct isc_buffer *buf = container_of(vbuf, struct isc_buffer, vb);
 868         struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
 869         unsigned long flags;
 870
 871         spin_lock_irqsave(&isc->dma_queue_lock, flags);
 872         if (!isc->cur_frm && list_empty(&isc->dma_queue) &&
 873                 vb2_is_streaming(vb->vb2_queue)) {
 874                 isc->cur_frm = buf;
 875                 isc_start_dma(isc);
 876         } else
 877                 list_add_tail(&buf->list, &isc->dma_queue);
 878         spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
 879 }
 880
 881 static struct isc_format *find_format_by_fourcc(struct isc_device *isc,
 882                                                  unsigned int fourcc)
 883 {
 884         unsigned int num_formats = isc->num_user_formats;
 885         struct isc_format *fmt;
 886         unsigned int i;
 887
 888         for (i = 0; i < num_formats; i++) {
 889                 fmt = isc->user_formats[i];
 890                 if (fmt->fourcc == fourcc)
 891                         return fmt;
 892         }
 893
 894         return NULL;
 895 }
 896
 897 static const struct vb2_ops isc_vb2_ops = {
 898         .queue_setup            = isc_queue_setup,
 899         .wait_prepare           = vb2_ops_wait_prepare,
 900         .wait_finish            = vb2_ops_wait_finish,
 901         .buf_prepare            = isc_buffer_prepare,
 902         .start_streaming        = isc_start_streaming,
 903         .stop_streaming         = isc_stop_streaming,
 904         .buf_queue              = isc_buffer_queue,
 905 };
 906
 907 static int isc_querycap(struct file *file, void *priv,
 908                          struct v4l2_capability *cap)
 909 {
 910         struct isc_device *isc = video_drvdata(file);
 911
 912         strscpy(cap->driver, "microchip-isc", sizeof(cap->driver));
 913         strscpy(cap->card, "Atmel Image Sensor Controller", sizeof(cap->card));
 914         snprintf(cap->bus_info, sizeof(cap->bus_info),
 915                  "platform:%s", isc->v4l2_dev.name);
 916
 917         return 0;
 918 }
 919
 920 static int isc_enum_fmt_vid_cap(struct file *file, void *priv,
 921                                  struct v4l2_fmtdesc *f)
 922 {
 923         u32 index = f->index;
 924         u32 i, supported_index;
 925
 926         if (index < ARRAY_SIZE(controller_formats)) {
 927                 f->pixelformat = controller_formats[index].fourcc;
 928                 return 0;
 929         }
 930
 931         index -= ARRAY_SIZE(controller_formats);
 932
 933         supported_index = 0;
 934
 935         for (i = 0; i < ARRAY_SIZE(formats_list); i++) {
 936                 if (!ISC_IS_FORMAT_RAW(formats_list[i].mbus_code) ||
 937                     !formats_list[i].sd_support)
 938                         continue;
 939                 if (supported_index == index) {
 940                         f->pixelformat = formats_list[i].fourcc;
 941                         return 0;
 942                 }
 943                 supported_index++;
 944         }
 945
 946         return -EINVAL;
 947 }
 948
 949 static int isc_g_fmt_vid_cap(struct file *file, void *priv,
 950                               struct v4l2_format *fmt)
 951 {
 952         struct isc_device *isc = video_drvdata(file);
 953
 954         *fmt = isc->fmt;
 955
 956         return 0;
 957 }
 958
 959 /*
 960  * Checks the current configured format, if ISC can output it,
 961  * considering which type of format the ISC receives from the sensor
 962  */
 963 static int isc_try_validate_formats(struct isc_device *isc)
 964 {
 965         int ret;
 966         bool bayer = false, yuv = false, rgb = false, grey = false;
 967
 968         /* all formats supported by the RLP module are OK */
 969         switch (isc->try_config.fourcc) {
 970         case V4L2_PIX_FMT_SBGGR8:
 971         case V4L2_PIX_FMT_SGBRG8:
 972         case V4L2_PIX_FMT_SGRBG8:
 973         case V4L2_PIX_FMT_SRGGB8:
 974         case V4L2_PIX_FMT_SBGGR10:
 975         case V4L2_PIX_FMT_SGBRG10:
 976         case V4L2_PIX_FMT_SGRBG10:
 977         case V4L2_PIX_FMT_SRGGB10:
 978         case V4L2_PIX_FMT_SBGGR12:
 979         case V4L2_PIX_FMT_SGBRG12:
 980         case V4L2_PIX_FMT_SGRBG12:
 981         case V4L2_PIX_FMT_SRGGB12:
 982                 ret = 0;
 983                 bayer = true;
 984                 break;
 985
 986         case V4L2_PIX_FMT_YUV420:
 987         case V4L2_PIX_FMT_YUV422P:
 988         case V4L2_PIX_FMT_YUYV:
 989                 ret = 0;
 990                 yuv = true;
 991                 break;
 992
 993         case V4L2_PIX_FMT_RGB565:
 994         case V4L2_PIX_FMT_ABGR32:
 995         case V4L2_PIX_FMT_XBGR32:
 996         case V4L2_PIX_FMT_ARGB444:
 997         case V4L2_PIX_FMT_ARGB555:
 998                 ret = 0;
 999                 rgb = true;
1000                 break;
1001         case V4L2_PIX_FMT_GREY:
1002         case V4L2_PIX_FMT_Y10:
1003                 ret = 0;
1004                 grey = true;
1005                 break;
1006         default:
1007         /* any other different formats are not supported */
1008                 ret = -EINVAL;
1009         }
1010         v4l2_dbg(1, debug, &isc->v4l2_dev,
1011                  "Format validation, requested rgb=%u, yuv=%u, grey=%u, bayer=%u\n",
1012                  rgb, yuv, grey, bayer);
1013
1014         /* we cannot output RAW if we do not receive RAW */
1015         if ((bayer) && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code))
1016                 return -EINVAL;
1017
1018         /* we cannot output GREY if we do not receive RAW/GREY */
1019         if (grey && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code) &&
1020             !ISC_IS_FORMAT_GREY(isc->try_config.sd_format->mbus_code))
1021                 return -EINVAL;
1022
1023         return ret;
1024 }
1025
1026 /*
1027  * Configures the RLP and DMA modules, depending on the output format
1028  * configured for the ISC.
1029  * If direct_dump == true, just dump raw data 8/16 bits depending on format.
1030  */
1031 static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump)
1032 {
1033         switch (isc->try_config.fourcc) {
1034         case V4L2_PIX_FMT_SBGGR8:
1035         case V4L2_PIX_FMT_SGBRG8:
1036         case V4L2_PIX_FMT_SGRBG8:
1037         case V4L2_PIX_FMT_SRGGB8:
1038                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8;
1039                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
1040                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1041                 isc->try_config.bpp = 8;
1042                 break;
1043         case V4L2_PIX_FMT_SBGGR10:
1044         case V4L2_PIX_FMT_SGBRG10:
1045         case V4L2_PIX_FMT_SGRBG10:
1046         case V4L2_PIX_FMT_SRGGB10:
1047                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT10;
1048                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1049                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1050                 isc->try_config.bpp = 16;
1051                 break;
1052         case V4L2_PIX_FMT_SBGGR12:
1053         case V4L2_PIX_FMT_SGBRG12:
1054         case V4L2_PIX_FMT_SGRBG12:
1055         case V4L2_PIX_FMT_SRGGB12:
1056                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT12;
1057                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1058                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1059                 isc->try_config.bpp = 16;
1060                 break;
1061         case V4L2_PIX_FMT_RGB565:
1062                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_RGB565;
1063                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1064                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1065                 isc->try_config.bpp = 16;
1066                 break;
1067         case V4L2_PIX_FMT_ARGB444:
1068                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB444;
1069                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1070                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1071                 isc->try_config.bpp = 16;
1072                 break;
1073         case V4L2_PIX_FMT_ARGB555:
1074                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB555;
1075                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1076                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1077                 isc->try_config.bpp = 16;
1078                 break;
1079         case V4L2_PIX_FMT_ABGR32:
1080         case V4L2_PIX_FMT_XBGR32:
1081                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB32;
1082                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
1083                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1084                 isc->try_config.bpp = 32;
1085                 break;
1086         case V4L2_PIX_FMT_YUV420:
1087                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
1088                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC420P;
1089                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR;
1090                 isc->try_config.bpp = 12;
1091                 break;
1092         case V4L2_PIX_FMT_YUV422P:
1093                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
1094                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC422P;
1095                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR;
1096                 isc->try_config.bpp = 16;
1097                 break;
1098         case V4L2_PIX_FMT_YUYV:
1099                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
1100                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
1101                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1102                 isc->try_config.bpp = 16;
1103                 break;
1104         case V4L2_PIX_FMT_GREY:
1105                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY8;
1106                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
1107                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1108                 isc->try_config.bpp = 8;
1109                 break;
1110         case V4L2_PIX_FMT_Y10:
1111                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10;
1112                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1113                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1114                 isc->try_config.bpp = 16;
1115                 break;
1116         default:
1117                 return -EINVAL;
1118         }
1119
1120         if (direct_dump) {
1121                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8;
1122                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
1123                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1124                 return 0;
1125         }
1126
1127         return 0;
1128 }
1129
1130 /*
1131  * Configuring pipeline modules, depending on which format the ISC outputs
1132  * and considering which format it has as input from the sensor.
1133  */
1134 static int isc_try_configure_pipeline(struct isc_device *isc)
1135 {
1136         switch (isc->try_config.fourcc) {
1137         case V4L2_PIX_FMT_RGB565:
1138         case V4L2_PIX_FMT_ARGB555:
1139         case V4L2_PIX_FMT_ARGB444:
1140         case V4L2_PIX_FMT_ABGR32:
1141         case V4L2_PIX_FMT_XBGR32:
1142                 /* if sensor format is RAW, we convert inside ISC */
1143                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1144                         isc->try_config.bits_pipeline = CFA_ENABLE |
1145                                 WB_ENABLE | GAM_ENABLES;
1146                 } else {
1147                         isc->try_config.bits_pipeline = 0x0;
1148                 }
1149                 break;
1150         case V4L2_PIX_FMT_YUV420:
1151                 /* if sensor format is RAW, we convert inside ISC */
1152                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1153                         isc->try_config.bits_pipeline = CFA_ENABLE |
1154                                 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
1155                                 SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE;
1156                 } else {
1157                         isc->try_config.bits_pipeline = 0x0;
1158                 }
1159                 break;
1160         case V4L2_PIX_FMT_YUV422P:
1161                 /* if sensor format is RAW, we convert inside ISC */
1162                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1163                         isc->try_config.bits_pipeline = CFA_ENABLE |
1164                                 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
1165                                 SUB422_ENABLE | CBC_ENABLE;
1166                 } else {
1167                         isc->try_config.bits_pipeline = 0x0;
1168                 }
1169                 break;
1170         case V4L2_PIX_FMT_YUYV:
1171                 /* if sensor format is RAW, we convert inside ISC */
1172                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1173                         isc->try_config.bits_pipeline = CFA_ENABLE |
1174                                 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
1175                                 SUB422_ENABLE | CBC_ENABLE;
1176                 } else {
1177                         isc->try_config.bits_pipeline = 0x0;
1178                 }
1179                 break;
1180         case V4L2_PIX_FMT_GREY:
1181                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1182                 /* if sensor format is RAW, we convert inside ISC */
1183                         isc->try_config.bits_pipeline = CFA_ENABLE |
1184                                 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
1185                                 CBC_ENABLE;
1186                 } else {
1187                         isc->try_config.bits_pipeline = 0x0;
1188                 }
1189                 break;
1190         default:
1191                 isc->try_config.bits_pipeline = 0x0;
1192         }
1193         return 0;
1194 }
1195
1196 static void isc_try_fse(struct isc_device *isc,
1197                         struct v4l2_subdev_pad_config *pad_cfg)
1198 {
1199         int ret;
1200         struct v4l2_subdev_frame_size_enum fse = {};
1201
1202         /*
1203          * If we do not know yet which format the subdev is using, we cannot
1204          * do anything.
1205          */
1206         if (!isc->try_config.sd_format)
1207                 return;
1208
1209         fse.code = isc->try_config.sd_format->mbus_code;
1210         fse.which = V4L2_SUBDEV_FORMAT_TRY;
1211
1212         ret = v4l2_subdev_call(isc->current_subdev->sd, pad, enum_frame_size,
1213                                pad_cfg, &fse);
1214         /*
1215          * Attempt to obtain format size from subdev. If not available,
1216          * just use the maximum ISC can receive.
1217          */
1218         if (ret) {
1219                 pad_cfg->try_crop.width = isc->max_width;
1220                 pad_cfg->try_crop.height = isc->max_height;
1221         } else {
1222                 pad_cfg->try_crop.width = fse.max_width;
1223                 pad_cfg->try_crop.height = fse.max_height;
1224         }
1225 }
1226
1227 static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f,
1228                         u32 *code)
1229 {
1230         int i;
1231         struct isc_format *sd_fmt = NULL, *direct_fmt = NULL;
1232         struct v4l2_pix_format *pixfmt = &f->fmt.pix;
1233         struct v4l2_subdev_pad_config pad_cfg = {};
1234         struct v4l2_subdev_format format = {
1235                 .which = V4L2_SUBDEV_FORMAT_TRY,
1236         };
1237         u32 mbus_code;
1238         int ret;
1239         bool rlp_dma_direct_dump = false;
1240
1241         if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1242                 return -EINVAL;
1243
1244         /* Step 1: find a RAW format that is supported */
1245         for (i = 0; i < isc->num_user_formats; i++) {
1246                 if (ISC_IS_FORMAT_RAW(isc->user_formats[i]->mbus_code)) {
1247                         sd_fmt = isc->user_formats[i];
1248                         break;
1249                 }
1250         }
1251         /* Step 2: We can continue with this RAW format, or we can look
1252          * for better: maybe sensor supports directly what we need.
1253          */
1254         direct_fmt = find_format_by_fourcc(isc, pixfmt->pixelformat);
1255
1256         /* Step 3: We have both. We decide given the module parameter which
1257          * one to use.
1258          */
1259         if (direct_fmt && sd_fmt && sensor_preferred)
1260                 sd_fmt = direct_fmt;
1261
1262         /* Step 4: we do not have RAW but we have a direct format. Use it. */
1263         if (direct_fmt && !sd_fmt)
1264                 sd_fmt = direct_fmt;
1265
1266         /* Step 5: if we are using a direct format, we need to package
1267          * everything as 8 bit data and just dump it
1268          */
1269         if (sd_fmt == direct_fmt)
1270                 rlp_dma_direct_dump = true;
1271
1272         /* Step 6: We have no format. This can happen if the userspace
1273          * requests some weird/invalid format.
1274          * In this case, default to whatever we have
1275          */
1276         if (!sd_fmt && !direct_fmt) {
1277                 sd_fmt = isc->user_formats[isc->num_user_formats - 1];
1278                 v4l2_dbg(1, debug, &isc->v4l2_dev,
1279                          "Sensor not supporting %.4s, using %.4s\n",
1280                          (char *)&pixfmt->pixelformat, (char *)&sd_fmt->fourcc);
1281         }
1282
1283         if (!sd_fmt) {
1284                 ret = -EINVAL;
1285                 goto isc_try_fmt_err;
1286         }
1287
1288         /* Step 7: Print out what we decided for debugging */
1289         v4l2_dbg(1, debug, &isc->v4l2_dev,
1290                  "Preferring to have sensor using format %.4s\n",
1291                  (char *)&sd_fmt->fourcc);
1292
1293         /* Step 8: at this moment we decided which format the subdev will use */
1294         isc->try_config.sd_format = sd_fmt;
1295
1296         /* Limit to Atmel ISC hardware capabilities */
1297         if (pixfmt->width > isc->max_width)
1298                 pixfmt->width = isc->max_width;
1299         if (pixfmt->height > isc->max_height)
1300                 pixfmt->height = isc->max_height;
1301
1302         /*
1303          * The mbus format is the one the subdev outputs.
1304          * The pixels will be transferred in this format Sensor -> ISC
1305          */
1306         mbus_code = sd_fmt->mbus_code;
1307
1308         /*
1309          * Validate formats. If the required format is not OK, default to raw.
1310          */
1311
1312         isc->try_config.fourcc = pixfmt->pixelformat;
1313
1314         if (isc_try_validate_formats(isc)) {
1315                 pixfmt->pixelformat = isc->try_config.fourcc = sd_fmt->fourcc;
1316                 /* Re-try to validate the new format */
1317                 ret = isc_try_validate_formats(isc);
1318                 if (ret)
1319                         goto isc_try_fmt_err;
1320         }
1321
1322         ret = isc_try_configure_rlp_dma(isc, rlp_dma_direct_dump);
1323         if (ret)
1324                 goto isc_try_fmt_err;
1325
1326         ret = isc_try_configure_pipeline(isc);
1327         if (ret)
1328                 goto isc_try_fmt_err;
1329
1330         /* Obtain frame sizes if possible to have crop requirements ready */
1331         isc_try_fse(isc, &pad_cfg);
1332
1333         v4l2_fill_mbus_format(&format.format, pixfmt, mbus_code);
1334         ret = v4l2_subdev_call(isc->current_subdev->sd, pad, set_fmt,
1335                                &pad_cfg, &format);
1336         if (ret < 0)
1337                 goto isc_try_fmt_subdev_err;
1338
1339         v4l2_fill_pix_format(pixfmt, &format.format);
1340
1341         /* Limit to Atmel ISC hardware capabilities */
1342         if (pixfmt->width > isc->max_width)
1343                 pixfmt->width = isc->max_width;
1344         if (pixfmt->height > isc->max_height)
1345                 pixfmt->height = isc->max_height;
1346
1347         pixfmt->field = V4L2_FIELD_NONE;
1348         pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp) >> 3;
1349         pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height;
1350
1351         if (code)
1352                 *code = mbus_code;
1353
1354         return 0;
1355
1356 isc_try_fmt_err:
1357         v4l2_err(&isc->v4l2_dev, "Could not find any possible format for a working pipeline\n");
1358 isc_try_fmt_subdev_err:
1359         memset(&isc->try_config, 0, sizeof(isc->try_config));
1360
1361         return ret;
1362 }
1363
1364 static int isc_set_fmt(struct isc_device *isc, struct v4l2_format *f)
1365 {
1366         struct v4l2_subdev_format format = {
1367                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1368         };
1369         u32 mbus_code = 0;
1370         int ret;
1371
1372         ret = isc_try_fmt(isc, f, &mbus_code);
1373         if (ret)
1374                 return ret;
1375
1376         v4l2_fill_mbus_format(&format.format, &f->fmt.pix, mbus_code);
1377         ret = v4l2_subdev_call(isc->current_subdev->sd, pad,
1378                                set_fmt, NULL, &format);
1379         if (ret < 0)
1380                 return ret;
1381
1382         /* Limit to Atmel ISC hardware capabilities */
1383         if (f->fmt.pix.width > isc->max_width)
1384                 f->fmt.pix.width = isc->max_width;
1385         if (f->fmt.pix.height > isc->max_height)
1386                 f->fmt.pix.height = isc->max_height;
1387
1388         isc->fmt = *f;
1389
1390         if (isc->try_config.sd_format && isc->config.sd_format &&
1391             isc->try_config.sd_format != isc->config.sd_format) {
1392                 isc->ctrls.hist_stat = HIST_INIT;
1393                 isc_reset_awb_ctrls(isc);
1394                 isc_update_v4l2_ctrls(isc);
1395         }
1396         /* make the try configuration active */
1397         isc->config = isc->try_config;
1398
1399         v4l2_dbg(1, debug, &isc->v4l2_dev, "New ISC configuration in place\n");
1400
1401         return 0;
1402 }
1403
1404 static int isc_s_fmt_vid_cap(struct file *file, void *priv,
1405                               struct v4l2_format *f)
1406 {
1407         struct isc_device *isc = video_drvdata(file);
1408
1409         if (vb2_is_streaming(&isc->vb2_vidq))
1410                 return -EBUSY;
1411
1412         return isc_set_fmt(isc, f);
1413 }
1414
1415 static int isc_try_fmt_vid_cap(struct file *file, void *priv,
1416                                 struct v4l2_format *f)
1417 {
1418         struct isc_device *isc = video_drvdata(file);
1419
1420         return isc_try_fmt(isc, f, NULL);
1421 }
1422
1423 static int isc_enum_input(struct file *file, void *priv,
1424                            struct v4l2_input *inp)
1425 {
1426         if (inp->index != 0)
1427                 return -EINVAL;
1428
1429         inp->type = V4L2_INPUT_TYPE_CAMERA;
1430         inp->std = 0;
1431         strscpy(inp->name, "Camera", sizeof(inp->name));
1432
1433         return 0;
1434 }
1435
1436 static int isc_g_input(struct file *file, void *priv, unsigned int *i)
1437 {
1438         *i = 0;
1439
1440         return 0;
1441 }
1442
1443 static int isc_s_input(struct file *file, void *priv, unsigned int i)
1444 {
1445         if (i > 0)
1446                 return -EINVAL;
1447
1448         return 0;
1449 }
1450
1451 static int isc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1452 {
1453         struct isc_device *isc = video_drvdata(file);
1454
1455         return v4l2_g_parm_cap(video_devdata(file), isc->current_subdev->sd, a);
1456 }
1457
1458 static int isc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1459 {
1460         struct isc_device *isc = video_drvdata(file);
1461
1462         return v4l2_s_parm_cap(video_devdata(file), isc->current_subdev->sd, a);
1463 }
1464
1465 static int isc_enum_framesizes(struct file *file, void *fh,
1466                                struct v4l2_frmsizeenum *fsize)
1467 {
1468         struct isc_device *isc = video_drvdata(file);
1469         struct v4l2_subdev_frame_size_enum fse = {
1470                 .code = isc->config.sd_format->mbus_code,
1471                 .index = fsize->index,
1472                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1473         };
1474         int ret = -EINVAL;
1475         int i;
1476
1477         for (i = 0; i < isc->num_user_formats; i++)
1478                 if (isc->user_formats[i]->fourcc == fsize->pixel_format)
1479                         ret = 0;
1480
1481         for (i = 0; i < ARRAY_SIZE(controller_formats); i++)
1482                 if (controller_formats[i].fourcc == fsize->pixel_format)
1483                         ret = 0;
1484
1485         if (ret)
1486                 return ret;
1487
1488         ret = v4l2_subdev_call(isc->current_subdev->sd, pad, enum_frame_size,
1489                                NULL, &fse);
1490         if (ret)
1491                 return ret;
1492
1493         fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1494         fsize->discrete.width = fse.max_width;
1495         fsize->discrete.height = fse.max_height;
1496
1497         return 0;
1498 }
1499
1500 static int isc_enum_frameintervals(struct file *file, void *fh,
1501                                     struct v4l2_frmivalenum *fival)
1502 {
1503         struct isc_device *isc = video_drvdata(file);
1504         struct v4l2_subdev_frame_interval_enum fie = {
1505                 .code = isc->config.sd_format->mbus_code,
1506                 .index = fival->index,
1507                 .width = fival->width,
1508                 .height = fival->height,
1509                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1510         };
1511         int ret = -EINVAL;
1512         unsigned int i;
1513
1514         for (i = 0; i < isc->num_user_formats; i++)
1515                 if (isc->user_formats[i]->fourcc == fival->pixel_format)
1516                         ret = 0;
1517
1518         for (i = 0; i < ARRAY_SIZE(controller_formats); i++)
1519                 if (controller_formats[i].fourcc == fival->pixel_format)
1520                         ret = 0;
1521
1522         if (ret)
1523                 return ret;
1524
1525         ret = v4l2_subdev_call(isc->current_subdev->sd, pad,
1526                                enum_frame_interval, NULL, &fie);
1527         if (ret)
1528                 return ret;
1529
1530         fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
1531         fival->discrete = fie.interval;
1532
1533         return 0;
1534 }
1535
1536 static const struct v4l2_ioctl_ops isc_ioctl_ops = {
1537         .vidioc_querycap                = isc_querycap,
1538         .vidioc_enum_fmt_vid_cap        = isc_enum_fmt_vid_cap,
1539         .vidioc_g_fmt_vid_cap           = isc_g_fmt_vid_cap,
1540         .vidioc_s_fmt_vid_cap           = isc_s_fmt_vid_cap,
1541         .vidioc_try_fmt_vid_cap         = isc_try_fmt_vid_cap,
1542
1543         .vidioc_enum_input              = isc_enum_input,
1544         .vidioc_g_input                 = isc_g_input,
1545         .vidioc_s_input                 = isc_s_input,
1546
1547         .vidioc_reqbufs                 = vb2_ioctl_reqbufs,
1548         .vidioc_querybuf                = vb2_ioctl_querybuf,
1549         .vidioc_qbuf                    = vb2_ioctl_qbuf,
1550         .vidioc_expbuf                  = vb2_ioctl_expbuf,
1551         .vidioc_dqbuf                   = vb2_ioctl_dqbuf,
1552         .vidioc_create_bufs             = vb2_ioctl_create_bufs,
1553         .vidioc_prepare_buf             = vb2_ioctl_prepare_buf,
1554         .vidioc_streamon                = vb2_ioctl_streamon,
1555         .vidioc_streamoff               = vb2_ioctl_streamoff,
1556
1557         .vidioc_g_parm                  = isc_g_parm,
1558         .vidioc_s_parm                  = isc_s_parm,
1559         .vidioc_enum_framesizes         = isc_enum_framesizes,
1560         .vidioc_enum_frameintervals     = isc_enum_frameintervals,
1561
1562         .vidioc_log_status              = v4l2_ctrl_log_status,
1563         .vidioc_subscribe_event         = v4l2_ctrl_subscribe_event,
1564         .vidioc_unsubscribe_event       = v4l2_event_unsubscribe,
1565 };
1566
1567 static int isc_open(struct file *file)
1568 {
1569         struct isc_device *isc = video_drvdata(file);
1570         struct v4l2_subdev *sd = isc->current_subdev->sd;
1571         int ret;
1572
1573         if (mutex_lock_interruptible(&isc->lock))
1574                 return -ERESTARTSYS;
1575
1576         ret = v4l2_fh_open(file);
1577         if (ret < 0)
1578                 goto unlock;
1579
1580         if (!v4l2_fh_is_singular_file(file))
1581                 goto unlock;
1582
1583         ret = v4l2_subdev_call(sd, core, s_power, 1);
1584         if (ret < 0 && ret != -ENOIOCTLCMD) {
1585                 v4l2_fh_release(file);
1586                 goto unlock;
1587         }
1588
1589         ret = isc_set_fmt(isc, &isc->fmt);
1590         if (ret) {
1591                 v4l2_subdev_call(sd, core, s_power, 0);
1592                 v4l2_fh_release(file);
1593         }
1594
1595 unlock:
1596         mutex_unlock(&isc->lock);
1597         return ret;
1598 }
1599
1600 static int isc_release(struct file *file)
1601 {
1602         struct isc_device *isc = video_drvdata(file);
1603         struct v4l2_subdev *sd = isc->current_subdev->sd;
1604         bool fh_singular;
1605         int ret;
1606
1607         mutex_lock(&isc->lock);
1608
1609         fh_singular = v4l2_fh_is_singular_file(file);
1610
1611         ret = _vb2_fop_release(file, NULL);
1612
1613         if (fh_singular)
1614                 v4l2_subdev_call(sd, core, s_power, 0);
1615
1616         mutex_unlock(&isc->lock);
1617
1618         return ret;
1619 }
1620
1621 static const struct v4l2_file_operations isc_fops = {
1622         .owner          = THIS_MODULE,
1623         .open           = isc_open,
1624         .release        = isc_release,
1625         .unlocked_ioctl = video_ioctl2,
1626         .read           = vb2_fop_read,
1627         .mmap           = vb2_fop_mmap,
1628         .poll           = vb2_fop_poll,
1629 };
1630
1631 irqreturn_t isc_interrupt(int irq, void *dev_id)
1632 {
1633         struct isc_device *isc = (struct isc_device *)dev_id;
1634         struct regmap *regmap = isc->regmap;
1635         u32 isc_intsr, isc_intmask, pending;
1636         irqreturn_t ret = IRQ_NONE;
1637
1638         regmap_read(regmap, ISC_INTSR, &isc_intsr);
1639         regmap_read(regmap, ISC_INTMASK, &isc_intmask);
1640
1641         pending = isc_intsr & isc_intmask;
1642
1643         if (likely(pending & ISC_INT_DDONE)) {
1644                 spin_lock(&isc->dma_queue_lock);
1645                 if (isc->cur_frm) {
1646                         struct vb2_v4l2_buffer *vbuf = &isc->cur_frm->vb;
1647                         struct vb2_buffer *vb = &vbuf->vb2_buf;
1648
1649                         vb->timestamp = ktime_get_ns();
1650                         vbuf->sequence = isc->sequence++;
1651                         vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1652                         isc->cur_frm = NULL;
1653                 }
1654
1655                 if (!list_empty(&isc->dma_queue) && !isc->stop) {
1656                         isc->cur_frm = list_first_entry(&isc->dma_queue,
1657                                                      struct isc_buffer, list);
1658                         list_del(&isc->cur_frm->list);
1659
1660                         isc_start_dma(isc);
1661                 }
1662
1663                 if (isc->stop)
1664                         complete(&isc->comp);
1665
1666                 ret = IRQ_HANDLED;
1667                 spin_unlock(&isc->dma_queue_lock);
1668         }
1669
1670         if (pending & ISC_INT_HISDONE) {
1671                 schedule_work(&isc->awb_work);
1672                 ret = IRQ_HANDLED;
1673         }
1674
1675         return ret;
1676 }
1677
1678 static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max)
1679 {
1680         struct regmap *regmap = isc->regmap;
1681         struct isc_ctrls *ctrls = &isc->ctrls;
1682         u32 *hist_count = &ctrls->hist_count[ctrls->hist_id];
1683         u32 *hist_entry = &ctrls->hist_entry[0];
1684         u32 i;
1685
1686         *min = 0;
1687         *max = HIST_ENTRIES;
1688
1689         regmap_bulk_read(regmap, ISC_HIS_ENTRY + isc->offsets.his_entry,
1690                          hist_entry, HIST_ENTRIES);
1691
1692         *hist_count = 0;
1693         /*
1694          * we deliberately ignore the end of the histogram,
1695          * the most white pixels
1696          */
1697         for (i = 1; i < HIST_ENTRIES; i++) {
1698                 if (*hist_entry && !*min)
1699                         *min = i;
1700                 if (*hist_entry)
1701                         *max = i;
1702                 *hist_count += i * (*hist_entry++);
1703         }
1704
1705         if (!*min)
1706                 *min = 1;
1707 }
1708
1709 static void isc_wb_update(struct isc_ctrls *ctrls)
1710 {
1711         u32 *hist_count = &ctrls->hist_count[0];
1712         u32 c, offset[4];
1713         u64 avg = 0;
1714         /* We compute two gains, stretch gain and grey world gain */
1715         u32 s_gain[4], gw_gain[4];
1716
1717         /*
1718          * According to Grey World, we need to set gains for R/B to normalize
1719          * them towards the green channel.
1720          * Thus we want to keep Green as fixed and adjust only Red/Blue
1721          * Compute the average of the both green channels first
1722          */
1723         avg = (u64)hist_count[ISC_HIS_CFG_MODE_GR] +
1724                 (u64)hist_count[ISC_HIS_CFG_MODE_GB];
1725         avg >>= 1;
1726
1727         /* Green histogram is null, nothing to do */
1728         if (!avg)
1729                 return;
1730
1731         for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) {
1732                 /*
1733                  * the color offset is the minimum value of the histogram.
1734                  * we stretch this color to the full range by substracting
1735                  * this value from the color component.
1736                  */
1737                 offset[c] = ctrls->hist_minmax[c][HIST_MIN_INDEX];
1738                 /*
1739                  * The offset is always at least 1. If the offset is 1, we do
1740                  * not need to adjust it, so our result must be zero.
1741                  * the offset is computed in a histogram on 9 bits (0..512)
1742                  * but the offset in register is based on
1743                  * 12 bits pipeline (0..4096).
1744                  * we need to shift with the 3 bits that the histogram is
1745                  * ignoring
1746                  */
1747                 ctrls->offset[c] = (offset[c] - 1) << 3;
1748
1749                 /*
1750                  * the offset is then taken and converted to 2's complements,
1751                  * and must be negative, as we subtract this value from the
1752                  * color components
1753                  */
1754                 ctrls->offset[c] = -ctrls->offset[c];
1755
1756                 /*
1757                  * the stretch gain is the total number of histogram bins
1758                  * divided by the actual range of color component (Max - Min)
1759                  * If we compute gain like this, the actual color component
1760                  * will be stretched to the full histogram.
1761                  * We need to shift 9 bits for precision, we have 9 bits for
1762                  * decimals
1763                  */
1764                 s_gain[c] = (HIST_ENTRIES << 9) /
1765                         (ctrls->hist_minmax[c][HIST_MAX_INDEX] -
1766                         ctrls->hist_minmax[c][HIST_MIN_INDEX] + 1);
1767
1768                 /*
1769                  * Now we have to compute the gain w.r.t. the average.
1770                  * Add/lose gain to the component towards the average.
1771                  * If it happens that the component is zero, use the
1772                  * fixed point value : 1.0 gain.
1773                  */
1774                 if (hist_count[c])
1775                         gw_gain[c] = div_u64(avg << 9, hist_count[c]);
1776                 else
1777                         gw_gain[c] = 1 << 9;
1778
1779                 /* multiply both gains and adjust for decimals */
1780                 ctrls->gain[c] = s_gain[c] * gw_gain[c];
1781                 ctrls->gain[c] >>= 9;
1782         }
1783 }
1784
1785 static void isc_awb_work(struct work_struct *w)
1786 {
1787         struct isc_device *isc =
1788                 container_of(w, struct isc_device, awb_work);
1789         struct regmap *regmap = isc->regmap;
1790         struct isc_ctrls *ctrls = &isc->ctrls;
1791         u32 hist_id = ctrls->hist_id;
1792         u32 baysel;
1793         unsigned long flags;
1794         u32 min, max;
1795         int ret;
1796
1797         /* streaming is not active anymore */
1798         if (isc->stop)
1799                 return;
1800
1801         if (ctrls->hist_stat != HIST_ENABLED)
1802                 return;
1803
1804         isc_hist_count(isc, &min, &max);
1805         ctrls->hist_minmax[hist_id][HIST_MIN_INDEX] = min;
1806         ctrls->hist_minmax[hist_id][HIST_MAX_INDEX] = max;
1807
1808         if (hist_id != ISC_HIS_CFG_MODE_B) {
1809                 hist_id++;
1810         } else {
1811                 isc_wb_update(ctrls);
1812                 hist_id = ISC_HIS_CFG_MODE_GR;
1813         }
1814
1815         ctrls->hist_id = hist_id;
1816         baysel = isc->config.sd_format->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT;
1817
1818         ret = pm_runtime_resume_and_get(isc->dev);
1819         if (ret < 0)
1820                 return;
1821
1822         /*
1823          * only update if we have all the required histograms and controls
1824          * if awb has been disabled, we need to reset registers as well.
1825          */
1826         if (hist_id == ISC_HIS_CFG_MODE_GR || ctrls->awb == ISC_WB_NONE) {
1827                 /*
1828                  * It may happen that DMA Done IRQ will trigger while we are
1829                  * updating white balance registers here.
1830                  * In that case, only parts of the controls have been updated.
1831                  * We can avoid that by locking the section.
1832                  */
1833                 spin_lock_irqsave(&isc->awb_lock, flags);
1834                 isc_update_awb_ctrls(isc);
1835                 spin_unlock_irqrestore(&isc->awb_lock, flags);
1836
1837                 /*
1838                  * if we are doing just the one time white balance adjustment,
1839                  * we are basically done.
1840                  */
1841                 if (ctrls->awb == ISC_WB_ONETIME) {
1842                         v4l2_info(&isc->v4l2_dev,
1843                                   "Completed one time white-balance adjustment.\n");
1844                         /* update the v4l2 controls values */
1845                         isc_update_v4l2_ctrls(isc);
1846                         ctrls->awb = ISC_WB_NONE;
1847                 }
1848         }
1849         regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his,
1850                      hist_id | baysel | ISC_HIS_CFG_RAR);
1851         isc_update_profile(isc);
1852         /* if awb has been disabled, we don't need to start another histogram */
1853         if (ctrls->awb)
1854                 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ);
1855
1856         pm_runtime_put_sync(isc->dev);
1857 }
1858
1859 static int isc_s_ctrl(struct v4l2_ctrl *ctrl)
1860 {
1861         struct isc_device *isc = container_of(ctrl->handler,
1862                                              struct isc_device, ctrls.handler);
1863         struct isc_ctrls *ctrls = &isc->ctrls;
1864
1865         if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
1866                 return 0;
1867
1868         switch (ctrl->id) {
1869         case V4L2_CID_BRIGHTNESS:
1870                 ctrls->brightness = ctrl->val & ISC_CBC_BRIGHT_MASK;
1871                 break;
1872         case V4L2_CID_CONTRAST:
1873                 ctrls->contrast = ctrl->val & ISC_CBC_CONTRAST_MASK;
1874                 break;
1875         case V4L2_CID_GAMMA:
1876                 ctrls->gamma_index = ctrl->val;
1877                 break;
1878         default:
1879                 return -EINVAL;
1880         }
1881
1882         return 0;
1883 }
1884
1885 static const struct v4l2_ctrl_ops isc_ctrl_ops = {
1886         .s_ctrl = isc_s_ctrl,
1887 };
1888
1889 static int isc_s_awb_ctrl(struct v4l2_ctrl *ctrl)
1890 {
1891         struct isc_device *isc = container_of(ctrl->handler,
1892                                              struct isc_device, ctrls.handler);
1893         struct isc_ctrls *ctrls = &isc->ctrls;
1894
1895         if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
1896                 return 0;
1897
1898         switch (ctrl->id) {
1899         case V4L2_CID_AUTO_WHITE_BALANCE:
1900                 if (ctrl->val == 1)
1901                         ctrls->awb = ISC_WB_AUTO;
1902                 else
1903                         ctrls->awb = ISC_WB_NONE;
1904
1905                 /* we did not configure ISC yet */
1906                 if (!isc->config.sd_format)
1907                         break;
1908
1909                 /* configure the controls with new values from v4l2 */
1910                 if (ctrl->cluster[ISC_CTRL_R_GAIN]->is_new)
1911                         ctrls->gain[ISC_HIS_CFG_MODE_R] = isc->r_gain_ctrl->val;
1912                 if (ctrl->cluster[ISC_CTRL_B_GAIN]->is_new)
1913                         ctrls->gain[ISC_HIS_CFG_MODE_B] = isc->b_gain_ctrl->val;
1914                 if (ctrl->cluster[ISC_CTRL_GR_GAIN]->is_new)
1915                         ctrls->gain[ISC_HIS_CFG_MODE_GR] = isc->gr_gain_ctrl->val;
1916                 if (ctrl->cluster[ISC_CTRL_GB_GAIN]->is_new)
1917                         ctrls->gain[ISC_HIS_CFG_MODE_GB] = isc->gb_gain_ctrl->val;
1918
1919                 if (ctrl->cluster[ISC_CTRL_R_OFF]->is_new)
1920                         ctrls->offset[ISC_HIS_CFG_MODE_R] = isc->r_off_ctrl->val;
1921                 if (ctrl->cluster[ISC_CTRL_B_OFF]->is_new)
1922                         ctrls->offset[ISC_HIS_CFG_MODE_B] = isc->b_off_ctrl->val;
1923                 if (ctrl->cluster[ISC_CTRL_GR_OFF]->is_new)
1924                         ctrls->offset[ISC_HIS_CFG_MODE_GR] = isc->gr_off_ctrl->val;
1925                 if (ctrl->cluster[ISC_CTRL_GB_OFF]->is_new)
1926                         ctrls->offset[ISC_HIS_CFG_MODE_GB] = isc->gb_off_ctrl->val;
1927
1928                 isc_update_awb_ctrls(isc);
1929
1930                 if (vb2_is_streaming(&isc->vb2_vidq)) {
1931                         /*
1932                          * If we are streaming, we can update profile to
1933                          * have the new settings in place.
1934                          */
1935                         isc_update_profile(isc);
1936                 } else {
1937                         /*
1938                          * The auto cluster will activate automatically this
1939                          * control. This has to be deactivated when not
1940                          * streaming.
1941                          */
1942                         v4l2_ctrl_activate(isc->do_wb_ctrl, false);
1943                 }
1944
1945                 /* if we have autowhitebalance on, start histogram procedure */
1946                 if (ctrls->awb == ISC_WB_AUTO &&
1947                     vb2_is_streaming(&isc->vb2_vidq) &&
1948                     ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
1949                         isc_set_histogram(isc, true);
1950
1951                 /*
1952                  * for one time whitebalance adjustment, check the button,
1953                  * if it's pressed, perform the one time operation.
1954                  */
1955                 if (ctrls->awb == ISC_WB_NONE &&
1956                     ctrl->cluster[ISC_CTRL_DO_WB]->is_new &&
1957                     !(ctrl->cluster[ISC_CTRL_DO_WB]->flags &
1958                     V4L2_CTRL_FLAG_INACTIVE)) {
1959                         ctrls->awb = ISC_WB_ONETIME;
1960                         isc_set_histogram(isc, true);
1961                         v4l2_dbg(1, debug, &isc->v4l2_dev,
1962                                  "One time white-balance started.\n");
1963                 }
1964                 return 0;
1965         }
1966         return 0;
1967 }
1968
1969 static int isc_g_volatile_awb_ctrl(struct v4l2_ctrl *ctrl)
1970 {
1971         struct isc_device *isc = container_of(ctrl->handler,
1972                                              struct isc_device, ctrls.handler);
1973         struct isc_ctrls *ctrls = &isc->ctrls;
1974
1975         switch (ctrl->id) {
1976         /* being a cluster, this id will be called for every control */
1977         case V4L2_CID_AUTO_WHITE_BALANCE:
1978                 ctrl->cluster[ISC_CTRL_R_GAIN]->val =
1979                                         ctrls->gain[ISC_HIS_CFG_MODE_R];
1980                 ctrl->cluster[ISC_CTRL_B_GAIN]->val =
1981                                         ctrls->gain[ISC_HIS_CFG_MODE_B];
1982                 ctrl->cluster[ISC_CTRL_GR_GAIN]->val =
1983                                         ctrls->gain[ISC_HIS_CFG_MODE_GR];
1984                 ctrl->cluster[ISC_CTRL_GB_GAIN]->val =
1985                                         ctrls->gain[ISC_HIS_CFG_MODE_GB];
1986
1987                 ctrl->cluster[ISC_CTRL_R_OFF]->val =
1988                         ctrls->offset[ISC_HIS_CFG_MODE_R];
1989                 ctrl->cluster[ISC_CTRL_B_OFF]->val =
1990                         ctrls->offset[ISC_HIS_CFG_MODE_B];
1991                 ctrl->cluster[ISC_CTRL_GR_OFF]->val =
1992                         ctrls->offset[ISC_HIS_CFG_MODE_GR];
1993                 ctrl->cluster[ISC_CTRL_GB_OFF]->val =
1994                         ctrls->offset[ISC_HIS_CFG_MODE_GB];
1995                 break;
1996         }
1997         return 0;
1998 }
1999
2000 static const struct v4l2_ctrl_ops isc_awb_ops = {
2001         .s_ctrl = isc_s_awb_ctrl,
2002         .g_volatile_ctrl = isc_g_volatile_awb_ctrl,
2003 };
2004
2005 #define ISC_CTRL_OFF(_name, _id, _name_str) \
2006         static const struct v4l2_ctrl_config _name = { \
2007                 .ops = &isc_awb_ops, \
2008                 .id = _id, \
2009                 .name = _name_str, \
2010                 .type = V4L2_CTRL_TYPE_INTEGER, \
2011                 .flags = V4L2_CTRL_FLAG_SLIDER, \
2012                 .min = -4095, \
2013                 .max = 4095, \
2014                 .step = 1, \
2015                 .def = 0, \
2016         }
2017
2018 ISC_CTRL_OFF(isc_r_off_ctrl, ISC_CID_R_OFFSET, "Red Component Offset");
2019 ISC_CTRL_OFF(isc_b_off_ctrl, ISC_CID_B_OFFSET, "Blue Component Offset");
2020 ISC_CTRL_OFF(isc_gr_off_ctrl, ISC_CID_GR_OFFSET, "Green Red Component Offset");
2021 ISC_CTRL_OFF(isc_gb_off_ctrl, ISC_CID_GB_OFFSET, "Green Blue Component Offset");
2022
2023 #define ISC_CTRL_GAIN(_name, _id, _name_str) \
2024         static const struct v4l2_ctrl_config _name = { \
2025                 .ops = &isc_awb_ops, \
2026                 .id = _id, \
2027                 .name = _name_str, \
2028                 .type = V4L2_CTRL_TYPE_INTEGER, \
2029                 .flags = V4L2_CTRL_FLAG_SLIDER, \
2030                 .min = 0, \
2031                 .max = 8191, \
2032                 .step = 1, \
2033                 .def = 512, \
2034         }
2035
2036 ISC_CTRL_GAIN(isc_r_gain_ctrl, ISC_CID_R_GAIN, "Red Component Gain");
2037 ISC_CTRL_GAIN(isc_b_gain_ctrl, ISC_CID_B_GAIN, "Blue Component Gain");
2038 ISC_CTRL_GAIN(isc_gr_gain_ctrl, ISC_CID_GR_GAIN, "Green Red Component Gain");
2039 ISC_CTRL_GAIN(isc_gb_gain_ctrl, ISC_CID_GB_GAIN, "Green Blue Component Gain");
2040
2041 static int isc_ctrl_init(struct isc_device *isc)
2042 {
2043         const struct v4l2_ctrl_ops *ops = &isc_ctrl_ops;
2044         struct isc_ctrls *ctrls = &isc->ctrls;
2045         struct v4l2_ctrl_handler *hdl = &ctrls->handler;
2046         int ret;
2047
2048         ctrls->hist_stat = HIST_INIT;
2049         isc_reset_awb_ctrls(isc);
2050
2051         ret = v4l2_ctrl_handler_init(hdl, 13);
2052         if (ret < 0)
2053                 return ret;
2054
2055         /* Initialize product specific controls. For example, contrast */
2056         isc->config_ctrls(isc, ops);
2057
2058         ctrls->brightness = 0;
2059
2060         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0);
2061         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1,
2062                           isc->gamma_max);
2063         isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,
2064                                           V4L2_CID_AUTO_WHITE_BALANCE,
2065                                           0, 1, 1, 1);
2066
2067         /* do_white_balance is a button, so min,max,step,default are ignored */
2068         isc->do_wb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,
2069                                             V4L2_CID_DO_WHITE_BALANCE,
2070                                             0, 0, 0, 0);
2071
2072         if (!isc->do_wb_ctrl) {
2073                 ret = hdl->error;
2074                 v4l2_ctrl_handler_free(hdl);
2075                 return ret;
2076         }
2077
2078         v4l2_ctrl_activate(isc->do_wb_ctrl, false);
2079
2080         isc->r_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_gain_ctrl, NULL);
2081         isc->b_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_gain_ctrl, NULL);
2082         isc->gr_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_gain_ctrl, NULL);
2083         isc->gb_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_gain_ctrl, NULL);
2084         isc->r_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_off_ctrl, NULL);
2085         isc->b_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_off_ctrl, NULL);
2086         isc->gr_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_off_ctrl, NULL);
2087         isc->gb_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_off_ctrl, NULL);
2088
2089         /*
2090          * The cluster is in auto mode with autowhitebalance enabled
2091          * and manual mode otherwise.
2092          */
2093         v4l2_ctrl_auto_cluster(10, &isc->awb_ctrl, 0, true);
2094
2095         v4l2_ctrl_handler_setup(hdl);
2096
2097         return 0;
2098 }
2099
2100 static int isc_async_bound(struct v4l2_async_notifier *notifier,
2101                             struct v4l2_subdev *subdev,
2102                             struct v4l2_async_subdev *asd)
2103 {
2104         struct isc_device *isc = container_of(notifier->v4l2_dev,
2105                                               struct isc_device, v4l2_dev);
2106         struct isc_subdev_entity *subdev_entity =
2107                 container_of(notifier, struct isc_subdev_entity, notifier);
2108
2109         if (video_is_registered(&isc->video_dev)) {
2110                 v4l2_err(&isc->v4l2_dev, "only supports one sub-device.\n");
2111                 return -EBUSY;
2112         }
2113
2114         subdev_entity->sd = subdev;
2115
2116         return 0;
2117 }
2118
2119 static void isc_async_unbind(struct v4l2_async_notifier *notifier,
2120                               struct v4l2_subdev *subdev,
2121                               struct v4l2_async_subdev *asd)
2122 {
2123         struct isc_device *isc = container_of(notifier->v4l2_dev,
2124                                               struct isc_device, v4l2_dev);
2125         cancel_work_sync(&isc->awb_work);
2126         video_unregister_device(&isc->video_dev);
2127         v4l2_ctrl_handler_free(&isc->ctrls.handler);
2128 }
2129
2130 static struct isc_format *find_format_by_code(unsigned int code, int *index)
2131 {
2132         struct isc_format *fmt = &formats_list[0];
2133         unsigned int i;
2134
2135         for (i = 0; i < ARRAY_SIZE(formats_list); i++) {
2136                 if (fmt->mbus_code == code) {
2137                         *index = i;
2138                         return fmt;
2139                 }
2140
2141                 fmt++;
2142         }
2143
2144         return NULL;
2145 }
2146
2147 static int isc_formats_init(struct isc_device *isc)
2148 {
2149         struct isc_format *fmt;
2150         struct v4l2_subdev *subdev = isc->current_subdev->sd;
2151         unsigned int num_fmts, i, j;
2152         u32 list_size = ARRAY_SIZE(formats_list);
2153         struct v4l2_subdev_mbus_code_enum mbus_code = {
2154                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
2155         };
2156
2157         num_fmts = 0;
2158         while (!v4l2_subdev_call(subdev, pad, enum_mbus_code,
2159                NULL, &mbus_code)) {
2160                 mbus_code.index++;
2161
2162                 fmt = find_format_by_code(mbus_code.code, &i);
2163                 if (!fmt) {
2164                         v4l2_warn(&isc->v4l2_dev, "Mbus code %x not supported\n",
2165                                   mbus_code.code);
2166                         continue;
2167                 }
2168
2169                 fmt->sd_support = true;
2170                 num_fmts++;
2171         }
2172
2173         if (!num_fmts)
2174                 return -ENXIO;
2175
2176         isc->num_user_formats = num_fmts;
2177         isc->user_formats = devm_kcalloc(isc->dev,
2178                                          num_fmts, sizeof(*isc->user_formats),
2179                                          GFP_KERNEL);
2180         if (!isc->user_formats)
2181                 return -ENOMEM;
2182
2183         fmt = &formats_list[0];
2184         for (i = 0, j = 0; i < list_size; i++) {
2185                 if (fmt->sd_support)
2186                         isc->user_formats[j++] = fmt;
2187                 fmt++;
2188         }
2189
2190         return 0;
2191 }
2192
2193 static int isc_set_default_fmt(struct isc_device *isc)
2194 {
2195         struct v4l2_format f = {
2196                 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
2197                 .fmt.pix = {
2198                         .width          = VGA_WIDTH,
2199                         .height         = VGA_HEIGHT,
2200                         .field          = V4L2_FIELD_NONE,
2201                         .pixelformat    = isc->user_formats[0]->fourcc,
2202                 },
2203         };
2204         int ret;
2205
2206         ret = isc_try_fmt(isc, &f, NULL);
2207         if (ret)
2208                 return ret;
2209
2210         isc->fmt = f;
2211         return 0;
2212 }
2213
2214 static int isc_async_complete(struct v4l2_async_notifier *notifier)
2215 {
2216         struct isc_device *isc = container_of(notifier->v4l2_dev,
2217                                               struct isc_device, v4l2_dev);
2218         struct video_device *vdev = &isc->video_dev;
2219         struct vb2_queue *q = &isc->vb2_vidq;
2220         int ret = 0;
2221
2222         INIT_WORK(&isc->awb_work, isc_awb_work);
2223
2224         ret = v4l2_device_register_subdev_nodes(&isc->v4l2_dev);
2225         if (ret < 0) {
2226                 v4l2_err(&isc->v4l2_dev, "Failed to register subdev nodes\n");
2227                 return ret;
2228         }
2229
2230         isc->current_subdev = container_of(notifier,
2231                                            struct isc_subdev_entity, notifier);
2232         mutex_init(&isc->lock);
2233         init_completion(&isc->comp);
2234
2235         /* Initialize videobuf2 queue */
2236         q->type                 = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2237         q->io_modes             = VB2_MMAP | VB2_DMABUF | VB2_READ;
2238         q->drv_priv             = isc;
2239         q->buf_struct_size      = sizeof(struct isc_buffer);
2240         q->ops                  = &isc_vb2_ops;
2241         q->mem_ops              = &vb2_dma_contig_memops;
2242         q->timestamp_flags      = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
2243         q->lock                 = &isc->lock;
2244         q->min_buffers_needed   = 1;
2245         q->dev                  = isc->dev;
2246
2247         ret = vb2_queue_init(q);
2248         if (ret < 0) {
2249                 v4l2_err(&isc->v4l2_dev,
2250                          "vb2_queue_init() failed: %d\n", ret);
2251                 goto isc_async_complete_err;
2252         }
2253
2254         /* Init video dma queues */
2255         INIT_LIST_HEAD(&isc->dma_queue);
2256         spin_lock_init(&isc->dma_queue_lock);
2257         spin_lock_init(&isc->awb_lock);
2258
2259         ret = isc_formats_init(isc);
2260         if (ret < 0) {
2261                 v4l2_err(&isc->v4l2_dev,
2262                          "Init format failed: %d\n", ret);
2263                 goto isc_async_complete_err;
2264         }
2265
2266         ret = isc_set_default_fmt(isc);
2267         if (ret) {
2268                 v4l2_err(&isc->v4l2_dev, "Could not set default format\n");
2269                 goto isc_async_complete_err;
2270         }
2271
2272         ret = isc_ctrl_init(isc);
2273         if (ret) {
2274                 v4l2_err(&isc->v4l2_dev, "Init isc ctrols failed: %d\n", ret);
2275                 goto isc_async_complete_err;
2276         }
2277
2278         /* Register video device */
2279         strscpy(vdev->name, "microchip-isc", sizeof(vdev->name));
2280         vdev->release           = video_device_release_empty;
2281         vdev->fops              = &isc_fops;
2282         vdev->ioctl_ops         = &isc_ioctl_ops;
2283         vdev->v4l2_dev          = &isc->v4l2_dev;
2284         vdev->vfl_dir           = VFL_DIR_RX;
2285         vdev->queue             = q;
2286         vdev->lock              = &isc->lock;
2287         vdev->ctrl_handler      = &isc->ctrls.handler;
2288         vdev->device_caps       = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE;
2289         video_set_drvdata(vdev, isc);
2290
2291         ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
2292         if (ret < 0) {
2293                 v4l2_err(&isc->v4l2_dev,
2294                          "video_register_device failed: %d\n", ret);
2295                 goto isc_async_complete_err;
2296         }
2297
2298         return 0;
2299
2300 isc_async_complete_err:
2301         mutex_destroy(&isc->lock);
2302         return ret;
2303 }
2304
2305 const struct v4l2_async_notifier_operations isc_async_ops = {
2306         .bound = isc_async_bound,
2307         .unbind = isc_async_unbind,
2308         .complete = isc_async_complete,
2309 };
2310
2311 void isc_subdev_cleanup(struct isc_device *isc)
2312 {
2313         struct isc_subdev_entity *subdev_entity;
2314
2315         list_for_each_entry(subdev_entity, &isc->subdev_entities, list) {
2316                 v4l2_async_notifier_unregister(&subdev_entity->notifier);
2317                 v4l2_async_notifier_cleanup(&subdev_entity->notifier);
2318         }
2319
2320         INIT_LIST_HEAD(&isc->subdev_entities);
2321 }
2322
2323 int isc_pipeline_init(struct isc_device *isc)
2324 {
2325         struct device *dev = isc->dev;
2326         struct regmap *regmap = isc->regmap;
2327         struct regmap_field *regs;
2328         unsigned int i;
2329
2330         /*
2331          * DPCEN-->GDCEN-->BLCEN-->WB-->CFA-->CC-->
2332          * GAM-->VHXS-->CSC-->CBC-->SUB422-->SUB420
2333          */
2334         const struct reg_field regfields[ISC_PIPE_LINE_NODE_NUM] = {
2335                 REG_FIELD(ISC_DPC_CTRL, 0, 0),
2336                 REG_FIELD(ISC_DPC_CTRL, 1, 1),
2337                 REG_FIELD(ISC_DPC_CTRL, 2, 2),
2338                 REG_FIELD(ISC_WB_CTRL, 0, 0),
2339                 REG_FIELD(ISC_CFA_CTRL, 0, 0),
2340                 REG_FIELD(ISC_CC_CTRL, 0, 0),
2341                 REG_FIELD(ISC_GAM_CTRL, 0, 0),
2342                 REG_FIELD(ISC_GAM_CTRL, 1, 1),
2343                 REG_FIELD(ISC_GAM_CTRL, 2, 2),
2344                 REG_FIELD(ISC_GAM_CTRL, 3, 3),
2345                 REG_FIELD(ISC_VHXS_CTRL, 0, 0),
2346                 REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0),
2347                 REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0),
2348                 REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0),
2349                 REG_FIELD(ISC_SUB420_CTRL + isc->offsets.sub420, 0, 0),
2350         };
2351
2352         for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
2353                 regs = devm_regmap_field_alloc(dev, regmap, regfields[i]);
2354                 if (IS_ERR(regs))
2355                         return PTR_ERR(regs);
2356
2357                 isc->pipeline[i] =  regs;
2358         }
2359
2360         return 0;
2361 }
2362
2363 /* regmap configuration */
2364 #define ATMEL_ISC_REG_MAX    0xd5c
2365 const struct regmap_config isc_regmap_config = {
2366         .reg_bits       = 32,
2367         .reg_stride     = 4,
2368         .val_bits       = 32,
2369         .max_register   = ATMEL_ISC_REG_MAX,
2370 };
2371