drivers/media/pci/cx23885/cx23885-core.c

   1 /*
   2  *  Driver for the Conexant CX23885 PCIe bridge
   3  *
   4  *  Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *
  15  *  GNU General Public License for more details.
  16  */
  17
  18 #include "cx23885.h"
  19
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/module.h>
  23 #include <linux/moduleparam.h>
  24 #include <linux/kmod.h>
  25 #include <linux/kernel.h>
  26 #include <linux/slab.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/delay.h>
  29 #include <asm/div64.h>
  30 #include <linux/firmware.h>
  31
  32 #include "cimax2.h"
  33 #include "altera-ci.h"
  34 #include "cx23888-ir.h"
  35 #include "cx23885-ir.h"
  36 #include "cx23885-av.h"
  37 #include "cx23885-input.h"
  38
  39 MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
  40 MODULE_AUTHOR("Steven Toth <stoth@linuxtv.org>");
  41 MODULE_LICENSE("GPL");
  42 MODULE_VERSION(CX23885_VERSION);
  43
  44 static unsigned int debug;
  45 module_param(debug, int, 0644);
  46 MODULE_PARM_DESC(debug, "enable debug messages");
  47
  48 static unsigned int card[]  = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
  49 module_param_array(card,  int, NULL, 0444);
  50 MODULE_PARM_DESC(card, "card type");
  51
  52 #define dprintk(level, fmt, arg...)\
  53         do { if (debug >= level)\
  54                 printk(KERN_DEBUG pr_fmt("%s: " fmt), \
  55                        __func__, ##arg); \
  56         } while (0)
  57
  58 static unsigned int cx23885_devcount;
  59
  60 #define NO_SYNC_LINE (-1U)
  61
  62 /* FIXME, these allocations will change when
  63  * analog arrives. The be reviewed.
  64  * CX23887 Assumptions
  65  * 1 line = 16 bytes of CDT
  66  * cmds size = 80
  67  * cdt size = 16 * linesize
  68  * iqsize = 64
  69  * maxlines = 6
  70  *
  71  * Address Space:
  72  * 0x00000000 0x00008fff FIFO clusters
  73  * 0x00010000 0x000104af Channel Management Data Structures
  74  * 0x000104b0 0x000104ff Free
  75  * 0x00010500 0x000108bf 15 channels * iqsize
  76  * 0x000108c0 0x000108ff Free
  77  * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
  78  *                       15 channels * (iqsize + (maxlines * linesize))
  79  * 0x00010ea0 0x00010xxx Free
  80  */
  81
  82 static struct sram_channel cx23885_sram_channels[] = {
  83         [SRAM_CH01] = {
  84                 .name           = "VID A",
  85                 .cmds_start     = 0x10000,
  86                 .ctrl_start     = 0x10380,
  87                 .cdt            = 0x104c0,
  88                 .fifo_start     = 0x40,
  89                 .fifo_size      = 0x2800,
  90                 .ptr1_reg       = DMA1_PTR1,
  91                 .ptr2_reg       = DMA1_PTR2,
  92                 .cnt1_reg       = DMA1_CNT1,
  93                 .cnt2_reg       = DMA1_CNT2,
  94         },
  95         [SRAM_CH02] = {
  96                 .name           = "ch2",
  97                 .cmds_start     = 0x0,
  98                 .ctrl_start     = 0x0,
  99                 .cdt            = 0x0,
 100                 .fifo_start     = 0x0,
 101                 .fifo_size      = 0x0,
 102                 .ptr1_reg       = DMA2_PTR1,
 103                 .ptr2_reg       = DMA2_PTR2,
 104                 .cnt1_reg       = DMA2_CNT1,
 105                 .cnt2_reg       = DMA2_CNT2,
 106         },
 107         [SRAM_CH03] = {
 108                 .name           = "TS1 B",
 109                 .cmds_start     = 0x100A0,
 110                 .ctrl_start     = 0x10400,
 111                 .cdt            = 0x10580,
 112                 .fifo_start     = 0x5000,
 113                 .fifo_size      = 0x1000,
 114                 .ptr1_reg       = DMA3_PTR1,
 115                 .ptr2_reg       = DMA3_PTR2,
 116                 .cnt1_reg       = DMA3_CNT1,
 117                 .cnt2_reg       = DMA3_CNT2,
 118         },
 119         [SRAM_CH04] = {
 120                 .name           = "ch4",
 121                 .cmds_start     = 0x0,
 122                 .ctrl_start     = 0x0,
 123                 .cdt            = 0x0,
 124                 .fifo_start     = 0x0,
 125                 .fifo_size      = 0x0,
 126                 .ptr1_reg       = DMA4_PTR1,
 127                 .ptr2_reg       = DMA4_PTR2,
 128                 .cnt1_reg       = DMA4_CNT1,
 129                 .cnt2_reg       = DMA4_CNT2,
 130         },
 131         [SRAM_CH05] = {
 132                 .name           = "ch5",
 133                 .cmds_start     = 0x0,
 134                 .ctrl_start     = 0x0,
 135                 .cdt            = 0x0,
 136                 .fifo_start     = 0x0,
 137                 .fifo_size      = 0x0,
 138                 .ptr1_reg       = DMA5_PTR1,
 139                 .ptr2_reg       = DMA5_PTR2,
 140                 .cnt1_reg       = DMA5_CNT1,
 141                 .cnt2_reg       = DMA5_CNT2,
 142         },
 143         [SRAM_CH06] = {
 144                 .name           = "TS2 C",
 145                 .cmds_start     = 0x10140,
 146                 .ctrl_start     = 0x10440,
 147                 .cdt            = 0x105e0,
 148                 .fifo_start     = 0x6000,
 149                 .fifo_size      = 0x1000,
 150                 .ptr1_reg       = DMA5_PTR1,
 151                 .ptr2_reg       = DMA5_PTR2,
 152                 .cnt1_reg       = DMA5_CNT1,
 153                 .cnt2_reg       = DMA5_CNT2,
 154         },
 155         [SRAM_CH07] = {
 156                 .name           = "TV Audio",
 157                 .cmds_start     = 0x10190,
 158                 .ctrl_start     = 0x10480,
 159                 .cdt            = 0x10a00,
 160                 .fifo_start     = 0x7000,
 161                 .fifo_size      = 0x1000,
 162                 .ptr1_reg       = DMA6_PTR1,
 163                 .ptr2_reg       = DMA6_PTR2,
 164                 .cnt1_reg       = DMA6_CNT1,
 165                 .cnt2_reg       = DMA6_CNT2,
 166         },
 167         [SRAM_CH08] = {
 168                 .name           = "ch8",
 169                 .cmds_start     = 0x0,
 170                 .ctrl_start     = 0x0,
 171                 .cdt            = 0x0,
 172                 .fifo_start     = 0x0,
 173                 .fifo_size      = 0x0,
 174                 .ptr1_reg       = DMA7_PTR1,
 175                 .ptr2_reg       = DMA7_PTR2,
 176                 .cnt1_reg       = DMA7_CNT1,
 177                 .cnt2_reg       = DMA7_CNT2,
 178         },
 179         [SRAM_CH09] = {
 180                 .name           = "ch9",
 181                 .cmds_start     = 0x0,
 182                 .ctrl_start     = 0x0,
 183                 .cdt            = 0x0,
 184                 .fifo_start     = 0x0,
 185                 .fifo_size      = 0x0,
 186                 .ptr1_reg       = DMA8_PTR1,
 187                 .ptr2_reg       = DMA8_PTR2,
 188                 .cnt1_reg       = DMA8_CNT1,
 189                 .cnt2_reg       = DMA8_CNT2,
 190         },
 191 };
 192
 193 static struct sram_channel cx23887_sram_channels[] = {
 194         [SRAM_CH01] = {
 195                 .name           = "VID A",
 196                 .cmds_start     = 0x10000,
 197                 .ctrl_start     = 0x105b0,
 198                 .cdt            = 0x107b0,
 199                 .fifo_start     = 0x40,
 200                 .fifo_size      = 0x2800,
 201                 .ptr1_reg       = DMA1_PTR1,
 202                 .ptr2_reg       = DMA1_PTR2,
 203                 .cnt1_reg       = DMA1_CNT1,
 204                 .cnt2_reg       = DMA1_CNT2,
 205         },
 206         [SRAM_CH02] = {
 207                 .name           = "VID A (VBI)",
 208                 .cmds_start     = 0x10050,
 209                 .ctrl_start     = 0x105F0,
 210                 .cdt            = 0x10810,
 211                 .fifo_start     = 0x3000,
 212                 .fifo_size      = 0x1000,
 213                 .ptr1_reg       = DMA2_PTR1,
 214                 .ptr2_reg       = DMA2_PTR2,
 215                 .cnt1_reg       = DMA2_CNT1,
 216                 .cnt2_reg       = DMA2_CNT2,
 217         },
 218         [SRAM_CH03] = {
 219                 .name           = "TS1 B",
 220                 .cmds_start     = 0x100A0,
 221                 .ctrl_start     = 0x10630,
 222                 .cdt            = 0x10870,
 223                 .fifo_start     = 0x5000,
 224                 .fifo_size      = 0x1000,
 225                 .ptr1_reg       = DMA3_PTR1,
 226                 .ptr2_reg       = DMA3_PTR2,
 227                 .cnt1_reg       = DMA3_CNT1,
 228                 .cnt2_reg       = DMA3_CNT2,
 229         },
 230         [SRAM_CH04] = {
 231                 .name           = "ch4",
 232                 .cmds_start     = 0x0,
 233                 .ctrl_start     = 0x0,
 234                 .cdt            = 0x0,
 235                 .fifo_start     = 0x0,
 236                 .fifo_size      = 0x0,
 237                 .ptr1_reg       = DMA4_PTR1,
 238                 .ptr2_reg       = DMA4_PTR2,
 239                 .cnt1_reg       = DMA4_CNT1,
 240                 .cnt2_reg       = DMA4_CNT2,
 241         },
 242         [SRAM_CH05] = {
 243                 .name           = "ch5",
 244                 .cmds_start     = 0x0,
 245                 .ctrl_start     = 0x0,
 246                 .cdt            = 0x0,
 247                 .fifo_start     = 0x0,
 248                 .fifo_size      = 0x0,
 249                 .ptr1_reg       = DMA5_PTR1,
 250                 .ptr2_reg       = DMA5_PTR2,
 251                 .cnt1_reg       = DMA5_CNT1,
 252                 .cnt2_reg       = DMA5_CNT2,
 253         },
 254         [SRAM_CH06] = {
 255                 .name           = "TS2 C",
 256                 .cmds_start     = 0x10140,
 257                 .ctrl_start     = 0x10670,
 258                 .cdt            = 0x108d0,
 259                 .fifo_start     = 0x6000,
 260                 .fifo_size      = 0x1000,
 261                 .ptr1_reg       = DMA5_PTR1,
 262                 .ptr2_reg       = DMA5_PTR2,
 263                 .cnt1_reg       = DMA5_CNT1,
 264                 .cnt2_reg       = DMA5_CNT2,
 265         },
 266         [SRAM_CH07] = {
 267                 .name           = "TV Audio",
 268                 .cmds_start     = 0x10190,
 269                 .ctrl_start     = 0x106B0,
 270                 .cdt            = 0x10930,
 271                 .fifo_start     = 0x7000,
 272                 .fifo_size      = 0x1000,
 273                 .ptr1_reg       = DMA6_PTR1,
 274                 .ptr2_reg       = DMA6_PTR2,
 275                 .cnt1_reg       = DMA6_CNT1,
 276                 .cnt2_reg       = DMA6_CNT2,
 277         },
 278         [SRAM_CH08] = {
 279                 .name           = "ch8",
 280                 .cmds_start     = 0x0,
 281                 .ctrl_start     = 0x0,
 282                 .cdt            = 0x0,
 283                 .fifo_start     = 0x0,
 284                 .fifo_size      = 0x0,
 285                 .ptr1_reg       = DMA7_PTR1,
 286                 .ptr2_reg       = DMA7_PTR2,
 287                 .cnt1_reg       = DMA7_CNT1,
 288                 .cnt2_reg       = DMA7_CNT2,
 289         },
 290         [SRAM_CH09] = {
 291                 .name           = "ch9",
 292                 .cmds_start     = 0x0,
 293                 .ctrl_start     = 0x0,
 294                 .cdt            = 0x0,
 295                 .fifo_start     = 0x0,
 296                 .fifo_size      = 0x0,
 297                 .ptr1_reg       = DMA8_PTR1,
 298                 .ptr2_reg       = DMA8_PTR2,
 299                 .cnt1_reg       = DMA8_CNT1,
 300                 .cnt2_reg       = DMA8_CNT2,
 301         },
 302 };
 303
 304 static void cx23885_irq_add(struct cx23885_dev *dev, u32 mask)
 305 {
 306         unsigned long flags;
 307         spin_lock_irqsave(&dev->pci_irqmask_lock, flags);
 308
 309         dev->pci_irqmask |= mask;
 310
 311         spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags);
 312 }
 313
 314 void cx23885_irq_add_enable(struct cx23885_dev *dev, u32 mask)
 315 {
 316         unsigned long flags;
 317         spin_lock_irqsave(&dev->pci_irqmask_lock, flags);
 318
 319         dev->pci_irqmask |= mask;
 320         cx_set(PCI_INT_MSK, mask);
 321
 322         spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags);
 323 }
 324
 325 void cx23885_irq_enable(struct cx23885_dev *dev, u32 mask)
 326 {
 327         u32 v;
 328         unsigned long flags;
 329         spin_lock_irqsave(&dev->pci_irqmask_lock, flags);
 330
 331         v = mask & dev->pci_irqmask;
 332         if (v)
 333                 cx_set(PCI_INT_MSK, v);
 334
 335         spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags);
 336 }
 337
 338 static inline void cx23885_irq_enable_all(struct cx23885_dev *dev)
 339 {
 340         cx23885_irq_enable(dev, 0xffffffff);
 341 }
 342
 343 void cx23885_irq_disable(struct cx23885_dev *dev, u32 mask)
 344 {
 345         unsigned long flags;
 346         spin_lock_irqsave(&dev->pci_irqmask_lock, flags);
 347
 348         cx_clear(PCI_INT_MSK, mask);
 349
 350         spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags);
 351 }
 352
 353 static inline void cx23885_irq_disable_all(struct cx23885_dev *dev)
 354 {
 355         cx23885_irq_disable(dev, 0xffffffff);
 356 }
 357
 358 void cx23885_irq_remove(struct cx23885_dev *dev, u32 mask)
 359 {
 360         unsigned long flags;
 361         spin_lock_irqsave(&dev->pci_irqmask_lock, flags);
 362
 363         dev->pci_irqmask &= ~mask;
 364         cx_clear(PCI_INT_MSK, mask);
 365
 366         spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags);
 367 }
 368
 369 static u32 cx23885_irq_get_mask(struct cx23885_dev *dev)
 370 {
 371         u32 v;
 372         unsigned long flags;
 373         spin_lock_irqsave(&dev->pci_irqmask_lock, flags);
 374
 375         v = cx_read(PCI_INT_MSK);
 376
 377         spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags);
 378         return v;
 379 }
 380
 381 static int cx23885_risc_decode(u32 risc)
 382 {
 383         static char *instr[16] = {
 384                 [RISC_SYNC    >> 28] = "sync",
 385                 [RISC_WRITE   >> 28] = "write",
 386                 [RISC_WRITEC  >> 28] = "writec",
 387                 [RISC_READ    >> 28] = "read",
 388                 [RISC_READC   >> 28] = "readc",
 389                 [RISC_JUMP    >> 28] = "jump",
 390                 [RISC_SKIP    >> 28] = "skip",
 391                 [RISC_WRITERM >> 28] = "writerm",
 392                 [RISC_WRITECM >> 28] = "writecm",
 393                 [RISC_WRITECR >> 28] = "writecr",
 394         };
 395         static int incr[16] = {
 396                 [RISC_WRITE   >> 28] = 3,
 397                 [RISC_JUMP    >> 28] = 3,
 398                 [RISC_SKIP    >> 28] = 1,
 399                 [RISC_SYNC    >> 28] = 1,
 400                 [RISC_WRITERM >> 28] = 3,
 401                 [RISC_WRITECM >> 28] = 3,
 402                 [RISC_WRITECR >> 28] = 4,
 403         };
 404         static char *bits[] = {
 405                 "12",   "13",   "14",   "resync",
 406                 "cnt0", "cnt1", "18",   "19",
 407                 "20",   "21",   "22",   "23",
 408                 "irq1", "irq2", "eol",  "sol",
 409         };
 410         int i;
 411
 412         printk(KERN_DEBUG "0x%08x [ %s", risc,
 413                instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
 414         for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
 415                 if (risc & (1 << (i + 12)))
 416                         pr_cont(" %s", bits[i]);
 417         pr_cont(" count=%d ]\n", risc & 0xfff);
 418         return incr[risc >> 28] ? incr[risc >> 28] : 1;
 419 }
 420
 421 static void cx23885_wakeup(struct cx23885_tsport *port,
 422                            struct cx23885_dmaqueue *q, u32 count)
 423 {
 424         struct cx23885_buffer *buf;
 425         int count_delta;
 426         int max_buf_done = 5; /* service maximum five buffers */
 427
 428         do {
 429                 if (list_empty(&q->active))
 430                         return;
 431                 buf = list_entry(q->active.next,
 432                                  struct cx23885_buffer, queue);
 433
 434                 buf->vb.vb2_buf.timestamp = ktime_get_ns();
 435                 buf->vb.sequence = q->count++;
 436                 if (count != (q->count % 65536)) {
 437                         dprintk(1, "[%p/%d] wakeup reg=%d buf=%d\n", buf,
 438                                 buf->vb.vb2_buf.index, count, q->count);
 439                 } else {
 440                         dprintk(7, "[%p/%d] wakeup reg=%d buf=%d\n", buf,
 441                                 buf->vb.vb2_buf.index, count, q->count);
 442                 }
 443                 list_del(&buf->queue);
 444                 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
 445                 max_buf_done--;
 446                 /* count register is 16 bits so apply modulo appropriately */
 447                 count_delta = ((int)count - (int)(q->count % 65536));
 448         } while ((count_delta > 0) && (max_buf_done > 0));
 449 }
 450
 451 int cx23885_sram_channel_setup(struct cx23885_dev *dev,
 452                                       struct sram_channel *ch,
 453                                       unsigned int bpl, u32 risc)
 454 {
 455         unsigned int i, lines;
 456         u32 cdt;
 457
 458         if (ch->cmds_start == 0) {
 459                 dprintk(1, "%s() Erasing channel [%s]\n", __func__,
 460                         ch->name);
 461                 cx_write(ch->ptr1_reg, 0);
 462                 cx_write(ch->ptr2_reg, 0);
 463                 cx_write(ch->cnt2_reg, 0);
 464                 cx_write(ch->cnt1_reg, 0);
 465                 return 0;
 466         } else {
 467                 dprintk(1, "%s() Configuring channel [%s]\n", __func__,
 468                         ch->name);
 469         }
 470
 471         bpl   = (bpl + 7) & ~7; /* alignment */
 472         cdt   = ch->cdt;
 473         lines = ch->fifo_size / bpl;
 474         if (lines > 6)
 475                 lines = 6;
 476         BUG_ON(lines < 2);
 477
 478         cx_write(8 + 0, RISC_JUMP | RISC_CNT_RESET);
 479         cx_write(8 + 4, 12);
 480         cx_write(8 + 8, 0);
 481
 482         /* write CDT */
 483         for (i = 0; i < lines; i++) {
 484                 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __func__, cdt + 16*i,
 485                         ch->fifo_start + bpl*i);
 486                 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
 487                 cx_write(cdt + 16*i +  4, 0);
 488                 cx_write(cdt + 16*i +  8, 0);
 489                 cx_write(cdt + 16*i + 12, 0);
 490         }
 491
 492         /* write CMDS */
 493         if (ch->jumponly)
 494                 cx_write(ch->cmds_start + 0, 8);
 495         else
 496                 cx_write(ch->cmds_start + 0, risc);
 497         cx_write(ch->cmds_start +  4, 0); /* 64 bits 63-32 */
 498         cx_write(ch->cmds_start +  8, cdt);
 499         cx_write(ch->cmds_start + 12, (lines*16) >> 3);
 500         cx_write(ch->cmds_start + 16, ch->ctrl_start);
 501         if (ch->jumponly)
 502                 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
 503         else
 504                 cx_write(ch->cmds_start + 20, 64 >> 2);
 505         for (i = 24; i < 80; i += 4)
 506                 cx_write(ch->cmds_start + i, 0);
 507
 508         /* fill registers */
 509         cx_write(ch->ptr1_reg, ch->fifo_start);
 510         cx_write(ch->ptr2_reg, cdt);
 511         cx_write(ch->cnt2_reg, (lines*16) >> 3);
 512         cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
 513
 514         dprintk(2, "[bridge %d] sram setup %s: bpl=%d lines=%d\n",
 515                 dev->bridge,
 516                 ch->name,
 517                 bpl,
 518                 lines);
 519
 520         return 0;
 521 }
 522
 523 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
 524                                       struct sram_channel *ch)
 525 {
 526         static char *name[] = {
 527                 "init risc lo",
 528                 "init risc hi",
 529                 "cdt base",
 530                 "cdt size",
 531                 "iq base",
 532                 "iq size",
 533                 "risc pc lo",
 534                 "risc pc hi",
 535                 "iq wr ptr",
 536                 "iq rd ptr",
 537                 "cdt current",
 538                 "pci target lo",
 539                 "pci target hi",
 540                 "line / byte",
 541         };
 542         u32 risc;
 543         unsigned int i, j, n;
 544
 545         pr_warn("%s: %s - dma channel status dump\n",
 546                 dev->name, ch->name);
 547         for (i = 0; i < ARRAY_SIZE(name); i++)
 548                 pr_warn("%s:   cmds: %-15s: 0x%08x\n",
 549                         dev->name, name[i],
 550                         cx_read(ch->cmds_start + 4*i));
 551
 552         for (i = 0; i < 4; i++) {
 553                 risc = cx_read(ch->cmds_start + 4 * (i + 14));
 554                 pr_warn("%s:   risc%d: ", dev->name, i);
 555                 cx23885_risc_decode(risc);
 556         }
 557         for (i = 0; i < (64 >> 2); i += n) {
 558                 risc = cx_read(ch->ctrl_start + 4 * i);
 559                 /* No consideration for bits 63-32 */
 560
 561                 pr_warn("%s:   (0x%08x) iq %x: ", dev->name,
 562                         ch->ctrl_start + 4 * i, i);
 563                 n = cx23885_risc_decode(risc);
 564                 for (j = 1; j < n; j++) {
 565                         risc = cx_read(ch->ctrl_start + 4 * (i + j));
 566                         pr_warn("%s:   iq %x: 0x%08x [ arg #%d ]\n",
 567                                 dev->name, i+j, risc, j);
 568                 }
 569         }
 570
 571         pr_warn("%s: fifo: 0x%08x -> 0x%x\n",
 572                 dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
 573         pr_warn("%s: ctrl: 0x%08x -> 0x%x\n",
 574                 dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
 575         pr_warn("%s:   ptr1_reg: 0x%08x\n",
 576                 dev->name, cx_read(ch->ptr1_reg));
 577         pr_warn("%s:   ptr2_reg: 0x%08x\n",
 578                 dev->name, cx_read(ch->ptr2_reg));
 579         pr_warn("%s:   cnt1_reg: 0x%08x\n",
 580                 dev->name, cx_read(ch->cnt1_reg));
 581         pr_warn("%s:   cnt2_reg: 0x%08x\n",
 582                 dev->name, cx_read(ch->cnt2_reg));
 583 }
 584
 585 static void cx23885_risc_disasm(struct cx23885_tsport *port,
 586                                 struct cx23885_riscmem *risc)
 587 {
 588         struct cx23885_dev *dev = port->dev;
 589         unsigned int i, j, n;
 590
 591         pr_info("%s: risc disasm: %p [dma=0x%08lx]\n",
 592                dev->name, risc->cpu, (unsigned long)risc->dma);
 593         for (i = 0; i < (risc->size >> 2); i += n) {
 594                 pr_info("%s:   %04d: ", dev->name, i);
 595                 n = cx23885_risc_decode(le32_to_cpu(risc->cpu[i]));
 596                 for (j = 1; j < n; j++)
 597                         pr_info("%s:   %04d: 0x%08x [ arg #%d ]\n",
 598                                 dev->name, i + j, risc->cpu[i + j], j);
 599                 if (risc->cpu[i] == cpu_to_le32(RISC_JUMP))
 600                         break;
 601         }
 602 }
 603
 604 static void cx23885_shutdown(struct cx23885_dev *dev)
 605 {
 606         /* disable RISC controller */
 607         cx_write(DEV_CNTRL2, 0);
 608
 609         /* Disable all IR activity */
 610         cx_write(IR_CNTRL_REG, 0);
 611
 612         /* Disable Video A/B activity */
 613         cx_write(VID_A_DMA_CTL, 0);
 614         cx_write(VID_B_DMA_CTL, 0);
 615         cx_write(VID_C_DMA_CTL, 0);
 616
 617         /* Disable Audio activity */
 618         cx_write(AUD_INT_DMA_CTL, 0);
 619         cx_write(AUD_EXT_DMA_CTL, 0);
 620
 621         /* Disable Serial port */
 622         cx_write(UART_CTL, 0);
 623
 624         /* Disable Interrupts */
 625         cx23885_irq_disable_all(dev);
 626         cx_write(VID_A_INT_MSK, 0);
 627         cx_write(VID_B_INT_MSK, 0);
 628         cx_write(VID_C_INT_MSK, 0);
 629         cx_write(AUDIO_INT_INT_MSK, 0);
 630         cx_write(AUDIO_EXT_INT_MSK, 0);
 631
 632 }
 633
 634 static void cx23885_reset(struct cx23885_dev *dev)
 635 {
 636         dprintk(1, "%s()\n", __func__);
 637
 638         cx23885_shutdown(dev);
 639
 640         cx_write(PCI_INT_STAT, 0xffffffff);
 641         cx_write(VID_A_INT_STAT, 0xffffffff);
 642         cx_write(VID_B_INT_STAT, 0xffffffff);
 643         cx_write(VID_C_INT_STAT, 0xffffffff);
 644         cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
 645         cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
 646         cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
 647         cx_write(PAD_CTRL, 0x00500300);
 648
 649         mdelay(100);
 650
 651         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01],
 652                 720*4, 0);
 653         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02], 128, 0);
 654         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH03],
 655                 188*4, 0);
 656         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH04], 128, 0);
 657         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH05], 128, 0);
 658         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH06],
 659                 188*4, 0);
 660         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH07], 128, 0);
 661         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH08], 128, 0);
 662         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH09], 128, 0);
 663
 664         cx23885_gpio_setup(dev);
 665 }
 666
 667
 668 static int cx23885_pci_quirks(struct cx23885_dev *dev)
 669 {
 670         dprintk(1, "%s()\n", __func__);
 671
 672         /* The cx23885 bridge has a weird bug which causes NMI to be asserted
 673          * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
 674          * occur on the cx23887 bridge.
 675          */
 676         if (dev->bridge == CX23885_BRIDGE_885)
 677                 cx_clear(RDR_TLCTL0, 1 << 4);
 678
 679         return 0;
 680 }
 681
 682 static int get_resources(struct cx23885_dev *dev)
 683 {
 684         if (request_mem_region(pci_resource_start(dev->pci, 0),
 685                                pci_resource_len(dev->pci, 0),
 686                                dev->name))
 687                 return 0;
 688
 689         pr_err("%s: can't get MMIO memory @ 0x%llx\n",
 690                dev->name, (unsigned long long)pci_resource_start(dev->pci, 0));
 691
 692         return -EBUSY;
 693 }
 694
 695 static int cx23885_init_tsport(struct cx23885_dev *dev,
 696         struct cx23885_tsport *port, int portno)
 697 {
 698         dprintk(1, "%s(portno=%d)\n", __func__, portno);
 699
 700         /* Transport bus init dma queue  - Common settings */
 701         port->dma_ctl_val        = 0x11; /* Enable RISC controller and Fifo */
 702         port->ts_int_msk_val     = 0x1111; /* TS port bits for RISC */
 703         port->vld_misc_val       = 0x0;
 704         port->hw_sop_ctrl_val    = (0x47 << 16 | 188 << 4);
 705
 706         spin_lock_init(&port->slock);
 707         port->dev = dev;
 708         port->nr = portno;
 709
 710         INIT_LIST_HEAD(&port->mpegq.active);
 711         mutex_init(&port->frontends.lock);
 712         INIT_LIST_HEAD(&port->frontends.felist);
 713         port->frontends.active_fe_id = 0;
 714
 715         /* This should be hardcoded allow a single frontend
 716          * attachment to this tsport, keeping the -dvb.c
 717          * code clean and safe.
 718          */
 719         if (!port->num_frontends)
 720                 port->num_frontends = 1;
 721
 722         switch (portno) {
 723         case 1:
 724                 port->reg_gpcnt          = VID_B_GPCNT;
 725                 port->reg_gpcnt_ctl      = VID_B_GPCNT_CTL;
 726                 port->reg_dma_ctl        = VID_B_DMA_CTL;
 727                 port->reg_lngth          = VID_B_LNGTH;
 728                 port->reg_hw_sop_ctrl    = VID_B_HW_SOP_CTL;
 729                 port->reg_gen_ctrl       = VID_B_GEN_CTL;
 730                 port->reg_bd_pkt_status  = VID_B_BD_PKT_STATUS;
 731                 port->reg_sop_status     = VID_B_SOP_STATUS;
 732                 port->reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT;
 733                 port->reg_vld_misc       = VID_B_VLD_MISC;
 734                 port->reg_ts_clk_en      = VID_B_TS_CLK_EN;
 735                 port->reg_src_sel        = VID_B_SRC_SEL;
 736                 port->reg_ts_int_msk     = VID_B_INT_MSK;
 737                 port->reg_ts_int_stat    = VID_B_INT_STAT;
 738                 port->sram_chno          = SRAM_CH03; /* VID_B */
 739                 port->pci_irqmask        = 0x02; /* VID_B bit1 */
 740                 break;
 741         case 2:
 742                 port->reg_gpcnt          = VID_C_GPCNT;
 743                 port->reg_gpcnt_ctl      = VID_C_GPCNT_CTL;
 744                 port->reg_dma_ctl        = VID_C_DMA_CTL;
 745                 port->reg_lngth          = VID_C_LNGTH;
 746                 port->reg_hw_sop_ctrl    = VID_C_HW_SOP_CTL;
 747                 port->reg_gen_ctrl       = VID_C_GEN_CTL;
 748                 port->reg_bd_pkt_status  = VID_C_BD_PKT_STATUS;
 749                 port->reg_sop_status     = VID_C_SOP_STATUS;
 750                 port->reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
 751                 port->reg_vld_misc       = VID_C_VLD_MISC;
 752                 port->reg_ts_clk_en      = VID_C_TS_CLK_EN;
 753                 port->reg_src_sel        = 0;
 754                 port->reg_ts_int_msk     = VID_C_INT_MSK;
 755                 port->reg_ts_int_stat    = VID_C_INT_STAT;
 756                 port->sram_chno          = SRAM_CH06; /* VID_C */
 757                 port->pci_irqmask        = 0x04; /* VID_C bit2 */
 758                 break;
 759         default:
 760                 BUG();
 761         }
 762
 763         return 0;
 764 }
 765
 766 static void cx23885_dev_checkrevision(struct cx23885_dev *dev)
 767 {
 768         switch (cx_read(RDR_CFG2) & 0xff) {
 769         case 0x00:
 770                 /* cx23885 */
 771                 dev->hwrevision = 0xa0;
 772                 break;
 773         case 0x01:
 774                 /* CX23885-12Z */
 775                 dev->hwrevision = 0xa1;
 776                 break;
 777         case 0x02:
 778                 /* CX23885-13Z/14Z */
 779                 dev->hwrevision = 0xb0;
 780                 break;
 781         case 0x03:
 782                 if (dev->pci->device == 0x8880) {
 783                         /* CX23888-21Z/22Z */
 784                         dev->hwrevision = 0xc0;
 785                 } else {
 786                         /* CX23885-14Z */
 787                         dev->hwrevision = 0xa4;
 788                 }
 789                 break;
 790         case 0x04:
 791                 if (dev->pci->device == 0x8880) {
 792                         /* CX23888-31Z */
 793                         dev->hwrevision = 0xd0;
 794                 } else {
 795                         /* CX23885-15Z, CX23888-31Z */
 796                         dev->hwrevision = 0xa5;
 797                 }
 798                 break;
 799         case 0x0e:
 800                 /* CX23887-15Z */
 801                 dev->hwrevision = 0xc0;
 802                 break;
 803         case 0x0f:
 804                 /* CX23887-14Z */
 805                 dev->hwrevision = 0xb1;
 806                 break;
 807         default:
 808                 pr_err("%s() New hardware revision found 0x%x\n",
 809                        __func__, dev->hwrevision);
 810         }
 811         if (dev->hwrevision)
 812                 pr_info("%s() Hardware revision = 0x%02x\n",
 813                         __func__, dev->hwrevision);
 814         else
 815                 pr_err("%s() Hardware revision unknown 0x%x\n",
 816                        __func__, dev->hwrevision);
 817 }
 818
 819 /* Find the first v4l2_subdev member of the group id in hw */
 820 struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw)
 821 {
 822         struct v4l2_subdev *result = NULL;
 823         struct v4l2_subdev *sd;
 824
 825         spin_lock(&dev->v4l2_dev.lock);
 826         v4l2_device_for_each_subdev(sd, &dev->v4l2_dev) {
 827                 if (sd->grp_id == hw) {
 828                         result = sd;
 829                         break;
 830                 }
 831         }
 832         spin_unlock(&dev->v4l2_dev.lock);
 833         return result;
 834 }
 835
 836 static int cx23885_dev_setup(struct cx23885_dev *dev)
 837 {
 838         int i;
 839
 840         spin_lock_init(&dev->pci_irqmask_lock);
 841         spin_lock_init(&dev->slock);
 842
 843         mutex_init(&dev->lock);
 844         mutex_init(&dev->gpio_lock);
 845
 846         atomic_inc(&dev->refcount);
 847
 848         dev->nr = cx23885_devcount++;
 849         sprintf(dev->name, "cx23885[%d]", dev->nr);
 850
 851         /* Configure the internal memory */
 852         if (dev->pci->device == 0x8880) {
 853                 /* Could be 887 or 888, assume an 888 default */
 854                 dev->bridge = CX23885_BRIDGE_888;
 855                 /* Apply a sensible clock frequency for the PCIe bridge */
 856                 dev->clk_freq = 50000000;
 857                 dev->sram_channels = cx23887_sram_channels;
 858         } else
 859         if (dev->pci->device == 0x8852) {
 860                 dev->bridge = CX23885_BRIDGE_885;
 861                 /* Apply a sensible clock frequency for the PCIe bridge */
 862                 dev->clk_freq = 28000000;
 863                 dev->sram_channels = cx23885_sram_channels;
 864         } else
 865                 BUG();
 866
 867         dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
 868                 __func__, dev->bridge);
 869
 870         /* board config */
 871         dev->board = UNSET;
 872         if (card[dev->nr] < cx23885_bcount)
 873                 dev->board = card[dev->nr];
 874         for (i = 0; UNSET == dev->board  &&  i < cx23885_idcount; i++)
 875                 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
 876                     dev->pci->subsystem_device == cx23885_subids[i].subdevice)
 877                         dev->board = cx23885_subids[i].card;
 878         if (UNSET == dev->board) {
 879                 dev->board = CX23885_BOARD_UNKNOWN;
 880                 cx23885_card_list(dev);
 881         }
 882
 883         if (dev->pci->device == 0x8852) {
 884                 /* no DIF on cx23885, so no analog tuner support possible */
 885                 if (dev->board == CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC)
 886                         dev->board = CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC_885;
 887                 else if (dev->board == CX23885_BOARD_HAUPPAUGE_QUADHD_DVB)
 888                         dev->board = CX23885_BOARD_HAUPPAUGE_QUADHD_DVB_885;
 889         }
 890
 891         /* If the user specific a clk freq override, apply it */
 892         if (cx23885_boards[dev->board].clk_freq > 0)
 893                 dev->clk_freq = cx23885_boards[dev->board].clk_freq;
 894
 895         if (dev->board == CX23885_BOARD_HAUPPAUGE_IMPACTVCBE &&
 896                 dev->pci->subsystem_device == 0x7137) {
 897                 /* Hauppauge ImpactVCBe device ID 0x7137 is populated
 898                  * with an 888, and a 25Mhz crystal, instead of the
 899                  * usual third overtone 50Mhz. The default clock rate must
 900                  * be overridden so the cx25840 is properly configured
 901                  */
 902                 dev->clk_freq = 25000000;
 903         }
 904
 905         dev->pci_bus  = dev->pci->bus->number;
 906         dev->pci_slot = PCI_SLOT(dev->pci->devfn);
 907         cx23885_irq_add(dev, 0x001f00);
 908
 909         /* External Master 1 Bus */
 910         dev->i2c_bus[0].nr = 0;
 911         dev->i2c_bus[0].dev = dev;
 912         dev->i2c_bus[0].reg_stat  = I2C1_STAT;
 913         dev->i2c_bus[0].reg_ctrl  = I2C1_CTRL;
 914         dev->i2c_bus[0].reg_addr  = I2C1_ADDR;
 915         dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
 916         dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
 917         dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
 918
 919         /* External Master 2 Bus */
 920         dev->i2c_bus[1].nr = 1;
 921         dev->i2c_bus[1].dev = dev;
 922         dev->i2c_bus[1].reg_stat  = I2C2_STAT;
 923         dev->i2c_bus[1].reg_ctrl  = I2C2_CTRL;
 924         dev->i2c_bus[1].reg_addr  = I2C2_ADDR;
 925         dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
 926         dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
 927         dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
 928
 929         /* Internal Master 3 Bus */
 930         dev->i2c_bus[2].nr = 2;
 931         dev->i2c_bus[2].dev = dev;
 932         dev->i2c_bus[2].reg_stat  = I2C3_STAT;
 933         dev->i2c_bus[2].reg_ctrl  = I2C3_CTRL;
 934         dev->i2c_bus[2].reg_addr  = I2C3_ADDR;
 935         dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
 936         dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
 937         dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
 938
 939         if ((cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) ||
 940                 (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER))
 941                 cx23885_init_tsport(dev, &dev->ts1, 1);
 942
 943         if ((cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) ||
 944                 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
 945                 cx23885_init_tsport(dev, &dev->ts2, 2);
 946
 947         if (get_resources(dev) < 0) {
 948                 pr_err("CORE %s No more PCIe resources for subsystem: %04x:%04x\n",
 949                        dev->name, dev->pci->subsystem_vendor,
 950                        dev->pci->subsystem_device);
 951
 952                 cx23885_devcount--;
 953                 return -ENODEV;
 954         }
 955
 956         /* PCIe stuff */
 957         dev->lmmio = ioremap(pci_resource_start(dev->pci, 0),
 958                              pci_resource_len(dev->pci, 0));
 959
 960         dev->bmmio = (u8 __iomem *)dev->lmmio;
 961
 962         pr_info("CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
 963                 dev->name, dev->pci->subsystem_vendor,
 964                 dev->pci->subsystem_device, cx23885_boards[dev->board].name,
 965                 dev->board, card[dev->nr] == dev->board ?
 966                 "insmod option" : "autodetected");
 967
 968         cx23885_pci_quirks(dev);
 969
 970         /* Assume some sensible defaults */
 971         dev->tuner_type = cx23885_boards[dev->board].tuner_type;
 972         dev->tuner_addr = cx23885_boards[dev->board].tuner_addr;
 973         dev->tuner_bus = cx23885_boards[dev->board].tuner_bus;
 974         dev->radio_type = cx23885_boards[dev->board].radio_type;
 975         dev->radio_addr = cx23885_boards[dev->board].radio_addr;
 976
 977         dprintk(1, "%s() tuner_type = 0x%x tuner_addr = 0x%x tuner_bus = %d\n",
 978                 __func__, dev->tuner_type, dev->tuner_addr, dev->tuner_bus);
 979         dprintk(1, "%s() radio_type = 0x%x radio_addr = 0x%x\n",
 980                 __func__, dev->radio_type, dev->radio_addr);
 981
 982         /* The cx23417 encoder has GPIO's that need to be initialised
 983          * before DVB, so that demodulators and tuners are out of
 984          * reset before DVB uses them.
 985          */
 986         if ((cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) ||
 987                 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
 988                         cx23885_mc417_init(dev);
 989
 990         /* init hardware */
 991         cx23885_reset(dev);
 992
 993         cx23885_i2c_register(&dev->i2c_bus[0]);
 994         cx23885_i2c_register(&dev->i2c_bus[1]);
 995         cx23885_i2c_register(&dev->i2c_bus[2]);
 996         cx23885_card_setup(dev);
 997         call_all(dev, tuner, standby);
 998         cx23885_ir_init(dev);
 999
1000         if (dev->board == CX23885_BOARD_VIEWCAST_460E) {
1001                 /*
1002                  * GPIOs 9/8 are input detection bits for the breakout video
1003                  * (gpio 8) and audio (gpio 9) cables. When they're attached,
1004                  * this gpios are pulled high. Make sure these GPIOs are marked
1005                  * as inputs.
1006                  */
1007                 cx23885_gpio_enable(dev, 0x300, 0);
1008         }
1009
1010         if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) {
1011                 if (cx23885_video_register(dev) < 0) {
1012                         pr_err("%s() Failed to register analog video adapters on VID_A\n",
1013                                __func__);
1014                 }
1015         }
1016
1017         if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
1018                 if (cx23885_boards[dev->board].num_fds_portb)
1019                         dev->ts1.num_frontends =
1020                                 cx23885_boards[dev->board].num_fds_portb;
1021                 if (cx23885_dvb_register(&dev->ts1) < 0) {
1022                         pr_err("%s() Failed to register dvb adapters on VID_B\n",
1023                                __func__);
1024                 }
1025         } else
1026         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1027                 if (cx23885_417_register(dev) < 0) {
1028                         pr_err("%s() Failed to register 417 on VID_B\n",
1029                                __func__);
1030                 }
1031         }
1032
1033         if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
1034                 if (cx23885_boards[dev->board].num_fds_portc)
1035                         dev->ts2.num_frontends =
1036                                 cx23885_boards[dev->board].num_fds_portc;
1037                 if (cx23885_dvb_register(&dev->ts2) < 0) {
1038                         pr_err("%s() Failed to register dvb on VID_C\n",
1039                                __func__);
1040                 }
1041         } else
1042         if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER) {
1043                 if (cx23885_417_register(dev) < 0) {
1044                         pr_err("%s() Failed to register 417 on VID_C\n",
1045                                __func__);
1046                 }
1047         }
1048
1049         cx23885_dev_checkrevision(dev);
1050
1051         /* disable MSI for NetUP cards, otherwise CI is not working */
1052         if (cx23885_boards[dev->board].ci_type > 0)
1053                 cx_clear(RDR_RDRCTL1, 1 << 8);
1054
1055         switch (dev->board) {
1056         case CX23885_BOARD_TEVII_S470:
1057         case CX23885_BOARD_TEVII_S471:
1058                 cx_clear(RDR_RDRCTL1, 1 << 8);
1059                 break;
1060         }
1061
1062         return 0;
1063 }
1064
1065 static void cx23885_dev_unregister(struct cx23885_dev *dev)
1066 {
1067         release_mem_region(pci_resource_start(dev->pci, 0),
1068                            pci_resource_len(dev->pci, 0));
1069
1070         if (!atomic_dec_and_test(&dev->refcount))
1071                 return;
1072
1073         if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO)
1074                 cx23885_video_unregister(dev);
1075
1076         if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
1077                 cx23885_dvb_unregister(&dev->ts1);
1078
1079         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1080                 cx23885_417_unregister(dev);
1081
1082         if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
1083                 cx23885_dvb_unregister(&dev->ts2);
1084
1085         if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
1086                 cx23885_417_unregister(dev);
1087
1088         cx23885_i2c_unregister(&dev->i2c_bus[2]);
1089         cx23885_i2c_unregister(&dev->i2c_bus[1]);
1090         cx23885_i2c_unregister(&dev->i2c_bus[0]);
1091
1092         iounmap(dev->lmmio);
1093 }
1094
1095 static __le32 *cx23885_risc_field(__le32 *rp, struct scatterlist *sglist,
1096                                unsigned int offset, u32 sync_line,
1097                                unsigned int bpl, unsigned int padding,
1098                                unsigned int lines,  unsigned int lpi, bool jump)
1099 {
1100         struct scatterlist *sg;
1101         unsigned int line, todo, sol;
1102
1103
1104         if (jump) {
1105                 *(rp++) = cpu_to_le32(RISC_JUMP);
1106                 *(rp++) = cpu_to_le32(0);
1107                 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1108         }
1109
1110         /* sync instruction */
1111         if (sync_line != NO_SYNC_LINE)
1112                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1113
1114         /* scan lines */
1115         sg = sglist;
1116         for (line = 0; line < lines; line++) {
1117                 while (offset && offset >= sg_dma_len(sg)) {
1118                         offset -= sg_dma_len(sg);
1119                         sg = sg_next(sg);
1120                 }
1121
1122                 if (lpi && line > 0 && !(line % lpi))
1123                         sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC;
1124                 else
1125                         sol = RISC_SOL;
1126
1127                 if (bpl <= sg_dma_len(sg)-offset) {
1128                         /* fits into current chunk */
1129                         *(rp++) = cpu_to_le32(RISC_WRITE|sol|RISC_EOL|bpl);
1130                         *(rp++) = cpu_to_le32(sg_dma_address(sg)+offset);
1131                         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1132                         offset += bpl;
1133                 } else {
1134                         /* scanline needs to be split */
1135                         todo = bpl;
1136                         *(rp++) = cpu_to_le32(RISC_WRITE|sol|
1137                                             (sg_dma_len(sg)-offset));
1138                         *(rp++) = cpu_to_le32(sg_dma_address(sg)+offset);
1139                         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1140                         todo -= (sg_dma_len(sg)-offset);
1141                         offset = 0;
1142                         sg = sg_next(sg);
1143                         while (todo > sg_dma_len(sg)) {
1144                                 *(rp++) = cpu_to_le32(RISC_WRITE|
1145                                                     sg_dma_len(sg));
1146                                 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1147                                 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1148                                 todo -= sg_dma_len(sg);
1149                                 sg = sg_next(sg);
1150                         }
1151                         *(rp++) = cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
1152                         *(rp++) = cpu_to_le32(sg_dma_address(sg));
1153                         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1154                         offset += todo;
1155                 }
1156                 offset += padding;
1157         }
1158
1159         return rp;
1160 }
1161
1162 int cx23885_risc_buffer(struct pci_dev *pci, struct cx23885_riscmem *risc,
1163                         struct scatterlist *sglist, unsigned int top_offset,
1164                         unsigned int bottom_offset, unsigned int bpl,
1165                         unsigned int padding, unsigned int lines)
1166 {
1167         u32 instructions, fields;
1168         __le32 *rp;
1169
1170         fields = 0;
1171         if (UNSET != top_offset)
1172                 fields++;
1173         if (UNSET != bottom_offset)
1174                 fields++;
1175
1176         /* estimate risc mem: worst case is one write per page border +
1177            one write per scan line + syncs + jump (all 2 dwords).  Padding
1178            can cause next bpl to start close to a page border.  First DMA
1179            region may be smaller than PAGE_SIZE */
1180         /* write and jump need and extra dword */
1181         instructions  = fields * (1 + ((bpl + padding) * lines)
1182                 / PAGE_SIZE + lines);
1183         instructions += 5;
1184         risc->size = instructions * 12;
1185         risc->cpu = pci_alloc_consistent(pci, risc->size, &risc->dma);
1186         if (risc->cpu == NULL)
1187                 return -ENOMEM;
1188
1189         /* write risc instructions */
1190         rp = risc->cpu;
1191         if (UNSET != top_offset)
1192                 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
1193                                         bpl, padding, lines, 0, true);
1194         if (UNSET != bottom_offset)
1195                 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
1196                                         bpl, padding, lines, 0, UNSET == top_offset);
1197
1198         /* save pointer to jmp instruction address */
1199         risc->jmp = rp;
1200         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1201         return 0;
1202 }
1203
1204 int cx23885_risc_databuffer(struct pci_dev *pci,
1205                                    struct cx23885_riscmem *risc,
1206                                    struct scatterlist *sglist,
1207                                    unsigned int bpl,
1208                                    unsigned int lines, unsigned int lpi)
1209 {
1210         u32 instructions;
1211         __le32 *rp;
1212
1213         /* estimate risc mem: worst case is one write per page border +
1214            one write per scan line + syncs + jump (all 2 dwords).  Here
1215            there is no padding and no sync.  First DMA region may be smaller
1216            than PAGE_SIZE */
1217         /* Jump and write need an extra dword */
1218         instructions  = 1 + (bpl * lines) / PAGE_SIZE + lines;
1219         instructions += 4;
1220
1221         risc->size = instructions * 12;
1222         risc->cpu = pci_alloc_consistent(pci, risc->size, &risc->dma);
1223         if (risc->cpu == NULL)
1224                 return -ENOMEM;
1225
1226         /* write risc instructions */
1227         rp = risc->cpu;
1228         rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE,
1229                                 bpl, 0, lines, lpi, lpi == 0);
1230
1231         /* save pointer to jmp instruction address */
1232         risc->jmp = rp;
1233         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1234         return 0;
1235 }
1236
1237 int cx23885_risc_vbibuffer(struct pci_dev *pci, struct cx23885_riscmem *risc,
1238                         struct scatterlist *sglist, unsigned int top_offset,
1239                         unsigned int bottom_offset, unsigned int bpl,
1240                         unsigned int padding, unsigned int lines)
1241 {
1242         u32 instructions, fields;
1243         __le32 *rp;
1244
1245         fields = 0;
1246         if (UNSET != top_offset)
1247                 fields++;
1248         if (UNSET != bottom_offset)
1249                 fields++;
1250
1251         /* estimate risc mem: worst case is one write per page border +
1252            one write per scan line + syncs + jump (all 2 dwords).  Padding
1253            can cause next bpl to start close to a page border.  First DMA
1254            region may be smaller than PAGE_SIZE */
1255         /* write and jump need and extra dword */
1256         instructions  = fields * (1 + ((bpl + padding) * lines)
1257                 / PAGE_SIZE + lines);
1258         instructions += 5;
1259         risc->size = instructions * 12;
1260         risc->cpu = pci_alloc_consistent(pci, risc->size, &risc->dma);
1261         if (risc->cpu == NULL)
1262                 return -ENOMEM;
1263         /* write risc instructions */
1264         rp = risc->cpu;
1265
1266         /* Sync to line 6, so US CC line 21 will appear in line '12'
1267          * in the userland vbi payload */
1268         if (UNSET != top_offset)
1269                 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
1270                                         bpl, padding, lines, 0, true);
1271
1272         if (UNSET != bottom_offset)
1273                 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
1274                                         bpl, padding, lines, 0, UNSET == top_offset);
1275
1276
1277
1278         /* save pointer to jmp instruction address */
1279         risc->jmp = rp;
1280         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1281         return 0;
1282 }
1283
1284
1285 void cx23885_free_buffer(struct cx23885_dev *dev, struct cx23885_buffer *buf)
1286 {
1287         struct cx23885_riscmem *risc = &buf->risc;
1288
1289         BUG_ON(in_interrupt());
1290         pci_free_consistent(dev->pci, risc->size, risc->cpu, risc->dma);
1291 }
1292
1293 static void cx23885_tsport_reg_dump(struct cx23885_tsport *port)
1294 {
1295         struct cx23885_dev *dev = port->dev;
1296
1297         dprintk(1, "%s() Register Dump\n", __func__);
1298         dprintk(1, "%s() DEV_CNTRL2               0x%08X\n", __func__,
1299                 cx_read(DEV_CNTRL2));
1300         dprintk(1, "%s() PCI_INT_MSK              0x%08X\n", __func__,
1301                 cx23885_irq_get_mask(dev));
1302         dprintk(1, "%s() AUD_INT_INT_MSK          0x%08X\n", __func__,
1303                 cx_read(AUDIO_INT_INT_MSK));
1304         dprintk(1, "%s() AUD_INT_DMA_CTL          0x%08X\n", __func__,
1305                 cx_read(AUD_INT_DMA_CTL));
1306         dprintk(1, "%s() AUD_EXT_INT_MSK          0x%08X\n", __func__,
1307                 cx_read(AUDIO_EXT_INT_MSK));
1308         dprintk(1, "%s() AUD_EXT_DMA_CTL          0x%08X\n", __func__,
1309                 cx_read(AUD_EXT_DMA_CTL));
1310         dprintk(1, "%s() PAD_CTRL                 0x%08X\n", __func__,
1311                 cx_read(PAD_CTRL));
1312         dprintk(1, "%s() ALT_PIN_OUT_SEL          0x%08X\n", __func__,
1313                 cx_read(ALT_PIN_OUT_SEL));
1314         dprintk(1, "%s() GPIO2                    0x%08X\n", __func__,
1315                 cx_read(GPIO2));
1316         dprintk(1, "%s() gpcnt(0x%08X)          0x%08X\n", __func__,
1317                 port->reg_gpcnt, cx_read(port->reg_gpcnt));
1318         dprintk(1, "%s() gpcnt_ctl(0x%08X)      0x%08x\n", __func__,
1319                 port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl));
1320         dprintk(1, "%s() dma_ctl(0x%08X)        0x%08x\n", __func__,
1321                 port->reg_dma_ctl, cx_read(port->reg_dma_ctl));
1322         if (port->reg_src_sel)
1323                 dprintk(1, "%s() src_sel(0x%08X)        0x%08x\n", __func__,
1324                         port->reg_src_sel, cx_read(port->reg_src_sel));
1325         dprintk(1, "%s() lngth(0x%08X)          0x%08x\n", __func__,
1326                 port->reg_lngth, cx_read(port->reg_lngth));
1327         dprintk(1, "%s() hw_sop_ctrl(0x%08X)    0x%08x\n", __func__,
1328                 port->reg_hw_sop_ctrl, cx_read(port->reg_hw_sop_ctrl));
1329         dprintk(1, "%s() gen_ctrl(0x%08X)       0x%08x\n", __func__,
1330                 port->reg_gen_ctrl, cx_read(port->reg_gen_ctrl));
1331         dprintk(1, "%s() bd_pkt_status(0x%08X)  0x%08x\n", __func__,
1332                 port->reg_bd_pkt_status, cx_read(port->reg_bd_pkt_status));
1333         dprintk(1, "%s() sop_status(0x%08X)     0x%08x\n", __func__,
1334                 port->reg_sop_status, cx_read(port->reg_sop_status));
1335         dprintk(1, "%s() fifo_ovfl_stat(0x%08X) 0x%08x\n", __func__,
1336                 port->reg_fifo_ovfl_stat, cx_read(port->reg_fifo_ovfl_stat));
1337         dprintk(1, "%s() vld_misc(0x%08X)       0x%08x\n", __func__,
1338                 port->reg_vld_misc, cx_read(port->reg_vld_misc));
1339         dprintk(1, "%s() ts_clk_en(0x%08X)      0x%08x\n", __func__,
1340                 port->reg_ts_clk_en, cx_read(port->reg_ts_clk_en));
1341         dprintk(1, "%s() ts_int_msk(0x%08X)     0x%08x\n", __func__,
1342                 port->reg_ts_int_msk, cx_read(port->reg_ts_int_msk));
1343 }
1344
1345 int cx23885_start_dma(struct cx23885_tsport *port,
1346                              struct cx23885_dmaqueue *q,
1347                              struct cx23885_buffer   *buf)
1348 {
1349         struct cx23885_dev *dev = port->dev;
1350         u32 reg;
1351
1352         dprintk(1, "%s() w: %d, h: %d, f: %d\n", __func__,
1353                 dev->width, dev->height, dev->field);
1354
1355         /* Stop the fifo and risc engine for this port */
1356         cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1357
1358         /* setup fifo + format */
1359         cx23885_sram_channel_setup(dev,
1360                                    &dev->sram_channels[port->sram_chno],
1361                                    port->ts_packet_size, buf->risc.dma);
1362         if (debug > 5) {
1363                 cx23885_sram_channel_dump(dev,
1364                         &dev->sram_channels[port->sram_chno]);
1365                 cx23885_risc_disasm(port, &buf->risc);
1366         }
1367
1368         /* write TS length to chip */
1369         cx_write(port->reg_lngth, port->ts_packet_size);
1370
1371         if ((!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
1372                 (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB))) {
1373                 pr_err("%s() Unsupported .portb/c (0x%08x)/(0x%08x)\n",
1374                         __func__,
1375                         cx23885_boards[dev->board].portb,
1376                         cx23885_boards[dev->board].portc);
1377                 return -EINVAL;
1378         }
1379
1380         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1381                 cx23885_av_clk(dev, 0);
1382
1383         udelay(100);
1384
1385         /* If the port supports SRC SELECT, configure it */
1386         if (port->reg_src_sel)
1387                 cx_write(port->reg_src_sel, port->src_sel_val);
1388
1389         cx_write(port->reg_hw_sop_ctrl, port->hw_sop_ctrl_val);
1390         cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1391         cx_write(port->reg_vld_misc, port->vld_misc_val);
1392         cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1393         udelay(100);
1394
1395         /* NOTE: this is 2 (reserved) for portb, does it matter? */
1396         /* reset counter to zero */
1397         cx_write(port->reg_gpcnt_ctl, 3);
1398         q->count = 0;
1399
1400         /* Set VIDB pins to input */
1401         if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
1402                 reg = cx_read(PAD_CTRL);
1403                 reg &= ~0x3; /* Clear TS1_OE & TS1_SOP_OE */
1404                 cx_write(PAD_CTRL, reg);
1405         }
1406
1407         /* Set VIDC pins to input */
1408         if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
1409                 reg = cx_read(PAD_CTRL);
1410                 reg &= ~0x4; /* Clear TS2_SOP_OE */
1411                 cx_write(PAD_CTRL, reg);
1412         }
1413
1414         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1415
1416                 reg = cx_read(PAD_CTRL);
1417                 reg = reg & ~0x1;    /* Clear TS1_OE */
1418
1419                 /* FIXME, bit 2 writing here is questionable */
1420                 /* set TS1_SOP_OE and TS1_OE_HI */
1421                 reg = reg | 0xa;
1422                 cx_write(PAD_CTRL, reg);
1423
1424                 /* FIXME and these two registers should be documented. */
1425                 cx_write(CLK_DELAY, cx_read(CLK_DELAY) | 0x80000011);
1426                 cx_write(ALT_PIN_OUT_SEL, 0x10100045);
1427         }
1428
1429         switch (dev->bridge) {
1430         case CX23885_BRIDGE_885:
1431         case CX23885_BRIDGE_887:
1432         case CX23885_BRIDGE_888:
1433                 /* enable irqs */
1434                 dprintk(1, "%s() enabling TS int's and DMA\n", __func__);
1435                 cx_set(port->reg_ts_int_msk,  port->ts_int_msk_val);
1436                 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1437                 cx23885_irq_add(dev, port->pci_irqmask);
1438                 cx23885_irq_enable_all(dev);
1439                 break;
1440         default:
1441                 BUG();
1442         }
1443
1444         cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1445
1446         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1447                 cx23885_av_clk(dev, 1);
1448
1449         if (debug > 4)
1450                 cx23885_tsport_reg_dump(port);
1451
1452         return 0;
1453 }
1454
1455 static int cx23885_stop_dma(struct cx23885_tsport *port)
1456 {
1457         struct cx23885_dev *dev = port->dev;
1458         u32 reg;
1459
1460         dprintk(1, "%s()\n", __func__);
1461
1462         /* Stop interrupts and DMA */
1463         cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1464         cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1465
1466         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1467
1468                 reg = cx_read(PAD_CTRL);
1469
1470                 /* Set TS1_OE */
1471                 reg = reg | 0x1;
1472
1473                 /* clear TS1_SOP_OE and TS1_OE_HI */
1474                 reg = reg & ~0xa;
1475                 cx_write(PAD_CTRL, reg);
1476                 cx_write(port->reg_src_sel, 0);
1477                 cx_write(port->reg_gen_ctrl, 8);
1478
1479         }
1480
1481         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1482                 cx23885_av_clk(dev, 0);
1483
1484         return 0;
1485 }
1486
1487 /* ------------------------------------------------------------------ */
1488
1489 int cx23885_buf_prepare(struct cx23885_buffer *buf, struct cx23885_tsport *port)
1490 {
1491         struct cx23885_dev *dev = port->dev;
1492         int size = port->ts_packet_size * port->ts_packet_count;
1493         struct sg_table *sgt = vb2_dma_sg_plane_desc(&buf->vb.vb2_buf, 0);
1494
1495         dprintk(1, "%s: %p\n", __func__, buf);
1496         if (vb2_plane_size(&buf->vb.vb2_buf, 0) < size)
1497                 return -EINVAL;
1498         vb2_set_plane_payload(&buf->vb.vb2_buf, 0, size);
1499
1500         cx23885_risc_databuffer(dev->pci, &buf->risc,
1501                                 sgt->sgl,
1502                                 port->ts_packet_size, port->ts_packet_count, 0);
1503         return 0;
1504 }
1505
1506 /*
1507  * The risc program for each buffer works as follows: it starts with a simple
1508  * 'JUMP to addr + 12', which is effectively a NOP. Then the code to DMA the
1509  * buffer follows and at the end we have a JUMP back to the start + 12 (skipping
1510  * the initial JUMP).
1511  *
1512  * This is the risc program of the first buffer to be queued if the active list
1513  * is empty and it just keeps DMAing this buffer without generating any
1514  * interrupts.
1515  *
1516  * If a new buffer is added then the initial JUMP in the code for that buffer
1517  * will generate an interrupt which signals that the previous buffer has been
1518  * DMAed successfully and that it can be returned to userspace.
1519  *
1520  * It also sets the final jump of the previous buffer to the start of the new
1521  * buffer, thus chaining the new buffer into the DMA chain. This is a single
1522  * atomic u32 write, so there is no race condition.
1523  *
1524  * The end-result of all this that you only get an interrupt when a buffer
1525  * is ready, so the control flow is very easy.
1526  */
1527 void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1528 {
1529         struct cx23885_buffer    *prev;
1530         struct cx23885_dev *dev = port->dev;
1531         struct cx23885_dmaqueue  *cx88q = &port->mpegq;
1532         unsigned long flags;
1533
1534         buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 12);
1535         buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC);
1536         buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 12);
1537         buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1538
1539         spin_lock_irqsave(&dev->slock, flags);
1540         if (list_empty(&cx88q->active)) {
1541                 list_add_tail(&buf->queue, &cx88q->active);
1542                 dprintk(1, "[%p/%d] %s - first active\n",
1543                         buf, buf->vb.vb2_buf.index, __func__);
1544         } else {
1545                 buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1);
1546                 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1547                                   queue);
1548                 list_add_tail(&buf->queue, &cx88q->active);
1549                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1550                 dprintk(1, "[%p/%d] %s - append to active\n",
1551                          buf, buf->vb.vb2_buf.index, __func__);
1552         }
1553         spin_unlock_irqrestore(&dev->slock, flags);
1554 }
1555
1556 /* ----------------------------------------------------------- */
1557
1558 static void do_cancel_buffers(struct cx23885_tsport *port, char *reason)
1559 {
1560         struct cx23885_dmaqueue *q = &port->mpegq;
1561         struct cx23885_buffer *buf;
1562         unsigned long flags;
1563
1564         spin_lock_irqsave(&port->slock, flags);
1565         while (!list_empty(&q->active)) {
1566                 buf = list_entry(q->active.next, struct cx23885_buffer,
1567                                  queue);
1568                 list_del(&buf->queue);
1569                 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1570                 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
1571                         buf, buf->vb.vb2_buf.index, reason,
1572                         (unsigned long)buf->risc.dma);
1573         }
1574         spin_unlock_irqrestore(&port->slock, flags);
1575 }
1576
1577 void cx23885_cancel_buffers(struct cx23885_tsport *port)
1578 {
1579         dprintk(1, "%s()\n", __func__);
1580         cx23885_stop_dma(port);
1581         do_cancel_buffers(port, "cancel");
1582 }
1583
1584 int cx23885_irq_417(struct cx23885_dev *dev, u32 status)
1585 {
1586         /* FIXME: port1 assumption here. */
1587         struct cx23885_tsport *port = &dev->ts1;
1588         int count = 0;
1589         int handled = 0;
1590
1591         if (status == 0)
1592                 return handled;
1593
1594         count = cx_read(port->reg_gpcnt);
1595         dprintk(7, "status: 0x%08x  mask: 0x%08x count: 0x%x\n",
1596                 status, cx_read(port->reg_ts_int_msk), count);
1597
1598         if ((status & VID_B_MSK_BAD_PKT)         ||
1599                 (status & VID_B_MSK_OPC_ERR)     ||
1600                 (status & VID_B_MSK_VBI_OPC_ERR) ||
1601                 (status & VID_B_MSK_SYNC)        ||
1602                 (status & VID_B_MSK_VBI_SYNC)    ||
1603                 (status & VID_B_MSK_OF)          ||
1604                 (status & VID_B_MSK_VBI_OF)) {
1605                 pr_err("%s: V4L mpeg risc op code error, status = 0x%x\n",
1606                        dev->name, status);
1607                 if (status & VID_B_MSK_BAD_PKT)
1608                         dprintk(1, "        VID_B_MSK_BAD_PKT\n");
1609                 if (status & VID_B_MSK_OPC_ERR)
1610                         dprintk(1, "        VID_B_MSK_OPC_ERR\n");
1611                 if (status & VID_B_MSK_VBI_OPC_ERR)
1612                         dprintk(1, "        VID_B_MSK_VBI_OPC_ERR\n");
1613                 if (status & VID_B_MSK_SYNC)
1614                         dprintk(1, "        VID_B_MSK_SYNC\n");
1615                 if (status & VID_B_MSK_VBI_SYNC)
1616                         dprintk(1, "        VID_B_MSK_VBI_SYNC\n");
1617                 if (status & VID_B_MSK_OF)
1618                         dprintk(1, "        VID_B_MSK_OF\n");
1619                 if (status & VID_B_MSK_VBI_OF)
1620                         dprintk(1, "        VID_B_MSK_VBI_OF\n");
1621
1622                 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1623                 cx23885_sram_channel_dump(dev,
1624                         &dev->sram_channels[port->sram_chno]);
1625                 cx23885_417_check_encoder(dev);
1626         } else if (status & VID_B_MSK_RISCI1) {
1627                 dprintk(7, "        VID_B_MSK_RISCI1\n");
1628                 spin_lock(&port->slock);
1629                 cx23885_wakeup(port, &port->mpegq, count);
1630                 spin_unlock(&port->slock);
1631         }
1632         if (status) {
1633                 cx_write(port->reg_ts_int_stat, status);
1634                 handled = 1;
1635         }
1636
1637         return handled;
1638 }
1639
1640 static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
1641 {
1642         struct cx23885_dev *dev = port->dev;
1643         int handled = 0;
1644         u32 count;
1645
1646         if ((status & VID_BC_MSK_OPC_ERR) ||
1647                 (status & VID_BC_MSK_BAD_PKT) ||
1648                 (status & VID_BC_MSK_SYNC) ||
1649                 (status & VID_BC_MSK_OF)) {
1650
1651                 if (status & VID_BC_MSK_OPC_ERR)
1652                         dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n",
1653                                 VID_BC_MSK_OPC_ERR);
1654
1655                 if (status & VID_BC_MSK_BAD_PKT)
1656                         dprintk(7, " (VID_BC_MSK_BAD_PKT 0x%08x)\n",
1657                                 VID_BC_MSK_BAD_PKT);
1658
1659                 if (status & VID_BC_MSK_SYNC)
1660                         dprintk(7, " (VID_BC_MSK_SYNC    0x%08x)\n",
1661                                 VID_BC_MSK_SYNC);
1662
1663                 if (status & VID_BC_MSK_OF)
1664                         dprintk(7, " (VID_BC_MSK_OF      0x%08x)\n",
1665                                 VID_BC_MSK_OF);
1666
1667                 pr_err("%s: mpeg risc op code error\n", dev->name);
1668
1669                 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1670                 cx23885_sram_channel_dump(dev,
1671                         &dev->sram_channels[port->sram_chno]);
1672
1673         } else if (status & VID_BC_MSK_RISCI1) {
1674
1675                 dprintk(7, " (RISCI1            0x%08x)\n", VID_BC_MSK_RISCI1);
1676
1677                 spin_lock(&port->slock);
1678                 count = cx_read(port->reg_gpcnt);
1679                 cx23885_wakeup(port, &port->mpegq, count);
1680                 spin_unlock(&port->slock);
1681
1682         }
1683         if (status) {
1684                 cx_write(port->reg_ts_int_stat, status);
1685                 handled = 1;
1686         }
1687
1688         return handled;
1689 }
1690
1691 static irqreturn_t cx23885_irq(int irq, void *dev_id)
1692 {
1693         struct cx23885_dev *dev = dev_id;
1694         struct cx23885_tsport *ts1 = &dev->ts1;
1695         struct cx23885_tsport *ts2 = &dev->ts2;
1696         u32 pci_status, pci_mask;
1697         u32 vida_status, vida_mask;
1698         u32 audint_status, audint_mask;
1699         u32 ts1_status, ts1_mask;
1700         u32 ts2_status, ts2_mask;
1701         int vida_count = 0, ts1_count = 0, ts2_count = 0, handled = 0;
1702         int audint_count = 0;
1703         bool subdev_handled;
1704
1705         pci_status = cx_read(PCI_INT_STAT);
1706         pci_mask = cx23885_irq_get_mask(dev);
1707         if ((pci_status & pci_mask) == 0) {
1708                 dprintk(7, "pci_status: 0x%08x  pci_mask: 0x%08x\n",
1709                         pci_status, pci_mask);
1710                 goto out;
1711         }
1712
1713         vida_status = cx_read(VID_A_INT_STAT);
1714         vida_mask = cx_read(VID_A_INT_MSK);
1715         audint_status = cx_read(AUDIO_INT_INT_STAT);
1716         audint_mask = cx_read(AUDIO_INT_INT_MSK);
1717         ts1_status = cx_read(VID_B_INT_STAT);
1718         ts1_mask = cx_read(VID_B_INT_MSK);
1719         ts2_status = cx_read(VID_C_INT_STAT);
1720         ts2_mask = cx_read(VID_C_INT_MSK);
1721
1722         if (((pci_status & pci_mask) == 0) &&
1723                 ((ts2_status & ts2_mask) == 0) &&
1724                 ((ts1_status & ts1_mask) == 0))
1725                 goto out;
1726
1727         vida_count = cx_read(VID_A_GPCNT);
1728         audint_count = cx_read(AUD_INT_A_GPCNT);
1729         ts1_count = cx_read(ts1->reg_gpcnt);
1730         ts2_count = cx_read(ts2->reg_gpcnt);
1731         dprintk(7, "pci_status: 0x%08x  pci_mask: 0x%08x\n",
1732                 pci_status, pci_mask);
1733         dprintk(7, "vida_status: 0x%08x vida_mask: 0x%08x count: 0x%x\n",
1734                 vida_status, vida_mask, vida_count);
1735         dprintk(7, "audint_status: 0x%08x audint_mask: 0x%08x count: 0x%x\n",
1736                 audint_status, audint_mask, audint_count);
1737         dprintk(7, "ts1_status: 0x%08x  ts1_mask: 0x%08x count: 0x%x\n",
1738                 ts1_status, ts1_mask, ts1_count);
1739         dprintk(7, "ts2_status: 0x%08x  ts2_mask: 0x%08x count: 0x%x\n",
1740                 ts2_status, ts2_mask, ts2_count);
1741
1742         if (pci_status & (PCI_MSK_RISC_RD | PCI_MSK_RISC_WR |
1743                           PCI_MSK_AL_RD   | PCI_MSK_AL_WR   | PCI_MSK_APB_DMA |
1744                           PCI_MSK_VID_C   | PCI_MSK_VID_B   | PCI_MSK_VID_A   |
1745                           PCI_MSK_AUD_INT | PCI_MSK_AUD_EXT |
1746                           PCI_MSK_GPIO0   | PCI_MSK_GPIO1   |
1747                           PCI_MSK_AV_CORE | PCI_MSK_IR)) {
1748
1749                 if (pci_status & PCI_MSK_RISC_RD)
1750                         dprintk(7, " (PCI_MSK_RISC_RD   0x%08x)\n",
1751                                 PCI_MSK_RISC_RD);
1752
1753                 if (pci_status & PCI_MSK_RISC_WR)
1754                         dprintk(7, " (PCI_MSK_RISC_WR   0x%08x)\n",
1755                                 PCI_MSK_RISC_WR);
1756
1757                 if (pci_status & PCI_MSK_AL_RD)
1758                         dprintk(7, " (PCI_MSK_AL_RD     0x%08x)\n",
1759                                 PCI_MSK_AL_RD);
1760
1761                 if (pci_status & PCI_MSK_AL_WR)
1762                         dprintk(7, " (PCI_MSK_AL_WR     0x%08x)\n",
1763                                 PCI_MSK_AL_WR);
1764
1765                 if (pci_status & PCI_MSK_APB_DMA)
1766                         dprintk(7, " (PCI_MSK_APB_DMA   0x%08x)\n",
1767                                 PCI_MSK_APB_DMA);
1768
1769                 if (pci_status & PCI_MSK_VID_C)
1770                         dprintk(7, " (PCI_MSK_VID_C     0x%08x)\n",
1771                                 PCI_MSK_VID_C);
1772
1773                 if (pci_status & PCI_MSK_VID_B)
1774                         dprintk(7, " (PCI_MSK_VID_B     0x%08x)\n",
1775                                 PCI_MSK_VID_B);
1776
1777                 if (pci_status & PCI_MSK_VID_A)
1778                         dprintk(7, " (PCI_MSK_VID_A     0x%08x)\n",
1779                                 PCI_MSK_VID_A);
1780
1781                 if (pci_status & PCI_MSK_AUD_INT)
1782                         dprintk(7, " (PCI_MSK_AUD_INT   0x%08x)\n",
1783                                 PCI_MSK_AUD_INT);
1784
1785                 if (pci_status & PCI_MSK_AUD_EXT)
1786                         dprintk(7, " (PCI_MSK_AUD_EXT   0x%08x)\n",
1787                                 PCI_MSK_AUD_EXT);
1788
1789                 if (pci_status & PCI_MSK_GPIO0)
1790                         dprintk(7, " (PCI_MSK_GPIO0     0x%08x)\n",
1791                                 PCI_MSK_GPIO0);
1792
1793                 if (pci_status & PCI_MSK_GPIO1)
1794                         dprintk(7, " (PCI_MSK_GPIO1     0x%08x)\n",
1795                                 PCI_MSK_GPIO1);
1796
1797                 if (pci_status & PCI_MSK_AV_CORE)
1798                         dprintk(7, " (PCI_MSK_AV_CORE   0x%08x)\n",
1799                                 PCI_MSK_AV_CORE);
1800
1801                 if (pci_status & PCI_MSK_IR)
1802                         dprintk(7, " (PCI_MSK_IR        0x%08x)\n",
1803                                 PCI_MSK_IR);
1804         }
1805
1806         if (cx23885_boards[dev->board].ci_type == 1 &&
1807                         (pci_status & (PCI_MSK_GPIO1 | PCI_MSK_GPIO0)))
1808                 handled += netup_ci_slot_status(dev, pci_status);
1809
1810         if (cx23885_boards[dev->board].ci_type == 2 &&
1811                         (pci_status & PCI_MSK_GPIO0))
1812                 handled += altera_ci_irq(dev);
1813
1814         if (ts1_status) {
1815                 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
1816                         handled += cx23885_irq_ts(ts1, ts1_status);
1817                 else
1818                 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1819                         handled += cx23885_irq_417(dev, ts1_status);
1820         }
1821
1822         if (ts2_status) {
1823                 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
1824                         handled += cx23885_irq_ts(ts2, ts2_status);
1825                 else
1826                 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
1827                         handled += cx23885_irq_417(dev, ts2_status);
1828         }
1829
1830         if (vida_status)
1831                 handled += cx23885_video_irq(dev, vida_status);
1832
1833         if (audint_status)
1834                 handled += cx23885_audio_irq(dev, audint_status, audint_mask);
1835
1836         if (pci_status & PCI_MSK_IR) {
1837                 subdev_handled = false;
1838                 v4l2_subdev_call(dev->sd_ir, core, interrupt_service_routine,
1839                                  pci_status, &subdev_handled);
1840                 if (subdev_handled)
1841                         handled++;
1842         }
1843
1844         if ((pci_status & pci_mask) & PCI_MSK_AV_CORE) {
1845                 cx23885_irq_disable(dev, PCI_MSK_AV_CORE);
1846                 schedule_work(&dev->cx25840_work);
1847                 handled++;
1848         }
1849
1850         if (handled)
1851                 cx_write(PCI_INT_STAT, pci_status & pci_mask);
1852 out:
1853         return IRQ_RETVAL(handled);
1854 }
1855
1856 static void cx23885_v4l2_dev_notify(struct v4l2_subdev *sd,
1857                                     unsigned int notification, void *arg)
1858 {
1859         struct cx23885_dev *dev;
1860
1861         if (sd == NULL)
1862                 return;
1863
1864         dev = to_cx23885(sd->v4l2_dev);
1865
1866         switch (notification) {
1867         case V4L2_SUBDEV_IR_RX_NOTIFY: /* Possibly called in an IRQ context */
1868                 if (sd == dev->sd_ir)
1869                         cx23885_ir_rx_v4l2_dev_notify(sd, *(u32 *)arg);
1870                 break;
1871         case V4L2_SUBDEV_IR_TX_NOTIFY: /* Possibly called in an IRQ context */
1872                 if (sd == dev->sd_ir)
1873                         cx23885_ir_tx_v4l2_dev_notify(sd, *(u32 *)arg);
1874                 break;
1875         }
1876 }
1877
1878 static void cx23885_v4l2_dev_notify_init(struct cx23885_dev *dev)
1879 {
1880         INIT_WORK(&dev->cx25840_work, cx23885_av_work_handler);
1881         INIT_WORK(&dev->ir_rx_work, cx23885_ir_rx_work_handler);
1882         INIT_WORK(&dev->ir_tx_work, cx23885_ir_tx_work_handler);
1883         dev->v4l2_dev.notify = cx23885_v4l2_dev_notify;
1884 }
1885
1886 static inline int encoder_on_portb(struct cx23885_dev *dev)
1887 {
1888         return cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER;
1889 }
1890
1891 static inline int encoder_on_portc(struct cx23885_dev *dev)
1892 {
1893         return cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER;
1894 }
1895
1896 /* Mask represents 32 different GPIOs, GPIO's are split into multiple
1897  * registers depending on the board configuration (and whether the
1898  * 417 encoder (wi it's own GPIO's) are present. Each GPIO bit will
1899  * be pushed into the correct hardware register, regardless of the
1900  * physical location. Certain registers are shared so we sanity check
1901  * and report errors if we think we're tampering with a GPIo that might
1902  * be assigned to the encoder (and used for the host bus).
1903  *
1904  * GPIO  2 thru  0 - On the cx23885 bridge
1905  * GPIO 18 thru  3 - On the cx23417 host bus interface
1906  * GPIO 23 thru 19 - On the cx25840 a/v core
1907  */
1908 void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask)
1909 {
1910         if (mask & 0x7)
1911                 cx_set(GP0_IO, mask & 0x7);
1912
1913         if (mask & 0x0007fff8) {
1914                 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1915                         pr_err("%s: Setting GPIO on encoder ports\n",
1916                                 dev->name);
1917                 cx_set(MC417_RWD, (mask & 0x0007fff8) >> 3);
1918         }
1919
1920         /* TODO: 23-19 */
1921         if (mask & 0x00f80000)
1922                 pr_info("%s: Unsupported\n", dev->name);
1923 }
1924
1925 void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask)
1926 {
1927         if (mask & 0x00000007)
1928                 cx_clear(GP0_IO, mask & 0x7);
1929
1930         if (mask & 0x0007fff8) {
1931                 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1932                         pr_err("%s: Clearing GPIO moving on encoder ports\n",
1933                                 dev->name);
1934                 cx_clear(MC417_RWD, (mask & 0x7fff8) >> 3);
1935         }
1936
1937         /* TODO: 23-19 */
1938         if (mask & 0x00f80000)
1939                 pr_info("%s: Unsupported\n", dev->name);
1940 }
1941
1942 u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask)
1943 {
1944         if (mask & 0x00000007)
1945                 return (cx_read(GP0_IO) >> 8) & mask & 0x7;
1946
1947         if (mask & 0x0007fff8) {
1948                 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1949                         pr_err("%s: Reading GPIO moving on encoder ports\n",
1950                                 dev->name);
1951                 return (cx_read(MC417_RWD) & ((mask & 0x7fff8) >> 3)) << 3;
1952         }
1953
1954         /* TODO: 23-19 */
1955         if (mask & 0x00f80000)
1956                 pr_info("%s: Unsupported\n", dev->name);
1957
1958         return 0;
1959 }
1960
1961 void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput)
1962 {
1963         if ((mask & 0x00000007) && asoutput)
1964                 cx_set(GP0_IO, (mask & 0x7) << 16);
1965         else if ((mask & 0x00000007) && !asoutput)
1966                 cx_clear(GP0_IO, (mask & 0x7) << 16);
1967
1968         if (mask & 0x0007fff8) {
1969                 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1970                         pr_err("%s: Enabling GPIO on encoder ports\n",
1971                                 dev->name);
1972         }
1973
1974         /* MC417_OEN is active low for output, write 1 for an input */
1975         if ((mask & 0x0007fff8) && asoutput)
1976                 cx_clear(MC417_OEN, (mask & 0x7fff8) >> 3);
1977
1978         else if ((mask & 0x0007fff8) && !asoutput)
1979                 cx_set(MC417_OEN, (mask & 0x7fff8) >> 3);
1980
1981         /* TODO: 23-19 */
1982 }
1983
1984 static int cx23885_initdev(struct pci_dev *pci_dev,
1985                            const struct pci_device_id *pci_id)
1986 {
1987         struct cx23885_dev *dev;
1988         struct v4l2_ctrl_handler *hdl;
1989         int err;
1990
1991         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1992         if (NULL == dev)
1993                 return -ENOMEM;
1994
1995         err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
1996         if (err < 0)
1997                 goto fail_free;
1998
1999         hdl = &dev->ctrl_handler;
2000         v4l2_ctrl_handler_init(hdl, 6);
2001         if (hdl->error) {
2002                 err = hdl->error;
2003                 goto fail_ctrl;
2004         }
2005         dev->v4l2_dev.ctrl_handler = hdl;
2006
2007         /* Prepare to handle notifications from subdevices */
2008         cx23885_v4l2_dev_notify_init(dev);
2009
2010         /* pci init */
2011         dev->pci = pci_dev;
2012         if (pci_enable_device(pci_dev)) {
2013                 err = -EIO;
2014                 goto fail_ctrl;
2015         }
2016
2017         if (cx23885_dev_setup(dev) < 0) {
2018                 err = -EINVAL;
2019                 goto fail_ctrl;
2020         }
2021
2022         /* print pci info */
2023         dev->pci_rev = pci_dev->revision;
2024         pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER,  &dev->pci_lat);
2025         pr_info("%s/0: found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n",
2026                dev->name,
2027                pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
2028                dev->pci_lat,
2029                 (unsigned long long)pci_resource_start(pci_dev, 0));
2030
2031         pci_set_master(pci_dev);
2032         err = pci_set_dma_mask(pci_dev, 0xffffffff);
2033         if (err) {
2034                 pr_err("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
2035                 goto fail_ctrl;
2036         }
2037
2038         err = request_irq(pci_dev->irq, cx23885_irq,
2039                           IRQF_SHARED, dev->name, dev);
2040         if (err < 0) {
2041                 pr_err("%s: can't get IRQ %d\n",
2042                        dev->name, pci_dev->irq);
2043                 goto fail_irq;
2044         }
2045
2046         switch (dev->board) {
2047         case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
2048                 cx23885_irq_add_enable(dev, PCI_MSK_GPIO1 | PCI_MSK_GPIO0);
2049                 break;
2050         case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
2051                 cx23885_irq_add_enable(dev, PCI_MSK_GPIO0);
2052                 break;
2053         }
2054
2055         /*
2056          * The CX2388[58] IR controller can start firing interrupts when
2057          * enabled, so these have to take place after the cx23885_irq() handler
2058          * is hooked up by the call to request_irq() above.
2059          */
2060         cx23885_ir_pci_int_enable(dev);
2061         cx23885_input_init(dev);
2062
2063         return 0;
2064
2065 fail_irq:
2066         cx23885_dev_unregister(dev);
2067 fail_ctrl:
2068         v4l2_ctrl_handler_free(hdl);
2069         v4l2_device_unregister(&dev->v4l2_dev);
2070 fail_free:
2071         kfree(dev);
2072         return err;
2073 }
2074
2075 static void cx23885_finidev(struct pci_dev *pci_dev)
2076 {
2077         struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
2078         struct cx23885_dev *dev = to_cx23885(v4l2_dev);
2079
2080         cx23885_input_fini(dev);
2081         cx23885_ir_fini(dev);
2082
2083         cx23885_shutdown(dev);
2084
2085         /* unregister stuff */
2086         free_irq(pci_dev->irq, dev);
2087
2088         pci_disable_device(pci_dev);
2089
2090         cx23885_dev_unregister(dev);
2091         v4l2_ctrl_handler_free(&dev->ctrl_handler);
2092         v4l2_device_unregister(v4l2_dev);
2093         kfree(dev);
2094 }
2095
2096 static const struct pci_device_id cx23885_pci_tbl[] = {
2097         {
2098                 /* CX23885 */
2099                 .vendor       = 0x14f1,
2100                 .device       = 0x8852,
2101                 .subvendor    = PCI_ANY_ID,
2102                 .subdevice    = PCI_ANY_ID,
2103         }, {
2104                 /* CX23887 Rev 2 */
2105                 .vendor       = 0x14f1,
2106                 .device       = 0x8880,
2107                 .subvendor    = PCI_ANY_ID,
2108                 .subdevice    = PCI_ANY_ID,
2109         }, {
2110                 /* --- end of list --- */
2111         }
2112 };
2113 MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
2114
2115 static struct pci_driver cx23885_pci_driver = {
2116         .name     = "cx23885",
2117         .id_table = cx23885_pci_tbl,
2118         .probe    = cx23885_initdev,
2119         .remove   = cx23885_finidev,
2120         /* TODO */
2121         .suspend  = NULL,
2122         .resume   = NULL,
2123 };
2124
2125 static int __init cx23885_init(void)
2126 {
2127         pr_info("cx23885 driver version %s loaded\n",
2128                 CX23885_VERSION);
2129         return pci_register_driver(&cx23885_pci_driver);
2130 }
2131
2132 static void __exit cx23885_fini(void)
2133 {
2134         pci_unregister_driver(&cx23885_pci_driver);
2135 }
2136
2137 module_init(cx23885_init);
2138 module_exit(cx23885_fini);