1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the OV7251 camera sensor.
5 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2017-2018, Linaro Ltd.
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/i2c.h>
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/slab.h>
19 #include <linux/types.h>
20 #include <media/v4l2-ctrls.h>
21 #include <media/v4l2-fwnode.h>
22 #include <media/v4l2-subdev.h>
24 #define OV7251_SC_MODE_SELECT 0x0100
25 #define OV7251_SC_MODE_SELECT_SW_STANDBY 0x0
26 #define OV7251_SC_MODE_SELECT_STREAMING 0x1
28 #define OV7251_CHIP_ID_HIGH 0x300a
29 #define OV7251_CHIP_ID_HIGH_BYTE 0x77
30 #define OV7251_CHIP_ID_LOW 0x300b
31 #define OV7251_CHIP_ID_LOW_BYTE 0x50
32 #define OV7251_SC_GP_IO_IN1 0x3029
33 #define OV7251_AEC_EXPO_0 0x3500
34 #define OV7251_AEC_EXPO_1 0x3501
35 #define OV7251_AEC_EXPO_2 0x3502
36 #define OV7251_AEC_AGC_ADJ_0 0x350a
37 #define OV7251_AEC_AGC_ADJ_1 0x350b
38 #define OV7251_TIMING_FORMAT1 0x3820
39 #define OV7251_TIMING_FORMAT1_VFLIP BIT(2)
40 #define OV7251_TIMING_FORMAT2 0x3821
41 #define OV7251_TIMING_FORMAT2_MIRROR BIT(2)
42 #define OV7251_PRE_ISP_00 0x5e00
43 #define OV7251_PRE_ISP_00_TEST_PATTERN BIT(7)
50 struct ov7251_mode_info {
53 const struct reg_value *data;
59 struct v4l2_fract timeperframe;
63 struct i2c_client *i2c_client;
65 struct v4l2_subdev sd;
67 struct v4l2_fwnode_endpoint ep;
68 struct v4l2_mbus_framefmt fmt;
69 struct v4l2_rect crop;
73 struct regulator *io_regulator;
74 struct regulator *core_regulator;
75 struct regulator *analog_regulator;
77 const struct ov7251_mode_info *current_mode;
79 struct v4l2_ctrl_handler ctrls;
80 struct v4l2_ctrl *pixel_clock;
81 struct v4l2_ctrl *link_freq;
82 struct v4l2_ctrl *exposure;
83 struct v4l2_ctrl *gain;
85 /* Cached register values */
91 struct mutex lock; /* lock to protect power state, ctrls and mode */
94 struct gpio_desc *enable_gpio;
97 static inline struct ov7251 *to_ov7251(struct v4l2_subdev *sd)
99 return container_of(sd, struct ov7251, sd);
102 static const struct reg_value ov7251_global_init_setting[] = {
107 static const struct reg_value ov7251_setting_vga_30fps[] = {
120 { 0x3098, 0x04 }, /* pll2 pre divider */
121 { 0x3099, 0x28 }, /* pll2 multiplier */
122 { 0x309a, 0x05 }, /* pll2 sys divider */
123 { 0x309b, 0x04 }, /* pll2 adc divider */
124 { 0x309d, 0x00 }, /* pll2 divider */
125 { 0x30b0, 0x0a }, /* pll1 pix divider */
126 { 0x30b1, 0x01 }, /* pll1 divider */
127 { 0x30b3, 0x64 }, /* pll1 multiplier */
128 { 0x30b4, 0x03 }, /* pll1 pre divider */
129 { 0x30b5, 0x05 }, /* pll1 mipi divider */
169 { 0x3808, 0x02 }, /* width high */
170 { 0x3809, 0x80 }, /* width low */
171 { 0x380a, 0x01 }, /* height high */
172 { 0x380b, 0xe0 }, /* height low */
173 { 0x380c, 0x03 }, /* total horiz timing high */
174 { 0x380d, 0xa0 }, /* total horiz timing low */
175 { 0x380e, 0x06 }, /* total vertical timing high */
176 { 0x380f, 0xbc }, /* total vertical timing low */
245 static const struct reg_value ov7251_setting_vga_60fps[] = {
258 { 0x3098, 0x04 }, /* pll2 pre divider */
259 { 0x3099, 0x28 }, /* pll2 multiplier */
260 { 0x309a, 0x05 }, /* pll2 sys divider */
261 { 0x309b, 0x04 }, /* pll2 adc divider */
262 { 0x309d, 0x00 }, /* pll2 divider */
263 { 0x30b0, 0x0a }, /* pll1 pix divider */
264 { 0x30b1, 0x01 }, /* pll1 divider */
265 { 0x30b3, 0x64 }, /* pll1 multiplier */
266 { 0x30b4, 0x03 }, /* pll1 pre divider */
267 { 0x30b5, 0x05 }, /* pll1 mipi divider */
307 { 0x3808, 0x02 }, /* width high */
308 { 0x3809, 0x80 }, /* width low */
309 { 0x380a, 0x01 }, /* height high */
310 { 0x380b, 0xe0 }, /* height low */
311 { 0x380c, 0x03 }, /* total horiz timing high */
312 { 0x380d, 0xa0 }, /* total horiz timing low */
313 { 0x380e, 0x03 }, /* total vertical timing high */
314 { 0x380f, 0x5c }, /* total vertical timing low */
383 static const struct reg_value ov7251_setting_vga_90fps[] = {
396 { 0x3098, 0x04 }, /* pll2 pre divider */
397 { 0x3099, 0x28 }, /* pll2 multiplier */
398 { 0x309a, 0x05 }, /* pll2 sys divider */
399 { 0x309b, 0x04 }, /* pll2 adc divider */
400 { 0x309d, 0x00 }, /* pll2 divider */
401 { 0x30b0, 0x0a }, /* pll1 pix divider */
402 { 0x30b1, 0x01 }, /* pll1 divider */
403 { 0x30b3, 0x64 }, /* pll1 multiplier */
404 { 0x30b4, 0x03 }, /* pll1 pre divider */
405 { 0x30b5, 0x05 }, /* pll1 mipi divider */
445 { 0x3808, 0x02 }, /* width high */
446 { 0x3809, 0x80 }, /* width low */
447 { 0x380a, 0x01 }, /* height high */
448 { 0x380b, 0xe0 }, /* height low */
449 { 0x380c, 0x03 }, /* total horiz timing high */
450 { 0x380d, 0xa0 }, /* total horiz timing low */
451 { 0x380e, 0x02 }, /* total vertical timing high */
452 { 0x380f, 0x3c }, /* total vertical timing low */
521 static const s64 link_freq[] = {
525 static const struct ov7251_mode_info ov7251_mode_info_data[] = {
529 .data = ov7251_setting_vga_30fps,
530 .data_size = ARRAY_SIZE(ov7251_setting_vga_30fps),
531 .pixel_clock = 48000000,
532 .link_freq = 0, /* an index in link_freq[] */
533 .exposure_max = 1704,
543 .data = ov7251_setting_vga_60fps,
544 .data_size = ARRAY_SIZE(ov7251_setting_vga_60fps),
545 .pixel_clock = 48000000,
546 .link_freq = 0, /* an index in link_freq[] */
557 .data = ov7251_setting_vga_90fps,
558 .data_size = ARRAY_SIZE(ov7251_setting_vga_90fps),
559 .pixel_clock = 48000000,
560 .link_freq = 0, /* an index in link_freq[] */
570 static int ov7251_regulators_enable(struct ov7251 *ov7251)
574 /* OV7251 power up sequence requires core regulator
575 * to be enabled not earlier than io regulator
578 ret = regulator_enable(ov7251->io_regulator);
580 dev_err(ov7251->dev, "set io voltage failed\n");
584 ret = regulator_enable(ov7251->analog_regulator);
586 dev_err(ov7251->dev, "set analog voltage failed\n");
590 ret = regulator_enable(ov7251->core_regulator);
592 dev_err(ov7251->dev, "set core voltage failed\n");
593 goto err_disable_analog;
599 regulator_disable(ov7251->analog_regulator);
602 regulator_disable(ov7251->io_regulator);
607 static void ov7251_regulators_disable(struct ov7251 *ov7251)
611 ret = regulator_disable(ov7251->core_regulator);
613 dev_err(ov7251->dev, "core regulator disable failed\n");
615 ret = regulator_disable(ov7251->analog_regulator);
617 dev_err(ov7251->dev, "analog regulator disable failed\n");
619 ret = regulator_disable(ov7251->io_regulator);
621 dev_err(ov7251->dev, "io regulator disable failed\n");
624 static int ov7251_write_reg(struct ov7251 *ov7251, u16 reg, u8 val)
629 regbuf[0] = reg >> 8;
630 regbuf[1] = reg & 0xff;
633 ret = i2c_master_send(ov7251->i2c_client, regbuf, 3);
635 dev_err(ov7251->dev, "%s: write reg error %d: reg=%x, val=%x\n",
636 __func__, ret, reg, val);
643 static int ov7251_write_seq_regs(struct ov7251 *ov7251, u16 reg, u8 *val,
647 u8 nregbuf = sizeof(reg) + num * sizeof(*val);
650 if (nregbuf > sizeof(regbuf))
653 regbuf[0] = reg >> 8;
654 regbuf[1] = reg & 0xff;
656 memcpy(regbuf + 2, val, num);
658 ret = i2c_master_send(ov7251->i2c_client, regbuf, nregbuf);
661 "%s: write seq regs error %d: first reg=%x\n",
669 static int ov7251_read_reg(struct ov7251 *ov7251, u16 reg, u8 *val)
674 regbuf[0] = reg >> 8;
675 regbuf[1] = reg & 0xff;
677 ret = i2c_master_send(ov7251->i2c_client, regbuf, 2);
679 dev_err(ov7251->dev, "%s: write reg error %d: reg=%x\n",
684 ret = i2c_master_recv(ov7251->i2c_client, val, 1);
686 dev_err(ov7251->dev, "%s: read reg error %d: reg=%x\n",
694 static int ov7251_set_exposure(struct ov7251 *ov7251, s32 exposure)
699 reg = OV7251_AEC_EXPO_0;
700 val[0] = (exposure & 0xf000) >> 12; /* goes to OV7251_AEC_EXPO_0 */
701 val[1] = (exposure & 0x0ff0) >> 4; /* goes to OV7251_AEC_EXPO_1 */
702 val[2] = (exposure & 0x000f) << 4; /* goes to OV7251_AEC_EXPO_2 */
704 return ov7251_write_seq_regs(ov7251, reg, val, 3);
707 static int ov7251_set_gain(struct ov7251 *ov7251, s32 gain)
712 reg = OV7251_AEC_AGC_ADJ_0;
713 val[0] = (gain & 0x0300) >> 8; /* goes to OV7251_AEC_AGC_ADJ_0 */
714 val[1] = gain & 0xff; /* goes to OV7251_AEC_AGC_ADJ_1 */
716 return ov7251_write_seq_regs(ov7251, reg, val, 2);
719 static int ov7251_set_register_array(struct ov7251 *ov7251,
720 const struct reg_value *settings,
721 unsigned int num_settings)
726 for (i = 0; i < num_settings; ++i, ++settings) {
727 ret = ov7251_write_reg(ov7251, settings->reg, settings->val);
735 static int ov7251_set_power_on(struct ov7251 *ov7251)
740 ret = ov7251_regulators_enable(ov7251);
744 ret = clk_prepare_enable(ov7251->xclk);
746 dev_err(ov7251->dev, "clk prepare enable failed\n");
747 ov7251_regulators_disable(ov7251);
751 gpiod_set_value_cansleep(ov7251->enable_gpio, 1);
753 /* wait at least 65536 external clock cycles */
754 wait_us = DIV_ROUND_UP(65536 * 1000,
755 DIV_ROUND_UP(ov7251->xclk_freq, 1000));
756 usleep_range(wait_us, wait_us + 1000);
761 static void ov7251_set_power_off(struct ov7251 *ov7251)
763 clk_disable_unprepare(ov7251->xclk);
764 gpiod_set_value_cansleep(ov7251->enable_gpio, 0);
765 ov7251_regulators_disable(ov7251);
768 static int ov7251_s_power(struct v4l2_subdev *sd, int on)
770 struct ov7251 *ov7251 = to_ov7251(sd);
773 mutex_lock(&ov7251->lock);
775 /* If the power state is not modified - no work to do. */
776 if (ov7251->power_on == !!on)
780 ret = ov7251_set_power_on(ov7251);
784 ret = ov7251_set_register_array(ov7251,
785 ov7251_global_init_setting,
786 ARRAY_SIZE(ov7251_global_init_setting));
788 dev_err(ov7251->dev, "could not set init registers\n");
789 ov7251_set_power_off(ov7251);
793 ov7251->power_on = true;
795 ov7251_set_power_off(ov7251);
796 ov7251->power_on = false;
800 mutex_unlock(&ov7251->lock);
805 static int ov7251_set_hflip(struct ov7251 *ov7251, s32 value)
807 u8 val = ov7251->timing_format2;
811 val |= OV7251_TIMING_FORMAT2_MIRROR;
813 val &= ~OV7251_TIMING_FORMAT2_MIRROR;
815 ret = ov7251_write_reg(ov7251, OV7251_TIMING_FORMAT2, val);
817 ov7251->timing_format2 = val;
822 static int ov7251_set_vflip(struct ov7251 *ov7251, s32 value)
824 u8 val = ov7251->timing_format1;
828 val |= OV7251_TIMING_FORMAT1_VFLIP;
830 val &= ~OV7251_TIMING_FORMAT1_VFLIP;
832 ret = ov7251_write_reg(ov7251, OV7251_TIMING_FORMAT1, val);
834 ov7251->timing_format1 = val;
839 static int ov7251_set_test_pattern(struct ov7251 *ov7251, s32 value)
841 u8 val = ov7251->pre_isp_00;
845 val |= OV7251_PRE_ISP_00_TEST_PATTERN;
847 val &= ~OV7251_PRE_ISP_00_TEST_PATTERN;
849 ret = ov7251_write_reg(ov7251, OV7251_PRE_ISP_00, val);
851 ov7251->pre_isp_00 = val;
856 static const char * const ov7251_test_pattern_menu[] = {
858 "Vertical Pattern Bars",
861 static int ov7251_s_ctrl(struct v4l2_ctrl *ctrl)
863 struct ov7251 *ov7251 = container_of(ctrl->handler,
864 struct ov7251, ctrls);
867 /* v4l2_ctrl_lock() locks our mutex */
869 if (!ov7251->power_on)
873 case V4L2_CID_EXPOSURE:
874 ret = ov7251_set_exposure(ov7251, ctrl->val);
877 ret = ov7251_set_gain(ov7251, ctrl->val);
879 case V4L2_CID_TEST_PATTERN:
880 ret = ov7251_set_test_pattern(ov7251, ctrl->val);
883 ret = ov7251_set_hflip(ov7251, ctrl->val);
886 ret = ov7251_set_vflip(ov7251, ctrl->val);
896 static const struct v4l2_ctrl_ops ov7251_ctrl_ops = {
897 .s_ctrl = ov7251_s_ctrl,
900 static int ov7251_enum_mbus_code(struct v4l2_subdev *sd,
901 struct v4l2_subdev_state *sd_state,
902 struct v4l2_subdev_mbus_code_enum *code)
907 code->code = MEDIA_BUS_FMT_Y10_1X10;
912 static int ov7251_enum_frame_size(struct v4l2_subdev *subdev,
913 struct v4l2_subdev_state *sd_state,
914 struct v4l2_subdev_frame_size_enum *fse)
916 if (fse->code != MEDIA_BUS_FMT_Y10_1X10)
919 if (fse->index >= ARRAY_SIZE(ov7251_mode_info_data))
922 fse->min_width = ov7251_mode_info_data[fse->index].width;
923 fse->max_width = ov7251_mode_info_data[fse->index].width;
924 fse->min_height = ov7251_mode_info_data[fse->index].height;
925 fse->max_height = ov7251_mode_info_data[fse->index].height;
930 static int ov7251_enum_frame_ival(struct v4l2_subdev *subdev,
931 struct v4l2_subdev_state *sd_state,
932 struct v4l2_subdev_frame_interval_enum *fie)
934 unsigned int index = fie->index;
937 for (i = 0; i < ARRAY_SIZE(ov7251_mode_info_data); i++) {
938 if (fie->width != ov7251_mode_info_data[i].width ||
939 fie->height != ov7251_mode_info_data[i].height)
943 fie->interval = ov7251_mode_info_data[i].timeperframe;
951 static struct v4l2_mbus_framefmt *
952 __ov7251_get_pad_format(struct ov7251 *ov7251,
953 struct v4l2_subdev_state *sd_state,
955 enum v4l2_subdev_format_whence which)
958 case V4L2_SUBDEV_FORMAT_TRY:
959 return v4l2_subdev_get_try_format(&ov7251->sd, sd_state, pad);
960 case V4L2_SUBDEV_FORMAT_ACTIVE:
967 static int ov7251_get_format(struct v4l2_subdev *sd,
968 struct v4l2_subdev_state *sd_state,
969 struct v4l2_subdev_format *format)
971 struct ov7251 *ov7251 = to_ov7251(sd);
973 mutex_lock(&ov7251->lock);
974 format->format = *__ov7251_get_pad_format(ov7251, sd_state,
977 mutex_unlock(&ov7251->lock);
982 static struct v4l2_rect *
983 __ov7251_get_pad_crop(struct ov7251 *ov7251,
984 struct v4l2_subdev_state *sd_state,
985 unsigned int pad, enum v4l2_subdev_format_whence which)
988 case V4L2_SUBDEV_FORMAT_TRY:
989 return v4l2_subdev_get_try_crop(&ov7251->sd, sd_state, pad);
990 case V4L2_SUBDEV_FORMAT_ACTIVE:
991 return &ov7251->crop;
997 static inline u32 avg_fps(const struct v4l2_fract *t)
999 return (t->denominator + (t->numerator >> 1)) / t->numerator;
1002 static const struct ov7251_mode_info *
1003 ov7251_find_mode_by_ival(struct ov7251 *ov7251, struct v4l2_fract *timeperframe)
1005 const struct ov7251_mode_info *mode = ov7251->current_mode;
1006 unsigned int fps_req = avg_fps(timeperframe);
1007 unsigned int max_dist_match = (unsigned int) -1;
1008 unsigned int i, n = 0;
1010 for (i = 0; i < ARRAY_SIZE(ov7251_mode_info_data); i++) {
1012 unsigned int fps_tmp;
1014 if (mode->width != ov7251_mode_info_data[i].width ||
1015 mode->height != ov7251_mode_info_data[i].height)
1018 fps_tmp = avg_fps(&ov7251_mode_info_data[i].timeperframe);
1020 dist = abs(fps_req - fps_tmp);
1022 if (dist < max_dist_match) {
1024 max_dist_match = dist;
1028 return &ov7251_mode_info_data[n];
1031 static int ov7251_set_format(struct v4l2_subdev *sd,
1032 struct v4l2_subdev_state *sd_state,
1033 struct v4l2_subdev_format *format)
1035 struct ov7251 *ov7251 = to_ov7251(sd);
1036 struct v4l2_mbus_framefmt *__format;
1037 struct v4l2_rect *__crop;
1038 const struct ov7251_mode_info *new_mode;
1041 mutex_lock(&ov7251->lock);
1043 __crop = __ov7251_get_pad_crop(ov7251, sd_state, format->pad,
1046 new_mode = v4l2_find_nearest_size(ov7251_mode_info_data,
1047 ARRAY_SIZE(ov7251_mode_info_data),
1049 format->format.width, format->format.height);
1051 __crop->width = new_mode->width;
1052 __crop->height = new_mode->height;
1054 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
1055 ret = __v4l2_ctrl_s_ctrl_int64(ov7251->pixel_clock,
1056 new_mode->pixel_clock);
1060 ret = __v4l2_ctrl_s_ctrl(ov7251->link_freq,
1061 new_mode->link_freq);
1065 ret = __v4l2_ctrl_modify_range(ov7251->exposure,
1066 1, new_mode->exposure_max,
1067 1, new_mode->exposure_def);
1071 ret = __v4l2_ctrl_s_ctrl(ov7251->exposure,
1072 new_mode->exposure_def);
1076 ret = __v4l2_ctrl_s_ctrl(ov7251->gain, 16);
1080 ov7251->current_mode = new_mode;
1083 __format = __ov7251_get_pad_format(ov7251, sd_state, format->pad,
1085 __format->width = __crop->width;
1086 __format->height = __crop->height;
1087 __format->code = MEDIA_BUS_FMT_Y10_1X10;
1088 __format->field = V4L2_FIELD_NONE;
1089 __format->colorspace = V4L2_COLORSPACE_SRGB;
1090 __format->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(__format->colorspace);
1091 __format->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true,
1092 __format->colorspace, __format->ycbcr_enc);
1093 __format->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(__format->colorspace);
1095 format->format = *__format;
1098 mutex_unlock(&ov7251->lock);
1103 static int ov7251_entity_init_cfg(struct v4l2_subdev *subdev,
1104 struct v4l2_subdev_state *sd_state)
1106 struct v4l2_subdev_format fmt = {
1107 .which = sd_state ? V4L2_SUBDEV_FORMAT_TRY
1108 : V4L2_SUBDEV_FORMAT_ACTIVE,
1115 ov7251_set_format(subdev, sd_state, &fmt);
1120 static int ov7251_get_selection(struct v4l2_subdev *sd,
1121 struct v4l2_subdev_state *sd_state,
1122 struct v4l2_subdev_selection *sel)
1124 struct ov7251 *ov7251 = to_ov7251(sd);
1126 if (sel->target != V4L2_SEL_TGT_CROP)
1129 mutex_lock(&ov7251->lock);
1130 sel->r = *__ov7251_get_pad_crop(ov7251, sd_state, sel->pad,
1132 mutex_unlock(&ov7251->lock);
1137 static int ov7251_s_stream(struct v4l2_subdev *subdev, int enable)
1139 struct ov7251 *ov7251 = to_ov7251(subdev);
1142 mutex_lock(&ov7251->lock);
1145 ret = ov7251_set_register_array(ov7251,
1146 ov7251->current_mode->data,
1147 ov7251->current_mode->data_size);
1149 dev_err(ov7251->dev, "could not set mode %dx%d\n",
1150 ov7251->current_mode->width,
1151 ov7251->current_mode->height);
1154 ret = __v4l2_ctrl_handler_setup(&ov7251->ctrls);
1156 dev_err(ov7251->dev, "could not sync v4l2 controls\n");
1159 ret = ov7251_write_reg(ov7251, OV7251_SC_MODE_SELECT,
1160 OV7251_SC_MODE_SELECT_STREAMING);
1162 ret = ov7251_write_reg(ov7251, OV7251_SC_MODE_SELECT,
1163 OV7251_SC_MODE_SELECT_SW_STANDBY);
1167 mutex_unlock(&ov7251->lock);
1172 static int ov7251_get_frame_interval(struct v4l2_subdev *subdev,
1173 struct v4l2_subdev_frame_interval *fi)
1175 struct ov7251 *ov7251 = to_ov7251(subdev);
1177 mutex_lock(&ov7251->lock);
1178 fi->interval = ov7251->current_mode->timeperframe;
1179 mutex_unlock(&ov7251->lock);
1184 static int ov7251_set_frame_interval(struct v4l2_subdev *subdev,
1185 struct v4l2_subdev_frame_interval *fi)
1187 struct ov7251 *ov7251 = to_ov7251(subdev);
1188 const struct ov7251_mode_info *new_mode;
1191 mutex_lock(&ov7251->lock);
1192 new_mode = ov7251_find_mode_by_ival(ov7251, &fi->interval);
1194 if (new_mode != ov7251->current_mode) {
1195 ret = __v4l2_ctrl_s_ctrl_int64(ov7251->pixel_clock,
1196 new_mode->pixel_clock);
1200 ret = __v4l2_ctrl_s_ctrl(ov7251->link_freq,
1201 new_mode->link_freq);
1205 ret = __v4l2_ctrl_modify_range(ov7251->exposure,
1206 1, new_mode->exposure_max,
1207 1, new_mode->exposure_def);
1211 ret = __v4l2_ctrl_s_ctrl(ov7251->exposure,
1212 new_mode->exposure_def);
1216 ret = __v4l2_ctrl_s_ctrl(ov7251->gain, 16);
1220 ov7251->current_mode = new_mode;
1223 fi->interval = ov7251->current_mode->timeperframe;
1226 mutex_unlock(&ov7251->lock);
1231 static const struct v4l2_subdev_core_ops ov7251_core_ops = {
1232 .s_power = ov7251_s_power,
1235 static const struct v4l2_subdev_video_ops ov7251_video_ops = {
1236 .s_stream = ov7251_s_stream,
1237 .g_frame_interval = ov7251_get_frame_interval,
1238 .s_frame_interval = ov7251_set_frame_interval,
1241 static const struct v4l2_subdev_pad_ops ov7251_subdev_pad_ops = {
1242 .init_cfg = ov7251_entity_init_cfg,
1243 .enum_mbus_code = ov7251_enum_mbus_code,
1244 .enum_frame_size = ov7251_enum_frame_size,
1245 .enum_frame_interval = ov7251_enum_frame_ival,
1246 .get_fmt = ov7251_get_format,
1247 .set_fmt = ov7251_set_format,
1248 .get_selection = ov7251_get_selection,
1251 static const struct v4l2_subdev_ops ov7251_subdev_ops = {
1252 .core = &ov7251_core_ops,
1253 .video = &ov7251_video_ops,
1254 .pad = &ov7251_subdev_pad_ops,
1257 static int ov7251_probe(struct i2c_client *client)
1259 struct device *dev = &client->dev;
1260 struct fwnode_handle *endpoint;
1261 struct ov7251 *ov7251;
1262 u8 chip_id_high, chip_id_low, chip_rev;
1265 ov7251 = devm_kzalloc(dev, sizeof(struct ov7251), GFP_KERNEL);
1269 ov7251->i2c_client = client;
1272 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL);
1274 dev_err(dev, "endpoint node not found\n");
1278 ret = v4l2_fwnode_endpoint_parse(endpoint, &ov7251->ep);
1279 fwnode_handle_put(endpoint);
1281 dev_err(dev, "parsing endpoint node failed\n");
1285 if (ov7251->ep.bus_type != V4L2_MBUS_CSI2_DPHY) {
1286 dev_err(dev, "invalid bus type (%u), must be CSI2 (%u)\n",
1287 ov7251->ep.bus_type, V4L2_MBUS_CSI2_DPHY);
1291 /* get system clock (xclk) */
1292 ov7251->xclk = devm_clk_get(dev, "xclk");
1293 if (IS_ERR(ov7251->xclk)) {
1294 dev_err(dev, "could not get xclk");
1295 return PTR_ERR(ov7251->xclk);
1298 ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
1299 &ov7251->xclk_freq);
1301 dev_err(dev, "could not get xclk frequency\n");
1305 /* external clock must be 24MHz, allow 1% tolerance */
1306 if (ov7251->xclk_freq < 23760000 || ov7251->xclk_freq > 24240000) {
1307 dev_err(dev, "external clock frequency %u is not supported\n",
1312 ret = clk_set_rate(ov7251->xclk, ov7251->xclk_freq);
1314 dev_err(dev, "could not set xclk frequency\n");
1318 ov7251->io_regulator = devm_regulator_get(dev, "vdddo");
1319 if (IS_ERR(ov7251->io_regulator)) {
1320 dev_err(dev, "cannot get io regulator\n");
1321 return PTR_ERR(ov7251->io_regulator);
1324 ov7251->core_regulator = devm_regulator_get(dev, "vddd");
1325 if (IS_ERR(ov7251->core_regulator)) {
1326 dev_err(dev, "cannot get core regulator\n");
1327 return PTR_ERR(ov7251->core_regulator);
1330 ov7251->analog_regulator = devm_regulator_get(dev, "vdda");
1331 if (IS_ERR(ov7251->analog_regulator)) {
1332 dev_err(dev, "cannot get analog regulator\n");
1333 return PTR_ERR(ov7251->analog_regulator);
1336 ov7251->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_HIGH);
1337 if (IS_ERR(ov7251->enable_gpio)) {
1338 dev_err(dev, "cannot get enable gpio\n");
1339 return PTR_ERR(ov7251->enable_gpio);
1342 mutex_init(&ov7251->lock);
1344 v4l2_ctrl_handler_init(&ov7251->ctrls, 7);
1345 ov7251->ctrls.lock = &ov7251->lock;
1347 v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1348 V4L2_CID_HFLIP, 0, 1, 1, 0);
1349 v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1350 V4L2_CID_VFLIP, 0, 1, 1, 0);
1351 ov7251->exposure = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1352 V4L2_CID_EXPOSURE, 1, 32, 1, 32);
1353 ov7251->gain = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1354 V4L2_CID_GAIN, 16, 1023, 1, 16);
1355 v4l2_ctrl_new_std_menu_items(&ov7251->ctrls, &ov7251_ctrl_ops,
1356 V4L2_CID_TEST_PATTERN,
1357 ARRAY_SIZE(ov7251_test_pattern_menu) - 1,
1358 0, 0, ov7251_test_pattern_menu);
1359 ov7251->pixel_clock = v4l2_ctrl_new_std(&ov7251->ctrls,
1361 V4L2_CID_PIXEL_RATE,
1363 ov7251->link_freq = v4l2_ctrl_new_int_menu(&ov7251->ctrls,
1366 ARRAY_SIZE(link_freq) - 1,
1368 if (ov7251->link_freq)
1369 ov7251->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1371 ov7251->sd.ctrl_handler = &ov7251->ctrls;
1373 if (ov7251->ctrls.error) {
1374 dev_err(dev, "%s: control initialization error %d\n",
1375 __func__, ov7251->ctrls.error);
1376 ret = ov7251->ctrls.error;
1380 v4l2_i2c_subdev_init(&ov7251->sd, client, &ov7251_subdev_ops);
1381 ov7251->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1382 ov7251->pad.flags = MEDIA_PAD_FL_SOURCE;
1383 ov7251->sd.dev = &client->dev;
1384 ov7251->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1386 ret = media_entity_pads_init(&ov7251->sd.entity, 1, &ov7251->pad);
1388 dev_err(dev, "could not register media entity\n");
1392 ret = ov7251_s_power(&ov7251->sd, true);
1394 dev_err(dev, "could not power up OV7251\n");
1398 ret = ov7251_read_reg(ov7251, OV7251_CHIP_ID_HIGH, &chip_id_high);
1399 if (ret < 0 || chip_id_high != OV7251_CHIP_ID_HIGH_BYTE) {
1400 dev_err(dev, "could not read ID high\n");
1404 ret = ov7251_read_reg(ov7251, OV7251_CHIP_ID_LOW, &chip_id_low);
1405 if (ret < 0 || chip_id_low != OV7251_CHIP_ID_LOW_BYTE) {
1406 dev_err(dev, "could not read ID low\n");
1411 ret = ov7251_read_reg(ov7251, OV7251_SC_GP_IO_IN1, &chip_rev);
1413 dev_err(dev, "could not read revision\n");
1419 dev_info(dev, "OV7251 revision %x (%s) detected at address 0x%02x\n",
1421 chip_rev == 0x4 ? "1A / 1B" :
1422 chip_rev == 0x5 ? "1C / 1D" :
1423 chip_rev == 0x6 ? "1E" :
1424 chip_rev == 0x7 ? "1F" : "unknown",
1427 ret = ov7251_read_reg(ov7251, OV7251_PRE_ISP_00,
1428 &ov7251->pre_isp_00);
1430 dev_err(dev, "could not read test pattern value\n");
1435 ret = ov7251_read_reg(ov7251, OV7251_TIMING_FORMAT1,
1436 &ov7251->timing_format1);
1438 dev_err(dev, "could not read vflip value\n");
1443 ret = ov7251_read_reg(ov7251, OV7251_TIMING_FORMAT2,
1444 &ov7251->timing_format2);
1446 dev_err(dev, "could not read hflip value\n");
1451 ov7251_s_power(&ov7251->sd, false);
1453 ret = v4l2_async_register_subdev(&ov7251->sd);
1455 dev_err(dev, "could not register v4l2 device\n");
1459 ov7251_entity_init_cfg(&ov7251->sd, NULL);
1464 ov7251_s_power(&ov7251->sd, false);
1466 media_entity_cleanup(&ov7251->sd.entity);
1468 v4l2_ctrl_handler_free(&ov7251->ctrls);
1469 mutex_destroy(&ov7251->lock);
1474 static int ov7251_remove(struct i2c_client *client)
1476 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1477 struct ov7251 *ov7251 = to_ov7251(sd);
1479 v4l2_async_unregister_subdev(&ov7251->sd);
1480 media_entity_cleanup(&ov7251->sd.entity);
1481 v4l2_ctrl_handler_free(&ov7251->ctrls);
1482 mutex_destroy(&ov7251->lock);
1487 static const struct of_device_id ov7251_of_match[] = {
1488 { .compatible = "ovti,ov7251" },
1491 MODULE_DEVICE_TABLE(of, ov7251_of_match);
1493 static struct i2c_driver ov7251_i2c_driver = {
1495 .of_match_table = ov7251_of_match,
1498 .probe_new = ov7251_probe,
1499 .remove = ov7251_remove,
1502 module_i2c_driver(ov7251_i2c_driver);
1504 MODULE_DESCRIPTION("Omnivision OV7251 Camera Driver");
1505 MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>");
1506 MODULE_LICENSE("GPL v2");