drivers/media/i2c/ov01a10.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2023 Intel Corporation.
   4  */
   5
   6 #include <asm/unaligned.h>
   7
   8 #include <linux/acpi.h>
   9 #include <linux/bitfield.h>
  10 #include <linux/i2c.h>
  11 #include <linux/module.h>
  12 #include <linux/pm_runtime.h>
  13
  14 #include <media/v4l2-ctrls.h>
  15 #include <media/v4l2-device.h>
  16 #include <media/v4l2-event.h>
  17 #include <media/v4l2-fwnode.h>
  18
  19 #define OV01A10_LINK_FREQ_400MHZ        400000000ULL
  20 #define OV01A10_SCLK                    40000000LL
  21 #define OV01A10_DATA_LANES              1
  22
  23 #define OV01A10_REG_CHIP_ID             0x300a
  24 #define OV01A10_CHIP_ID                 0x560141
  25
  26 #define OV01A10_REG_MODE_SELECT         0x0100
  27 #define OV01A10_MODE_STANDBY            0x00
  28 #define OV01A10_MODE_STREAMING          0x01
  29
  30 /* pixel array */
  31 #define OV01A10_PIXEL_ARRAY_WIDTH       1296
  32 #define OV01A10_PIXEL_ARRAY_HEIGHT      816
  33 #define OV01A10_ACITVE_WIDTH            1280
  34 #define OV01A10_ACITVE_HEIGHT           800
  35
  36 /* vertical and horizontal timings */
  37 #define OV01A10_REG_VTS                 0x380e
  38 #define OV01A10_VTS_DEF                 0x0380
  39 #define OV01A10_VTS_MIN                 0x0380
  40 #define OV01A10_VTS_MAX                 0xffff
  41 #define OV01A10_HTS_DEF                 1488
  42
  43 /* exposure controls */
  44 #define OV01A10_REG_EXPOSURE            0x3501
  45 #define OV01A10_EXPOSURE_MIN            4
  46 #define OV01A10_EXPOSURE_MAX_MARGIN     8
  47 #define OV01A10_EXPOSURE_STEP           1
  48
  49 /* analog gain controls */
  50 #define OV01A10_REG_ANALOG_GAIN         0x3508
  51 #define OV01A10_ANAL_GAIN_MIN           0x100
  52 #define OV01A10_ANAL_GAIN_MAX           0xffff
  53 #define OV01A10_ANAL_GAIN_STEP          1
  54
  55 /* digital gain controls */
  56 #define OV01A10_REG_DIGITAL_GAIN_B      0x350a
  57 #define OV01A10_REG_DIGITAL_GAIN_GB     0x3510
  58 #define OV01A10_REG_DIGITAL_GAIN_GR     0x3513
  59 #define OV01A10_REG_DIGITAL_GAIN_R      0x3516
  60 #define OV01A10_DGTL_GAIN_MIN           0
  61 #define OV01A10_DGTL_GAIN_MAX           0x3ffff
  62 #define OV01A10_DGTL_GAIN_STEP          1
  63 #define OV01A10_DGTL_GAIN_DEFAULT       1024
  64
  65 /* test pattern control */
  66 #define OV01A10_REG_TEST_PATTERN        0x4503
  67 #define OV01A10_TEST_PATTERN_ENABLE     BIT(7)
  68 #define OV01A10_LINK_FREQ_400MHZ_INDEX  0
  69
  70 /* flip and mirror control */
  71 #define OV01A10_REG_FORMAT1             0x3820
  72 #define OV01A10_VFLIP_MASK              BIT(4)
  73 #define OV01A10_HFLIP_MASK              BIT(3)
  74
  75 /* window offset */
  76 #define OV01A10_REG_X_WIN               0x3811
  77 #define OV01A10_REG_Y_WIN               0x3813
  78
  79 struct ov01a10_reg {
  80         u16 address;
  81         u8 val;
  82 };
  83
  84 struct ov01a10_reg_list {
  85         u32 num_of_regs;
  86         const struct ov01a10_reg *regs;
  87 };
  88
  89 struct ov01a10_link_freq_config {
  90         const struct ov01a10_reg_list reg_list;
  91 };
  92
  93 struct ov01a10_mode {
  94         u32 width;
  95         u32 height;
  96         u32 hts;
  97         u32 vts_def;
  98         u32 vts_min;
  99         u32 link_freq_index;
 100
 101         const struct ov01a10_reg_list reg_list;
 102 };
 103
 104 static const struct ov01a10_reg mipi_data_rate_720mbps[] = {
 105         {0x0103, 0x01},
 106         {0x0302, 0x00},
 107         {0x0303, 0x06},
 108         {0x0304, 0x01},
 109         {0x0305, 0xe0},
 110         {0x0306, 0x00},
 111         {0x0308, 0x01},
 112         {0x0309, 0x00},
 113         {0x030c, 0x01},
 114         {0x0322, 0x01},
 115         {0x0323, 0x06},
 116         {0x0324, 0x01},
 117         {0x0325, 0x68},
 118 };
 119
 120 static const struct ov01a10_reg sensor_1280x800_setting[] = {
 121         {0x3002, 0xa1},
 122         {0x301e, 0xf0},
 123         {0x3022, 0x01},
 124         {0x3501, 0x03},
 125         {0x3502, 0x78},
 126         {0x3504, 0x0c},
 127         {0x3508, 0x01},
 128         {0x3509, 0x00},
 129         {0x3601, 0xc0},
 130         {0x3603, 0x71},
 131         {0x3610, 0x68},
 132         {0x3611, 0x86},
 133         {0x3640, 0x10},
 134         {0x3641, 0x80},
 135         {0x3642, 0xdc},
 136         {0x3646, 0x55},
 137         {0x3647, 0x57},
 138         {0x364b, 0x00},
 139         {0x3653, 0x10},
 140         {0x3655, 0x00},
 141         {0x3656, 0x00},
 142         {0x365f, 0x0f},
 143         {0x3661, 0x45},
 144         {0x3662, 0x24},
 145         {0x3663, 0x11},
 146         {0x3664, 0x07},
 147         {0x3709, 0x34},
 148         {0x370b, 0x6f},
 149         {0x3714, 0x22},
 150         {0x371b, 0x27},
 151         {0x371c, 0x67},
 152         {0x371d, 0xa7},
 153         {0x371e, 0xe7},
 154         {0x3730, 0x81},
 155         {0x3733, 0x10},
 156         {0x3734, 0x40},
 157         {0x3737, 0x04},
 158         {0x3739, 0x1c},
 159         {0x3767, 0x00},
 160         {0x376c, 0x81},
 161         {0x3772, 0x14},
 162         {0x37c2, 0x04},
 163         {0x37d8, 0x03},
 164         {0x37d9, 0x0c},
 165         {0x37e0, 0x00},
 166         {0x37e1, 0x08},
 167         {0x37e2, 0x10},
 168         {0x37e3, 0x04},
 169         {0x37e4, 0x04},
 170         {0x37e5, 0x03},
 171         {0x37e6, 0x04},
 172         {0x3800, 0x00},
 173         {0x3801, 0x00},
 174         {0x3802, 0x00},
 175         {0x3803, 0x00},
 176         {0x3804, 0x05},
 177         {0x3805, 0x0f},
 178         {0x3806, 0x03},
 179         {0x3807, 0x2f},
 180         {0x3808, 0x05},
 181         {0x3809, 0x00},
 182         {0x380a, 0x03},
 183         {0x380b, 0x20},
 184         {0x380c, 0x02},
 185         {0x380d, 0xe8},
 186         {0x380e, 0x03},
 187         {0x380f, 0x80},
 188         {0x3810, 0x00},
 189         {0x3811, 0x08},
 190         {0x3812, 0x00},
 191         {0x3813, 0x08},
 192         {0x3814, 0x01},
 193         {0x3815, 0x01},
 194         {0x3816, 0x01},
 195         {0x3817, 0x01},
 196         {0x3820, 0xa0},
 197         {0x3822, 0x13},
 198         {0x3832, 0x28},
 199         {0x3833, 0x10},
 200         {0x3b00, 0x00},
 201         {0x3c80, 0x00},
 202         {0x3c88, 0x02},
 203         {0x3c8c, 0x07},
 204         {0x3c8d, 0x40},
 205         {0x3cc7, 0x80},
 206         {0x4000, 0xc3},
 207         {0x4001, 0xe0},
 208         {0x4003, 0x40},
 209         {0x4008, 0x02},
 210         {0x4009, 0x19},
 211         {0x400a, 0x01},
 212         {0x400b, 0x6c},
 213         {0x4011, 0x00},
 214         {0x4041, 0x00},
 215         {0x4300, 0xff},
 216         {0x4301, 0x00},
 217         {0x4302, 0x0f},
 218         {0x4503, 0x00},
 219         {0x4601, 0x50},
 220         {0x4800, 0x64},
 221         {0x481f, 0x34},
 222         {0x4825, 0x33},
 223         {0x4837, 0x11},
 224         {0x4881, 0x40},
 225         {0x4883, 0x01},
 226         {0x4890, 0x00},
 227         {0x4901, 0x00},
 228         {0x4902, 0x00},
 229         {0x4b00, 0x2a},
 230         {0x4b0d, 0x00},
 231         {0x450a, 0x04},
 232         {0x450b, 0x00},
 233         {0x5000, 0x65},
 234         {0x5200, 0x18},
 235         {0x5004, 0x00},
 236         {0x5080, 0x40},
 237         {0x0305, 0xf4},
 238         {0x0325, 0xc2},
 239 };
 240
 241 static const char * const ov01a10_test_pattern_menu[] = {
 242         "Disabled",
 243         "Color Bar",
 244         "Top-Bottom Darker Color Bar",
 245         "Right-Left Darker Color Bar",
 246         "Color Bar type 4",
 247 };
 248
 249 static const s64 link_freq_menu_items[] = {
 250         OV01A10_LINK_FREQ_400MHZ,
 251 };
 252
 253 static const struct ov01a10_link_freq_config link_freq_configs[] = {
 254         [OV01A10_LINK_FREQ_400MHZ_INDEX] = {
 255                 .reg_list = {
 256                         .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps),
 257                         .regs = mipi_data_rate_720mbps,
 258                 }
 259         },
 260 };
 261
 262 static const struct ov01a10_mode supported_modes[] = {
 263         {
 264                 .width = OV01A10_ACITVE_WIDTH,
 265                 .height = OV01A10_ACITVE_HEIGHT,
 266                 .hts = OV01A10_HTS_DEF,
 267                 .vts_def = OV01A10_VTS_DEF,
 268                 .vts_min = OV01A10_VTS_MIN,
 269                 .reg_list = {
 270                         .num_of_regs = ARRAY_SIZE(sensor_1280x800_setting),
 271                         .regs = sensor_1280x800_setting,
 272                 },
 273                 .link_freq_index = OV01A10_LINK_FREQ_400MHZ_INDEX,
 274         },
 275 };
 276
 277 struct ov01a10 {
 278         struct v4l2_subdev sd;
 279         struct media_pad pad;
 280         struct v4l2_ctrl_handler ctrl_handler;
 281
 282         /* v4l2 controls */
 283         struct v4l2_ctrl *link_freq;
 284         struct v4l2_ctrl *pixel_rate;
 285         struct v4l2_ctrl *vblank;
 286         struct v4l2_ctrl *hblank;
 287         struct v4l2_ctrl *exposure;
 288
 289         const struct ov01a10_mode *cur_mode;
 290
 291         /* streaming state */
 292         bool streaming;
 293 };
 294
 295 static inline struct ov01a10 *to_ov01a10(struct v4l2_subdev *subdev)
 296 {
 297         return container_of(subdev, struct ov01a10, sd);
 298 }
 299
 300 static int ov01a10_read_reg(struct ov01a10 *ov01a10, u16 reg, u16 len, u32 *val)
 301 {
 302         struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
 303         struct i2c_msg msgs[2];
 304         u8 addr_buf[2];
 305         u8 data_buf[4] = {0};
 306         int ret = 0;
 307
 308         if (len > sizeof(data_buf))
 309                 return -EINVAL;
 310
 311         put_unaligned_be16(reg, addr_buf);
 312         msgs[0].addr = client->addr;
 313         msgs[0].flags = 0;
 314         msgs[0].len = sizeof(addr_buf);
 315         msgs[0].buf = addr_buf;
 316         msgs[1].addr = client->addr;
 317         msgs[1].flags = I2C_M_RD;
 318         msgs[1].len = len;
 319         msgs[1].buf = &data_buf[sizeof(data_buf) - len];
 320
 321         ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
 322
 323         if (ret != ARRAY_SIZE(msgs))
 324                 return ret < 0 ? ret : -EIO;
 325
 326         *val = get_unaligned_be32(data_buf);
 327
 328         return 0;
 329 }
 330
 331 static int ov01a10_write_reg(struct ov01a10 *ov01a10, u16 reg, u16 len, u32 val)
 332 {
 333         struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
 334         u8 buf[6];
 335         int ret = 0;
 336
 337         if (len > 4)
 338                 return -EINVAL;
 339
 340         put_unaligned_be16(reg, buf);
 341         put_unaligned_be32(val << 8 * (4 - len), buf + 2);
 342
 343         ret = i2c_master_send(client, buf, len + 2);
 344         if (ret != len + 2)
 345                 return ret < 0 ? ret : -EIO;
 346
 347         return 0;
 348 }
 349
 350 static int ov01a10_write_reg_list(struct ov01a10 *ov01a10,
 351                                   const struct ov01a10_reg_list *r_list)
 352 {
 353         struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
 354         unsigned int i;
 355         int ret = 0;
 356
 357         for (i = 0; i < r_list->num_of_regs; i++) {
 358                 ret = ov01a10_write_reg(ov01a10, r_list->regs[i].address, 1,
 359                                         r_list->regs[i].val);
 360                 if (ret) {
 361                         dev_err_ratelimited(&client->dev,
 362                                             "write reg 0x%4.4x err = %d\n",
 363                                             r_list->regs[i].address, ret);
 364                         return ret;
 365                 }
 366         }
 367
 368         return 0;
 369 }
 370
 371 static int ov01a10_update_digital_gain(struct ov01a10 *ov01a10, u32 d_gain)
 372 {
 373         struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
 374         u32 real = d_gain << 6;
 375         int ret = 0;
 376
 377         ret = ov01a10_write_reg(ov01a10, OV01A10_REG_DIGITAL_GAIN_B, 3, real);
 378         if (ret) {
 379                 dev_err(&client->dev, "failed to set DIGITAL_GAIN_B\n");
 380                 return ret;
 381         }
 382
 383         ret = ov01a10_write_reg(ov01a10, OV01A10_REG_DIGITAL_GAIN_GB, 3, real);
 384         if (ret) {
 385                 dev_err(&client->dev, "failed to set DIGITAL_GAIN_GB\n");
 386                 return ret;
 387         }
 388
 389         ret = ov01a10_write_reg(ov01a10, OV01A10_REG_DIGITAL_GAIN_GR, 3, real);
 390         if (ret) {
 391                 dev_err(&client->dev, "failed to set DIGITAL_GAIN_GR\n");
 392                 return ret;
 393         }
 394
 395         ret = ov01a10_write_reg(ov01a10, OV01A10_REG_DIGITAL_GAIN_R, 3, real);
 396         if (ret)
 397                 dev_err(&client->dev, "failed to set DIGITAL_GAIN_R\n");
 398
 399         return ret;
 400 }
 401
 402 static int ov01a10_test_pattern(struct ov01a10 *ov01a10, u32 pattern)
 403 {
 404         if (!pattern)
 405                 return 0;
 406
 407         pattern = (pattern - 1) | OV01A10_TEST_PATTERN_ENABLE;
 408
 409         return ov01a10_write_reg(ov01a10, OV01A10_REG_TEST_PATTERN, 1, pattern);
 410 }
 411
 412 /* for vflip and hflip, use 0x9 as window offset to keep the bayer */
 413 static int ov01a10_set_hflip(struct ov01a10 *ov01a10, u32 hflip)
 414 {
 415         int ret;
 416         u32 val, offset;
 417
 418         offset = hflip ? 0x9 : 0x8;
 419         ret = ov01a10_write_reg(ov01a10, OV01A10_REG_X_WIN, 1, offset);
 420         if (ret)
 421                 return ret;
 422
 423         ret = ov01a10_read_reg(ov01a10, OV01A10_REG_FORMAT1, 1, &val);
 424         if (ret)
 425                 return ret;
 426
 427         val = hflip ? val | FIELD_PREP(OV01A10_HFLIP_MASK, 0x1) :
 428                 val & ~OV01A10_HFLIP_MASK;
 429
 430         return ov01a10_write_reg(ov01a10, OV01A10_REG_FORMAT1, 1, val);
 431 }
 432
 433 static int ov01a10_set_vflip(struct ov01a10 *ov01a10, u32 vflip)
 434 {
 435         int ret;
 436         u32 val, offset;
 437
 438         offset = vflip ? 0x9 : 0x8;
 439         ret = ov01a10_write_reg(ov01a10, OV01A10_REG_Y_WIN, 1, offset);
 440         if (ret)
 441                 return ret;
 442
 443         ret = ov01a10_read_reg(ov01a10, OV01A10_REG_FORMAT1, 1, &val);
 444         if (ret)
 445                 return ret;
 446
 447         val = vflip ? val | FIELD_PREP(OV01A10_VFLIP_MASK, 0x1) :
 448                 val & ~OV01A10_VFLIP_MASK;
 449
 450         return ov01a10_write_reg(ov01a10, OV01A10_REG_FORMAT1, 1, val);
 451 }
 452
 453 static int ov01a10_set_ctrl(struct v4l2_ctrl *ctrl)
 454 {
 455         struct ov01a10 *ov01a10 = container_of(ctrl->handler,
 456                                                struct ov01a10, ctrl_handler);
 457         struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
 458         s64 exposure_max;
 459         int ret = 0;
 460
 461         if (ctrl->id == V4L2_CID_VBLANK) {
 462                 exposure_max = ov01a10->cur_mode->height + ctrl->val -
 463                         OV01A10_EXPOSURE_MAX_MARGIN;
 464                 __v4l2_ctrl_modify_range(ov01a10->exposure,
 465                                          ov01a10->exposure->minimum,
 466                                          exposure_max, ov01a10->exposure->step,
 467                                          exposure_max);
 468         }
 469
 470         if (!pm_runtime_get_if_in_use(&client->dev))
 471                 return 0;
 472
 473         switch (ctrl->id) {
 474         case V4L2_CID_ANALOGUE_GAIN:
 475                 ret = ov01a10_write_reg(ov01a10, OV01A10_REG_ANALOG_GAIN, 2,
 476                                         ctrl->val);
 477                 break;
 478
 479         case V4L2_CID_DIGITAL_GAIN:
 480                 ret = ov01a10_update_digital_gain(ov01a10, ctrl->val);
 481                 break;
 482
 483         case V4L2_CID_EXPOSURE:
 484                 ret = ov01a10_write_reg(ov01a10, OV01A10_REG_EXPOSURE, 2,
 485                                         ctrl->val);
 486                 break;
 487
 488         case V4L2_CID_VBLANK:
 489                 ret = ov01a10_write_reg(ov01a10, OV01A10_REG_VTS, 2,
 490                                         ov01a10->cur_mode->height + ctrl->val);
 491                 break;
 492
 493         case V4L2_CID_TEST_PATTERN:
 494                 ret = ov01a10_test_pattern(ov01a10, ctrl->val);
 495                 break;
 496
 497         case V4L2_CID_HFLIP:
 498                 ov01a10_set_hflip(ov01a10, ctrl->val);
 499                 break;
 500
 501         case V4L2_CID_VFLIP:
 502                 ov01a10_set_vflip(ov01a10, ctrl->val);
 503                 break;
 504
 505         default:
 506                 ret = -EINVAL;
 507                 break;
 508         }
 509
 510         pm_runtime_put(&client->dev);
 511
 512         return ret;
 513 }
 514
 515 static const struct v4l2_ctrl_ops ov01a10_ctrl_ops = {
 516         .s_ctrl = ov01a10_set_ctrl,
 517 };
 518
 519 static int ov01a10_init_controls(struct ov01a10 *ov01a10)
 520 {
 521         struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
 522         struct v4l2_fwnode_device_properties props;
 523         u32 vblank_min, vblank_max, vblank_default;
 524         struct v4l2_ctrl_handler *ctrl_hdlr;
 525         const struct ov01a10_mode *cur_mode;
 526         s64 exposure_max, h_blank;
 527         int ret = 0;
 528         int size;
 529
 530         ret = v4l2_fwnode_device_parse(&client->dev, &props);
 531         if (ret)
 532                 return ret;
 533
 534         ctrl_hdlr = &ov01a10->ctrl_handler;
 535         ret = v4l2_ctrl_handler_init(ctrl_hdlr, 12);
 536         if (ret)
 537                 return ret;
 538
 539         cur_mode = ov01a10->cur_mode;
 540         size = ARRAY_SIZE(link_freq_menu_items);
 541
 542         ov01a10->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
 543                                                     &ov01a10_ctrl_ops,
 544                                                     V4L2_CID_LINK_FREQ,
 545                                                     size - 1, 0,
 546                                                     link_freq_menu_items);
 547         if (ov01a10->link_freq)
 548                 ov01a10->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
 549
 550         ov01a10->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops,
 551                                                 V4L2_CID_PIXEL_RATE, 0,
 552                                                 OV01A10_SCLK, 1, OV01A10_SCLK);
 553
 554         vblank_min = cur_mode->vts_min - cur_mode->height;
 555         vblank_max = OV01A10_VTS_MAX - cur_mode->height;
 556         vblank_default = cur_mode->vts_def - cur_mode->height;
 557         ov01a10->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops,
 558                                             V4L2_CID_VBLANK, vblank_min,
 559                                             vblank_max, 1, vblank_default);
 560
 561         h_blank = cur_mode->hts - cur_mode->width;
 562         ov01a10->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops,
 563                                             V4L2_CID_HBLANK, h_blank, h_blank,
 564                                             1, h_blank);
 565         if (ov01a10->hblank)
 566                 ov01a10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
 567
 568         v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
 569                           OV01A10_ANAL_GAIN_MIN, OV01A10_ANAL_GAIN_MAX,
 570                           OV01A10_ANAL_GAIN_STEP, OV01A10_ANAL_GAIN_MIN);
 571         v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
 572                           OV01A10_DGTL_GAIN_MIN, OV01A10_DGTL_GAIN_MAX,
 573                           OV01A10_DGTL_GAIN_STEP, OV01A10_DGTL_GAIN_DEFAULT);
 574
 575         exposure_max = cur_mode->vts_def - OV01A10_EXPOSURE_MAX_MARGIN;
 576         ov01a10->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops,
 577                                               V4L2_CID_EXPOSURE,
 578                                               OV01A10_EXPOSURE_MIN,
 579                                               exposure_max,
 580                                               OV01A10_EXPOSURE_STEP,
 581                                               exposure_max);
 582
 583         v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov01a10_ctrl_ops,
 584                                      V4L2_CID_TEST_PATTERN,
 585                                      ARRAY_SIZE(ov01a10_test_pattern_menu) - 1,
 586                                      0, 0, ov01a10_test_pattern_menu);
 587
 588         v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops, V4L2_CID_HFLIP,
 589                           0, 1, 1, 0);
 590         v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops, V4L2_CID_VFLIP,
 591                           0, 1, 1, 0);
 592
 593         ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov01a10_ctrl_ops,
 594                                               &props);
 595         if (ret)
 596                 goto fail;
 597
 598         if (ctrl_hdlr->error) {
 599                 ret = ctrl_hdlr->error;
 600                 goto fail;
 601         }
 602
 603         ov01a10->sd.ctrl_handler = ctrl_hdlr;
 604
 605         return 0;
 606 fail:
 607         v4l2_ctrl_handler_free(ctrl_hdlr);
 608
 609         return ret;
 610 }
 611
 612 static void ov01a10_update_pad_format(const struct ov01a10_mode *mode,
 613                                       struct v4l2_mbus_framefmt *fmt)
 614 {
 615         fmt->width = mode->width;
 616         fmt->height = mode->height;
 617         fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
 618         fmt->field = V4L2_FIELD_NONE;
 619         fmt->colorspace = V4L2_COLORSPACE_RAW;
 620 }
 621
 622 static int ov01a10_start_streaming(struct ov01a10 *ov01a10)
 623 {
 624         struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
 625         const struct ov01a10_reg_list *reg_list;
 626         int link_freq_index;
 627         int ret = 0;
 628
 629         link_freq_index = ov01a10->cur_mode->link_freq_index;
 630         reg_list = &link_freq_configs[link_freq_index].reg_list;
 631         ret = ov01a10_write_reg_list(ov01a10, reg_list);
 632         if (ret) {
 633                 dev_err(&client->dev, "failed to set plls\n");
 634                 return ret;
 635         }
 636
 637         reg_list = &ov01a10->cur_mode->reg_list;
 638         ret = ov01a10_write_reg_list(ov01a10, reg_list);
 639         if (ret) {
 640                 dev_err(&client->dev, "failed to set mode\n");
 641                 return ret;
 642         }
 643
 644         ret = __v4l2_ctrl_handler_setup(ov01a10->sd.ctrl_handler);
 645         if (ret)
 646                 return ret;
 647
 648         ret = ov01a10_write_reg(ov01a10, OV01A10_REG_MODE_SELECT, 1,
 649                                 OV01A10_MODE_STREAMING);
 650         if (ret)
 651                 dev_err(&client->dev, "failed to start streaming\n");
 652
 653         return ret;
 654 }
 655
 656 static void ov01a10_stop_streaming(struct ov01a10 *ov01a10)
 657 {
 658         struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
 659         int ret = 0;
 660
 661         ret = ov01a10_write_reg(ov01a10, OV01A10_REG_MODE_SELECT, 1,
 662                                 OV01A10_MODE_STANDBY);
 663         if (ret)
 664                 dev_err(&client->dev, "failed to stop streaming\n");
 665 }
 666
 667 static int ov01a10_set_stream(struct v4l2_subdev *sd, int enable)
 668 {
 669         struct ov01a10 *ov01a10 = to_ov01a10(sd);
 670         struct i2c_client *client = v4l2_get_subdevdata(sd);
 671         struct v4l2_subdev_state *state;
 672         int ret = 0;
 673
 674         state = v4l2_subdev_lock_and_get_active_state(sd);
 675         if (ov01a10->streaming == enable)
 676                 goto unlock;
 677
 678         if (enable) {
 679                 ret = pm_runtime_resume_and_get(&client->dev);
 680                 if (ret < 0)
 681                         goto unlock;
 682
 683                 ret = ov01a10_start_streaming(ov01a10);
 684                 if (ret) {
 685                         pm_runtime_put(&client->dev);
 686                         goto unlock;
 687                 }
 688
 689                 goto done;
 690         }
 691
 692         ov01a10_stop_streaming(ov01a10);
 693         pm_runtime_put(&client->dev);
 694 done:
 695         ov01a10->streaming = enable;
 696 unlock:
 697         v4l2_subdev_unlock_state(state);
 698
 699         return ret;
 700 }
 701
 702 static int __maybe_unused ov01a10_suspend(struct device *dev)
 703 {
 704         struct i2c_client *client = to_i2c_client(dev);
 705         struct v4l2_subdev *sd = i2c_get_clientdata(client);
 706         struct ov01a10 *ov01a10 = to_ov01a10(sd);
 707         struct v4l2_subdev_state *state;
 708
 709         state = v4l2_subdev_lock_and_get_active_state(sd);
 710         if (ov01a10->streaming)
 711                 ov01a10_stop_streaming(ov01a10);
 712
 713         v4l2_subdev_unlock_state(state);
 714
 715         return 0;
 716 }
 717
 718 static int __maybe_unused ov01a10_resume(struct device *dev)
 719 {
 720         struct i2c_client *client = to_i2c_client(dev);
 721         struct v4l2_subdev *sd = i2c_get_clientdata(client);
 722         struct ov01a10 *ov01a10 = to_ov01a10(sd);
 723         struct v4l2_subdev_state *state;
 724         int ret = 0;
 725
 726         state = v4l2_subdev_lock_and_get_active_state(sd);
 727         if (!ov01a10->streaming)
 728                 goto exit;
 729
 730         ret = ov01a10_start_streaming(ov01a10);
 731         if (ret) {
 732                 ov01a10->streaming = false;
 733                 ov01a10_stop_streaming(ov01a10);
 734         }
 735
 736 exit:
 737         v4l2_subdev_unlock_state(state);
 738
 739         return ret;
 740 }
 741
 742 static int ov01a10_set_format(struct v4l2_subdev *sd,
 743                               struct v4l2_subdev_state *sd_state,
 744                               struct v4l2_subdev_format *fmt)
 745 {
 746         struct ov01a10 *ov01a10 = to_ov01a10(sd);
 747         const struct ov01a10_mode *mode;
 748         struct v4l2_mbus_framefmt *format;
 749         s32 vblank_def, h_blank;
 750
 751         mode = v4l2_find_nearest_size(supported_modes,
 752                                       ARRAY_SIZE(supported_modes), width,
 753                                       height, fmt->format.width,
 754                                       fmt->format.height);
 755
 756         ov01a10_update_pad_format(mode, &fmt->format);
 757
 758         if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
 759                 ov01a10->cur_mode = mode;
 760                 __v4l2_ctrl_s_ctrl(ov01a10->link_freq, mode->link_freq_index);
 761                 __v4l2_ctrl_s_ctrl_int64(ov01a10->pixel_rate, OV01A10_SCLK);
 762
 763                 vblank_def = mode->vts_def - mode->height;
 764                 __v4l2_ctrl_modify_range(ov01a10->vblank,
 765                                          mode->vts_min - mode->height,
 766                                          OV01A10_VTS_MAX - mode->height, 1,
 767                                          vblank_def);
 768                 __v4l2_ctrl_s_ctrl(ov01a10->vblank, vblank_def);
 769                 h_blank = mode->hts - mode->width;
 770                 __v4l2_ctrl_modify_range(ov01a10->hblank, h_blank, h_blank, 1,
 771                                          h_blank);
 772         }
 773
 774         format = v4l2_subdev_get_pad_format(sd, sd_state, fmt->stream);
 775         *format = fmt->format;
 776
 777         return 0;
 778 }
 779
 780 static int ov01a10_init_cfg(struct v4l2_subdev *sd,
 781                             struct v4l2_subdev_state *state)
 782 {
 783         struct v4l2_subdev_format fmt = {
 784                 .which = V4L2_SUBDEV_FORMAT_TRY,
 785                 .format = {
 786                         .width = OV01A10_ACITVE_WIDTH,
 787                         .height = OV01A10_ACITVE_HEIGHT,
 788                 },
 789         };
 790
 791         ov01a10_set_format(sd, state, &fmt);
 792
 793         return 0;
 794 }
 795
 796 static int ov01a10_enum_mbus_code(struct v4l2_subdev *sd,
 797                                   struct v4l2_subdev_state *sd_state,
 798                                   struct v4l2_subdev_mbus_code_enum *code)
 799 {
 800         if (code->index > 0)
 801                 return -EINVAL;
 802
 803         code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
 804
 805         return 0;
 806 }
 807
 808 static int ov01a10_enum_frame_size(struct v4l2_subdev *sd,
 809                                    struct v4l2_subdev_state *sd_state,
 810                                    struct v4l2_subdev_frame_size_enum *fse)
 811 {
 812         if (fse->index >= ARRAY_SIZE(supported_modes) ||
 813             fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
 814                 return -EINVAL;
 815
 816         fse->min_width = supported_modes[fse->index].width;
 817         fse->max_width = fse->min_width;
 818         fse->min_height = supported_modes[fse->index].height;
 819         fse->max_height = fse->min_height;
 820
 821         return 0;
 822 }
 823
 824 static int ov01a10_get_selection(struct v4l2_subdev *sd,
 825                                  struct v4l2_subdev_state *state,
 826                                  struct v4l2_subdev_selection *sel)
 827 {
 828         if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
 829                 return -EINVAL;
 830
 831         switch (sel->target) {
 832         case V4L2_SEL_TGT_NATIVE_SIZE:
 833         case V4L2_SEL_TGT_CROP_BOUNDS:
 834                 sel->r.top = 0;
 835                 sel->r.left = 0;
 836                 sel->r.width = OV01A10_PIXEL_ARRAY_WIDTH;
 837                 sel->r.height = OV01A10_PIXEL_ARRAY_HEIGHT;
 838                 return 0;
 839         case V4L2_SEL_TGT_CROP:
 840         case V4L2_SEL_TGT_CROP_DEFAULT:
 841                 sel->r.top = (OV01A10_PIXEL_ARRAY_HEIGHT -
 842                               OV01A10_ACITVE_HEIGHT) / 2;
 843                 sel->r.left = (OV01A10_PIXEL_ARRAY_WIDTH -
 844                                OV01A10_ACITVE_WIDTH) / 2;
 845                 sel->r.width = OV01A10_ACITVE_WIDTH;
 846                 sel->r.height = OV01A10_ACITVE_HEIGHT;
 847                 return 0;
 848         }
 849
 850         return -EINVAL;
 851 }
 852
 853 static const struct v4l2_subdev_core_ops ov01a10_core_ops = {
 854         .log_status = v4l2_ctrl_subdev_log_status,
 855         .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
 856         .unsubscribe_event = v4l2_event_subdev_unsubscribe,
 857 };
 858
 859 static const struct v4l2_subdev_video_ops ov01a10_video_ops = {
 860         .s_stream = ov01a10_set_stream,
 861 };
 862
 863 static const struct v4l2_subdev_pad_ops ov01a10_pad_ops = {
 864         .init_cfg = ov01a10_init_cfg,
 865         .set_fmt = ov01a10_set_format,
 866         .get_fmt = v4l2_subdev_get_fmt,
 867         .get_selection = ov01a10_get_selection,
 868         .enum_mbus_code = ov01a10_enum_mbus_code,
 869         .enum_frame_size = ov01a10_enum_frame_size,
 870 };
 871
 872 static const struct v4l2_subdev_ops ov01a10_subdev_ops = {
 873         .core = &ov01a10_core_ops,
 874         .video = &ov01a10_video_ops,
 875         .pad = &ov01a10_pad_ops,
 876 };
 877
 878 static const struct media_entity_operations ov01a10_subdev_entity_ops = {
 879         .link_validate = v4l2_subdev_link_validate,
 880 };
 881
 882 static int ov01a10_identify_module(struct ov01a10 *ov01a10)
 883 {
 884         struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
 885         int ret;
 886         u32 val;
 887
 888         ret = ov01a10_read_reg(ov01a10, OV01A10_REG_CHIP_ID, 3, &val);
 889         if (ret)
 890                 return ret;
 891
 892         if (val != OV01A10_CHIP_ID) {
 893                 dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
 894                         OV01A10_CHIP_ID, val);
 895                 return -EIO;
 896         }
 897
 898         return 0;
 899 }
 900
 901 static void ov01a10_remove(struct i2c_client *client)
 902 {
 903         struct v4l2_subdev *sd = i2c_get_clientdata(client);
 904
 905         v4l2_async_unregister_subdev(sd);
 906         media_entity_cleanup(&sd->entity);
 907         v4l2_ctrl_handler_free(sd->ctrl_handler);
 908
 909         pm_runtime_disable(&client->dev);
 910 }
 911
 912 static int ov01a10_probe(struct i2c_client *client)
 913 {
 914         struct device *dev = &client->dev;
 915         struct ov01a10 *ov01a10;
 916         int ret = 0;
 917
 918         ov01a10 = devm_kzalloc(dev, sizeof(*ov01a10), GFP_KERNEL);
 919         if (!ov01a10)
 920                 return -ENOMEM;
 921
 922         v4l2_i2c_subdev_init(&ov01a10->sd, client, &ov01a10_subdev_ops);
 923
 924         ret = ov01a10_identify_module(ov01a10);
 925         if (ret)
 926                 return dev_err_probe(dev, ret,
 927                                      "failed to find sensor\n");
 928
 929         ov01a10->cur_mode = &supported_modes[0];
 930
 931         ret = ov01a10_init_controls(ov01a10);
 932         if (ret) {
 933                 dev_err(dev, "failed to init controls: %d\n", ret);
 934                 return ret;
 935         }
 936
 937         ov01a10->sd.state_lock = ov01a10->ctrl_handler.lock;
 938         ov01a10->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
 939                 V4L2_SUBDEV_FL_HAS_EVENTS;
 940         ov01a10->sd.entity.ops = &ov01a10_subdev_entity_ops;
 941         ov01a10->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
 942         ov01a10->pad.flags = MEDIA_PAD_FL_SOURCE;
 943
 944         ret = media_entity_pads_init(&ov01a10->sd.entity, 1, &ov01a10->pad);
 945         if (ret) {
 946                 dev_err(dev, "Failed to init entity pads: %d\n", ret);
 947                 goto err_handler_free;
 948         }
 949
 950         ret = v4l2_subdev_init_finalize(&ov01a10->sd);
 951         if (ret) {
 952                 dev_err(dev, "Failed to allocate subdev state: %d\n", ret);
 953                 goto err_media_entity_cleanup;
 954         }
 955
 956         ret = v4l2_async_register_subdev_sensor(&ov01a10->sd);
 957         if (ret < 0) {
 958                 dev_err(dev, "Failed to register subdev: %d\n", ret);
 959                 goto err_media_entity_cleanup;
 960         }
 961
 962         pm_runtime_enable(dev);
 963         pm_runtime_idle(dev);
 964
 965         return 0;
 966
 967 err_media_entity_cleanup:
 968         media_entity_cleanup(&ov01a10->sd.entity);
 969
 970 err_handler_free:
 971         v4l2_ctrl_handler_free(ov01a10->sd.ctrl_handler);
 972
 973         return ret;
 974 }
 975
 976 static const struct dev_pm_ops ov01a10_pm_ops = {
 977         SET_SYSTEM_SLEEP_PM_OPS(ov01a10_suspend, ov01a10_resume)
 978 };
 979
 980 #ifdef CONFIG_ACPI
 981 static const struct acpi_device_id ov01a10_acpi_ids[] = {
 982         { "OVTI01A0" },
 983         { }
 984 };
 985
 986 MODULE_DEVICE_TABLE(acpi, ov01a10_acpi_ids);
 987 #endif
 988
 989 static struct i2c_driver ov01a10_i2c_driver = {
 990         .driver = {
 991                 .name = "ov01a10",
 992                 .pm = &ov01a10_pm_ops,
 993                 .acpi_match_table = ACPI_PTR(ov01a10_acpi_ids),
 994         },
 995         .probe = ov01a10_probe,
 996         .remove = ov01a10_remove,
 997 };
 998
 999 module_i2c_driver(ov01a10_i2c_driver);
1000
1001 MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>");
1002 MODULE_AUTHOR("Wang Yating <yating.wang@intel.com>");
1003 MODULE_DESCRIPTION("OmniVision OV01A10 sensor driver");
1004 MODULE_LICENSE("GPL");