1 // SPDX-License-Identifier: GPL-2.0
3 * Sony IMX462 / IMX290 / IMX327 CMOS Image Sensor Driver
5 * The IMX462, IMX290,and IMX327 are very similar 1920x1080 1/2.8 CMOS image
7 * IMX327 can support up to 60fps with 10 or 12bit readout.
8 * IMX290 adds support for 120fps, but only 10bit and when connected over 4
10 * IMX462 adds support for 120fps in both 10 and 12bit readout modes.
12 * The modules don't appear to have a mechanism to identify whether the mono or
13 * colour variant is connected, therefore it is done via compatible string.
15 * Copyright (C) 2019 FRAMOS GmbH.
17 * Copyright (C) 2019 Linaro Ltd.
18 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/gpio/consumer.h>
24 #include <linux/i2c.h>
25 #include <linux/module.h>
26 #include <linux/of_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/regmap.h>
29 #include <linux/regulator/consumer.h>
30 #include <media/media-entity.h>
31 #include <media/v4l2-ctrls.h>
32 #include <media/v4l2-device.h>
33 #include <media/v4l2-fwnode.h>
34 #include <media/v4l2-subdev.h>
36 enum imx290_clk_index {
41 #define IMX290_STANDBY 0x3000
42 #define IMX290_REGHOLD 0x3001
43 #define IMX290_XMSTA 0x3002
44 #define IMX290_FLIP_WINMODE 0x3007
45 #define IMX290_FR_FDG_SEL 0x3009
46 #define IMX290_BLKLEVEL_LOW 0x300a
47 #define IMX290_BLKLEVEL_HIGH 0x300b
48 #define IMX290_GAIN 0x3014
49 #define IMX290_VMAX_LOW 0x3018
50 #define IMX290_VMAX_MAX 0x3fff
51 #define IMX290_HMAX_LOW 0x301c
52 #define IMX290_HMAX_HIGH 0x301d
53 #define IMX290_HMAX_MIN 2200 /* Min of 2200 pixels = 60fps */
54 #define IMX290_HMAX_MAX 0xffff
56 #define IMX290_EXPOSURE_MIN 1
57 #define IMX290_EXPOSURE_STEP 1
58 #define IMX290_EXPOSURE_LOW 0x3020
59 #define IMX290_PGCTRL 0x308c
60 #define IMX290_PHY_LANE_NUM 0x3407
61 #define IMX290_CSI_LANE_MODE 0x3443
63 #define IMX290_PGCTRL_REGEN BIT(0)
64 #define IMX290_PGCTRL_THRU BIT(1)
65 #define IMX290_PGCTRL_MODE(n) ((n) << 4)
67 #define IMX290_NATIVE_WIDTH 1945U
68 #define IMX290_NATIVE_HEIGHT 1109U
69 #define IMX290_PIXEL_ARRAY_LEFT 4U
70 #define IMX290_PIXEL_ARRAY_TOP 12U
71 #define IMX290_PIXEL_ARRAY_WIDTH 1937U
72 #define IMX290_PIXEL_ARRAY_HEIGHT 1097U
74 static const char * const imx290_supply_name[] = {
80 #define IMX290_NUM_SUPPLIES ARRAY_SIZE(imx290_supply_name)
82 struct imx290_regval {
93 struct v4l2_rect crop;
95 const struct imx290_regval *mode_data;
97 const struct imx290_regval *lane_data;
101 /* Clock setup can vary. Index as enum imx290_clk_index */
102 const struct imx290_regval *clk_data[2];
110 struct regmap *regmap;
115 const struct imx290_pixfmt *formats;
117 struct v4l2_subdev sd;
118 struct media_pad pad;
119 struct v4l2_mbus_framefmt current_format;
120 const struct imx290_mode *current_mode;
122 struct regulator_bulk_data supplies[IMX290_NUM_SUPPLIES];
123 struct gpio_desc *rst_gpio;
125 struct v4l2_ctrl_handler ctrls;
126 struct v4l2_ctrl *link_freq;
127 struct v4l2_ctrl *pixel_rate;
128 struct v4l2_ctrl *hblank;
129 struct v4l2_ctrl *vblank;
130 struct v4l2_ctrl *hflip;
131 struct v4l2_ctrl *vflip;
132 struct v4l2_ctrl *exposure;
137 struct imx290_pixfmt {
142 #define IMX290_NUM_FORMATS 2
144 static const struct imx290_pixfmt imx290_colour_formats[IMX290_NUM_FORMATS] = {
145 { MEDIA_BUS_FMT_SRGGB10_1X10, 10 },
146 { MEDIA_BUS_FMT_SRGGB12_1X12, 12 },
149 static const struct imx290_pixfmt imx290_mono_formats[IMX290_NUM_FORMATS] = {
150 { MEDIA_BUS_FMT_Y10_1X10, 10 },
151 { MEDIA_BUS_FMT_Y12_1X12, 12 },
154 static const struct regmap_config imx290_regmap_config = {
157 .cache_type = REGCACHE_RBTREE,
160 static const char * const imx290_test_pattern_menu[] = {
162 "Sequence Pattern 1",
163 "Horizontal Color-bar Chart",
164 "Vertical Color-bar Chart",
165 "Sequence Pattern 2",
166 "Gradation Pattern 1",
167 "Gradation Pattern 2",
168 "000/555h Toggle Pattern",
171 static const struct imx290_regval imx290_global_init_settings[] = {
227 static const struct imx290_regval imx290_37_125mhz_clock_1080p[] = {
239 static const struct imx290_regval imx290_74_250mhz_clock_1080p[] = {
251 static const struct imx290_regval imx290_1080p_common_settings[] = {
253 { IMX290_FR_FDG_SEL, 0x01 },
265 static const struct imx290_regval imx290_1080p_2lane_settings[] = {
267 /* data rate settings */
268 { IMX290_PHY_LANE_NUM, 0x01 },
269 { IMX290_CSI_LANE_MODE, 0x01 },
288 static const struct imx290_regval imx290_1080p_4lane_settings[] = {
290 /* data rate settings */
291 { IMX290_PHY_LANE_NUM, 0x03 },
292 { IMX290_CSI_LANE_MODE, 0x03 },
311 static const struct imx290_regval imx290_37_125mhz_clock_720p[] = {
323 static const struct imx290_regval imx290_74_250mhz_clock_720p[] = {
335 static const struct imx290_regval imx290_720p_common_settings[] = {
337 { IMX290_FR_FDG_SEL, 0x01 },
349 static const struct imx290_regval imx290_720p_2lane_settings[] = {
351 { IMX290_PHY_LANE_NUM, 0x01 },
352 { IMX290_CSI_LANE_MODE, 0x01 },
353 /* data rate settings */
372 static const struct imx290_regval imx290_720p_4lane_settings[] = {
374 { IMX290_PHY_LANE_NUM, 0x03 },
375 { IMX290_CSI_LANE_MODE, 0x03 },
376 /* data rate settings */
395 static const struct imx290_regval imx290_10bit_settings[] = {
407 static const struct imx290_regval imx290_12bit_settings[] = {
419 /* supported link frequencies */
420 #define FREQ_INDEX_1080P 0
421 #define FREQ_INDEX_720P 1
422 static const s64 imx290_link_freq_2lanes[] = {
423 [FREQ_INDEX_1080P] = 445500000,
424 [FREQ_INDEX_720P] = 297000000,
426 static const s64 imx290_link_freq_4lanes[] = {
427 [FREQ_INDEX_1080P] = 222750000,
428 [FREQ_INDEX_720P] = 148500000,
432 * In this function and in the similar ones below We rely on imx290_probe()
433 * to ensure that nlanes is either 2 or 4.
435 static inline const s64 *imx290_link_freqs_ptr(const struct imx290 *imx290)
437 if (imx290->nlanes == 2)
438 return imx290_link_freq_2lanes;
440 return imx290_link_freq_4lanes;
443 static inline int imx290_link_freqs_num(const struct imx290 *imx290)
445 if (imx290->nlanes == 2)
446 return ARRAY_SIZE(imx290_link_freq_2lanes);
448 return ARRAY_SIZE(imx290_link_freq_4lanes);
452 static const struct imx290_mode imx290_modes_2lanes[] = {
458 .link_freq_index = FREQ_INDEX_1080P,
465 .mode_data = imx290_1080p_common_settings,
466 .mode_data_size = ARRAY_SIZE(imx290_1080p_common_settings),
467 .lane_data = imx290_1080p_2lane_settings,
468 .lane_data_size = ARRAY_SIZE(imx290_1080p_2lane_settings),
470 [CLK_37_125] = imx290_37_125mhz_clock_1080p,
471 [CLK_74_25] = imx290_74_250mhz_clock_1080p,
473 .clk_size = ARRAY_SIZE(imx290_37_125mhz_clock_1080p),
480 .link_freq_index = FREQ_INDEX_720P,
487 .mode_data = imx290_720p_common_settings,
488 .mode_data_size = ARRAY_SIZE(imx290_720p_common_settings),
489 .lane_data = imx290_720p_2lane_settings,
490 .lane_data_size = ARRAY_SIZE(imx290_720p_2lane_settings),
492 [CLK_37_125] = imx290_37_125mhz_clock_720p,
493 [CLK_74_25] = imx290_74_250mhz_clock_720p,
495 .clk_size = ARRAY_SIZE(imx290_37_125mhz_clock_720p),
499 static const struct imx290_mode imx290_modes_4lanes[] = {
505 .link_freq_index = FREQ_INDEX_1080P,
512 .mode_data = imx290_1080p_common_settings,
513 .mode_data_size = ARRAY_SIZE(imx290_1080p_common_settings),
514 .lane_data = imx290_1080p_4lane_settings,
515 .lane_data_size = ARRAY_SIZE(imx290_1080p_4lane_settings),
517 [CLK_37_125] = imx290_37_125mhz_clock_1080p,
518 [CLK_74_25] = imx290_74_250mhz_clock_1080p,
520 .clk_size = ARRAY_SIZE(imx290_37_125mhz_clock_1080p),
527 .link_freq_index = FREQ_INDEX_720P,
534 .mode_data = imx290_720p_common_settings,
535 .mode_data_size = ARRAY_SIZE(imx290_720p_common_settings),
536 .lane_data = imx290_720p_4lane_settings,
537 .lane_data_size = ARRAY_SIZE(imx290_720p_4lane_settings),
539 [CLK_37_125] = imx290_37_125mhz_clock_720p,
540 [CLK_74_25] = imx290_74_250mhz_clock_720p,
542 .clk_size = ARRAY_SIZE(imx290_37_125mhz_clock_720p),
546 static inline const struct imx290_mode *imx290_modes_ptr(const struct imx290 *imx290)
548 if (imx290->nlanes == 2)
549 return imx290_modes_2lanes;
551 return imx290_modes_4lanes;
554 static inline int imx290_modes_num(const struct imx290 *imx290)
556 if (imx290->nlanes == 2)
557 return ARRAY_SIZE(imx290_modes_2lanes);
559 return ARRAY_SIZE(imx290_modes_4lanes);
562 static inline struct imx290 *to_imx290(struct v4l2_subdev *_sd)
564 return container_of(_sd, struct imx290, sd);
567 static inline int imx290_read_reg(struct imx290 *imx290, u16 addr, u8 *value)
572 ret = regmap_read(imx290->regmap, addr, ®val);
574 dev_err(imx290->dev, "I2C read failed for addr: %x\n", addr);
578 *value = regval & 0xff;
583 static int imx290_write_reg(struct imx290 *imx290, u16 addr, u8 value)
587 ret = regmap_write(imx290->regmap, addr, value);
589 dev_err(imx290->dev, "I2C write failed for addr: %x\n", addr);
596 static int imx290_set_register_array(struct imx290 *imx290,
597 const struct imx290_regval *settings,
598 unsigned int num_settings)
603 for (i = 0; i < num_settings; ++i, ++settings) {
604 ret = imx290_write_reg(imx290, settings->reg, settings->val);
609 /* Provide 10ms settle time */
610 usleep_range(10000, 11000);
615 static int imx290_write_buffered_reg(struct imx290 *imx290, u16 address_low,
616 u8 nr_regs, u32 value)
621 ret = imx290_write_reg(imx290, IMX290_REGHOLD, 0x01);
623 dev_err(imx290->dev, "Error setting hold register\n");
627 for (i = 0; i < nr_regs; i++) {
628 ret = imx290_write_reg(imx290, address_low + i,
629 (u8)(value >> (i * 8)));
631 dev_err(imx290->dev, "Error writing buffered registers\n");
636 ret = imx290_write_reg(imx290, IMX290_REGHOLD, 0x00);
638 dev_err(imx290->dev, "Error setting hold register\n");
645 static int imx290_set_gain(struct imx290 *imx290, u32 value)
649 ret = imx290_write_buffered_reg(imx290, IMX290_GAIN, 1, value);
651 dev_err(imx290->dev, "Unable to write gain\n");
656 static int imx290_set_exposure(struct imx290 *imx290, u32 value)
658 u32 exposure = (imx290->current_mode->height + imx290->vblank->val) -
662 ret = imx290_write_buffered_reg(imx290, IMX290_EXPOSURE_LOW, 3,
665 dev_err(imx290->dev, "Unable to write exposure\n");
670 static int imx290_set_hmax(struct imx290 *imx290, u32 val)
672 u32 hmax = val + imx290->current_mode->width;
675 ret = imx290_write_buffered_reg(imx290, IMX290_HMAX_LOW, 2,
678 dev_err(imx290->dev, "Error setting HMAX register\n");
683 static int imx290_set_vmax(struct imx290 *imx290, u32 val)
685 u32 vmax = val + imx290->current_mode->height;
688 ret = imx290_write_buffered_reg(imx290, IMX290_VMAX_LOW, 3,
691 dev_err(imx290->dev, "Unable to write vmax\n");
694 * Changing vblank changes the allowed range for exposure.
695 * We don't supply the current exposure as default here as it
696 * may lie outside the new range. We will reset it just below.
698 __v4l2_ctrl_modify_range(imx290->exposure,
701 IMX290_EXPOSURE_STEP,
705 * Becuse of the way exposure works for this sensor, updating
706 * vblank causes the effective exposure to change, so we must
707 * set it back to the "new" correct value.
709 imx290_set_exposure(imx290, imx290->exposure->val);
715 static int imx290_stop_streaming(struct imx290 *imx290)
719 ret = imx290_write_reg(imx290, IMX290_STANDBY, 0x01);
725 return imx290_write_reg(imx290, IMX290_XMSTA, 0x01);
728 static int imx290_set_ctrl(struct v4l2_ctrl *ctrl)
730 struct imx290 *imx290 = container_of(ctrl->handler,
731 struct imx290, ctrls);
735 /* V4L2 controls values will be applied only when power is already up */
736 if (!pm_runtime_get_if_in_use(imx290->dev))
740 case V4L2_CID_ANALOGUE_GAIN:
741 ret = imx290_set_gain(imx290, ctrl->val);
743 case V4L2_CID_EXPOSURE:
744 ret = imx290_set_exposure(imx290, ctrl->val);
746 case V4L2_CID_HBLANK:
747 ret = imx290_set_hmax(imx290, ctrl->val);
749 case V4L2_CID_VBLANK:
750 ret = imx290_set_vmax(imx290, ctrl->val);
754 /* WINMODE is in bits [6:4], so need to read-modify-write */
755 ret = imx290_read_reg(imx290, IMX290_FLIP_WINMODE, &val);
759 val |= imx290->vflip->val | (imx290->hflip->val << 1);
760 ret = imx290_write_reg(imx290, IMX290_FLIP_WINMODE, val);
762 case V4L2_CID_TEST_PATTERN:
764 imx290_write_reg(imx290, IMX290_BLKLEVEL_LOW, 0x00);
765 imx290_write_reg(imx290, IMX290_BLKLEVEL_HIGH, 0x00);
766 usleep_range(10000, 11000);
767 imx290_write_reg(imx290, IMX290_PGCTRL,
768 (u8)(IMX290_PGCTRL_REGEN |
770 IMX290_PGCTRL_MODE(ctrl->val)));
772 imx290_write_reg(imx290, IMX290_PGCTRL, 0x00);
773 usleep_range(10000, 11000);
774 if (imx290->bpp == 10)
775 imx290_write_reg(imx290, IMX290_BLKLEVEL_LOW,
777 else /* 12 bits per pixel */
778 imx290_write_reg(imx290, IMX290_BLKLEVEL_LOW,
780 imx290_write_reg(imx290, IMX290_BLKLEVEL_HIGH, 0x00);
788 pm_runtime_put(imx290->dev);
793 static const struct v4l2_ctrl_ops imx290_ctrl_ops = {
794 .s_ctrl = imx290_set_ctrl,
797 static int imx290_enum_mbus_code(struct v4l2_subdev *sd,
798 struct v4l2_subdev_state *sd_state,
799 struct v4l2_subdev_mbus_code_enum *code)
801 const struct imx290 *imx290 = to_imx290(sd);
803 if (code->index >= IMX290_NUM_FORMATS)
806 code->code = imx290->formats[code->index].code;
811 static int imx290_enum_frame_size(struct v4l2_subdev *sd,
812 struct v4l2_subdev_state *sd_state,
813 struct v4l2_subdev_frame_size_enum *fse)
815 const struct imx290 *imx290 = to_imx290(sd);
816 const struct imx290_mode *imx290_modes = imx290_modes_ptr(imx290);
818 if (fse->code != imx290->formats[0].code &&
819 fse->code != imx290->formats[1].code)
822 if (fse->index >= imx290_modes_num(imx290))
825 fse->min_width = imx290_modes[fse->index].width;
826 fse->max_width = imx290_modes[fse->index].width;
827 fse->min_height = imx290_modes[fse->index].height;
828 fse->max_height = imx290_modes[fse->index].height;
833 static int imx290_get_fmt(struct v4l2_subdev *sd,
834 struct v4l2_subdev_state *sd_state,
835 struct v4l2_subdev_format *fmt)
837 struct imx290 *imx290 = to_imx290(sd);
838 struct v4l2_mbus_framefmt *framefmt;
840 mutex_lock(&imx290->lock);
842 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
843 framefmt = v4l2_subdev_get_try_format(&imx290->sd, sd_state,
846 framefmt = &imx290->current_format;
848 fmt->format = *framefmt;
850 mutex_unlock(&imx290->lock);
855 static inline u8 imx290_get_link_freq_index(struct imx290 *imx290)
857 return imx290->current_mode->link_freq_index;
860 static u64 imx290_calc_pixel_rate(struct imx290 *imx290)
865 static int imx290_set_fmt(struct v4l2_subdev *sd,
866 struct v4l2_subdev_state *sd_state,
867 struct v4l2_subdev_format *fmt)
869 struct imx290 *imx290 = to_imx290(sd);
870 const struct imx290_mode *mode;
871 struct v4l2_mbus_framefmt *format;
874 mutex_lock(&imx290->lock);
876 mode = v4l2_find_nearest_size(imx290_modes_ptr(imx290),
877 imx290_modes_num(imx290), width, height,
878 fmt->format.width, fmt->format.height);
880 fmt->format.width = mode->width;
881 fmt->format.height = mode->height;
883 for (i = 0; i < IMX290_NUM_FORMATS; i++)
884 if (imx290->formats[i].code == fmt->format.code)
887 if (i >= IMX290_NUM_FORMATS)
890 fmt->format.code = imx290->formats[i].code;
891 fmt->format.field = V4L2_FIELD_NONE;
892 fmt->format.colorspace = V4L2_COLORSPACE_RAW;
893 fmt->format.ycbcr_enc =
894 V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->format.colorspace);
895 fmt->format.quantization =
896 V4L2_MAP_QUANTIZATION_DEFAULT(true, fmt->format.colorspace,
897 fmt->format.ycbcr_enc);
898 fmt->format.xfer_func =
899 V4L2_MAP_XFER_FUNC_DEFAULT(fmt->format.colorspace);
901 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
902 format = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
904 format = &imx290->current_format;
905 imx290->current_mode = mode;
906 imx290->bpp = imx290->formats[i].bpp;
908 if (imx290->link_freq)
909 __v4l2_ctrl_s_ctrl(imx290->link_freq,
910 imx290_get_link_freq_index(imx290));
911 if (imx290->pixel_rate)
912 __v4l2_ctrl_s_ctrl_int64(imx290->pixel_rate,
913 imx290_calc_pixel_rate(imx290));
915 if (imx290->hblank) {
916 __v4l2_ctrl_modify_range(imx290->hblank,
917 imx290->hmax_min - mode->width,
918 IMX290_HMAX_MAX - mode->width,
919 1, mode->hmax - mode->width);
920 __v4l2_ctrl_s_ctrl(imx290->hblank,
921 mode->hmax - mode->width);
923 if (imx290->vblank) {
924 __v4l2_ctrl_modify_range(imx290->vblank,
925 mode->vmax - mode->height,
926 IMX290_VMAX_MAX - mode->height,
928 mode->vmax - mode->height);
929 __v4l2_ctrl_s_ctrl(imx290->vblank,
930 mode->vmax - mode->height);
932 if (imx290->exposure)
933 __v4l2_ctrl_modify_range(imx290->exposure,
936 IMX290_EXPOSURE_STEP,
940 *format = fmt->format;
942 mutex_unlock(&imx290->lock);
947 static int imx290_entity_init_cfg(struct v4l2_subdev *subdev,
948 struct v4l2_subdev_state *sd_state)
950 struct v4l2_subdev_format fmt = { 0 };
952 fmt.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
953 fmt.format.width = 1920;
954 fmt.format.height = 1080;
956 imx290_set_fmt(subdev, sd_state, &fmt);
961 static int imx290_write_current_format(struct imx290 *imx290)
965 switch (imx290->current_format.code) {
966 case MEDIA_BUS_FMT_SRGGB10_1X10:
967 case MEDIA_BUS_FMT_Y10_1X10:
968 ret = imx290_set_register_array(imx290, imx290_10bit_settings,
970 imx290_10bit_settings));
972 dev_err(imx290->dev, "Could not set format registers\n");
976 case MEDIA_BUS_FMT_SRGGB12_1X12:
977 case MEDIA_BUS_FMT_Y12_1X12:
978 ret = imx290_set_register_array(imx290, imx290_12bit_settings,
980 imx290_12bit_settings));
982 dev_err(imx290->dev, "Could not set format registers\n");
987 dev_err(imx290->dev, "Unknown pixel format\n");
994 static const struct v4l2_rect *
995 __imx290_get_pad_crop(struct imx290 *imx290,
996 struct v4l2_subdev_state *sd_state,
997 unsigned int pad, enum v4l2_subdev_format_whence which)
1000 case V4L2_SUBDEV_FORMAT_TRY:
1001 return v4l2_subdev_get_try_crop(&imx290->sd, sd_state, pad);
1002 case V4L2_SUBDEV_FORMAT_ACTIVE:
1003 return &imx290->current_mode->crop;
1009 static int imx290_get_selection(struct v4l2_subdev *sd,
1010 struct v4l2_subdev_state *sd_state,
1011 struct v4l2_subdev_selection *sel)
1013 switch (sel->target) {
1014 case V4L2_SEL_TGT_CROP: {
1015 struct imx290 *imx290 = to_imx290(sd);
1017 mutex_lock(&imx290->lock);
1018 sel->r = *__imx290_get_pad_crop(imx290, sd_state, sel->pad,
1020 mutex_unlock(&imx290->lock);
1025 case V4L2_SEL_TGT_NATIVE_SIZE:
1028 sel->r.width = IMX290_NATIVE_WIDTH;
1029 sel->r.height = IMX290_NATIVE_HEIGHT;
1033 case V4L2_SEL_TGT_CROP_DEFAULT:
1034 case V4L2_SEL_TGT_CROP_BOUNDS:
1035 sel->r.top = IMX290_PIXEL_ARRAY_TOP;
1036 sel->r.left = IMX290_PIXEL_ARRAY_LEFT;
1037 sel->r.width = IMX290_PIXEL_ARRAY_WIDTH;
1038 sel->r.height = IMX290_PIXEL_ARRAY_HEIGHT;
1046 /* Start streaming */
1047 static int imx290_start_streaming(struct imx290 *imx290)
1049 enum imx290_clk_index clk_idx = imx290->xclk_freq == 37125000 ?
1050 CLK_37_125 : CLK_74_25;
1053 /* Set init register settings */
1054 ret = imx290_set_register_array(imx290, imx290_global_init_settings,
1056 imx290_global_init_settings));
1058 dev_err(imx290->dev, "Could not set init registers\n");
1062 ret = imx290_set_register_array(imx290,
1063 imx290->current_mode->clk_data[clk_idx],
1064 imx290->current_mode->clk_size);
1066 dev_err(imx290->dev, "Could not set clock registers\n");
1070 /* Apply the register values related to current frame format */
1071 ret = imx290_write_current_format(imx290);
1073 dev_err(imx290->dev, "Could not set frame format\n");
1077 /* Apply default values of current mode */
1078 ret = imx290_set_register_array(imx290,
1079 imx290->current_mode->mode_data,
1080 imx290->current_mode->mode_data_size);
1082 dev_err(imx290->dev, "Could not set current mode\n");
1086 /* Apply lane config registers of current mode */
1087 ret = imx290_set_register_array(imx290,
1088 imx290->current_mode->lane_data,
1089 imx290->current_mode->lane_data_size);
1091 dev_err(imx290->dev, "Could not set current mode\n");
1095 /* Apply customized values from user */
1096 ret = v4l2_ctrl_handler_setup(imx290->sd.ctrl_handler);
1098 dev_err(imx290->dev, "Could not sync v4l2 controls\n");
1102 ret = imx290_write_reg(imx290, IMX290_STANDBY, 0x00);
1108 /* Start streaming */
1109 return imx290_write_reg(imx290, IMX290_XMSTA, 0x00);
1112 static int imx290_set_stream(struct v4l2_subdev *sd, int enable)
1114 struct imx290 *imx290 = to_imx290(sd);
1118 ret = pm_runtime_resume_and_get(imx290->dev);
1120 goto unlock_and_return;
1122 ret = imx290_start_streaming(imx290);
1124 dev_err(imx290->dev, "Start stream failed\n");
1125 pm_runtime_put(imx290->dev);
1126 goto unlock_and_return;
1129 imx290_stop_streaming(imx290);
1130 pm_runtime_put(imx290->dev);
1132 /* vflip and hflip cannot change during streaming */
1133 __v4l2_ctrl_grab(imx290->vflip, enable);
1134 __v4l2_ctrl_grab(imx290->hflip, enable);
1141 static int imx290_get_regulators(struct device *dev, struct imx290 *imx290)
1145 for (i = 0; i < IMX290_NUM_SUPPLIES; i++)
1146 imx290->supplies[i].supply = imx290_supply_name[i];
1148 return devm_regulator_bulk_get(dev, IMX290_NUM_SUPPLIES,
1152 static int imx290_power_on(struct device *dev)
1154 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1155 struct imx290 *imx290 = to_imx290(sd);
1158 ret = clk_prepare_enable(imx290->xclk);
1160 dev_err(dev, "Failed to enable clock\n");
1164 ret = regulator_bulk_enable(IMX290_NUM_SUPPLIES, imx290->supplies);
1166 dev_err(dev, "Failed to enable regulators\n");
1167 clk_disable_unprepare(imx290->xclk);
1172 gpiod_set_value_cansleep(imx290->rst_gpio, 0);
1173 usleep_range(30000, 31000);
1178 static int imx290_power_off(struct device *dev)
1180 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1181 struct imx290 *imx290 = to_imx290(sd);
1183 clk_disable_unprepare(imx290->xclk);
1184 gpiod_set_value_cansleep(imx290->rst_gpio, 1);
1185 regulator_bulk_disable(IMX290_NUM_SUPPLIES, imx290->supplies);
1190 static const struct dev_pm_ops imx290_pm_ops = {
1191 SET_RUNTIME_PM_OPS(imx290_power_off, imx290_power_on, NULL)
1194 static const struct v4l2_subdev_video_ops imx290_video_ops = {
1195 .s_stream = imx290_set_stream,
1198 static const struct v4l2_subdev_pad_ops imx290_pad_ops = {
1199 .init_cfg = imx290_entity_init_cfg,
1200 .enum_mbus_code = imx290_enum_mbus_code,
1201 .enum_frame_size = imx290_enum_frame_size,
1202 .get_fmt = imx290_get_fmt,
1203 .set_fmt = imx290_set_fmt,
1204 .get_selection = imx290_get_selection,
1207 static const struct v4l2_subdev_ops imx290_subdev_ops = {
1208 .video = &imx290_video_ops,
1209 .pad = &imx290_pad_ops,
1212 static const struct media_entity_operations imx290_subdev_entity_ops = {
1213 .link_validate = v4l2_subdev_link_validate,
1217 * Returns 0 if all link frequencies used by the driver for the given number
1218 * of MIPI data lanes are mentioned in the device tree, or the value of the
1219 * first missing frequency otherwise.
1221 static s64 imx290_check_link_freqs(const struct imx290 *imx290,
1222 const struct v4l2_fwnode_endpoint *ep)
1225 const s64 *freqs = imx290_link_freqs_ptr(imx290);
1226 int freqs_count = imx290_link_freqs_num(imx290);
1228 for (i = 0; i < freqs_count; i++) {
1229 for (j = 0; j < ep->nr_of_link_frequencies; j++)
1230 if (freqs[i] == ep->link_frequencies[j])
1232 if (j == ep->nr_of_link_frequencies)
1238 static const struct of_device_id imx290_of_match[] = {
1240 * imx327 supports 1080p60 at 10 and 12bit.
1241 * imx290 adds 10bit 1080p120.
1242 * imx462 adds 10 and 12bit 1080p120.
1243 * This driver currently maxes out at 1080p60, which is supported by all
1244 * of them, but add the compatible strings for future implementation.
1246 { .compatible = "sony,imx327", .data = imx290_colour_formats },
1247 { .compatible = "sony,imx327-mono", .data = imx290_mono_formats },
1248 { .compatible = "sony,imx290", .data = imx290_colour_formats },
1249 { .compatible = "sony,imx290-mono", .data = imx290_mono_formats },
1250 { .compatible = "sony,imx462", .data = imx290_colour_formats },
1251 { .compatible = "sony,imx462-mono", .data = imx290_mono_formats },
1255 static int imx290_probe(struct i2c_client *client)
1257 struct v4l2_fwnode_device_properties props;
1258 struct device *dev = &client->dev;
1259 struct fwnode_handle *endpoint;
1260 /* Only CSI2 is supported for now: */
1261 struct v4l2_fwnode_endpoint ep = {
1262 .bus_type = V4L2_MBUS_CSI2_DPHY
1264 const struct of_device_id *match;
1265 const struct imx290_mode *mode;
1266 struct imx290 *imx290;
1270 imx290 = devm_kzalloc(dev, sizeof(*imx290), GFP_KERNEL);
1275 imx290->regmap = devm_regmap_init_i2c(client, &imx290_regmap_config);
1276 if (IS_ERR(imx290->regmap)) {
1277 dev_err(dev, "Unable to initialize I2C\n");
1281 match = of_match_device(imx290_of_match, dev);
1284 imx290->formats = (const struct imx290_pixfmt *)match->data;
1286 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL);
1288 dev_err(dev, "Endpoint node not found\n");
1292 ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep);
1293 fwnode_handle_put(endpoint);
1294 if (ret == -ENXIO) {
1295 dev_err(dev, "Unsupported bus type, should be CSI2\n");
1298 dev_err(dev, "Parsing endpoint node failed\n");
1302 /* Get number of data lanes */
1303 imx290->nlanes = ep.bus.mipi_csi2.num_data_lanes;
1304 if (imx290->nlanes != 2 && imx290->nlanes != 4) {
1305 dev_err(dev, "Invalid data lanes: %d\n", imx290->nlanes);
1309 imx290->hmax_min = IMX290_HMAX_MIN;
1311 dev_dbg(dev, "Using %u data lanes\n", imx290->nlanes);
1313 if (!ep.nr_of_link_frequencies) {
1314 dev_err(dev, "link-frequency property not found in DT\n");
1319 /* Check that link frequences for all the modes are in device tree */
1320 fq = imx290_check_link_freqs(imx290, &ep);
1322 dev_err(dev, "Link frequency of %lld is not supported\n", fq);
1327 /* get system clock (xclk) */
1328 imx290->xclk = devm_clk_get(dev, "xclk");
1329 if (IS_ERR(imx290->xclk)) {
1330 dev_err(dev, "Could not get xclk");
1331 ret = PTR_ERR(imx290->xclk);
1335 ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
1336 &imx290->xclk_freq);
1338 dev_err(dev, "Could not get xclk frequency\n");
1342 /* external clock must be 37.125 MHz */
1343 if (imx290->xclk_freq != 37125000 && imx290->xclk_freq != 74250000) {
1344 dev_err(dev, "External clock frequency %u is not supported\n",
1350 ret = clk_set_rate(imx290->xclk, imx290->xclk_freq);
1352 dev_err(dev, "Could not set xclk frequency\n");
1356 ret = imx290_get_regulators(dev, imx290);
1358 dev_err(dev, "Cannot get regulators\n");
1362 imx290->rst_gpio = devm_gpiod_get_optional(dev, "reset",
1364 if (IS_ERR(imx290->rst_gpio)) {
1365 dev_err(dev, "Cannot get reset gpio\n");
1366 ret = PTR_ERR(imx290->rst_gpio);
1370 mutex_init(&imx290->lock);
1373 * Initialize the frame format. In particular, imx290->current_mode
1374 * and imx290->bpp are set to defaults: imx290_calc_pixel_rate() call
1375 * below relies on these fields.
1377 imx290_entity_init_cfg(&imx290->sd, NULL);
1379 v4l2_ctrl_handler_init(&imx290->ctrls, 11);
1381 v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
1382 V4L2_CID_ANALOGUE_GAIN, 0, 100, 1, 0);
1384 mode = imx290->current_mode;
1385 imx290->hblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
1387 imx290->hmax_min - mode->width,
1388 IMX290_HMAX_MAX - mode->width, 1,
1389 mode->hmax - mode->width);
1391 imx290->vblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
1393 mode->vmax - mode->height,
1394 IMX290_VMAX_MAX - mode->height, 1,
1395 mode->vmax - mode->height);
1397 imx290->exposure = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
1399 IMX290_EXPOSURE_MIN,
1401 IMX290_EXPOSURE_STEP,
1404 imx290->hflip = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
1405 V4L2_CID_HFLIP, 0, 1, 1, 0);
1406 imx290->vflip = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
1407 V4L2_CID_VFLIP, 0, 1, 1, 0);
1410 v4l2_ctrl_new_int_menu(&imx290->ctrls, &imx290_ctrl_ops,
1412 imx290_link_freqs_num(imx290) - 1, 0,
1413 imx290_link_freqs_ptr(imx290));
1414 if (imx290->link_freq)
1415 imx290->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1417 imx290->pixel_rate = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
1418 V4L2_CID_PIXEL_RATE,
1420 imx290_calc_pixel_rate(imx290));
1422 v4l2_ctrl_new_std_menu_items(&imx290->ctrls, &imx290_ctrl_ops,
1423 V4L2_CID_TEST_PATTERN,
1424 ARRAY_SIZE(imx290_test_pattern_menu) - 1,
1425 0, 0, imx290_test_pattern_menu);
1427 ret = v4l2_fwnode_device_parse(&client->dev, &props);
1431 ret = v4l2_ctrl_new_fwnode_properties(&imx290->ctrls, &imx290_ctrl_ops,
1436 imx290->sd.ctrl_handler = &imx290->ctrls;
1438 if (imx290->ctrls.error) {
1439 dev_err(dev, "Control initialization error %d\n",
1440 imx290->ctrls.error);
1441 ret = imx290->ctrls.error;
1445 v4l2_i2c_subdev_init(&imx290->sd, client, &imx290_subdev_ops);
1446 imx290->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1447 imx290->sd.dev = &client->dev;
1448 imx290->sd.entity.ops = &imx290_subdev_entity_ops;
1449 imx290->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1451 imx290->pad.flags = MEDIA_PAD_FL_SOURCE;
1452 ret = media_entity_pads_init(&imx290->sd.entity, 1, &imx290->pad);
1454 dev_err(dev, "Could not register media entity\n");
1458 /* Initialize the frame format (this also sets imx290->current_mode) */
1459 imx290_entity_init_cfg(&imx290->sd, NULL);
1461 ret = v4l2_async_register_subdev(&imx290->sd);
1463 dev_err(dev, "Could not register v4l2 device\n");
1467 /* Power on the device to match runtime PM state below */
1468 ret = imx290_power_on(dev);
1470 dev_err(dev, "Could not power on the device\n");
1474 pm_runtime_set_active(dev);
1475 pm_runtime_enable(dev);
1476 pm_runtime_idle(dev);
1478 v4l2_fwnode_endpoint_free(&ep);
1483 media_entity_cleanup(&imx290->sd.entity);
1485 v4l2_ctrl_handler_free(&imx290->ctrls);
1486 mutex_destroy(&imx290->lock);
1488 v4l2_fwnode_endpoint_free(&ep);
1493 static int imx290_remove(struct i2c_client *client)
1495 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1496 struct imx290 *imx290 = to_imx290(sd);
1498 v4l2_async_unregister_subdev(sd);
1499 media_entity_cleanup(&sd->entity);
1500 v4l2_ctrl_handler_free(sd->ctrl_handler);
1502 mutex_destroy(&imx290->lock);
1504 pm_runtime_disable(imx290->dev);
1505 if (!pm_runtime_status_suspended(imx290->dev))
1506 imx290_power_off(imx290->dev);
1507 pm_runtime_set_suspended(imx290->dev);
1512 MODULE_DEVICE_TABLE(of, imx290_of_match);
1514 static struct i2c_driver imx290_i2c_driver = {
1515 .probe_new = imx290_probe,
1516 .remove = imx290_remove,
1519 .pm = &imx290_pm_ops,
1520 .of_match_table = of_match_ptr(imx290_of_match),
1524 module_i2c_driver(imx290_i2c_driver);
1526 MODULE_DESCRIPTION("Sony IMX290 CMOS Image Sensor Driver");
1527 MODULE_AUTHOR("FRAMOS GmbH");
1528 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
1529 MODULE_LICENSE("GPL v2");