drivers/media/i2c/ds90ub960.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for the Texas Instruments DS90UB960-Q1 video deserializer
   4  *
   5  * Copyright (c) 2019 Luca Ceresoli <luca@lucaceresoli.net>
   6  * Copyright (c) 2023 Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
   7  */
   8
   9 /*
  10  * (Possible) TODOs:
  11  *
  12  * - PM for serializer and remote peripherals. We need to manage:
  13  *   - VPOC
  14  *     - Power domain? Regulator? Somehow any remote device should be able to
  15  *       cause the VPOC to be turned on.
  16  *   - Link between the deserializer and the serializer
  17  *     - Related to VPOC management. We probably always want to turn on the VPOC
  18  *       and then enable the link.
  19  *   - Serializer's services: i2c, gpios, power
  20  *     - The serializer needs to resume before the remote peripherals can
  21  *       e.g. use the i2c.
  22  *     - How to handle gpios? Reserving a gpio essentially keeps the provider
  23  *       (serializer) always powered on.
  24  * - Do we need a new bus for the FPD-Link? At the moment the serializers
  25  *   are children of the same i2c-adapter where the deserializer resides.
  26  * - i2c-atr could be made embeddable instead of allocatable.
  27  */
  28
  29 #include <linux/bitops.h>
  30 #include <linux/clk.h>
  31 #include <linux/delay.h>
  32 #include <linux/fwnode.h>
  33 #include <linux/gpio/consumer.h>
  34 #include <linux/i2c-atr.h>
  35 #include <linux/i2c.h>
  36 #include <linux/init.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/kthread.h>
  40 #include <linux/module.h>
  41 #include <linux/mutex.h>
  42 #include <linux/property.h>
  43 #include <linux/regmap.h>
  44 #include <linux/regulator/consumer.h>
  45 #include <linux/slab.h>
  46 #include <linux/workqueue.h>
  47
  48 #include <media/i2c/ds90ub9xx.h>
  49 #include <media/mipi-csi2.h>
  50 #include <media/v4l2-ctrls.h>
  51 #include <media/v4l2-event.h>
  52 #include <media/v4l2-fwnode.h>
  53 #include <media/v4l2-subdev.h>
  54
  55 #define MHZ(v) ((u32)((v) * 1000000U))
  56
  57 #define UB960_POLL_TIME_MS      500
  58
  59 #define UB960_MAX_RX_NPORTS     4
  60 #define UB960_MAX_TX_NPORTS     2
  61 #define UB960_MAX_NPORTS        (UB960_MAX_RX_NPORTS + UB960_MAX_TX_NPORTS)
  62
  63 #define UB960_MAX_PORT_ALIASES  8
  64
  65 #define UB960_NUM_BC_GPIOS              4
  66
  67 /*
  68  * Register map
  69  *
  70  * 0x00-0x32   Shared (UB960_SR)
  71  * 0x33-0x3a   CSI-2 TX (per-port paged on DS90UB960, shared on 954) (UB960_TR)
  72  * 0x4c        Shared (UB960_SR)
  73  * 0x4d-0x7f   FPD-Link RX, per-port paged (UB960_RR)
  74  * 0xb0-0xbf   Shared (UB960_SR)
  75  * 0xd0-0xdf   FPD-Link RX, per-port paged (UB960_RR)
  76  * 0xf0-0xf5   Shared (UB960_SR)
  77  * 0xf8-0xfb   Shared (UB960_SR)
  78  * All others  Reserved
  79  *
  80  * Register prefixes:
  81  * UB960_SR_* = Shared register
  82  * UB960_RR_* = FPD-Link RX, per-port paged register
  83  * UB960_TR_* = CSI-2 TX, per-port paged register
  84  * UB960_XR_* = Reserved register
  85  * UB960_IR_* = Indirect register
  86  */
  87
  88 #define UB960_SR_I2C_DEV_ID                     0x00
  89 #define UB960_SR_RESET                          0x01
  90 #define UB960_SR_RESET_DIGITAL_RESET1           BIT(1)
  91 #define UB960_SR_RESET_DIGITAL_RESET0           BIT(0)
  92 #define UB960_SR_RESET_GPIO_LOCK_RELEASE        BIT(5)
  93
  94 #define UB960_SR_GEN_CONFIG                     0x02
  95 #define UB960_SR_REV_MASK                       0x03
  96 #define UB960_SR_DEVICE_STS                     0x04
  97 #define UB960_SR_PAR_ERR_THOLD_HI               0x05
  98 #define UB960_SR_PAR_ERR_THOLD_LO               0x06
  99 #define UB960_SR_BCC_WDOG_CTL                   0x07
 100 #define UB960_SR_I2C_CTL1                       0x08
 101 #define UB960_SR_I2C_CTL2                       0x09
 102 #define UB960_SR_SCL_HIGH_TIME                  0x0a
 103 #define UB960_SR_SCL_LOW_TIME                   0x0b
 104 #define UB960_SR_RX_PORT_CTL                    0x0c
 105 #define UB960_SR_IO_CTL                         0x0d
 106 #define UB960_SR_GPIO_PIN_STS                   0x0e
 107 #define UB960_SR_GPIO_INPUT_CTL                 0x0f
 108 #define UB960_SR_GPIO_PIN_CTL(n)                (0x10 + (n)) /* n < UB960_NUM_GPIOS */
 109 #define UB960_SR_GPIO_PIN_CTL_GPIO_OUT_SEL              5
 110 #define UB960_SR_GPIO_PIN_CTL_GPIO_OUT_SRC_SHIFT        2
 111 #define UB960_SR_GPIO_PIN_CTL_GPIO_OUT_EN               BIT(0)
 112
 113 #define UB960_SR_FS_CTL                         0x18
 114 #define UB960_SR_FS_HIGH_TIME_1                 0x19
 115 #define UB960_SR_FS_HIGH_TIME_0                 0x1a
 116 #define UB960_SR_FS_LOW_TIME_1                  0x1b
 117 #define UB960_SR_FS_LOW_TIME_0                  0x1c
 118 #define UB960_SR_MAX_FRM_HI                     0x1d
 119 #define UB960_SR_MAX_FRM_LO                     0x1e
 120 #define UB960_SR_CSI_PLL_CTL                    0x1f
 121
 122 #define UB960_SR_FWD_CTL1                       0x20
 123 #define UB960_SR_FWD_CTL1_PORT_DIS(n)           BIT((n) + 4)
 124
 125 #define UB960_SR_FWD_CTL2                       0x21
 126 #define UB960_SR_FWD_STS                        0x22
 127
 128 #define UB960_SR_INTERRUPT_CTL                  0x23
 129 #define UB960_SR_INTERRUPT_CTL_INT_EN           BIT(7)
 130 #define UB960_SR_INTERRUPT_CTL_IE_CSI_TX0       BIT(4)
 131 #define UB960_SR_INTERRUPT_CTL_IE_RX(n)         BIT((n)) /* rxport[n] IRQ */
 132
 133 #define UB960_SR_INTERRUPT_STS                  0x24
 134 #define UB960_SR_INTERRUPT_STS_INT              BIT(7)
 135 #define UB960_SR_INTERRUPT_STS_IS_CSI_TX(n)     BIT(4 + (n)) /* txport[n] IRQ */
 136 #define UB960_SR_INTERRUPT_STS_IS_RX(n)         BIT((n)) /* rxport[n] IRQ */
 137
 138 #define UB960_SR_TS_CONFIG                      0x25
 139 #define UB960_SR_TS_CONTROL                     0x26
 140 #define UB960_SR_TS_LINE_HI                     0x27
 141 #define UB960_SR_TS_LINE_LO                     0x28
 142 #define UB960_SR_TS_STATUS                      0x29
 143 #define UB960_SR_TIMESTAMP_P0_HI                0x2a
 144 #define UB960_SR_TIMESTAMP_P0_LO                0x2b
 145 #define UB960_SR_TIMESTAMP_P1_HI                0x2c
 146 #define UB960_SR_TIMESTAMP_P1_LO                0x2d
 147
 148 #define UB960_SR_CSI_PORT_SEL                   0x32
 149
 150 #define UB960_TR_CSI_CTL                        0x33
 151 #define UB960_TR_CSI_CTL_CSI_CAL_EN             BIT(6)
 152 #define UB960_TR_CSI_CTL_CSI_ENABLE             BIT(0)
 153
 154 #define UB960_TR_CSI_CTL2                       0x34
 155 #define UB960_TR_CSI_STS                        0x35
 156 #define UB960_TR_CSI_TX_ICR                     0x36
 157
 158 #define UB960_TR_CSI_TX_ISR                     0x37
 159 #define UB960_TR_CSI_TX_ISR_IS_CSI_SYNC_ERROR   BIT(3)
 160 #define UB960_TR_CSI_TX_ISR_IS_CSI_PASS_ERROR   BIT(1)
 161
 162 #define UB960_TR_CSI_TEST_CTL                   0x38
 163 #define UB960_TR_CSI_TEST_PATT_HI               0x39
 164 #define UB960_TR_CSI_TEST_PATT_LO               0x3a
 165
 166 #define UB960_XR_SFILTER_CFG                    0x41
 167 #define UB960_XR_SFILTER_CFG_SFILTER_MAX_SHIFT  4
 168 #define UB960_XR_SFILTER_CFG_SFILTER_MIN_SHIFT  0
 169
 170 #define UB960_XR_AEQ_CTL1                       0x42
 171 #define UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_FPD_CLK   BIT(6)
 172 #define UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_ENCODING  BIT(5)
 173 #define UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_PARITY    BIT(4)
 174 #define UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_MASK        \
 175         (UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_FPD_CLK |  \
 176          UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_ENCODING | \
 177          UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_PARITY)
 178 #define UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN        BIT(0)
 179
 180 #define UB960_XR_AEQ_ERR_THOLD                  0x43
 181
 182 #define UB960_RR_BCC_ERR_CTL                    0x46
 183 #define UB960_RR_BCC_STATUS                     0x47
 184 #define UB960_RR_BCC_STATUS_SEQ_ERROR           BIT(5)
 185 #define UB960_RR_BCC_STATUS_MASTER_ERR          BIT(4)
 186 #define UB960_RR_BCC_STATUS_MASTER_TO           BIT(3)
 187 #define UB960_RR_BCC_STATUS_SLAVE_ERR           BIT(2)
 188 #define UB960_RR_BCC_STATUS_SLAVE_TO            BIT(1)
 189 #define UB960_RR_BCC_STATUS_RESP_ERR            BIT(0)
 190 #define UB960_RR_BCC_STATUS_ERROR_MASK                                    \
 191         (UB960_RR_BCC_STATUS_SEQ_ERROR | UB960_RR_BCC_STATUS_MASTER_ERR | \
 192          UB960_RR_BCC_STATUS_MASTER_TO | UB960_RR_BCC_STATUS_SLAVE_ERR |  \
 193          UB960_RR_BCC_STATUS_SLAVE_TO | UB960_RR_BCC_STATUS_RESP_ERR)
 194
 195 #define UB960_RR_FPD3_CAP                       0x4a
 196 #define UB960_RR_RAW_EMBED_DTYPE                0x4b
 197 #define UB960_RR_RAW_EMBED_DTYPE_LINES_SHIFT    6
 198
 199 #define UB960_SR_FPD3_PORT_SEL                  0x4c
 200
 201 #define UB960_RR_RX_PORT_STS1                   0x4d
 202 #define UB960_RR_RX_PORT_STS1_BCC_CRC_ERROR     BIT(5)
 203 #define UB960_RR_RX_PORT_STS1_LOCK_STS_CHG      BIT(4)
 204 #define UB960_RR_RX_PORT_STS1_BCC_SEQ_ERROR     BIT(3)
 205 #define UB960_RR_RX_PORT_STS1_PARITY_ERROR      BIT(2)
 206 #define UB960_RR_RX_PORT_STS1_PORT_PASS         BIT(1)
 207 #define UB960_RR_RX_PORT_STS1_LOCK_STS          BIT(0)
 208 #define UB960_RR_RX_PORT_STS1_ERROR_MASK       \
 209         (UB960_RR_RX_PORT_STS1_BCC_CRC_ERROR | \
 210          UB960_RR_RX_PORT_STS1_BCC_SEQ_ERROR | \
 211          UB960_RR_RX_PORT_STS1_PARITY_ERROR)
 212
 213 #define UB960_RR_RX_PORT_STS2                   0x4e
 214 #define UB960_RR_RX_PORT_STS2_LINE_LEN_UNSTABLE BIT(7)
 215 #define UB960_RR_RX_PORT_STS2_LINE_LEN_CHG      BIT(6)
 216 #define UB960_RR_RX_PORT_STS2_FPD3_ENCODE_ERROR BIT(5)
 217 #define UB960_RR_RX_PORT_STS2_BUFFER_ERROR      BIT(4)
 218 #define UB960_RR_RX_PORT_STS2_CSI_ERROR         BIT(3)
 219 #define UB960_RR_RX_PORT_STS2_FREQ_STABLE       BIT(2)
 220 #define UB960_RR_RX_PORT_STS2_CABLE_FAULT       BIT(1)
 221 #define UB960_RR_RX_PORT_STS2_LINE_CNT_CHG      BIT(0)
 222 #define UB960_RR_RX_PORT_STS2_ERROR_MASK       \
 223         UB960_RR_RX_PORT_STS2_BUFFER_ERROR
 224
 225 #define UB960_RR_RX_FREQ_HIGH                   0x4f
 226 #define UB960_RR_RX_FREQ_LOW                    0x50
 227 #define UB960_RR_SENSOR_STS_0                   0x51
 228 #define UB960_RR_SENSOR_STS_1                   0x52
 229 #define UB960_RR_SENSOR_STS_2                   0x53
 230 #define UB960_RR_SENSOR_STS_3                   0x54
 231 #define UB960_RR_RX_PAR_ERR_HI                  0x55
 232 #define UB960_RR_RX_PAR_ERR_LO                  0x56
 233 #define UB960_RR_BIST_ERR_COUNT                 0x57
 234
 235 #define UB960_RR_BCC_CONFIG                     0x58
 236 #define UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH    BIT(6)
 237 #define UB960_RR_BCC_CONFIG_BC_FREQ_SEL_MASK    GENMASK(2, 0)
 238
 239 #define UB960_RR_DATAPATH_CTL1                  0x59
 240 #define UB960_RR_DATAPATH_CTL2                  0x5a
 241 #define UB960_RR_SER_ID                         0x5b
 242 #define UB960_RR_SER_ALIAS_ID                   0x5c
 243
 244 /* For these two register sets: n < UB960_MAX_PORT_ALIASES */
 245 #define UB960_RR_SLAVE_ID(n)                    (0x5d + (n))
 246 #define UB960_RR_SLAVE_ALIAS(n)                 (0x65 + (n))
 247
 248 #define UB960_RR_PORT_CONFIG                    0x6d
 249 #define UB960_RR_PORT_CONFIG_FPD3_MODE_MASK     GENMASK(1, 0)
 250
 251 #define UB960_RR_BC_GPIO_CTL(n)                 (0x6e + (n)) /* n < 2 */
 252 #define UB960_RR_RAW10_ID                       0x70
 253 #define UB960_RR_RAW10_ID_VC_SHIFT              6
 254 #define UB960_RR_RAW10_ID_DT_SHIFT              0
 255
 256 #define UB960_RR_RAW12_ID                       0x71
 257 #define UB960_RR_CSI_VC_MAP                     0x72
 258 #define UB960_RR_CSI_VC_MAP_SHIFT(x)            ((x) * 2)
 259
 260 #define UB960_RR_LINE_COUNT_HI                  0x73
 261 #define UB960_RR_LINE_COUNT_LO                  0x74
 262 #define UB960_RR_LINE_LEN_1                     0x75
 263 #define UB960_RR_LINE_LEN_0                     0x76
 264 #define UB960_RR_FREQ_DET_CTL                   0x77
 265 #define UB960_RR_MAILBOX_1                      0x78
 266 #define UB960_RR_MAILBOX_2                      0x79
 267
 268 #define UB960_RR_CSI_RX_STS                     0x7a
 269 #define UB960_RR_CSI_RX_STS_LENGTH_ERR          BIT(3)
 270 #define UB960_RR_CSI_RX_STS_CKSUM_ERR           BIT(2)
 271 #define UB960_RR_CSI_RX_STS_ECC2_ERR            BIT(1)
 272 #define UB960_RR_CSI_RX_STS_ECC1_ERR            BIT(0)
 273 #define UB960_RR_CSI_RX_STS_ERROR_MASK                                    \
 274         (UB960_RR_CSI_RX_STS_LENGTH_ERR | UB960_RR_CSI_RX_STS_CKSUM_ERR | \
 275          UB960_RR_CSI_RX_STS_ECC2_ERR | UB960_RR_CSI_RX_STS_ECC1_ERR)
 276
 277 #define UB960_RR_CSI_ERR_COUNTER                0x7b
 278 #define UB960_RR_PORT_CONFIG2                   0x7c
 279 #define UB960_RR_PORT_CONFIG2_RAW10_8BIT_CTL_MASK GENMASK(7, 6)
 280 #define UB960_RR_PORT_CONFIG2_RAW10_8BIT_CTL_SHIFT 6
 281
 282 #define UB960_RR_PORT_CONFIG2_LV_POL_LOW        BIT(1)
 283 #define UB960_RR_PORT_CONFIG2_FV_POL_LOW        BIT(0)
 284
 285 #define UB960_RR_PORT_PASS_CTL                  0x7d
 286 #define UB960_RR_SEN_INT_RISE_CTL               0x7e
 287 #define UB960_RR_SEN_INT_FALL_CTL               0x7f
 288
 289 #define UB960_SR_CSI_FRAME_COUNT_HI(n)          (0x90 + 8 * (n))
 290 #define UB960_SR_CSI_FRAME_COUNT_LO(n)          (0x91 + 8 * (n))
 291 #define UB960_SR_CSI_FRAME_ERR_COUNT_HI(n)      (0x92 + 8 * (n))
 292 #define UB960_SR_CSI_FRAME_ERR_COUNT_LO(n)      (0x93 + 8 * (n))
 293 #define UB960_SR_CSI_LINE_COUNT_HI(n)           (0x94 + 8 * (n))
 294 #define UB960_SR_CSI_LINE_COUNT_LO(n)           (0x95 + 8 * (n))
 295 #define UB960_SR_CSI_LINE_ERR_COUNT_HI(n)       (0x96 + 8 * (n))
 296 #define UB960_SR_CSI_LINE_ERR_COUNT_LO(n)       (0x97 + 8 * (n))
 297
 298 #define UB960_XR_REFCLK_FREQ                    0xa5    /* UB960 */
 299
 300 #define UB960_RR_VC_ID_MAP(x)                   (0xa0 + (x)) /* UB9702 */
 301
 302 #define UB960_SR_IND_ACC_CTL                    0xb0
 303 #define UB960_SR_IND_ACC_CTL_IA_AUTO_INC        BIT(1)
 304
 305 #define UB960_SR_IND_ACC_ADDR                   0xb1
 306 #define UB960_SR_IND_ACC_DATA                   0xb2
 307 #define UB960_SR_BIST_CONTROL                   0xb3
 308 #define UB960_SR_MODE_IDX_STS                   0xb8
 309 #define UB960_SR_LINK_ERROR_COUNT               0xb9
 310 #define UB960_SR_FPD3_ENC_CTL                   0xba
 311 #define UB960_SR_FV_MIN_TIME                    0xbc
 312 #define UB960_SR_GPIO_PD_CTL                    0xbe
 313
 314 #define UB960_SR_FPD_RATE_CFG                   0xc2    /* UB9702 */
 315 #define UB960_SR_CSI_PLL_DIV                    0xc9    /* UB9702 */
 316
 317 #define UB960_RR_PORT_DEBUG                     0xd0
 318 #define UB960_RR_AEQ_CTL2                       0xd2
 319 #define UB960_RR_AEQ_CTL2_SET_AEQ_FLOOR         BIT(2)
 320
 321 #define UB960_RR_AEQ_STATUS                     0xd3
 322 #define UB960_RR_AEQ_STATUS_STATUS_2            GENMASK(5, 3)
 323 #define UB960_RR_AEQ_STATUS_STATUS_1            GENMASK(2, 0)
 324
 325 #define UB960_RR_AEQ_BYPASS                     0xd4
 326 #define UB960_RR_AEQ_BYPASS_EQ_STAGE1_VALUE_SHIFT       5
 327 #define UB960_RR_AEQ_BYPASS_EQ_STAGE1_VALUE_MASK        GENMASK(7, 5)
 328 #define UB960_RR_AEQ_BYPASS_EQ_STAGE2_VALUE_SHIFT       1
 329 #define UB960_RR_AEQ_BYPASS_EQ_STAGE2_VALUE_MASK        GENMASK(3, 1)
 330 #define UB960_RR_AEQ_BYPASS_ENABLE                      BIT(0)
 331
 332 #define UB960_RR_AEQ_MIN_MAX                    0xd5
 333 #define UB960_RR_AEQ_MIN_MAX_AEQ_MAX_SHIFT      4
 334 #define UB960_RR_AEQ_MIN_MAX_AEQ_FLOOR_SHIFT    0
 335
 336 #define UB960_RR_SFILTER_STS_0                  0xd6
 337 #define UB960_RR_SFILTER_STS_1                  0xd7
 338 #define UB960_RR_PORT_ICR_HI                    0xd8
 339 #define UB960_RR_PORT_ICR_LO                    0xd9
 340 #define UB960_RR_PORT_ISR_HI                    0xda
 341 #define UB960_RR_PORT_ISR_LO                    0xdb
 342 #define UB960_RR_FC_GPIO_STS                    0xdc
 343 #define UB960_RR_FC_GPIO_ICR                    0xdd
 344 #define UB960_RR_SEN_INT_RISE_STS               0xde
 345 #define UB960_RR_SEN_INT_FALL_STS               0xdf
 346
 347 #define UB960_RR_CHANNEL_MODE                   0xe4    /* UB9702 */
 348
 349 #define UB960_SR_FPD3_RX_ID(n)                  (0xf0 + (n))
 350 #define UB960_SR_FPD3_RX_ID_LEN                 6
 351
 352 #define UB960_SR_I2C_RX_ID(n)                   (0xf8 + (n)) /* < UB960_FPD_RX_NPORTS */
 353
 354 /* Indirect register blocks */
 355 #define UB960_IND_TARGET_PAT_GEN                0x00
 356 #define UB960_IND_TARGET_RX_ANA(n)              (0x01 + (n))
 357 #define UB960_IND_TARGET_CSI_CSIPLL_REG_1       0x92    /* UB9702 */
 358 #define UB960_IND_TARGET_CSI_ANA                0x07
 359
 360 /* UB960_IR_PGEN_*: Indirect Registers for Test Pattern Generator */
 361
 362 #define UB960_IR_PGEN_CTL                       0x01
 363 #define UB960_IR_PGEN_CTL_PGEN_ENABLE           BIT(0)
 364
 365 #define UB960_IR_PGEN_CFG                       0x02
 366 #define UB960_IR_PGEN_CSI_DI                    0x03
 367 #define UB960_IR_PGEN_LINE_SIZE1                0x04
 368 #define UB960_IR_PGEN_LINE_SIZE0                0x05
 369 #define UB960_IR_PGEN_BAR_SIZE1                 0x06
 370 #define UB960_IR_PGEN_BAR_SIZE0                 0x07
 371 #define UB960_IR_PGEN_ACT_LPF1                  0x08
 372 #define UB960_IR_PGEN_ACT_LPF0                  0x09
 373 #define UB960_IR_PGEN_TOT_LPF1                  0x0a
 374 #define UB960_IR_PGEN_TOT_LPF0                  0x0b
 375 #define UB960_IR_PGEN_LINE_PD1                  0x0c
 376 #define UB960_IR_PGEN_LINE_PD0                  0x0d
 377 #define UB960_IR_PGEN_VBP                       0x0e
 378 #define UB960_IR_PGEN_VFP                       0x0f
 379 #define UB960_IR_PGEN_COLOR(n)                  (0x10 + (n)) /* n < 15 */
 380
 381 #define UB960_IR_RX_ANA_STROBE_SET_CLK          0x08
 382 #define UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY   BIT(3)
 383 #define UB960_IR_RX_ANA_STROBE_SET_CLK_DELAY_MASK       GENMASK(2, 0)
 384
 385 #define UB960_IR_RX_ANA_STROBE_SET_DATA         0x09
 386 #define UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY  BIT(3)
 387 #define UB960_IR_RX_ANA_STROBE_SET_DATA_DELAY_MASK      GENMASK(2, 0)
 388
 389 /* EQ related */
 390
 391 #define UB960_MIN_AEQ_STROBE_POS -7
 392 #define UB960_MAX_AEQ_STROBE_POS  7
 393
 394 #define UB960_MANUAL_STROBE_EXTRA_DELAY 6
 395
 396 #define UB960_MIN_MANUAL_STROBE_POS -(7 + UB960_MANUAL_STROBE_EXTRA_DELAY)
 397 #define UB960_MAX_MANUAL_STROBE_POS  (7 + UB960_MANUAL_STROBE_EXTRA_DELAY)
 398 #define UB960_NUM_MANUAL_STROBE_POS  (UB960_MAX_MANUAL_STROBE_POS - UB960_MIN_MANUAL_STROBE_POS + 1)
 399
 400 #define UB960_MIN_EQ_LEVEL  0
 401 #define UB960_MAX_EQ_LEVEL  14
 402 #define UB960_NUM_EQ_LEVELS (UB960_MAX_EQ_LEVEL - UB960_MIN_EQ_LEVEL + 1)
 403
 404 struct ub960_hw_data {
 405         const char *model;
 406         u8 num_rxports;
 407         u8 num_txports;
 408         bool is_ub9702;
 409         bool is_fpdlink4;
 410 };
 411
 412 enum ub960_rxport_mode {
 413         RXPORT_MODE_RAW10 = 0,
 414         RXPORT_MODE_RAW12_HF = 1,
 415         RXPORT_MODE_RAW12_LF = 2,
 416         RXPORT_MODE_CSI2_SYNC = 3,
 417         RXPORT_MODE_CSI2_ASYNC = 4,
 418         RXPORT_MODE_LAST = RXPORT_MODE_CSI2_ASYNC,
 419 };
 420
 421 enum ub960_rxport_cdr {
 422         RXPORT_CDR_FPD3 = 0,
 423         RXPORT_CDR_FPD4 = 1,
 424         RXPORT_CDR_LAST = RXPORT_CDR_FPD4,
 425 };
 426
 427 struct ub960_rxport {
 428         struct ub960_data      *priv;
 429         u8                      nport;  /* RX port number, and index in priv->rxport[] */
 430
 431         struct {
 432                 struct v4l2_subdev *sd;
 433                 u16 pad;
 434                 struct fwnode_handle *ep_fwnode;
 435         } source;
 436
 437         /* Serializer */
 438         struct {
 439                 struct fwnode_handle *fwnode;
 440                 struct i2c_client *client;
 441                 unsigned short alias; /* I2C alias (lower 7 bits) */
 442                 struct ds90ub9xx_platform_data pdata;
 443         } ser;
 444
 445         enum ub960_rxport_mode  rx_mode;
 446         enum ub960_rxport_cdr   cdr_mode;
 447
 448         u8                      lv_fv_pol;      /* LV and FV polarities */
 449
 450         struct regulator        *vpoc;
 451
 452         /* EQ settings */
 453         struct {
 454                 bool manual_eq;
 455
 456                 s8 strobe_pos;
 457
 458                 union {
 459                         struct {
 460                                 u8 eq_level_min;
 461                                 u8 eq_level_max;
 462                         } aeq;
 463
 464                         struct {
 465                                 u8 eq_level;
 466                         } manual;
 467                 };
 468         } eq;
 469
 470         const struct i2c_client *aliased_clients[UB960_MAX_PORT_ALIASES];
 471 };
 472
 473 struct ub960_asd {
 474         struct v4l2_async_connection base;
 475         struct ub960_rxport *rxport;
 476 };
 477
 478 static inline struct ub960_asd *to_ub960_asd(struct v4l2_async_connection *asd)
 479 {
 480         return container_of(asd, struct ub960_asd, base);
 481 }
 482
 483 struct ub960_txport {
 484         struct ub960_data      *priv;
 485         u8                      nport;  /* TX port number, and index in priv->txport[] */
 486
 487         u32 num_data_lanes;
 488 };
 489
 490 struct ub960_data {
 491         const struct ub960_hw_data      *hw_data;
 492         struct i2c_client       *client; /* for shared local registers */
 493         struct regmap           *regmap;
 494
 495         /* lock for register access */
 496         struct mutex            reg_lock;
 497
 498         struct clk              *refclk;
 499
 500         struct regulator        *vddio;
 501
 502         struct gpio_desc        *pd_gpio;
 503         struct delayed_work     poll_work;
 504         struct ub960_rxport     *rxports[UB960_MAX_RX_NPORTS];
 505         struct ub960_txport     *txports[UB960_MAX_TX_NPORTS];
 506
 507         struct v4l2_subdev      sd;
 508         struct media_pad        pads[UB960_MAX_NPORTS];
 509
 510         struct v4l2_ctrl_handler   ctrl_handler;
 511         struct v4l2_async_notifier notifier;
 512
 513         u32 tx_data_rate;               /* Nominal data rate (Gb/s) */
 514         s64 tx_link_freq[1];
 515
 516         struct i2c_atr *atr;
 517
 518         struct {
 519                 u8 rxport;
 520                 u8 txport;
 521                 u8 indirect_target;
 522         } reg_current;
 523
 524         bool streaming;
 525
 526         u8 stored_fwd_ctl;
 527
 528         u64 stream_enable_mask[UB960_MAX_NPORTS];
 529
 530         /* These are common to all ports */
 531         struct {
 532                 bool manual;
 533
 534                 s8 min;
 535                 s8 max;
 536         } strobe;
 537 };
 538
 539 static inline struct ub960_data *sd_to_ub960(struct v4l2_subdev *sd)
 540 {
 541         return container_of(sd, struct ub960_data, sd);
 542 }
 543
 544 static inline bool ub960_pad_is_sink(struct ub960_data *priv, u32 pad)
 545 {
 546         return pad < priv->hw_data->num_rxports;
 547 }
 548
 549 static inline bool ub960_pad_is_source(struct ub960_data *priv, u32 pad)
 550 {
 551         return pad >= priv->hw_data->num_rxports;
 552 }
 553
 554 static inline unsigned int ub960_pad_to_port(struct ub960_data *priv, u32 pad)
 555 {
 556         if (ub960_pad_is_sink(priv, pad))
 557                 return pad;
 558         else
 559                 return pad - priv->hw_data->num_rxports;
 560 }
 561
 562 struct ub960_format_info {
 563         u32 code;
 564         u32 bpp;
 565         u8 datatype;
 566         bool meta;
 567 };
 568
 569 static const struct ub960_format_info ub960_formats[] = {
 570         { .code = MEDIA_BUS_FMT_YUYV8_1X16, .bpp = 16, .datatype = MIPI_CSI2_DT_YUV422_8B, },
 571         { .code = MEDIA_BUS_FMT_UYVY8_1X16, .bpp = 16, .datatype = MIPI_CSI2_DT_YUV422_8B, },
 572         { .code = MEDIA_BUS_FMT_VYUY8_1X16, .bpp = 16, .datatype = MIPI_CSI2_DT_YUV422_8B, },
 573         { .code = MEDIA_BUS_FMT_YVYU8_1X16, .bpp = 16, .datatype = MIPI_CSI2_DT_YUV422_8B, },
 574
 575         { .code = MEDIA_BUS_FMT_SBGGR12_1X12, .bpp = 12, .datatype = MIPI_CSI2_DT_RAW12, },
 576         { .code = MEDIA_BUS_FMT_SGBRG12_1X12, .bpp = 12, .datatype = MIPI_CSI2_DT_RAW12, },
 577         { .code = MEDIA_BUS_FMT_SGRBG12_1X12, .bpp = 12, .datatype = MIPI_CSI2_DT_RAW12, },
 578         { .code = MEDIA_BUS_FMT_SRGGB12_1X12, .bpp = 12, .datatype = MIPI_CSI2_DT_RAW12, },
 579 };
 580
 581 static const struct ub960_format_info *ub960_find_format(u32 code)
 582 {
 583         unsigned int i;
 584
 585         for (i = 0; i < ARRAY_SIZE(ub960_formats); i++) {
 586                 if (ub960_formats[i].code == code)
 587                         return &ub960_formats[i];
 588         }
 589
 590         return NULL;
 591 }
 592
 593 /* -----------------------------------------------------------------------------
 594  * Basic device access
 595  */
 596
 597 static int ub960_read(struct ub960_data *priv, u8 reg, u8 *val)
 598 {
 599         struct device *dev = &priv->client->dev;
 600         unsigned int v;
 601         int ret;
 602
 603         mutex_lock(&priv->reg_lock);
 604
 605         ret = regmap_read(priv->regmap, reg, &v);
 606         if (ret) {
 607                 dev_err(dev, "%s: cannot read register 0x%02x (%d)!\n",
 608                         __func__, reg, ret);
 609                 goto out_unlock;
 610         }
 611
 612         *val = v;
 613
 614 out_unlock:
 615         mutex_unlock(&priv->reg_lock);
 616
 617         return ret;
 618 }
 619
 620 static int ub960_write(struct ub960_data *priv, u8 reg, u8 val)
 621 {
 622         struct device *dev = &priv->client->dev;
 623         int ret;
 624
 625         mutex_lock(&priv->reg_lock);
 626
 627         ret = regmap_write(priv->regmap, reg, val);
 628         if (ret)
 629                 dev_err(dev, "%s: cannot write register 0x%02x (%d)!\n",
 630                         __func__, reg, ret);
 631
 632         mutex_unlock(&priv->reg_lock);
 633
 634         return ret;
 635 }
 636
 637 static int ub960_update_bits(struct ub960_data *priv, u8 reg, u8 mask, u8 val)
 638 {
 639         struct device *dev = &priv->client->dev;
 640         int ret;
 641
 642         mutex_lock(&priv->reg_lock);
 643
 644         ret = regmap_update_bits(priv->regmap, reg, mask, val);
 645         if (ret)
 646                 dev_err(dev, "%s: cannot update register 0x%02x (%d)!\n",
 647                         __func__, reg, ret);
 648
 649         mutex_unlock(&priv->reg_lock);
 650
 651         return ret;
 652 }
 653
 654 static int ub960_read16(struct ub960_data *priv, u8 reg, u16 *val)
 655 {
 656         struct device *dev = &priv->client->dev;
 657         __be16 __v;
 658         int ret;
 659
 660         mutex_lock(&priv->reg_lock);
 661
 662         ret = regmap_bulk_read(priv->regmap, reg, &__v, sizeof(__v));
 663         if (ret) {
 664                 dev_err(dev, "%s: cannot read register 0x%02x (%d)!\n",
 665                         __func__, reg, ret);
 666                 goto out_unlock;
 667         }
 668
 669         *val = be16_to_cpu(__v);
 670
 671 out_unlock:
 672         mutex_unlock(&priv->reg_lock);
 673
 674         return ret;
 675 }
 676
 677 static int ub960_rxport_select(struct ub960_data *priv, u8 nport)
 678 {
 679         struct device *dev = &priv->client->dev;
 680         int ret;
 681
 682         lockdep_assert_held(&priv->reg_lock);
 683
 684         if (priv->reg_current.rxport == nport)
 685                 return 0;
 686
 687         ret = regmap_write(priv->regmap, UB960_SR_FPD3_PORT_SEL,
 688                            (nport << 4) | BIT(nport));
 689         if (ret) {
 690                 dev_err(dev, "%s: cannot select rxport %d (%d)!\n", __func__,
 691                         nport, ret);
 692                 return ret;
 693         }
 694
 695         priv->reg_current.rxport = nport;
 696
 697         return 0;
 698 }
 699
 700 static int ub960_rxport_read(struct ub960_data *priv, u8 nport, u8 reg, u8 *val)
 701 {
 702         struct device *dev = &priv->client->dev;
 703         unsigned int v;
 704         int ret;
 705
 706         mutex_lock(&priv->reg_lock);
 707
 708         ret = ub960_rxport_select(priv, nport);
 709         if (ret)
 710                 goto out_unlock;
 711
 712         ret = regmap_read(priv->regmap, reg, &v);
 713         if (ret) {
 714                 dev_err(dev, "%s: cannot read register 0x%02x (%d)!\n",
 715                         __func__, reg, ret);
 716                 goto out_unlock;
 717         }
 718
 719         *val = v;
 720
 721 out_unlock:
 722         mutex_unlock(&priv->reg_lock);
 723
 724         return ret;
 725 }
 726
 727 static int ub960_rxport_write(struct ub960_data *priv, u8 nport, u8 reg, u8 val)
 728 {
 729         struct device *dev = &priv->client->dev;
 730         int ret;
 731
 732         mutex_lock(&priv->reg_lock);
 733
 734         ret = ub960_rxport_select(priv, nport);
 735         if (ret)
 736                 goto out_unlock;
 737
 738         ret = regmap_write(priv->regmap, reg, val);
 739         if (ret)
 740                 dev_err(dev, "%s: cannot write register 0x%02x (%d)!\n",
 741                         __func__, reg, ret);
 742
 743 out_unlock:
 744         mutex_unlock(&priv->reg_lock);
 745
 746         return ret;
 747 }
 748
 749 static int ub960_rxport_update_bits(struct ub960_data *priv, u8 nport, u8 reg,
 750                                     u8 mask, u8 val)
 751 {
 752         struct device *dev = &priv->client->dev;
 753         int ret;
 754
 755         mutex_lock(&priv->reg_lock);
 756
 757         ret = ub960_rxport_select(priv, nport);
 758         if (ret)
 759                 goto out_unlock;
 760
 761         ret = regmap_update_bits(priv->regmap, reg, mask, val);
 762         if (ret)
 763                 dev_err(dev, "%s: cannot update register 0x%02x (%d)!\n",
 764                         __func__, reg, ret);
 765
 766 out_unlock:
 767         mutex_unlock(&priv->reg_lock);
 768
 769         return ret;
 770 }
 771
 772 static int ub960_rxport_read16(struct ub960_data *priv, u8 nport, u8 reg,
 773                                u16 *val)
 774 {
 775         struct device *dev = &priv->client->dev;
 776         __be16 __v;
 777         int ret;
 778
 779         mutex_lock(&priv->reg_lock);
 780
 781         ret = ub960_rxport_select(priv, nport);
 782         if (ret)
 783                 goto out_unlock;
 784
 785         ret = regmap_bulk_read(priv->regmap, reg, &__v, sizeof(__v));
 786         if (ret) {
 787                 dev_err(dev, "%s: cannot read register 0x%02x (%d)!\n",
 788                         __func__, reg, ret);
 789                 goto out_unlock;
 790         }
 791
 792         *val = be16_to_cpu(__v);
 793
 794 out_unlock:
 795         mutex_unlock(&priv->reg_lock);
 796
 797         return ret;
 798 }
 799
 800 static int ub960_txport_select(struct ub960_data *priv, u8 nport)
 801 {
 802         struct device *dev = &priv->client->dev;
 803         int ret;
 804
 805         lockdep_assert_held(&priv->reg_lock);
 806
 807         if (priv->reg_current.txport == nport)
 808                 return 0;
 809
 810         ret = regmap_write(priv->regmap, UB960_SR_CSI_PORT_SEL,
 811                            (nport << 4) | BIT(nport));
 812         if (ret) {
 813                 dev_err(dev, "%s: cannot select tx port %d (%d)!\n", __func__,
 814                         nport, ret);
 815                 return ret;
 816         }
 817
 818         priv->reg_current.txport = nport;
 819
 820         return 0;
 821 }
 822
 823 static int ub960_txport_read(struct ub960_data *priv, u8 nport, u8 reg, u8 *val)
 824 {
 825         struct device *dev = &priv->client->dev;
 826         unsigned int v;
 827         int ret;
 828
 829         mutex_lock(&priv->reg_lock);
 830
 831         ret = ub960_txport_select(priv, nport);
 832         if (ret)
 833                 goto out_unlock;
 834
 835         ret = regmap_read(priv->regmap, reg, &v);
 836         if (ret) {
 837                 dev_err(dev, "%s: cannot read register 0x%02x (%d)!\n",
 838                         __func__, reg, ret);
 839                 goto out_unlock;
 840         }
 841
 842         *val = v;
 843
 844 out_unlock:
 845         mutex_unlock(&priv->reg_lock);
 846
 847         return ret;
 848 }
 849
 850 static int ub960_txport_write(struct ub960_data *priv, u8 nport, u8 reg, u8 val)
 851 {
 852         struct device *dev = &priv->client->dev;
 853         int ret;
 854
 855         mutex_lock(&priv->reg_lock);
 856
 857         ret = ub960_txport_select(priv, nport);
 858         if (ret)
 859                 goto out_unlock;
 860
 861         ret = regmap_write(priv->regmap, reg, val);
 862         if (ret)
 863                 dev_err(dev, "%s: cannot write register 0x%02x (%d)!\n",
 864                         __func__, reg, ret);
 865
 866 out_unlock:
 867         mutex_unlock(&priv->reg_lock);
 868
 869         return ret;
 870 }
 871
 872 static int ub960_txport_update_bits(struct ub960_data *priv, u8 nport, u8 reg,
 873                                     u8 mask, u8 val)
 874 {
 875         struct device *dev = &priv->client->dev;
 876         int ret;
 877
 878         mutex_lock(&priv->reg_lock);
 879
 880         ret = ub960_txport_select(priv, nport);
 881         if (ret)
 882                 goto out_unlock;
 883
 884         ret = regmap_update_bits(priv->regmap, reg, mask, val);
 885         if (ret)
 886                 dev_err(dev, "%s: cannot update register 0x%02x (%d)!\n",
 887                         __func__, reg, ret);
 888
 889 out_unlock:
 890         mutex_unlock(&priv->reg_lock);
 891
 892         return ret;
 893 }
 894
 895 static int ub960_select_ind_reg_block(struct ub960_data *priv, u8 block)
 896 {
 897         struct device *dev = &priv->client->dev;
 898         int ret;
 899
 900         lockdep_assert_held(&priv->reg_lock);
 901
 902         if (priv->reg_current.indirect_target == block)
 903                 return 0;
 904
 905         ret = regmap_write(priv->regmap, UB960_SR_IND_ACC_CTL, block << 2);
 906         if (ret) {
 907                 dev_err(dev, "%s: cannot select indirect target %u (%d)!\n",
 908                         __func__, block, ret);
 909                 return ret;
 910         }
 911
 912         priv->reg_current.indirect_target = block;
 913
 914         return 0;
 915 }
 916
 917 static int ub960_read_ind(struct ub960_data *priv, u8 block, u8 reg, u8 *val)
 918 {
 919         struct device *dev = &priv->client->dev;
 920         unsigned int v;
 921         int ret;
 922
 923         mutex_lock(&priv->reg_lock);
 924
 925         ret = ub960_select_ind_reg_block(priv, block);
 926         if (ret)
 927                 goto out_unlock;
 928
 929         ret = regmap_write(priv->regmap, UB960_SR_IND_ACC_ADDR, reg);
 930         if (ret) {
 931                 dev_err(dev,
 932                         "Write to IND_ACC_ADDR failed when reading %u:%x02x: %d\n",
 933                         block, reg, ret);
 934                 goto out_unlock;
 935         }
 936
 937         ret = regmap_read(priv->regmap, UB960_SR_IND_ACC_DATA, &v);
 938         if (ret) {
 939                 dev_err(dev,
 940                         "Write to IND_ACC_DATA failed when reading %u:%x02x: %d\n",
 941                         block, reg, ret);
 942                 goto out_unlock;
 943         }
 944
 945         *val = v;
 946
 947 out_unlock:
 948         mutex_unlock(&priv->reg_lock);
 949
 950         return ret;
 951 }
 952
 953 static int ub960_write_ind(struct ub960_data *priv, u8 block, u8 reg, u8 val)
 954 {
 955         struct device *dev = &priv->client->dev;
 956         int ret;
 957
 958         mutex_lock(&priv->reg_lock);
 959
 960         ret = ub960_select_ind_reg_block(priv, block);
 961         if (ret)
 962                 goto out_unlock;
 963
 964         ret = regmap_write(priv->regmap, UB960_SR_IND_ACC_ADDR, reg);
 965         if (ret) {
 966                 dev_err(dev,
 967                         "Write to IND_ACC_ADDR failed when writing %u:%x02x: %d\n",
 968                         block, reg, ret);
 969                 goto out_unlock;
 970         }
 971
 972         ret = regmap_write(priv->regmap, UB960_SR_IND_ACC_DATA, val);
 973         if (ret) {
 974                 dev_err(dev,
 975                         "Write to IND_ACC_DATA failed when writing %u:%x02x: %d\n",
 976                         block, reg, ret);
 977                 goto out_unlock;
 978         }
 979
 980 out_unlock:
 981         mutex_unlock(&priv->reg_lock);
 982
 983         return ret;
 984 }
 985
 986 static int ub960_ind_update_bits(struct ub960_data *priv, u8 block, u8 reg,
 987                                  u8 mask, u8 val)
 988 {
 989         struct device *dev = &priv->client->dev;
 990         int ret;
 991
 992         mutex_lock(&priv->reg_lock);
 993
 994         ret = ub960_select_ind_reg_block(priv, block);
 995         if (ret)
 996                 goto out_unlock;
 997
 998         ret = regmap_write(priv->regmap, UB960_SR_IND_ACC_ADDR, reg);
 999         if (ret) {
1000                 dev_err(dev,
1001                         "Write to IND_ACC_ADDR failed when updating %u:%x02x: %d\n",
1002                         block, reg, ret);
1003                 goto out_unlock;
1004         }
1005
1006         ret = regmap_update_bits(priv->regmap, UB960_SR_IND_ACC_DATA, mask,
1007                                  val);
1008         if (ret) {
1009                 dev_err(dev,
1010                         "Write to IND_ACC_DATA failed when updating %u:%x02x: %d\n",
1011                         block, reg, ret);
1012                 goto out_unlock;
1013         }
1014
1015 out_unlock:
1016         mutex_unlock(&priv->reg_lock);
1017
1018         return ret;
1019 }
1020
1021 /* -----------------------------------------------------------------------------
1022  * I2C-ATR (address translator)
1023  */
1024
1025 static int ub960_atr_attach_client(struct i2c_atr *atr, u32 chan_id,
1026                                    const struct i2c_client *client, u16 alias)
1027 {
1028         struct ub960_data *priv = i2c_atr_get_driver_data(atr);
1029         struct ub960_rxport *rxport = priv->rxports[chan_id];
1030         struct device *dev = &priv->client->dev;
1031         unsigned int reg_idx;
1032
1033         for (reg_idx = 0; reg_idx < ARRAY_SIZE(rxport->aliased_clients); reg_idx++) {
1034                 if (!rxport->aliased_clients[reg_idx])
1035                         break;
1036         }
1037
1038         if (reg_idx == ARRAY_SIZE(rxport->aliased_clients)) {
1039                 dev_err(dev, "rx%u: alias pool exhausted\n", rxport->nport);
1040                 return -EADDRNOTAVAIL;
1041         }
1042
1043         rxport->aliased_clients[reg_idx] = client;
1044
1045         ub960_rxport_write(priv, chan_id, UB960_RR_SLAVE_ID(reg_idx),
1046                            client->addr << 1);
1047         ub960_rxport_write(priv, chan_id, UB960_RR_SLAVE_ALIAS(reg_idx),
1048                            alias << 1);
1049
1050         dev_dbg(dev, "rx%u: client 0x%02x assigned alias 0x%02x at slot %u\n",
1051                 rxport->nport, client->addr, alias, reg_idx);
1052
1053         return 0;
1054 }
1055
1056 static void ub960_atr_detach_client(struct i2c_atr *atr, u32 chan_id,
1057                                     const struct i2c_client *client)
1058 {
1059         struct ub960_data *priv = i2c_atr_get_driver_data(atr);
1060         struct ub960_rxport *rxport = priv->rxports[chan_id];
1061         struct device *dev = &priv->client->dev;
1062         unsigned int reg_idx;
1063
1064         for (reg_idx = 0; reg_idx < ARRAY_SIZE(rxport->aliased_clients); reg_idx++) {
1065                 if (rxport->aliased_clients[reg_idx] == client)
1066                         break;
1067         }
1068
1069         if (reg_idx == ARRAY_SIZE(rxport->aliased_clients)) {
1070                 dev_err(dev, "rx%u: client 0x%02x is not mapped!\n",
1071                         rxport->nport, client->addr);
1072                 return;
1073         }
1074
1075         rxport->aliased_clients[reg_idx] = NULL;
1076
1077         ub960_rxport_write(priv, chan_id, UB960_RR_SLAVE_ALIAS(reg_idx), 0);
1078
1079         dev_dbg(dev, "rx%u: client 0x%02x released at slot %u\n", rxport->nport,
1080                 client->addr, reg_idx);
1081 }
1082
1083 static const struct i2c_atr_ops ub960_atr_ops = {
1084         .attach_client = ub960_atr_attach_client,
1085         .detach_client = ub960_atr_detach_client,
1086 };
1087
1088 static int ub960_init_atr(struct ub960_data *priv)
1089 {
1090         struct device *dev = &priv->client->dev;
1091         struct i2c_adapter *parent_adap = priv->client->adapter;
1092
1093         priv->atr = i2c_atr_new(parent_adap, dev, &ub960_atr_ops,
1094                                 priv->hw_data->num_rxports);
1095         if (IS_ERR(priv->atr))
1096                 return PTR_ERR(priv->atr);
1097
1098         i2c_atr_set_driver_data(priv->atr, priv);
1099
1100         return 0;
1101 }
1102
1103 static void ub960_uninit_atr(struct ub960_data *priv)
1104 {
1105         i2c_atr_delete(priv->atr);
1106         priv->atr = NULL;
1107 }
1108
1109 /* -----------------------------------------------------------------------------
1110  * TX ports
1111  */
1112
1113 static int ub960_parse_dt_txport(struct ub960_data *priv,
1114                                  struct fwnode_handle *ep_fwnode,
1115                                  u8 nport)
1116 {
1117         struct device *dev = &priv->client->dev;
1118         struct v4l2_fwnode_endpoint vep = {};
1119         struct ub960_txport *txport;
1120         int ret;
1121
1122         txport = kzalloc(sizeof(*txport), GFP_KERNEL);
1123         if (!txport)
1124                 return -ENOMEM;
1125
1126         txport->priv = priv;
1127         txport->nport = nport;
1128
1129         vep.bus_type = V4L2_MBUS_CSI2_DPHY;
1130         ret = v4l2_fwnode_endpoint_alloc_parse(ep_fwnode, &vep);
1131         if (ret) {
1132                 dev_err(dev, "tx%u: failed to parse endpoint data\n", nport);
1133                 goto err_free_txport;
1134         }
1135
1136         txport->num_data_lanes = vep.bus.mipi_csi2.num_data_lanes;
1137
1138         if (vep.nr_of_link_frequencies != 1) {
1139                 ret = -EINVAL;
1140                 goto err_free_vep;
1141         }
1142
1143         priv->tx_link_freq[0] = vep.link_frequencies[0];
1144         priv->tx_data_rate = priv->tx_link_freq[0] * 2;
1145
1146         if (priv->tx_data_rate != MHZ(1600) &&
1147             priv->tx_data_rate != MHZ(1200) &&
1148             priv->tx_data_rate != MHZ(800) &&
1149             priv->tx_data_rate != MHZ(400)) {
1150                 dev_err(dev, "tx%u: invalid 'link-frequencies' value\n", nport);
1151                 ret = -EINVAL;
1152                 goto err_free_vep;
1153         }
1154
1155         v4l2_fwnode_endpoint_free(&vep);
1156
1157         priv->txports[nport] = txport;
1158
1159         return 0;
1160
1161 err_free_vep:
1162         v4l2_fwnode_endpoint_free(&vep);
1163 err_free_txport:
1164         kfree(txport);
1165
1166         return ret;
1167 }
1168
1169 static void ub960_csi_handle_events(struct ub960_data *priv, u8 nport)
1170 {
1171         struct device *dev = &priv->client->dev;
1172         u8 csi_tx_isr;
1173         int ret;
1174
1175         ret = ub960_txport_read(priv, nport, UB960_TR_CSI_TX_ISR, &csi_tx_isr);
1176         if (ret)
1177                 return;
1178
1179         if (csi_tx_isr & UB960_TR_CSI_TX_ISR_IS_CSI_SYNC_ERROR)
1180                 dev_warn(dev, "TX%u: CSI_SYNC_ERROR\n", nport);
1181
1182         if (csi_tx_isr & UB960_TR_CSI_TX_ISR_IS_CSI_PASS_ERROR)
1183                 dev_warn(dev, "TX%u: CSI_PASS_ERROR\n", nport);
1184 }
1185
1186 /* -----------------------------------------------------------------------------
1187  * RX ports
1188  */
1189
1190 static int ub960_rxport_enable_vpocs(struct ub960_data *priv)
1191 {
1192         unsigned int nport;
1193         int ret;
1194
1195         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
1196                 struct ub960_rxport *rxport = priv->rxports[nport];
1197
1198                 if (!rxport || !rxport->vpoc)
1199                         continue;
1200
1201                 ret = regulator_enable(rxport->vpoc);
1202                 if (ret)
1203                         goto err_disable_vpocs;
1204         }
1205
1206         return 0;
1207
1208 err_disable_vpocs:
1209         while (nport--) {
1210                 struct ub960_rxport *rxport = priv->rxports[nport];
1211
1212                 if (!rxport || !rxport->vpoc)
1213                         continue;
1214
1215                 regulator_disable(rxport->vpoc);
1216         }
1217
1218         return ret;
1219 }
1220
1221 static void ub960_rxport_disable_vpocs(struct ub960_data *priv)
1222 {
1223         unsigned int nport;
1224
1225         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
1226                 struct ub960_rxport *rxport = priv->rxports[nport];
1227
1228                 if (!rxport || !rxport->vpoc)
1229                         continue;
1230
1231                 regulator_disable(rxport->vpoc);
1232         }
1233 }
1234
1235 static void ub960_rxport_clear_errors(struct ub960_data *priv,
1236                                       unsigned int nport)
1237 {
1238         u8 v;
1239
1240         ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1, &v);
1241         ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2, &v);
1242         ub960_rxport_read(priv, nport, UB960_RR_CSI_RX_STS, &v);
1243         ub960_rxport_read(priv, nport, UB960_RR_BCC_STATUS, &v);
1244
1245         ub960_rxport_read(priv, nport, UB960_RR_RX_PAR_ERR_HI, &v);
1246         ub960_rxport_read(priv, nport, UB960_RR_RX_PAR_ERR_LO, &v);
1247
1248         ub960_rxport_read(priv, nport, UB960_RR_CSI_ERR_COUNTER, &v);
1249 }
1250
1251 static void ub960_clear_rx_errors(struct ub960_data *priv)
1252 {
1253         unsigned int nport;
1254
1255         for (nport = 0; nport < priv->hw_data->num_rxports; nport++)
1256                 ub960_rxport_clear_errors(priv, nport);
1257 }
1258
1259 static int ub960_rxport_get_strobe_pos(struct ub960_data *priv,
1260                                        unsigned int nport, s8 *strobe_pos)
1261 {
1262         u8 v;
1263         u8 clk_delay, data_delay;
1264         int ret;
1265
1266         ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
1267                        UB960_IR_RX_ANA_STROBE_SET_CLK, &v);
1268
1269         clk_delay = (v & UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY) ?
1270                             0 : UB960_MANUAL_STROBE_EXTRA_DELAY;
1271
1272         ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
1273                        UB960_IR_RX_ANA_STROBE_SET_DATA, &v);
1274
1275         data_delay = (v & UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY) ?
1276                              0 : UB960_MANUAL_STROBE_EXTRA_DELAY;
1277
1278         ret = ub960_rxport_read(priv, nport, UB960_RR_SFILTER_STS_0, &v);
1279         if (ret)
1280                 return ret;
1281
1282         clk_delay += v & UB960_IR_RX_ANA_STROBE_SET_CLK_DELAY_MASK;
1283
1284         ub960_rxport_read(priv, nport, UB960_RR_SFILTER_STS_1, &v);
1285         if (ret)
1286                 return ret;
1287
1288         data_delay += v & UB960_IR_RX_ANA_STROBE_SET_DATA_DELAY_MASK;
1289
1290         *strobe_pos = data_delay - clk_delay;
1291
1292         return 0;
1293 }
1294
1295 static void ub960_rxport_set_strobe_pos(struct ub960_data *priv,
1296                                         unsigned int nport, s8 strobe_pos)
1297 {
1298         u8 clk_delay, data_delay;
1299
1300         clk_delay = UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY;
1301         data_delay = UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY;
1302
1303         if (strobe_pos < UB960_MIN_AEQ_STROBE_POS)
1304                 clk_delay = abs(strobe_pos) - UB960_MANUAL_STROBE_EXTRA_DELAY;
1305         else if (strobe_pos > UB960_MAX_AEQ_STROBE_POS)
1306                 data_delay = strobe_pos - UB960_MANUAL_STROBE_EXTRA_DELAY;
1307         else if (strobe_pos < 0)
1308                 clk_delay = abs(strobe_pos) | UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY;
1309         else if (strobe_pos > 0)
1310                 data_delay = strobe_pos | UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY;
1311
1312         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
1313                         UB960_IR_RX_ANA_STROBE_SET_CLK, clk_delay);
1314
1315         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
1316                         UB960_IR_RX_ANA_STROBE_SET_DATA, data_delay);
1317 }
1318
1319 static void ub960_rxport_set_strobe_range(struct ub960_data *priv,
1320                                           s8 strobe_min, s8 strobe_max)
1321 {
1322         /* Convert the signed strobe pos to positive zero based value */
1323         strobe_min -= UB960_MIN_AEQ_STROBE_POS;
1324         strobe_max -= UB960_MIN_AEQ_STROBE_POS;
1325
1326         ub960_write(priv, UB960_XR_SFILTER_CFG,
1327                     ((u8)strobe_min << UB960_XR_SFILTER_CFG_SFILTER_MIN_SHIFT) |
1328                     ((u8)strobe_max << UB960_XR_SFILTER_CFG_SFILTER_MAX_SHIFT));
1329 }
1330
1331 static int ub960_rxport_get_eq_level(struct ub960_data *priv,
1332                                      unsigned int nport, u8 *eq_level)
1333 {
1334         int ret;
1335         u8 v;
1336
1337         ret = ub960_rxport_read(priv, nport, UB960_RR_AEQ_STATUS, &v);
1338         if (ret)
1339                 return ret;
1340
1341         *eq_level = (v & UB960_RR_AEQ_STATUS_STATUS_1) +
1342                     (v & UB960_RR_AEQ_STATUS_STATUS_2);
1343
1344         return 0;
1345 }
1346
1347 static void ub960_rxport_set_eq_level(struct ub960_data *priv,
1348                                       unsigned int nport, u8 eq_level)
1349 {
1350         u8 eq_stage_1_select_value, eq_stage_2_select_value;
1351         const unsigned int eq_stage_max = 7;
1352         u8 v;
1353
1354         if (eq_level <= eq_stage_max) {
1355                 eq_stage_1_select_value = eq_level;
1356                 eq_stage_2_select_value = 0;
1357         } else {
1358                 eq_stage_1_select_value = eq_stage_max;
1359                 eq_stage_2_select_value = eq_level - eq_stage_max;
1360         }
1361
1362         ub960_rxport_read(priv, nport, UB960_RR_AEQ_BYPASS, &v);
1363
1364         v &= ~(UB960_RR_AEQ_BYPASS_EQ_STAGE1_VALUE_MASK |
1365                UB960_RR_AEQ_BYPASS_EQ_STAGE2_VALUE_MASK);
1366         v |= eq_stage_1_select_value << UB960_RR_AEQ_BYPASS_EQ_STAGE1_VALUE_SHIFT;
1367         v |= eq_stage_2_select_value << UB960_RR_AEQ_BYPASS_EQ_STAGE2_VALUE_SHIFT;
1368         v |= UB960_RR_AEQ_BYPASS_ENABLE;
1369
1370         ub960_rxport_write(priv, nport, UB960_RR_AEQ_BYPASS, v);
1371 }
1372
1373 static void ub960_rxport_set_eq_range(struct ub960_data *priv,
1374                                       unsigned int nport, u8 eq_min, u8 eq_max)
1375 {
1376         ub960_rxport_write(priv, nport, UB960_RR_AEQ_MIN_MAX,
1377                            (eq_min << UB960_RR_AEQ_MIN_MAX_AEQ_FLOOR_SHIFT) |
1378                            (eq_max << UB960_RR_AEQ_MIN_MAX_AEQ_MAX_SHIFT));
1379
1380         /* Enable AEQ min setting */
1381         ub960_rxport_update_bits(priv, nport, UB960_RR_AEQ_CTL2,
1382                                  UB960_RR_AEQ_CTL2_SET_AEQ_FLOOR,
1383                                  UB960_RR_AEQ_CTL2_SET_AEQ_FLOOR);
1384 }
1385
1386 static void ub960_rxport_config_eq(struct ub960_data *priv, unsigned int nport)
1387 {
1388         struct ub960_rxport *rxport = priv->rxports[nport];
1389
1390         /* We also set common settings here. Should be moved elsewhere. */
1391
1392         if (priv->strobe.manual) {
1393                 /* Disable AEQ_SFILTER_EN */
1394                 ub960_update_bits(priv, UB960_XR_AEQ_CTL1,
1395                                   UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN, 0);
1396         } else {
1397                 /* Enable SFILTER and error control */
1398                 ub960_write(priv, UB960_XR_AEQ_CTL1,
1399                             UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_MASK |
1400                                     UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN);
1401
1402                 /* Set AEQ strobe range */
1403                 ub960_rxport_set_strobe_range(priv, priv->strobe.min,
1404                                               priv->strobe.max);
1405         }
1406
1407         /* The rest are port specific */
1408
1409         if (priv->strobe.manual)
1410                 ub960_rxport_set_strobe_pos(priv, nport, rxport->eq.strobe_pos);
1411         else
1412                 ub960_rxport_set_strobe_pos(priv, nport, 0);
1413
1414         if (rxport->eq.manual_eq) {
1415                 ub960_rxport_set_eq_level(priv, nport,
1416                                           rxport->eq.manual.eq_level);
1417
1418                 /* Enable AEQ Bypass */
1419                 ub960_rxport_update_bits(priv, nport, UB960_RR_AEQ_BYPASS,
1420                                          UB960_RR_AEQ_BYPASS_ENABLE,
1421                                          UB960_RR_AEQ_BYPASS_ENABLE);
1422         } else {
1423                 ub960_rxport_set_eq_range(priv, nport,
1424                                           rxport->eq.aeq.eq_level_min,
1425                                           rxport->eq.aeq.eq_level_max);
1426
1427                 /* Disable AEQ Bypass */
1428                 ub960_rxport_update_bits(priv, nport, UB960_RR_AEQ_BYPASS,
1429                                          UB960_RR_AEQ_BYPASS_ENABLE, 0);
1430         }
1431 }
1432
1433 static int ub960_rxport_link_ok(struct ub960_data *priv, unsigned int nport,
1434                                 bool *ok)
1435 {
1436         u8 rx_port_sts1, rx_port_sts2;
1437         u16 parity_errors;
1438         u8 csi_rx_sts;
1439         u8 csi_err_cnt;
1440         u8 bcc_sts;
1441         int ret;
1442         bool errors;
1443
1444         ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1,
1445                                 &rx_port_sts1);
1446         if (ret)
1447                 return ret;
1448
1449         if (!(rx_port_sts1 & UB960_RR_RX_PORT_STS1_LOCK_STS)) {
1450                 *ok = false;
1451                 return 0;
1452         }
1453
1454         ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2,
1455                                 &rx_port_sts2);
1456         if (ret)
1457                 return ret;
1458
1459         ret = ub960_rxport_read(priv, nport, UB960_RR_CSI_RX_STS, &csi_rx_sts);
1460         if (ret)
1461                 return ret;
1462
1463         ret = ub960_rxport_read(priv, nport, UB960_RR_CSI_ERR_COUNTER,
1464                                 &csi_err_cnt);
1465         if (ret)
1466                 return ret;
1467
1468         ret = ub960_rxport_read(priv, nport, UB960_RR_BCC_STATUS, &bcc_sts);
1469         if (ret)
1470                 return ret;
1471
1472         ret = ub960_rxport_read16(priv, nport, UB960_RR_RX_PAR_ERR_HI,
1473                                   &parity_errors);
1474         if (ret)
1475                 return ret;
1476
1477         errors = (rx_port_sts1 & UB960_RR_RX_PORT_STS1_ERROR_MASK) ||
1478                  (rx_port_sts2 & UB960_RR_RX_PORT_STS2_ERROR_MASK) ||
1479                  (bcc_sts & UB960_RR_BCC_STATUS_ERROR_MASK) ||
1480                  (csi_rx_sts & UB960_RR_CSI_RX_STS_ERROR_MASK) || csi_err_cnt ||
1481                  parity_errors;
1482
1483         *ok = !errors;
1484
1485         return 0;
1486 }
1487
1488 /*
1489  * Wait for the RX ports to lock, have no errors and have stable strobe position
1490  * and EQ level.
1491  */
1492 static int ub960_rxport_wait_locks(struct ub960_data *priv,
1493                                    unsigned long port_mask,
1494                                    unsigned int *lock_mask)
1495 {
1496         struct device *dev = &priv->client->dev;
1497         unsigned long timeout;
1498         unsigned int link_ok_mask;
1499         unsigned int missing;
1500         unsigned int loops;
1501         u8 nport;
1502         int ret;
1503
1504         if (port_mask == 0) {
1505                 if (lock_mask)
1506                         *lock_mask = 0;
1507                 return 0;
1508         }
1509
1510         if (port_mask >= BIT(priv->hw_data->num_rxports))
1511                 return -EINVAL;
1512
1513         timeout = jiffies + msecs_to_jiffies(1000);
1514         loops = 0;
1515         link_ok_mask = 0;
1516
1517         while (time_before(jiffies, timeout)) {
1518                 missing = 0;
1519
1520                 for_each_set_bit(nport, &port_mask,
1521                                  priv->hw_data->num_rxports) {
1522                         struct ub960_rxport *rxport = priv->rxports[nport];
1523                         bool ok;
1524
1525                         if (!rxport)
1526                                 continue;
1527
1528                         ret = ub960_rxport_link_ok(priv, nport, &ok);
1529                         if (ret)
1530                                 return ret;
1531
1532                         /*
1533                          * We want the link to be ok for two consecutive loops,
1534                          * as a link could get established just before our test
1535                          * and drop soon after.
1536                          */
1537                         if (!ok || !(link_ok_mask & BIT(nport)))
1538                                 missing++;
1539
1540                         if (ok)
1541                                 link_ok_mask |= BIT(nport);
1542                         else
1543                                 link_ok_mask &= ~BIT(nport);
1544                 }
1545
1546                 loops++;
1547
1548                 if (missing == 0)
1549                         break;
1550
1551                 msleep(50);
1552         }
1553
1554         if (lock_mask)
1555                 *lock_mask = link_ok_mask;
1556
1557         dev_dbg(dev, "Wait locks done in %u loops\n", loops);
1558         for_each_set_bit(nport, &port_mask, priv->hw_data->num_rxports) {
1559                 struct ub960_rxport *rxport = priv->rxports[nport];
1560                 s8 strobe_pos, eq_level;
1561                 u16 v;
1562
1563                 if (!rxport)
1564                         continue;
1565
1566                 if (!(link_ok_mask & BIT(nport))) {
1567                         dev_dbg(dev, "\trx%u: not locked\n", nport);
1568                         continue;
1569                 }
1570
1571                 ub960_rxport_read16(priv, nport, UB960_RR_RX_FREQ_HIGH, &v);
1572
1573                 ret = ub960_rxport_get_strobe_pos(priv, nport, &strobe_pos);
1574                 if (ret)
1575                         return ret;
1576
1577                 ret = ub960_rxport_get_eq_level(priv, nport, &eq_level);
1578                 if (ret)
1579                         return ret;
1580
1581                 dev_dbg(dev, "\trx%u: locked, SP: %d, EQ: %u, freq %llu Hz\n",
1582                         nport, strobe_pos, eq_level, (v * 1000000ULL) >> 8);
1583         }
1584
1585         return 0;
1586 }
1587
1588 static unsigned long ub960_calc_bc_clk_rate_ub960(struct ub960_data *priv,
1589                                                   struct ub960_rxport *rxport)
1590 {
1591         unsigned int mult;
1592         unsigned int div;
1593
1594         switch (rxport->rx_mode) {
1595         case RXPORT_MODE_RAW10:
1596         case RXPORT_MODE_RAW12_HF:
1597         case RXPORT_MODE_RAW12_LF:
1598                 mult = 1;
1599                 div = 10;
1600                 break;
1601
1602         case RXPORT_MODE_CSI2_SYNC:
1603                 mult = 2;
1604                 div = 1;
1605                 break;
1606
1607         case RXPORT_MODE_CSI2_ASYNC:
1608                 mult = 2;
1609                 div = 5;
1610                 break;
1611
1612         default:
1613                 return 0;
1614         }
1615
1616         return clk_get_rate(priv->refclk) * mult / div;
1617 }
1618
1619 static unsigned long ub960_calc_bc_clk_rate_ub9702(struct ub960_data *priv,
1620                                                    struct ub960_rxport *rxport)
1621 {
1622         switch (rxport->rx_mode) {
1623         case RXPORT_MODE_RAW10:
1624         case RXPORT_MODE_RAW12_HF:
1625         case RXPORT_MODE_RAW12_LF:
1626                 return 2359400;
1627
1628         case RXPORT_MODE_CSI2_SYNC:
1629                 return 47187500;
1630
1631         case RXPORT_MODE_CSI2_ASYNC:
1632                 return 9437500;
1633
1634         default:
1635                 return 0;
1636         }
1637 }
1638
1639 static int ub960_rxport_add_serializer(struct ub960_data *priv, u8 nport)
1640 {
1641         struct ub960_rxport *rxport = priv->rxports[nport];
1642         struct device *dev = &priv->client->dev;
1643         struct ds90ub9xx_platform_data *ser_pdata = &rxport->ser.pdata;
1644         struct i2c_board_info ser_info = {
1645                 .of_node = to_of_node(rxport->ser.fwnode),
1646                 .fwnode = rxport->ser.fwnode,
1647                 .platform_data = ser_pdata,
1648         };
1649
1650         ser_pdata->port = nport;
1651         ser_pdata->atr = priv->atr;
1652         if (priv->hw_data->is_ub9702)
1653                 ser_pdata->bc_rate = ub960_calc_bc_clk_rate_ub9702(priv, rxport);
1654         else
1655                 ser_pdata->bc_rate = ub960_calc_bc_clk_rate_ub960(priv, rxport);
1656
1657         /*
1658          * The serializer is added under the same i2c adapter as the
1659          * deserializer. This is not quite right, as the serializer is behind
1660          * the FPD-Link.
1661          */
1662         ser_info.addr = rxport->ser.alias;
1663         rxport->ser.client =
1664                 i2c_new_client_device(priv->client->adapter, &ser_info);
1665         if (IS_ERR(rxport->ser.client)) {
1666                 dev_err(dev, "rx%u: cannot add %s i2c device", nport,
1667                         ser_info.type);
1668                 return PTR_ERR(rxport->ser.client);
1669         }
1670
1671         dev_dbg(dev, "rx%u: remote serializer at alias 0x%02x (%u-%04x)\n",
1672                 nport, rxport->ser.client->addr,
1673                 rxport->ser.client->adapter->nr, rxport->ser.client->addr);
1674
1675         return 0;
1676 }
1677
1678 static void ub960_rxport_remove_serializer(struct ub960_data *priv, u8 nport)
1679 {
1680         struct ub960_rxport *rxport = priv->rxports[nport];
1681
1682         i2c_unregister_device(rxport->ser.client);
1683         rxport->ser.client = NULL;
1684 }
1685
1686 /* Add serializer i2c devices for all initialized ports */
1687 static int ub960_rxport_add_serializers(struct ub960_data *priv)
1688 {
1689         unsigned int nport;
1690         int ret;
1691
1692         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
1693                 struct ub960_rxport *rxport = priv->rxports[nport];
1694
1695                 if (!rxport)
1696                         continue;
1697
1698                 ret = ub960_rxport_add_serializer(priv, nport);
1699                 if (ret)
1700                         goto err_remove_sers;
1701         }
1702
1703         return 0;
1704
1705 err_remove_sers:
1706         while (nport--) {
1707                 struct ub960_rxport *rxport = priv->rxports[nport];
1708
1709                 if (!rxport)
1710                         continue;
1711
1712                 ub960_rxport_remove_serializer(priv, nport);
1713         }
1714
1715         return ret;
1716 }
1717
1718 static void ub960_rxport_remove_serializers(struct ub960_data *priv)
1719 {
1720         unsigned int nport;
1721
1722         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
1723                 struct ub960_rxport *rxport = priv->rxports[nport];
1724
1725                 if (!rxport)
1726                         continue;
1727
1728                 ub960_rxport_remove_serializer(priv, nport);
1729         }
1730 }
1731
1732 static void ub960_init_tx_port(struct ub960_data *priv,
1733                                struct ub960_txport *txport)
1734 {
1735         unsigned int nport = txport->nport;
1736         u8 csi_ctl = 0;
1737
1738         /*
1739          * From the datasheet: "initial CSI Skew-Calibration
1740          * sequence [...] should be set when operating at 1.6 Gbps"
1741          */
1742         if (priv->tx_data_rate == MHZ(1600))
1743                 csi_ctl |= UB960_TR_CSI_CTL_CSI_CAL_EN;
1744
1745         csi_ctl |= (4 - txport->num_data_lanes) << 4;
1746
1747         ub960_txport_write(priv, nport, UB960_TR_CSI_CTL, csi_ctl);
1748 }
1749
1750 static int ub960_init_tx_ports(struct ub960_data *priv)
1751 {
1752         unsigned int nport;
1753         u8 speed_select;
1754         u8 pll_div;
1755
1756         /* TX ports */
1757
1758         switch (priv->tx_data_rate) {
1759         case MHZ(1600):
1760         default:
1761                 speed_select = 0;
1762                 pll_div = 0x10;
1763                 break;
1764         case MHZ(1200):
1765                 speed_select = 1;
1766                 break;
1767         case MHZ(800):
1768                 speed_select = 2;
1769                 pll_div = 0x10;
1770                 break;
1771         case MHZ(400):
1772                 speed_select = 3;
1773                 pll_div = 0x10;
1774                 break;
1775         }
1776
1777         ub960_write(priv, UB960_SR_CSI_PLL_CTL, speed_select);
1778
1779         if (priv->hw_data->is_ub9702) {
1780                 ub960_write(priv, UB960_SR_CSI_PLL_DIV, pll_div);
1781
1782                 switch (priv->tx_data_rate) {
1783                 case MHZ(1600):
1784                 default:
1785                         ub960_write_ind(priv, UB960_IND_TARGET_CSI_ANA, 0x92, 0x80);
1786                         ub960_write_ind(priv, UB960_IND_TARGET_CSI_ANA, 0x4b, 0x2a);
1787                         break;
1788                 case MHZ(800):
1789                         ub960_write_ind(priv, UB960_IND_TARGET_CSI_ANA, 0x92, 0x90);
1790                         ub960_write_ind(priv, UB960_IND_TARGET_CSI_ANA, 0x4f, 0x2a);
1791                         ub960_write_ind(priv, UB960_IND_TARGET_CSI_ANA, 0x4b, 0x2a);
1792                         break;
1793                 case MHZ(400):
1794                         ub960_write_ind(priv, UB960_IND_TARGET_CSI_ANA, 0x92, 0xa0);
1795                         break;
1796                 }
1797         }
1798
1799         for (nport = 0; nport < priv->hw_data->num_txports; nport++) {
1800                 struct ub960_txport *txport = priv->txports[nport];
1801
1802                 if (!txport)
1803                         continue;
1804
1805                 ub960_init_tx_port(priv, txport);
1806         }
1807
1808         return 0;
1809 }
1810
1811 static void ub960_init_rx_port_ub960(struct ub960_data *priv,
1812                                      struct ub960_rxport *rxport)
1813 {
1814         unsigned int nport = rxport->nport;
1815         u32 bc_freq_val;
1816
1817         /*
1818          * Back channel frequency select.
1819          * Override FREQ_SELECT from the strap.
1820          * 0 - 2.5 Mbps (DS90UB913A-Q1 / DS90UB933-Q1)
1821          * 2 - 10 Mbps
1822          * 6 - 50 Mbps (DS90UB953-Q1)
1823          *
1824          * Note that changing this setting will result in some errors on the back
1825          * channel for a short period of time.
1826          */
1827
1828         switch (rxport->rx_mode) {
1829         case RXPORT_MODE_RAW10:
1830         case RXPORT_MODE_RAW12_HF:
1831         case RXPORT_MODE_RAW12_LF:
1832                 bc_freq_val = 0;
1833                 break;
1834
1835         case RXPORT_MODE_CSI2_ASYNC:
1836                 bc_freq_val = 2;
1837                 break;
1838
1839         case RXPORT_MODE_CSI2_SYNC:
1840                 bc_freq_val = 6;
1841                 break;
1842
1843         default:
1844                 return;
1845         }
1846
1847         ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG,
1848                                  UB960_RR_BCC_CONFIG_BC_FREQ_SEL_MASK,
1849                                  bc_freq_val);
1850
1851         switch (rxport->rx_mode) {
1852         case RXPORT_MODE_RAW10:
1853                 /* FPD3_MODE = RAW10 Mode (DS90UB913A-Q1 / DS90UB933-Q1 compatible) */
1854                 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG,
1855                                          UB960_RR_PORT_CONFIG_FPD3_MODE_MASK,
1856                                          0x3);
1857
1858                 /*
1859                  * RAW10_8BIT_CTL = 0b10 : 8-bit processing using upper 8 bits
1860                  */
1861                 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG2,
1862                         UB960_RR_PORT_CONFIG2_RAW10_8BIT_CTL_MASK,
1863                         0x2 << UB960_RR_PORT_CONFIG2_RAW10_8BIT_CTL_SHIFT);
1864
1865                 break;
1866
1867         case RXPORT_MODE_RAW12_HF:
1868         case RXPORT_MODE_RAW12_LF:
1869                 /* Not implemented */
1870                 return;
1871
1872         case RXPORT_MODE_CSI2_SYNC:
1873         case RXPORT_MODE_CSI2_ASYNC:
1874                 /* CSI-2 Mode (DS90UB953-Q1 compatible) */
1875                 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG, 0x3,
1876                                          0x0);
1877
1878                 break;
1879         }
1880
1881         /* LV_POLARITY & FV_POLARITY */
1882         ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG2, 0x3,
1883                                  rxport->lv_fv_pol);
1884
1885         /* Enable all interrupt sources from this port */
1886         ub960_rxport_write(priv, nport, UB960_RR_PORT_ICR_HI, 0x07);
1887         ub960_rxport_write(priv, nport, UB960_RR_PORT_ICR_LO, 0x7f);
1888
1889         /* Enable I2C_PASS_THROUGH */
1890         ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG,
1891                                  UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH,
1892                                  UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH);
1893
1894         /* Enable I2C communication to the serializer via the alias addr */
1895         ub960_rxport_write(priv, nport, UB960_RR_SER_ALIAS_ID,
1896                            rxport->ser.alias << 1);
1897
1898         /* Configure EQ related settings */
1899         ub960_rxport_config_eq(priv, nport);
1900
1901         /* Enable RX port */
1902         ub960_update_bits(priv, UB960_SR_RX_PORT_CTL, BIT(nport), BIT(nport));
1903 }
1904
1905 static void ub960_init_rx_port_ub9702_fpd3(struct ub960_data *priv,
1906                                            struct ub960_rxport *rxport)
1907 {
1908         unsigned int nport = rxport->nport;
1909         u8 bc_freq_val;
1910         u8 fpd_func_mode;
1911
1912         switch (rxport->rx_mode) {
1913         case RXPORT_MODE_RAW10:
1914                 bc_freq_val = 0;
1915                 fpd_func_mode = 5;
1916                 break;
1917
1918         case RXPORT_MODE_RAW12_HF:
1919                 bc_freq_val = 0;
1920                 fpd_func_mode = 4;
1921                 break;
1922
1923         case RXPORT_MODE_RAW12_LF:
1924                 bc_freq_val = 0;
1925                 fpd_func_mode = 6;
1926                 break;
1927
1928         case RXPORT_MODE_CSI2_SYNC:
1929                 bc_freq_val = 6;
1930                 fpd_func_mode = 2;
1931                 break;
1932
1933         case RXPORT_MODE_CSI2_ASYNC:
1934                 bc_freq_val = 2;
1935                 fpd_func_mode = 2;
1936                 break;
1937
1938         default:
1939                 return;
1940         }
1941
1942         ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG, 0x7,
1943                                  bc_freq_val);
1944         ub960_rxport_write(priv, nport, UB960_RR_CHANNEL_MODE, fpd_func_mode);
1945
1946         /* set serdes_eq_mode = 1 */
1947         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0xa8, 0x80);
1948
1949         /* enable serdes driver */
1950         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x0d, 0x7f);
1951
1952         /* set serdes_eq_offset=4 */
1953         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2b, 0x04);
1954
1955         /* init default serdes_eq_max in 0xa9 */
1956         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0xa9, 0x23);
1957
1958         /* init serdes_eq_min in 0xaa */
1959         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0xaa, 0);
1960
1961         /* serdes_driver_ctl2 control: DS90UB953-Q1/DS90UB933-Q1/DS90UB913A-Q1 */
1962         ub960_ind_update_bits(priv, UB960_IND_TARGET_RX_ANA(nport), 0x1b,
1963                               BIT(3), BIT(3));
1964
1965         /* RX port to half-rate */
1966         ub960_update_bits(priv, UB960_SR_FPD_RATE_CFG, 0x3 << (nport * 2),
1967                           BIT(nport * 2));
1968 }
1969
1970 static void ub960_init_rx_port_ub9702_fpd4_aeq(struct ub960_data *priv,
1971                                                struct ub960_rxport *rxport)
1972 {
1973         unsigned int nport = rxport->nport;
1974         bool first_time_power_up = true;
1975
1976         if (first_time_power_up) {
1977                 u8 v;
1978
1979                 /* AEQ init */
1980                 ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2c, &v);
1981
1982                 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x27, v);
1983                 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x28, v + 1);
1984
1985                 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2b, 0x00);
1986         }
1987
1988         /* enable serdes_eq_ctl2 */
1989         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x9e, 0x00);
1990
1991         /* enable serdes_eq_ctl1 */
1992         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x90, 0x40);
1993
1994         /* enable serdes_eq_en */
1995         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2e, 0x40);
1996
1997         /* disable serdes_eq_override */
1998         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0xf0, 0x00);
1999
2000         /* disable serdes_gain_override */
2001         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x71, 0x00);
2002 }
2003
2004 static void ub960_init_rx_port_ub9702_fpd4(struct ub960_data *priv,
2005                                            struct ub960_rxport *rxport)
2006 {
2007         unsigned int nport = rxport->nport;
2008         u8 bc_freq_val;
2009
2010         switch (rxport->rx_mode) {
2011         case RXPORT_MODE_RAW10:
2012                 bc_freq_val = 0;
2013                 break;
2014
2015         case RXPORT_MODE_RAW12_HF:
2016                 bc_freq_val = 0;
2017                 break;
2018
2019         case RXPORT_MODE_RAW12_LF:
2020                 bc_freq_val = 0;
2021                 break;
2022
2023         case RXPORT_MODE_CSI2_SYNC:
2024                 bc_freq_val = 6;
2025                 break;
2026
2027         case RXPORT_MODE_CSI2_ASYNC:
2028                 bc_freq_val = 2;
2029                 break;
2030
2031         default:
2032                 return;
2033         }
2034
2035         ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG, 0x7,
2036                                  bc_freq_val);
2037
2038         /* FPD4 Sync Mode */
2039         ub960_rxport_write(priv, nport, UB960_RR_CHANNEL_MODE, 0);
2040
2041         /* add serdes_eq_offset of 4 */
2042         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2b, 0x04);
2043
2044         /* FPD4 serdes_start_eq in 0x27: assign default */
2045         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x27, 0x0);
2046         /* FPD4 serdes_end_eq in 0x28: assign default */
2047         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x28, 0x23);
2048
2049         /* set serdes_driver_mode into FPD IV mode */
2050         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x04, 0x00);
2051         /* set FPD PBC drv into FPD IV mode */
2052         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x1b, 0x00);
2053
2054         /* set serdes_system_init to 0x2f */
2055         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x21, 0x2f);
2056         /* set serdes_system_rst in reset mode */
2057         ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x25, 0xc1);
2058
2059         /* RX port to 7.55G mode */
2060         ub960_update_bits(priv, UB960_SR_FPD_RATE_CFG, 0x3 << (nport * 2),
2061                           0 << (nport * 2));
2062
2063         ub960_init_rx_port_ub9702_fpd4_aeq(priv, rxport);
2064 }
2065
2066 static void ub960_init_rx_port_ub9702(struct ub960_data *priv,
2067                                       struct ub960_rxport *rxport)
2068 {
2069         unsigned int nport = rxport->nport;
2070
2071         if (rxport->cdr_mode == RXPORT_CDR_FPD3)
2072                 ub960_init_rx_port_ub9702_fpd3(priv, rxport);
2073         else /* RXPORT_CDR_FPD4 */
2074                 ub960_init_rx_port_ub9702_fpd4(priv, rxport);
2075
2076         switch (rxport->rx_mode) {
2077         case RXPORT_MODE_RAW10:
2078                 /*
2079                  * RAW10_8BIT_CTL = 0b11 : 8-bit processing using lower 8 bits
2080                  * 0b10 : 8-bit processing using upper 8 bits
2081                  */
2082                 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG2,
2083                                          0x3 << 6, 0x2 << 6);
2084
2085                 break;
2086
2087         case RXPORT_MODE_RAW12_HF:
2088         case RXPORT_MODE_RAW12_LF:
2089                 /* Not implemented */
2090                 return;
2091
2092         case RXPORT_MODE_CSI2_SYNC:
2093         case RXPORT_MODE_CSI2_ASYNC:
2094
2095                 break;
2096         }
2097
2098         /* LV_POLARITY & FV_POLARITY */
2099         ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG2, 0x3,
2100                                  rxport->lv_fv_pol);
2101
2102         /* Enable all interrupt sources from this port */
2103         ub960_rxport_write(priv, nport, UB960_RR_PORT_ICR_HI, 0x07);
2104         ub960_rxport_write(priv, nport, UB960_RR_PORT_ICR_LO, 0x7f);
2105
2106         /* Enable I2C_PASS_THROUGH */
2107         ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG,
2108                                  UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH,
2109                                  UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH);
2110
2111         /* Enable I2C communication to the serializer via the alias addr */
2112         ub960_rxport_write(priv, nport, UB960_RR_SER_ALIAS_ID,
2113                            rxport->ser.alias << 1);
2114
2115         /* Enable RX port */
2116         ub960_update_bits(priv, UB960_SR_RX_PORT_CTL, BIT(nport), BIT(nport));
2117
2118         if (rxport->cdr_mode == RXPORT_CDR_FPD4) {
2119                 /* unreset 960 AEQ */
2120                 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x25, 0x41);
2121         }
2122 }
2123
2124 static int ub960_init_rx_ports(struct ub960_data *priv)
2125 {
2126         unsigned int nport;
2127
2128         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
2129                 struct ub960_rxport *rxport = priv->rxports[nport];
2130
2131                 if (!rxport)
2132                         continue;
2133
2134                 if (priv->hw_data->is_ub9702)
2135                         ub960_init_rx_port_ub9702(priv, rxport);
2136                 else
2137                         ub960_init_rx_port_ub960(priv, rxport);
2138         }
2139
2140         return 0;
2141 }
2142
2143 static void ub960_rxport_handle_events(struct ub960_data *priv, u8 nport)
2144 {
2145         struct device *dev = &priv->client->dev;
2146         u8 rx_port_sts1;
2147         u8 rx_port_sts2;
2148         u8 csi_rx_sts;
2149         u8 bcc_sts;
2150         int ret = 0;
2151
2152         /* Read interrupts (also clears most of them) */
2153         if (!ret)
2154                 ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1,
2155                                         &rx_port_sts1);
2156         if (!ret)
2157                 ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2,
2158                                         &rx_port_sts2);
2159         if (!ret)
2160                 ret = ub960_rxport_read(priv, nport, UB960_RR_CSI_RX_STS,
2161                                         &csi_rx_sts);
2162         if (!ret)
2163                 ret = ub960_rxport_read(priv, nport, UB960_RR_BCC_STATUS,
2164                                         &bcc_sts);
2165
2166         if (ret)
2167                 return;
2168
2169         if (rx_port_sts1 & UB960_RR_RX_PORT_STS1_PARITY_ERROR) {
2170                 u16 v;
2171
2172                 ret = ub960_rxport_read16(priv, nport, UB960_RR_RX_PAR_ERR_HI,
2173                                           &v);
2174                 if (!ret)
2175                         dev_err(dev, "rx%u parity errors: %u\n", nport, v);
2176         }
2177
2178         if (rx_port_sts1 & UB960_RR_RX_PORT_STS1_BCC_CRC_ERROR)
2179                 dev_err(dev, "rx%u BCC CRC error\n", nport);
2180
2181         if (rx_port_sts1 & UB960_RR_RX_PORT_STS1_BCC_SEQ_ERROR)
2182                 dev_err(dev, "rx%u BCC SEQ error\n", nport);
2183
2184         if (rx_port_sts2 & UB960_RR_RX_PORT_STS2_LINE_LEN_UNSTABLE)
2185                 dev_err(dev, "rx%u line length unstable\n", nport);
2186
2187         if (rx_port_sts2 & UB960_RR_RX_PORT_STS2_FPD3_ENCODE_ERROR)
2188                 dev_err(dev, "rx%u FPD3 encode error\n", nport);
2189
2190         if (rx_port_sts2 & UB960_RR_RX_PORT_STS2_BUFFER_ERROR)
2191                 dev_err(dev, "rx%u buffer error\n", nport);
2192
2193         if (csi_rx_sts)
2194                 dev_err(dev, "rx%u CSI error: %#02x\n", nport, csi_rx_sts);
2195
2196         if (csi_rx_sts & UB960_RR_CSI_RX_STS_ECC1_ERR)
2197                 dev_err(dev, "rx%u CSI ECC1 error\n", nport);
2198
2199         if (csi_rx_sts & UB960_RR_CSI_RX_STS_ECC2_ERR)
2200                 dev_err(dev, "rx%u CSI ECC2 error\n", nport);
2201
2202         if (csi_rx_sts & UB960_RR_CSI_RX_STS_CKSUM_ERR)
2203                 dev_err(dev, "rx%u CSI checksum error\n", nport);
2204
2205         if (csi_rx_sts & UB960_RR_CSI_RX_STS_LENGTH_ERR)
2206                 dev_err(dev, "rx%u CSI length error\n", nport);
2207
2208         if (bcc_sts)
2209                 dev_err(dev, "rx%u BCC error: %#02x\n", nport, bcc_sts);
2210
2211         if (bcc_sts & UB960_RR_BCC_STATUS_RESP_ERR)
2212                 dev_err(dev, "rx%u BCC response error", nport);
2213
2214         if (bcc_sts & UB960_RR_BCC_STATUS_SLAVE_TO)
2215                 dev_err(dev, "rx%u BCC slave timeout", nport);
2216
2217         if (bcc_sts & UB960_RR_BCC_STATUS_SLAVE_ERR)
2218                 dev_err(dev, "rx%u BCC slave error", nport);
2219
2220         if (bcc_sts & UB960_RR_BCC_STATUS_MASTER_TO)
2221                 dev_err(dev, "rx%u BCC master timeout", nport);
2222
2223         if (bcc_sts & UB960_RR_BCC_STATUS_MASTER_ERR)
2224                 dev_err(dev, "rx%u BCC master error", nport);
2225
2226         if (bcc_sts & UB960_RR_BCC_STATUS_SEQ_ERROR)
2227                 dev_err(dev, "rx%u BCC sequence error", nport);
2228
2229         if (rx_port_sts2 & UB960_RR_RX_PORT_STS2_LINE_LEN_CHG) {
2230                 u16 v;
2231
2232                 ret = ub960_rxport_read16(priv, nport, UB960_RR_LINE_LEN_1, &v);
2233                 if (!ret)
2234                         dev_dbg(dev, "rx%u line len changed: %u\n", nport, v);
2235         }
2236
2237         if (rx_port_sts2 & UB960_RR_RX_PORT_STS2_LINE_CNT_CHG) {
2238                 u16 v;
2239
2240                 ret = ub960_rxport_read16(priv, nport, UB960_RR_LINE_COUNT_HI,
2241                                           &v);
2242                 if (!ret)
2243                         dev_dbg(dev, "rx%u line count changed: %u\n", nport, v);
2244         }
2245
2246         if (rx_port_sts1 & UB960_RR_RX_PORT_STS1_LOCK_STS_CHG) {
2247                 dev_dbg(dev, "rx%u: %s, %s, %s, %s\n", nport,
2248                         (rx_port_sts1 & UB960_RR_RX_PORT_STS1_LOCK_STS) ?
2249                                 "locked" :
2250                                 "unlocked",
2251                         (rx_port_sts1 & UB960_RR_RX_PORT_STS1_PORT_PASS) ?
2252                                 "passed" :
2253                                 "not passed",
2254                         (rx_port_sts2 & UB960_RR_RX_PORT_STS2_CABLE_FAULT) ?
2255                                 "no clock" :
2256                                 "clock ok",
2257                         (rx_port_sts2 & UB960_RR_RX_PORT_STS2_FREQ_STABLE) ?
2258                                 "stable freq" :
2259                                 "unstable freq");
2260         }
2261 }
2262
2263 /* -----------------------------------------------------------------------------
2264  * V4L2
2265  */
2266
2267 /*
2268  * The current implementation only supports a simple VC mapping, where all VCs
2269  * from a one RX port will be mapped to the same VC. Also, the hardware
2270  * dictates that all streams from an RX port must go to a single TX port.
2271  *
2272  * This function decides the target VC numbers for each RX port with a simple
2273  * algorithm, so that for each TX port, we get VC numbers starting from 0,
2274  * and counting up.
2275  *
2276  * E.g. if all four RX ports are in use, of which the first two go to the
2277  * first TX port and the secont two go to the second TX port, we would get
2278  * the following VCs for the four RX ports: 0, 1, 0, 1.
2279  *
2280  * TODO: implement a more sophisticated VC mapping. As the driver cannot know
2281  * what VCs the sinks expect (say, an FPGA with hardcoded VC routing), this
2282  * probably needs to be somehow configurable. Device tree?
2283  */
2284 static void ub960_get_vc_maps(struct ub960_data *priv,
2285                               struct v4l2_subdev_state *state, u8 *vc)
2286 {
2287         u8 cur_vc[UB960_MAX_TX_NPORTS] = {};
2288         struct v4l2_subdev_route *route;
2289         u8 handled_mask = 0;
2290
2291         for_each_active_route(&state->routing, route) {
2292                 unsigned int rx, tx;
2293
2294                 rx = ub960_pad_to_port(priv, route->sink_pad);
2295                 if (BIT(rx) & handled_mask)
2296                         continue;
2297
2298                 tx = ub960_pad_to_port(priv, route->source_pad);
2299
2300                 vc[rx] = cur_vc[tx]++;
2301                 handled_mask |= BIT(rx);
2302         }
2303 }
2304
2305 static int ub960_enable_tx_port(struct ub960_data *priv, unsigned int nport)
2306 {
2307         struct device *dev = &priv->client->dev;
2308
2309         dev_dbg(dev, "enable TX port %u\n", nport);
2310
2311         return ub960_txport_update_bits(priv, nport, UB960_TR_CSI_CTL,
2312                                         UB960_TR_CSI_CTL_CSI_ENABLE,
2313                                         UB960_TR_CSI_CTL_CSI_ENABLE);
2314 }
2315
2316 static void ub960_disable_tx_port(struct ub960_data *priv, unsigned int nport)
2317 {
2318         struct device *dev = &priv->client->dev;
2319
2320         dev_dbg(dev, "disable TX port %u\n", nport);
2321
2322         ub960_txport_update_bits(priv, nport, UB960_TR_CSI_CTL,
2323                                  UB960_TR_CSI_CTL_CSI_ENABLE, 0);
2324 }
2325
2326 static int ub960_enable_rx_port(struct ub960_data *priv, unsigned int nport)
2327 {
2328         struct device *dev = &priv->client->dev;
2329
2330         dev_dbg(dev, "enable RX port %u\n", nport);
2331
2332         /* Enable forwarding */
2333         return ub960_update_bits(priv, UB960_SR_FWD_CTL1,
2334                                  UB960_SR_FWD_CTL1_PORT_DIS(nport), 0);
2335 }
2336
2337 static void ub960_disable_rx_port(struct ub960_data *priv, unsigned int nport)
2338 {
2339         struct device *dev = &priv->client->dev;
2340
2341         dev_dbg(dev, "disable RX port %u\n", nport);
2342
2343         /* Disable forwarding */
2344         ub960_update_bits(priv, UB960_SR_FWD_CTL1,
2345                           UB960_SR_FWD_CTL1_PORT_DIS(nport),
2346                           UB960_SR_FWD_CTL1_PORT_DIS(nport));
2347 }
2348
2349 /*
2350  * The driver only supports using a single VC for each source. This function
2351  * checks that each source only provides streams using a single VC.
2352  */
2353 static int ub960_validate_stream_vcs(struct ub960_data *priv)
2354 {
2355         unsigned int nport;
2356         unsigned int i;
2357
2358         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
2359                 struct ub960_rxport *rxport = priv->rxports[nport];
2360                 struct v4l2_mbus_frame_desc desc;
2361                 int ret;
2362                 u8 vc;
2363
2364                 if (!rxport)
2365                         continue;
2366
2367                 ret = v4l2_subdev_call(rxport->source.sd, pad, get_frame_desc,
2368                                        rxport->source.pad, &desc);
2369                 if (ret)
2370                         return ret;
2371
2372                 if (desc.type != V4L2_MBUS_FRAME_DESC_TYPE_CSI2)
2373                         continue;
2374
2375                 if (desc.num_entries == 0)
2376                         continue;
2377
2378                 vc = desc.entry[0].bus.csi2.vc;
2379
2380                 for (i = 1; i < desc.num_entries; i++) {
2381                         if (vc == desc.entry[i].bus.csi2.vc)
2382                                 continue;
2383
2384                         dev_err(&priv->client->dev,
2385                                 "rx%u: source with multiple virtual-channels is not supported\n",
2386                                 nport);
2387                         return -ENODEV;
2388                 }
2389         }
2390
2391         return 0;
2392 }
2393
2394 static int ub960_configure_ports_for_streaming(struct ub960_data *priv,
2395                                                struct v4l2_subdev_state *state)
2396 {
2397         u8 fwd_ctl;
2398         struct {
2399                 u32 num_streams;
2400                 u8 pixel_dt;
2401                 u8 meta_dt;
2402                 u32 meta_lines;
2403                 u32 tx_port;
2404         } rx_data[UB960_MAX_RX_NPORTS] = {};
2405         u8 vc_map[UB960_MAX_RX_NPORTS] = {};
2406         struct v4l2_subdev_route *route;
2407         unsigned int nport;
2408         int ret;
2409
2410         ret = ub960_validate_stream_vcs(priv);
2411         if (ret)
2412                 return ret;
2413
2414         ub960_get_vc_maps(priv, state, vc_map);
2415
2416         for_each_active_route(&state->routing, route) {
2417                 struct ub960_rxport *rxport;
2418                 struct ub960_txport *txport;
2419                 struct v4l2_mbus_framefmt *fmt;
2420                 const struct ub960_format_info *ub960_fmt;
2421                 unsigned int nport;
2422
2423                 nport = ub960_pad_to_port(priv, route->sink_pad);
2424
2425                 rxport = priv->rxports[nport];
2426                 if (!rxport)
2427                         return -EINVAL;
2428
2429                 txport = priv->txports[ub960_pad_to_port(priv, route->source_pad)];
2430                 if (!txport)
2431                         return -EINVAL;
2432
2433                 rx_data[nport].tx_port = ub960_pad_to_port(priv, route->source_pad);
2434
2435                 rx_data[nport].num_streams++;
2436
2437                 /* For the rest, we are only interested in parallel busses */
2438                 if (rxport->rx_mode == RXPORT_MODE_CSI2_SYNC ||
2439                     rxport->rx_mode == RXPORT_MODE_CSI2_ASYNC)
2440                         continue;
2441
2442                 if (rx_data[nport].num_streams > 2)
2443                         return -EPIPE;
2444
2445                 fmt = v4l2_subdev_state_get_stream_format(state,
2446                                                           route->sink_pad,
2447                                                           route->sink_stream);
2448                 if (!fmt)
2449                         return -EPIPE;
2450
2451                 ub960_fmt = ub960_find_format(fmt->code);
2452                 if (!ub960_fmt)
2453                         return -EPIPE;
2454
2455                 if (ub960_fmt->meta) {
2456                         if (fmt->height > 3) {
2457                                 dev_err(&priv->client->dev,
2458                                         "rx%u: unsupported metadata height %u\n",
2459                                         nport, fmt->height);
2460                                 return -EPIPE;
2461                         }
2462
2463                         rx_data[nport].meta_dt = ub960_fmt->datatype;
2464                         rx_data[nport].meta_lines = fmt->height;
2465                 } else {
2466                         rx_data[nport].pixel_dt = ub960_fmt->datatype;
2467                 }
2468         }
2469
2470         /* Configure RX ports */
2471
2472         /*
2473          * Keep all port forwardings disabled by default. Forwarding will be
2474          * enabled in ub960_enable_rx_port.
2475          */
2476         fwd_ctl = GENMASK(7, 4);
2477
2478         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
2479                 struct ub960_rxport *rxport = priv->rxports[nport];
2480                 u8 vc = vc_map[nport];
2481
2482                 if (rx_data[nport].num_streams == 0)
2483                         continue;
2484
2485                 switch (rxport->rx_mode) {
2486                 case RXPORT_MODE_RAW10:
2487                         ub960_rxport_write(priv, nport, UB960_RR_RAW10_ID,
2488                                 rx_data[nport].pixel_dt | (vc << UB960_RR_RAW10_ID_VC_SHIFT));
2489
2490                         ub960_rxport_write(priv, rxport->nport,
2491                                 UB960_RR_RAW_EMBED_DTYPE,
2492                                 (rx_data[nport].meta_lines << UB960_RR_RAW_EMBED_DTYPE_LINES_SHIFT) |
2493                                         rx_data[nport].meta_dt);
2494
2495                         break;
2496
2497                 case RXPORT_MODE_RAW12_HF:
2498                 case RXPORT_MODE_RAW12_LF:
2499                         /* Not implemented */
2500                         break;
2501
2502                 case RXPORT_MODE_CSI2_SYNC:
2503                 case RXPORT_MODE_CSI2_ASYNC:
2504                         if (!priv->hw_data->is_ub9702) {
2505                                 /* Map all VCs from this port to the same VC */
2506                                 ub960_rxport_write(priv, nport, UB960_RR_CSI_VC_MAP,
2507                                                    (vc << UB960_RR_CSI_VC_MAP_SHIFT(3)) |
2508                                                    (vc << UB960_RR_CSI_VC_MAP_SHIFT(2)) |
2509                                                    (vc << UB960_RR_CSI_VC_MAP_SHIFT(1)) |
2510                                                    (vc << UB960_RR_CSI_VC_MAP_SHIFT(0)));
2511                         } else {
2512                                 unsigned int i;
2513
2514                                 /* Map all VCs from this port to VC(nport) */
2515                                 for (i = 0; i < 8; i++)
2516                                         ub960_rxport_write(priv, nport,
2517                                                            UB960_RR_VC_ID_MAP(i),
2518                                                            nport);
2519                         }
2520
2521                         break;
2522                 }
2523
2524                 if (rx_data[nport].tx_port == 1)
2525                         fwd_ctl |= BIT(nport); /* forward to TX1 */
2526                 else
2527                         fwd_ctl &= ~BIT(nport); /* forward to TX0 */
2528         }
2529
2530         ub960_write(priv, UB960_SR_FWD_CTL1, fwd_ctl);
2531
2532         return 0;
2533 }
2534
2535 static void ub960_update_streaming_status(struct ub960_data *priv)
2536 {
2537         unsigned int i;
2538
2539         for (i = 0; i < UB960_MAX_NPORTS; i++) {
2540                 if (priv->stream_enable_mask[i])
2541                         break;
2542         }
2543
2544         priv->streaming = i < UB960_MAX_NPORTS;
2545 }
2546
2547 static int ub960_enable_streams(struct v4l2_subdev *sd,
2548                                 struct v4l2_subdev_state *state, u32 source_pad,
2549                                 u64 source_streams_mask)
2550 {
2551         struct ub960_data *priv = sd_to_ub960(sd);
2552         struct device *dev = &priv->client->dev;
2553         u64 sink_streams[UB960_MAX_RX_NPORTS] = {};
2554         struct v4l2_subdev_route *route;
2555         unsigned int failed_port;
2556         unsigned int nport;
2557         int ret;
2558
2559         if (!priv->streaming) {
2560                 dev_dbg(dev, "Prepare for streaming\n");
2561                 ret = ub960_configure_ports_for_streaming(priv, state);
2562                 if (ret)
2563                         return ret;
2564         }
2565
2566         /* Enable TX port if not yet enabled */
2567         if (!priv->stream_enable_mask[source_pad]) {
2568                 ret = ub960_enable_tx_port(priv,
2569                                            ub960_pad_to_port(priv, source_pad));
2570                 if (ret)
2571                         return ret;
2572         }
2573
2574         priv->stream_enable_mask[source_pad] |= source_streams_mask;
2575
2576         /* Collect sink streams per pad which we need to enable */
2577         for_each_active_route(&state->routing, route) {
2578                 if (route->source_pad != source_pad)
2579                         continue;
2580
2581                 if (!(source_streams_mask & BIT_ULL(route->source_stream)))
2582                         continue;
2583
2584                 nport = ub960_pad_to_port(priv, route->sink_pad);
2585
2586                 sink_streams[nport] |= BIT_ULL(route->sink_stream);
2587         }
2588
2589         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
2590                 if (!sink_streams[nport])
2591                         continue;
2592
2593                 /* Enable the RX port if not yet enabled */
2594                 if (!priv->stream_enable_mask[nport]) {
2595                         ret = ub960_enable_rx_port(priv, nport);
2596                         if (ret) {
2597                                 failed_port = nport;
2598                                 goto err;
2599                         }
2600                 }
2601
2602                 priv->stream_enable_mask[nport] |= sink_streams[nport];
2603
2604                 dev_dbg(dev, "enable RX port %u streams %#llx\n", nport,
2605                         sink_streams[nport]);
2606
2607                 ret = v4l2_subdev_enable_streams(
2608                         priv->rxports[nport]->source.sd,
2609                         priv->rxports[nport]->source.pad,
2610                         sink_streams[nport]);
2611                 if (ret) {
2612                         priv->stream_enable_mask[nport] &= ~sink_streams[nport];
2613
2614                         if (!priv->stream_enable_mask[nport])
2615                                 ub960_disable_rx_port(priv, nport);
2616
2617                         failed_port = nport;
2618                         goto err;
2619                 }
2620         }
2621
2622         priv->streaming = true;
2623
2624         return 0;
2625
2626 err:
2627         for (nport = 0; nport < failed_port; nport++) {
2628                 if (!sink_streams[nport])
2629                         continue;
2630
2631                 dev_dbg(dev, "disable RX port %u streams %#llx\n", nport,
2632                         sink_streams[nport]);
2633
2634                 ret = v4l2_subdev_disable_streams(
2635                         priv->rxports[nport]->source.sd,
2636                         priv->rxports[nport]->source.pad,
2637                         sink_streams[nport]);
2638                 if (ret)
2639                         dev_err(dev, "Failed to disable streams: %d\n", ret);
2640
2641                 priv->stream_enable_mask[nport] &= ~sink_streams[nport];
2642
2643                 /* Disable RX port if no active streams */
2644                 if (!priv->stream_enable_mask[nport])
2645                         ub960_disable_rx_port(priv, nport);
2646         }
2647
2648         priv->stream_enable_mask[source_pad] &= ~source_streams_mask;
2649
2650         if (!priv->stream_enable_mask[source_pad])
2651                 ub960_disable_tx_port(priv,
2652                                       ub960_pad_to_port(priv, source_pad));
2653
2654         ub960_update_streaming_status(priv);
2655
2656         return ret;
2657 }
2658
2659 static int ub960_disable_streams(struct v4l2_subdev *sd,
2660                                  struct v4l2_subdev_state *state,
2661                                  u32 source_pad, u64 source_streams_mask)
2662 {
2663         struct ub960_data *priv = sd_to_ub960(sd);
2664         struct device *dev = &priv->client->dev;
2665         u64 sink_streams[UB960_MAX_RX_NPORTS] = {};
2666         struct v4l2_subdev_route *route;
2667         unsigned int nport;
2668         int ret;
2669
2670         /* Collect sink streams per pad which we need to disable */
2671         for_each_active_route(&state->routing, route) {
2672                 if (route->source_pad != source_pad)
2673                         continue;
2674
2675                 if (!(source_streams_mask & BIT_ULL(route->source_stream)))
2676                         continue;
2677
2678                 nport = ub960_pad_to_port(priv, route->sink_pad);
2679
2680                 sink_streams[nport] |= BIT_ULL(route->sink_stream);
2681         }
2682
2683         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
2684                 if (!sink_streams[nport])
2685                         continue;
2686
2687                 dev_dbg(dev, "disable RX port %u streams %#llx\n", nport,
2688                         sink_streams[nport]);
2689
2690                 ret = v4l2_subdev_disable_streams(
2691                         priv->rxports[nport]->source.sd,
2692                         priv->rxports[nport]->source.pad,
2693                         sink_streams[nport]);
2694                 if (ret)
2695                         dev_err(dev, "Failed to disable streams: %d\n", ret);
2696
2697                 priv->stream_enable_mask[nport] &= ~sink_streams[nport];
2698
2699                 /* Disable RX port if no active streams */
2700                 if (!priv->stream_enable_mask[nport])
2701                         ub960_disable_rx_port(priv, nport);
2702         }
2703
2704         /* Disable TX port if no active streams */
2705
2706         priv->stream_enable_mask[source_pad] &= ~source_streams_mask;
2707
2708         if (!priv->stream_enable_mask[source_pad])
2709                 ub960_disable_tx_port(priv,
2710                                       ub960_pad_to_port(priv, source_pad));
2711
2712         ub960_update_streaming_status(priv);
2713
2714         return 0;
2715 }
2716
2717 static int _ub960_set_routing(struct v4l2_subdev *sd,
2718                               struct v4l2_subdev_state *state,
2719                               struct v4l2_subdev_krouting *routing)
2720 {
2721         static const struct v4l2_mbus_framefmt format = {
2722                 .width = 640,
2723                 .height = 480,
2724                 .code = MEDIA_BUS_FMT_UYVY8_1X16,
2725                 .field = V4L2_FIELD_NONE,
2726                 .colorspace = V4L2_COLORSPACE_SRGB,
2727                 .ycbcr_enc = V4L2_YCBCR_ENC_601,
2728                 .quantization = V4L2_QUANTIZATION_LIM_RANGE,
2729                 .xfer_func = V4L2_XFER_FUNC_SRGB,
2730         };
2731         int ret;
2732
2733         /*
2734          * Note: we can only support up to V4L2_FRAME_DESC_ENTRY_MAX, until
2735          * frame desc is made dynamically allocated.
2736          */
2737
2738         if (routing->num_routes > V4L2_FRAME_DESC_ENTRY_MAX)
2739                 return -E2BIG;
2740
2741         ret = v4l2_subdev_routing_validate(sd, routing,
2742                                            V4L2_SUBDEV_ROUTING_ONLY_1_TO_1 |
2743                                            V4L2_SUBDEV_ROUTING_NO_SINK_STREAM_MIX);
2744         if (ret)
2745                 return ret;
2746
2747         ret = v4l2_subdev_set_routing_with_fmt(sd, state, routing, &format);
2748         if (ret)
2749                 return ret;
2750
2751         return 0;
2752 }
2753
2754 static int ub960_set_routing(struct v4l2_subdev *sd,
2755                              struct v4l2_subdev_state *state,
2756                              enum v4l2_subdev_format_whence which,
2757                              struct v4l2_subdev_krouting *routing)
2758 {
2759         struct ub960_data *priv = sd_to_ub960(sd);
2760
2761         if (which == V4L2_SUBDEV_FORMAT_ACTIVE && priv->streaming)
2762                 return -EBUSY;
2763
2764         return _ub960_set_routing(sd, state, routing);
2765 }
2766
2767 static int ub960_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
2768                                 struct v4l2_mbus_frame_desc *fd)
2769 {
2770         struct ub960_data *priv = sd_to_ub960(sd);
2771         struct v4l2_subdev_route *route;
2772         struct v4l2_subdev_state *state;
2773         int ret = 0;
2774         struct device *dev = &priv->client->dev;
2775         u8 vc_map[UB960_MAX_RX_NPORTS] = {};
2776
2777         if (!ub960_pad_is_source(priv, pad))
2778                 return -EINVAL;
2779
2780         memset(fd, 0, sizeof(*fd));
2781
2782         fd->type = V4L2_MBUS_FRAME_DESC_TYPE_CSI2;
2783
2784         state = v4l2_subdev_lock_and_get_active_state(&priv->sd);
2785
2786         ub960_get_vc_maps(priv, state, vc_map);
2787
2788         for_each_active_route(&state->routing, route) {
2789                 struct v4l2_mbus_frame_desc_entry *source_entry = NULL;
2790                 struct v4l2_mbus_frame_desc source_fd;
2791                 unsigned int nport;
2792                 unsigned int i;
2793
2794                 if (route->source_pad != pad)
2795                         continue;
2796
2797                 nport = ub960_pad_to_port(priv, route->sink_pad);
2798
2799                 ret = v4l2_subdev_call(priv->rxports[nport]->source.sd, pad,
2800                                        get_frame_desc,
2801                                        priv->rxports[nport]->source.pad,
2802                                        &source_fd);
2803                 if (ret) {
2804                         dev_err(dev,
2805                                 "Failed to get source frame desc for pad %u\n",
2806                                 route->sink_pad);
2807                         goto out_unlock;
2808                 }
2809
2810                 for (i = 0; i < source_fd.num_entries; i++) {
2811                         if (source_fd.entry[i].stream == route->sink_stream) {
2812                                 source_entry = &source_fd.entry[i];
2813                                 break;
2814                         }
2815                 }
2816
2817                 if (!source_entry) {
2818                         dev_err(dev,
2819                                 "Failed to find stream from source frame desc\n");
2820                         ret = -EPIPE;
2821                         goto out_unlock;
2822                 }
2823
2824                 fd->entry[fd->num_entries].stream = route->source_stream;
2825                 fd->entry[fd->num_entries].flags = source_entry->flags;
2826                 fd->entry[fd->num_entries].length = source_entry->length;
2827                 fd->entry[fd->num_entries].pixelcode = source_entry->pixelcode;
2828
2829                 fd->entry[fd->num_entries].bus.csi2.vc = vc_map[nport];
2830
2831                 if (source_fd.type == V4L2_MBUS_FRAME_DESC_TYPE_CSI2) {
2832                         fd->entry[fd->num_entries].bus.csi2.dt =
2833                                 source_entry->bus.csi2.dt;
2834                 } else {
2835                         const struct ub960_format_info *ub960_fmt;
2836                         struct v4l2_mbus_framefmt *fmt;
2837
2838                         fmt = v4l2_subdev_state_get_stream_format(state, pad,
2839                                                                   route->source_stream);
2840
2841                         if (!fmt) {
2842                                 ret = -EINVAL;
2843                                 goto out_unlock;
2844                         }
2845
2846                         ub960_fmt = ub960_find_format(fmt->code);
2847                         if (!ub960_fmt) {
2848                                 dev_err(dev, "Unable to find format\n");
2849                                 ret = -EINVAL;
2850                                 goto out_unlock;
2851                         }
2852
2853                         fd->entry[fd->num_entries].bus.csi2.dt =
2854                                 ub960_fmt->datatype;
2855                 }
2856
2857                 fd->num_entries++;
2858         }
2859
2860 out_unlock:
2861         v4l2_subdev_unlock_state(state);
2862
2863         return ret;
2864 }
2865
2866 static int ub960_set_fmt(struct v4l2_subdev *sd,
2867                          struct v4l2_subdev_state *state,
2868                          struct v4l2_subdev_format *format)
2869 {
2870         struct ub960_data *priv = sd_to_ub960(sd);
2871         struct v4l2_mbus_framefmt *fmt;
2872
2873         if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE && priv->streaming)
2874                 return -EBUSY;
2875
2876         /* No transcoding, source and sink formats must match. */
2877         if (ub960_pad_is_source(priv, format->pad))
2878                 return v4l2_subdev_get_fmt(sd, state, format);
2879
2880         /*
2881          * Default to the first format if the requested media bus code isn't
2882          * supported.
2883          */
2884         if (!ub960_find_format(format->format.code))
2885                 format->format.code = ub960_formats[0].code;
2886
2887         fmt = v4l2_subdev_state_get_stream_format(state, format->pad,
2888                                                   format->stream);
2889         if (!fmt)
2890                 return -EINVAL;
2891
2892         *fmt = format->format;
2893
2894         fmt = v4l2_subdev_state_get_opposite_stream_format(state, format->pad,
2895                                                            format->stream);
2896         if (!fmt)
2897                 return -EINVAL;
2898
2899         *fmt = format->format;
2900
2901         return 0;
2902 }
2903
2904 static int ub960_init_cfg(struct v4l2_subdev *sd,
2905                           struct v4l2_subdev_state *state)
2906 {
2907         struct ub960_data *priv = sd_to_ub960(sd);
2908
2909         struct v4l2_subdev_route routes[] = {
2910                 {
2911                         .sink_pad = 0,
2912                         .sink_stream = 0,
2913                         .source_pad = priv->hw_data->num_rxports,
2914                         .source_stream = 0,
2915                         .flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE,
2916                 },
2917         };
2918
2919         struct v4l2_subdev_krouting routing = {
2920                 .num_routes = ARRAY_SIZE(routes),
2921                 .routes = routes,
2922         };
2923
2924         return _ub960_set_routing(sd, state, &routing);
2925 }
2926
2927 static const struct v4l2_subdev_pad_ops ub960_pad_ops = {
2928         .enable_streams = ub960_enable_streams,
2929         .disable_streams = ub960_disable_streams,
2930
2931         .set_routing = ub960_set_routing,
2932         .get_frame_desc = ub960_get_frame_desc,
2933
2934         .get_fmt = v4l2_subdev_get_fmt,
2935         .set_fmt = ub960_set_fmt,
2936
2937         .init_cfg = ub960_init_cfg,
2938 };
2939
2940 static int ub960_log_status(struct v4l2_subdev *sd)
2941 {
2942         struct ub960_data *priv = sd_to_ub960(sd);
2943         struct device *dev = &priv->client->dev;
2944         struct v4l2_subdev_state *state;
2945         unsigned int nport;
2946         unsigned int i;
2947         u16 v16 = 0;
2948         u8 v = 0;
2949         u8 id[UB960_SR_FPD3_RX_ID_LEN];
2950
2951         state = v4l2_subdev_lock_and_get_active_state(sd);
2952
2953         for (i = 0; i < sizeof(id); i++)
2954                 ub960_read(priv, UB960_SR_FPD3_RX_ID(i), &id[i]);
2955
2956         dev_info(dev, "ID '%.*s'\n", (int)sizeof(id), id);
2957
2958         for (nport = 0; nport < priv->hw_data->num_txports; nport++) {
2959                 struct ub960_txport *txport = priv->txports[nport];
2960
2961                 dev_info(dev, "TX %u\n", nport);
2962
2963                 if (!txport) {
2964                         dev_info(dev, "\tNot initialized\n");
2965                         continue;
2966                 }
2967
2968                 ub960_txport_read(priv, nport, UB960_TR_CSI_STS, &v);
2969                 dev_info(dev, "\tsync %u, pass %u\n", v & (u8)BIT(1),
2970                          v & (u8)BIT(0));
2971
2972                 ub960_read16(priv, UB960_SR_CSI_FRAME_COUNT_HI(nport), &v16);
2973                 dev_info(dev, "\tframe counter %u\n", v16);
2974
2975                 ub960_read16(priv, UB960_SR_CSI_FRAME_ERR_COUNT_HI(nport), &v16);
2976                 dev_info(dev, "\tframe error counter %u\n", v16);
2977
2978                 ub960_read16(priv, UB960_SR_CSI_LINE_COUNT_HI(nport), &v16);
2979                 dev_info(dev, "\tline counter %u\n", v16);
2980
2981                 ub960_read16(priv, UB960_SR_CSI_LINE_ERR_COUNT_HI(nport), &v16);
2982                 dev_info(dev, "\tline error counter %u\n", v16);
2983         }
2984
2985         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
2986                 struct ub960_rxport *rxport = priv->rxports[nport];
2987                 u8 eq_level;
2988                 s8 strobe_pos;
2989                 unsigned int i;
2990
2991                 dev_info(dev, "RX %u\n", nport);
2992
2993                 if (!rxport) {
2994                         dev_info(dev, "\tNot initialized\n");
2995                         continue;
2996                 }
2997
2998                 ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1, &v);
2999
3000                 if (v & UB960_RR_RX_PORT_STS1_LOCK_STS)
3001                         dev_info(dev, "\tLocked\n");
3002                 else
3003                         dev_info(dev, "\tNot locked\n");
3004
3005                 dev_info(dev, "\trx_port_sts1 %#02x\n", v);
3006                 ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2, &v);
3007                 dev_info(dev, "\trx_port_sts2 %#02x\n", v);
3008
3009                 ub960_rxport_read16(priv, nport, UB960_RR_RX_FREQ_HIGH, &v16);
3010                 dev_info(dev, "\tlink freq %llu Hz\n", (v16 * 1000000ULL) >> 8);
3011
3012                 ub960_rxport_read16(priv, nport, UB960_RR_RX_PAR_ERR_HI, &v16);
3013                 dev_info(dev, "\tparity errors %u\n", v16);
3014
3015                 ub960_rxport_read16(priv, nport, UB960_RR_LINE_COUNT_HI, &v16);
3016                 dev_info(dev, "\tlines per frame %u\n", v16);
3017
3018                 ub960_rxport_read16(priv, nport, UB960_RR_LINE_LEN_1, &v16);
3019                 dev_info(dev, "\tbytes per line %u\n", v16);
3020
3021                 ub960_rxport_read(priv, nport, UB960_RR_CSI_ERR_COUNTER, &v);
3022                 dev_info(dev, "\tcsi_err_counter %u\n", v);
3023
3024                 /* Strobe */
3025
3026                 ub960_read(priv, UB960_XR_AEQ_CTL1, &v);
3027
3028                 dev_info(dev, "\t%s strobe\n",
3029                          (v & UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN) ? "Adaptive" :
3030                                                                   "Manual");
3031
3032                 if (v & UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN) {
3033                         ub960_read(priv, UB960_XR_SFILTER_CFG, &v);
3034
3035                         dev_info(dev, "\tStrobe range [%d, %d]\n",
3036                                  ((v >> UB960_XR_SFILTER_CFG_SFILTER_MIN_SHIFT) & 0xf) - 7,
3037                                  ((v >> UB960_XR_SFILTER_CFG_SFILTER_MAX_SHIFT) & 0xf) - 7);
3038                 }
3039
3040                 ub960_rxport_get_strobe_pos(priv, nport, &strobe_pos);
3041
3042                 dev_info(dev, "\tStrobe pos %d\n", strobe_pos);
3043
3044                 /* EQ */
3045
3046                 ub960_rxport_read(priv, nport, UB960_RR_AEQ_BYPASS, &v);
3047
3048                 dev_info(dev, "\t%s EQ\n",
3049                          (v & UB960_RR_AEQ_BYPASS_ENABLE) ? "Manual" :
3050                                                             "Adaptive");
3051
3052                 if (!(v & UB960_RR_AEQ_BYPASS_ENABLE)) {
3053                         ub960_rxport_read(priv, nport, UB960_RR_AEQ_MIN_MAX, &v);
3054
3055                         dev_info(dev, "\tEQ range [%u, %u]\n",
3056                                  (v >> UB960_RR_AEQ_MIN_MAX_AEQ_FLOOR_SHIFT) & 0xf,
3057                                  (v >> UB960_RR_AEQ_MIN_MAX_AEQ_MAX_SHIFT) & 0xf);
3058                 }
3059
3060                 if (ub960_rxport_get_eq_level(priv, nport, &eq_level) == 0)
3061                         dev_info(dev, "\tEQ level %u\n", eq_level);
3062
3063                 /* GPIOs */
3064                 for (i = 0; i < UB960_NUM_BC_GPIOS; i++) {
3065                         u8 ctl_reg;
3066                         u8 ctl_shift;
3067
3068                         ctl_reg = UB960_RR_BC_GPIO_CTL(i / 2);
3069                         ctl_shift = (i % 2) * 4;
3070
3071                         ub960_rxport_read(priv, nport, ctl_reg, &v);
3072
3073                         dev_info(dev, "\tGPIO%u: mode %u\n", i,
3074                                  (v >> ctl_shift) & 0xf);
3075                 }
3076         }
3077
3078         v4l2_subdev_unlock_state(state);
3079
3080         return 0;
3081 }
3082
3083 static const struct v4l2_subdev_core_ops ub960_subdev_core_ops = {
3084         .log_status = ub960_log_status,
3085         .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
3086         .unsubscribe_event = v4l2_event_subdev_unsubscribe,
3087 };
3088
3089 static const struct v4l2_subdev_ops ub960_subdev_ops = {
3090         .core = &ub960_subdev_core_ops,
3091         .pad = &ub960_pad_ops,
3092 };
3093
3094 static const struct media_entity_operations ub960_entity_ops = {
3095         .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
3096         .link_validate = v4l2_subdev_link_validate,
3097         .has_pad_interdep = v4l2_subdev_has_pad_interdep,
3098 };
3099
3100 /* -----------------------------------------------------------------------------
3101  * Core
3102  */
3103
3104 static irqreturn_t ub960_handle_events(int irq, void *arg)
3105 {
3106         struct ub960_data *priv = arg;
3107         unsigned int i;
3108         u8 int_sts;
3109         u8 fwd_sts;
3110         int ret;
3111
3112         ret = ub960_read(priv, UB960_SR_INTERRUPT_STS, &int_sts);
3113         if (ret || !int_sts)
3114                 return IRQ_NONE;
3115
3116         dev_dbg(&priv->client->dev, "INTERRUPT_STS %x\n", int_sts);
3117
3118         ret = ub960_read(priv, UB960_SR_FWD_STS, &fwd_sts);
3119         if (ret)
3120                 return IRQ_NONE;
3121
3122         dev_dbg(&priv->client->dev, "FWD_STS %#02x\n", fwd_sts);
3123
3124         for (i = 0; i < priv->hw_data->num_txports; i++) {
3125                 if (int_sts & UB960_SR_INTERRUPT_STS_IS_CSI_TX(i))
3126                         ub960_csi_handle_events(priv, i);
3127         }
3128
3129         for (i = 0; i < priv->hw_data->num_rxports; i++) {
3130                 if (!priv->rxports[i])
3131                         continue;
3132
3133                 if (int_sts & UB960_SR_INTERRUPT_STS_IS_RX(i))
3134                         ub960_rxport_handle_events(priv, i);
3135         }
3136
3137         return IRQ_HANDLED;
3138 }
3139
3140 static void ub960_handler_work(struct work_struct *work)
3141 {
3142         struct delayed_work *dwork = to_delayed_work(work);
3143         struct ub960_data *priv =
3144                 container_of(dwork, struct ub960_data, poll_work);
3145
3146         ub960_handle_events(0, priv);
3147
3148         schedule_delayed_work(&priv->poll_work,
3149                               msecs_to_jiffies(UB960_POLL_TIME_MS));
3150 }
3151
3152 static void ub960_txport_free_ports(struct ub960_data *priv)
3153 {
3154         unsigned int nport;
3155
3156         for (nport = 0; nport < priv->hw_data->num_txports; nport++) {
3157                 struct ub960_txport *txport = priv->txports[nport];
3158
3159                 if (!txport)
3160                         continue;
3161
3162                 kfree(txport);
3163                 priv->txports[nport] = NULL;
3164         }
3165 }
3166
3167 static void ub960_rxport_free_ports(struct ub960_data *priv)
3168 {
3169         unsigned int nport;
3170
3171         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
3172                 struct ub960_rxport *rxport = priv->rxports[nport];
3173
3174                 if (!rxport)
3175                         continue;
3176
3177                 fwnode_handle_put(rxport->source.ep_fwnode);
3178                 fwnode_handle_put(rxport->ser.fwnode);
3179
3180                 kfree(rxport);
3181                 priv->rxports[nport] = NULL;
3182         }
3183 }
3184
3185 static int
3186 ub960_parse_dt_rxport_link_properties(struct ub960_data *priv,
3187                                       struct fwnode_handle *link_fwnode,
3188                                       struct ub960_rxport *rxport)
3189 {
3190         struct device *dev = &priv->client->dev;
3191         unsigned int nport = rxport->nport;
3192         u32 rx_mode;
3193         u32 cdr_mode;
3194         s32 strobe_pos;
3195         u32 eq_level;
3196         u32 ser_i2c_alias;
3197         int ret;
3198
3199         cdr_mode = RXPORT_CDR_FPD3;
3200
3201         ret = fwnode_property_read_u32(link_fwnode, "ti,cdr-mode", &cdr_mode);
3202         if (ret < 0 && ret != -EINVAL) {
3203                 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
3204                         "ti,cdr-mode", ret);
3205                 return ret;
3206         }
3207
3208         if (cdr_mode > RXPORT_CDR_LAST) {
3209                 dev_err(dev, "rx%u: bad 'ti,cdr-mode' %u\n", nport, cdr_mode);
3210                 return -EINVAL;
3211         }
3212
3213         if (!priv->hw_data->is_fpdlink4 && cdr_mode == RXPORT_CDR_FPD4) {
3214                 dev_err(dev, "rx%u: FPD-Link 4 CDR not supported\n", nport);
3215                 return -EINVAL;
3216         }
3217
3218         rxport->cdr_mode = cdr_mode;
3219
3220         ret = fwnode_property_read_u32(link_fwnode, "ti,rx-mode", &rx_mode);
3221         if (ret < 0) {
3222                 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
3223                         "ti,rx-mode", ret);
3224                 return ret;
3225         }
3226
3227         if (rx_mode > RXPORT_MODE_LAST) {
3228                 dev_err(dev, "rx%u: bad 'ti,rx-mode' %u\n", nport, rx_mode);
3229                 return -EINVAL;
3230         }
3231
3232         switch (rx_mode) {
3233         case RXPORT_MODE_RAW12_HF:
3234         case RXPORT_MODE_RAW12_LF:
3235         case RXPORT_MODE_CSI2_ASYNC:
3236                 dev_err(dev, "rx%u: unsupported 'ti,rx-mode' %u\n", nport,
3237                         rx_mode);
3238                 return -EINVAL;
3239         default:
3240                 break;
3241         }
3242
3243         rxport->rx_mode = rx_mode;
3244
3245         /* EQ & Strobe related */
3246
3247         /* Defaults */
3248         rxport->eq.manual_eq = false;
3249         rxport->eq.aeq.eq_level_min = UB960_MIN_EQ_LEVEL;
3250         rxport->eq.aeq.eq_level_max = UB960_MAX_EQ_LEVEL;
3251
3252         ret = fwnode_property_read_u32(link_fwnode, "ti,strobe-pos",
3253                                        &strobe_pos);
3254         if (ret) {
3255                 if (ret != -EINVAL) {
3256                         dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
3257                                 "ti,strobe-pos", ret);
3258                         return ret;
3259                 }
3260         } else {
3261                 if (strobe_pos < UB960_MIN_MANUAL_STROBE_POS ||
3262                     strobe_pos > UB960_MAX_MANUAL_STROBE_POS) {
3263                         dev_err(dev, "rx%u: illegal 'strobe-pos' value: %d\n",
3264                                 nport, strobe_pos);
3265                         return -EINVAL;
3266                 }
3267
3268                 /* NOTE: ignored unless global manual strobe pos is also set */
3269                 rxport->eq.strobe_pos = strobe_pos;
3270                 if (!priv->strobe.manual)
3271                         dev_warn(dev,
3272                                  "rx%u: 'ti,strobe-pos' ignored as 'ti,manual-strobe' not set\n",
3273                                  nport);
3274         }
3275
3276         ret = fwnode_property_read_u32(link_fwnode, "ti,eq-level", &eq_level);
3277         if (ret) {
3278                 if (ret != -EINVAL) {
3279                         dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
3280                                 "ti,eq-level", ret);
3281                         return ret;
3282                 }
3283         } else {
3284                 if (eq_level > UB960_MAX_EQ_LEVEL) {
3285                         dev_err(dev, "rx%u: illegal 'ti,eq-level' value: %d\n",
3286                                 nport, eq_level);
3287                         return -EINVAL;
3288                 }
3289
3290                 rxport->eq.manual_eq = true;
3291                 rxport->eq.manual.eq_level = eq_level;
3292         }
3293
3294         ret = fwnode_property_read_u32(link_fwnode, "i2c-alias",
3295                                        &ser_i2c_alias);
3296         if (ret) {
3297                 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
3298                         "i2c-alias", ret);
3299                 return ret;
3300         }
3301         rxport->ser.alias = ser_i2c_alias;
3302
3303         rxport->ser.fwnode = fwnode_get_named_child_node(link_fwnode, "serializer");
3304         if (!rxport->ser.fwnode) {
3305                 dev_err(dev, "rx%u: missing 'serializer' node\n", nport);
3306                 return -EINVAL;
3307         }
3308
3309         return 0;
3310 }
3311
3312 static int ub960_parse_dt_rxport_ep_properties(struct ub960_data *priv,
3313                                                struct fwnode_handle *ep_fwnode,
3314                                                struct ub960_rxport *rxport)
3315 {
3316         struct device *dev = &priv->client->dev;
3317         struct v4l2_fwnode_endpoint vep = {};
3318         unsigned int nport = rxport->nport;
3319         bool hsync_hi;
3320         bool vsync_hi;
3321         int ret;
3322
3323         rxport->source.ep_fwnode = fwnode_graph_get_remote_endpoint(ep_fwnode);
3324         if (!rxport->source.ep_fwnode) {
3325                 dev_err(dev, "rx%u: no remote endpoint\n", nport);
3326                 return -ENODEV;
3327         }
3328
3329         /* We currently have properties only for RAW modes */
3330
3331         switch (rxport->rx_mode) {
3332         case RXPORT_MODE_RAW10:
3333         case RXPORT_MODE_RAW12_HF:
3334         case RXPORT_MODE_RAW12_LF:
3335                 break;
3336         default:
3337                 return 0;
3338         }
3339
3340         vep.bus_type = V4L2_MBUS_PARALLEL;
3341         ret = v4l2_fwnode_endpoint_parse(ep_fwnode, &vep);
3342         if (ret) {
3343                 dev_err(dev, "rx%u: failed to parse endpoint data\n", nport);
3344                 goto err_put_source_ep_fwnode;
3345         }
3346
3347         hsync_hi = !!(vep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH);
3348         vsync_hi = !!(vep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH);
3349
3350         /* LineValid and FrameValid are inverse to the h/vsync active */
3351         rxport->lv_fv_pol = (hsync_hi ? UB960_RR_PORT_CONFIG2_LV_POL_LOW : 0) |
3352                             (vsync_hi ? UB960_RR_PORT_CONFIG2_FV_POL_LOW : 0);
3353
3354         return 0;
3355
3356 err_put_source_ep_fwnode:
3357         fwnode_handle_put(rxport->source.ep_fwnode);
3358         return ret;
3359 }
3360
3361 static int ub960_parse_dt_rxport(struct ub960_data *priv, unsigned int nport,
3362                                  struct fwnode_handle *link_fwnode,
3363                                  struct fwnode_handle *ep_fwnode)
3364 {
3365         static const char *vpoc_names[UB960_MAX_RX_NPORTS] = {
3366                 "vpoc0", "vpoc1", "vpoc2", "vpoc3"
3367         };
3368         struct device *dev = &priv->client->dev;
3369         struct ub960_rxport *rxport;
3370         int ret;
3371
3372         rxport = kzalloc(sizeof(*rxport), GFP_KERNEL);
3373         if (!rxport)
3374                 return -ENOMEM;
3375
3376         priv->rxports[nport] = rxport;
3377
3378         rxport->nport = nport;
3379         rxport->priv = priv;
3380
3381         ret = ub960_parse_dt_rxport_link_properties(priv, link_fwnode, rxport);
3382         if (ret)
3383                 goto err_free_rxport;
3384
3385         rxport->vpoc = devm_regulator_get_optional(dev, vpoc_names[nport]);
3386         if (IS_ERR(rxport->vpoc)) {
3387                 ret = PTR_ERR(rxport->vpoc);
3388                 if (ret == -ENODEV) {
3389                         rxport->vpoc = NULL;
3390                 } else {
3391                         dev_err(dev, "rx%u: failed to get VPOC supply: %d\n",
3392                                 nport, ret);
3393                         goto err_put_remote_fwnode;
3394                 }
3395         }
3396
3397         ret = ub960_parse_dt_rxport_ep_properties(priv, ep_fwnode, rxport);
3398         if (ret)
3399                 goto err_put_remote_fwnode;
3400
3401         return 0;
3402
3403 err_put_remote_fwnode:
3404         fwnode_handle_put(rxport->ser.fwnode);
3405 err_free_rxport:
3406         priv->rxports[nport] = NULL;
3407         kfree(rxport);
3408         return ret;
3409 }
3410
3411 static struct fwnode_handle *
3412 ub960_fwnode_get_link_by_regs(struct fwnode_handle *links_fwnode,
3413                               unsigned int nport)
3414 {
3415         struct fwnode_handle *link_fwnode;
3416         int ret;
3417
3418         fwnode_for_each_child_node(links_fwnode, link_fwnode) {
3419                 u32 link_num;
3420
3421                 if (!str_has_prefix(fwnode_get_name(link_fwnode), "link@"))
3422                         continue;
3423
3424                 ret = fwnode_property_read_u32(link_fwnode, "reg", &link_num);
3425                 if (ret) {
3426                         fwnode_handle_put(link_fwnode);
3427                         return NULL;
3428                 }
3429
3430                 if (nport == link_num)
3431                         return link_fwnode;
3432         }
3433
3434         return NULL;
3435 }
3436
3437 static int ub960_parse_dt_rxports(struct ub960_data *priv)
3438 {
3439         struct device *dev = &priv->client->dev;
3440         struct fwnode_handle *links_fwnode;
3441         unsigned int nport;
3442         int ret;
3443
3444         links_fwnode = fwnode_get_named_child_node(dev_fwnode(dev), "links");
3445         if (!links_fwnode) {
3446                 dev_err(dev, "'links' node missing\n");
3447                 return -ENODEV;
3448         }
3449
3450         /* Defaults, recommended by TI */
3451         priv->strobe.min = 2;
3452         priv->strobe.max = 3;
3453
3454         priv->strobe.manual = fwnode_property_read_bool(links_fwnode, "ti,manual-strobe");
3455
3456         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
3457                 struct fwnode_handle *link_fwnode;
3458                 struct fwnode_handle *ep_fwnode;
3459
3460                 link_fwnode = ub960_fwnode_get_link_by_regs(links_fwnode, nport);
3461                 if (!link_fwnode)
3462                         continue;
3463
3464                 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
3465                                                             nport, 0, 0);
3466                 if (!ep_fwnode) {
3467                         fwnode_handle_put(link_fwnode);
3468                         continue;
3469                 }
3470
3471                 ret = ub960_parse_dt_rxport(priv, nport, link_fwnode,
3472                                             ep_fwnode);
3473
3474                 fwnode_handle_put(link_fwnode);
3475                 fwnode_handle_put(ep_fwnode);
3476
3477                 if (ret) {
3478                         dev_err(dev, "rx%u: failed to parse RX port\n", nport);
3479                         goto err_put_links;
3480                 }
3481         }
3482
3483         fwnode_handle_put(links_fwnode);
3484
3485         return 0;
3486
3487 err_put_links:
3488         fwnode_handle_put(links_fwnode);
3489
3490         return ret;
3491 }
3492
3493 static int ub960_parse_dt_txports(struct ub960_data *priv)
3494 {
3495         struct device *dev = &priv->client->dev;
3496         u32 nport;
3497         int ret;
3498
3499         for (nport = 0; nport < priv->hw_data->num_txports; nport++) {
3500                 unsigned int port = nport + priv->hw_data->num_rxports;
3501                 struct fwnode_handle *ep_fwnode;
3502
3503                 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
3504                                                             port, 0, 0);
3505                 if (!ep_fwnode)
3506                         continue;
3507
3508                 ret = ub960_parse_dt_txport(priv, ep_fwnode, nport);
3509
3510                 fwnode_handle_put(ep_fwnode);
3511
3512                 if (ret)
3513                         break;
3514         }
3515
3516         return 0;
3517 }
3518
3519 static int ub960_parse_dt(struct ub960_data *priv)
3520 {
3521         int ret;
3522
3523         ret = ub960_parse_dt_rxports(priv);
3524         if (ret)
3525                 return ret;
3526
3527         ret = ub960_parse_dt_txports(priv);
3528         if (ret)
3529                 goto err_free_rxports;
3530
3531         return 0;
3532
3533 err_free_rxports:
3534         ub960_rxport_free_ports(priv);
3535
3536         return ret;
3537 }
3538
3539 static int ub960_notify_bound(struct v4l2_async_notifier *notifier,
3540                               struct v4l2_subdev *subdev,
3541                               struct v4l2_async_connection *asd)
3542 {
3543         struct ub960_data *priv = sd_to_ub960(notifier->sd);
3544         struct ub960_rxport *rxport = to_ub960_asd(asd)->rxport;
3545         struct device *dev = &priv->client->dev;
3546         u8 nport = rxport->nport;
3547         unsigned int i;
3548         int ret;
3549
3550         ret = media_entity_get_fwnode_pad(&subdev->entity,
3551                                           rxport->source.ep_fwnode,
3552                                           MEDIA_PAD_FL_SOURCE);
3553         if (ret < 0) {
3554                 dev_err(dev, "Failed to find pad for %s\n", subdev->name);
3555                 return ret;
3556         }
3557
3558         rxport->source.sd = subdev;
3559         rxport->source.pad = ret;
3560
3561         ret = media_create_pad_link(&rxport->source.sd->entity,
3562                                     rxport->source.pad, &priv->sd.entity, nport,
3563                                     MEDIA_LNK_FL_ENABLED |
3564                                             MEDIA_LNK_FL_IMMUTABLE);
3565         if (ret) {
3566                 dev_err(dev, "Unable to link %s:%u -> %s:%u\n",
3567                         rxport->source.sd->name, rxport->source.pad,
3568                         priv->sd.name, nport);
3569                 return ret;
3570         }
3571
3572         for (i = 0; i < priv->hw_data->num_rxports; i++) {
3573                 if (priv->rxports[i] && !priv->rxports[i]->source.sd) {
3574                         dev_dbg(dev, "Waiting for more subdevs to be bound\n");
3575                         return 0;
3576                 }
3577         }
3578
3579         return 0;
3580 }
3581
3582 static void ub960_notify_unbind(struct v4l2_async_notifier *notifier,
3583                                 struct v4l2_subdev *subdev,
3584                                 struct v4l2_async_connection *asd)
3585 {
3586         struct ub960_rxport *rxport = to_ub960_asd(asd)->rxport;
3587
3588         rxport->source.sd = NULL;
3589 }
3590
3591 static const struct v4l2_async_notifier_operations ub960_notify_ops = {
3592         .bound = ub960_notify_bound,
3593         .unbind = ub960_notify_unbind,
3594 };
3595
3596 static int ub960_v4l2_notifier_register(struct ub960_data *priv)
3597 {
3598         struct device *dev = &priv->client->dev;
3599         unsigned int i;
3600         int ret;
3601
3602         v4l2_async_subdev_nf_init(&priv->notifier, &priv->sd);
3603
3604         for (i = 0; i < priv->hw_data->num_rxports; i++) {
3605                 struct ub960_rxport *rxport = priv->rxports[i];
3606                 struct ub960_asd *asd;
3607
3608                 if (!rxport)
3609                         continue;
3610
3611                 asd = v4l2_async_nf_add_fwnode(&priv->notifier,
3612                                                rxport->source.ep_fwnode,
3613                                                struct ub960_asd);
3614                 if (IS_ERR(asd)) {
3615                         dev_err(dev, "Failed to add subdev for source %u: %pe",
3616                                 i, asd);
3617                         v4l2_async_nf_cleanup(&priv->notifier);
3618                         return PTR_ERR(asd);
3619                 }
3620
3621                 asd->rxport = rxport;
3622         }
3623
3624         priv->notifier.ops = &ub960_notify_ops;
3625
3626         ret = v4l2_async_nf_register(&priv->notifier);
3627         if (ret) {
3628                 dev_err(dev, "Failed to register subdev_notifier");
3629                 v4l2_async_nf_cleanup(&priv->notifier);
3630                 return ret;
3631         }
3632
3633         return 0;
3634 }
3635
3636 static void ub960_v4l2_notifier_unregister(struct ub960_data *priv)
3637 {
3638         v4l2_async_nf_unregister(&priv->notifier);
3639         v4l2_async_nf_cleanup(&priv->notifier);
3640 }
3641
3642 static int ub960_create_subdev(struct ub960_data *priv)
3643 {
3644         struct device *dev = &priv->client->dev;
3645         unsigned int i;
3646         int ret;
3647
3648         v4l2_i2c_subdev_init(&priv->sd, priv->client, &ub960_subdev_ops);
3649
3650         v4l2_ctrl_handler_init(&priv->ctrl_handler, 1);
3651         priv->sd.ctrl_handler = &priv->ctrl_handler;
3652
3653         v4l2_ctrl_new_int_menu(&priv->ctrl_handler, NULL, V4L2_CID_LINK_FREQ,
3654                                ARRAY_SIZE(priv->tx_link_freq) - 1, 0,
3655                                priv->tx_link_freq);
3656
3657         if (priv->ctrl_handler.error) {
3658                 ret = priv->ctrl_handler.error;
3659                 goto err_free_ctrl;
3660         }
3661
3662         priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
3663                           V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_STREAMS;
3664         priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
3665         priv->sd.entity.ops = &ub960_entity_ops;
3666
3667         for (i = 0; i < priv->hw_data->num_rxports + priv->hw_data->num_txports; i++) {
3668                 priv->pads[i].flags = ub960_pad_is_sink(priv, i) ?
3669                                               MEDIA_PAD_FL_SINK :
3670                                               MEDIA_PAD_FL_SOURCE;
3671         }
3672
3673         ret = media_entity_pads_init(&priv->sd.entity,
3674                                      priv->hw_data->num_rxports +
3675                                              priv->hw_data->num_txports,
3676                                      priv->pads);
3677         if (ret)
3678                 goto err_free_ctrl;
3679
3680         priv->sd.state_lock = priv->sd.ctrl_handler->lock;
3681
3682         ret = v4l2_subdev_init_finalize(&priv->sd);
3683         if (ret)
3684                 goto err_entity_cleanup;
3685
3686         ret = ub960_v4l2_notifier_register(priv);
3687         if (ret) {
3688                 dev_err(dev, "v4l2 subdev notifier register failed: %d\n", ret);
3689                 goto err_subdev_cleanup;
3690         }
3691
3692         ret = v4l2_async_register_subdev(&priv->sd);
3693         if (ret) {
3694                 dev_err(dev, "v4l2_async_register_subdev error: %d\n", ret);
3695                 goto err_unreg_notif;
3696         }
3697
3698         return 0;
3699
3700 err_unreg_notif:
3701         ub960_v4l2_notifier_unregister(priv);
3702 err_subdev_cleanup:
3703         v4l2_subdev_cleanup(&priv->sd);
3704 err_entity_cleanup:
3705         media_entity_cleanup(&priv->sd.entity);
3706 err_free_ctrl:
3707         v4l2_ctrl_handler_free(&priv->ctrl_handler);
3708
3709         return ret;
3710 }
3711
3712 static void ub960_destroy_subdev(struct ub960_data *priv)
3713 {
3714         ub960_v4l2_notifier_unregister(priv);
3715         v4l2_async_unregister_subdev(&priv->sd);
3716
3717         v4l2_subdev_cleanup(&priv->sd);
3718
3719         media_entity_cleanup(&priv->sd.entity);
3720         v4l2_ctrl_handler_free(&priv->ctrl_handler);
3721 }
3722
3723 static const struct regmap_config ub960_regmap_config = {
3724         .name = "ds90ub960",
3725
3726         .reg_bits = 8,
3727         .val_bits = 8,
3728
3729         .max_register = 0xff,
3730
3731         /*
3732          * We do locking in the driver to cover the TX/RX port selection and the
3733          * indirect register access.
3734          */
3735         .disable_locking = true,
3736 };
3737
3738 static void ub960_reset(struct ub960_data *priv, bool reset_regs)
3739 {
3740         struct device *dev = &priv->client->dev;
3741         unsigned int v;
3742         int ret;
3743         u8 bit;
3744
3745         bit = reset_regs ? UB960_SR_RESET_DIGITAL_RESET1 :
3746                            UB960_SR_RESET_DIGITAL_RESET0;
3747
3748         ub960_write(priv, UB960_SR_RESET, bit);
3749
3750         mutex_lock(&priv->reg_lock);
3751
3752         ret = regmap_read_poll_timeout(priv->regmap, UB960_SR_RESET, v,
3753                                        (v & bit) == 0, 2000, 100000);
3754
3755         mutex_unlock(&priv->reg_lock);
3756
3757         if (ret)
3758                 dev_err(dev, "reset failed: %d\n", ret);
3759 }
3760
3761 static int ub960_get_hw_resources(struct ub960_data *priv)
3762 {
3763         struct device *dev = &priv->client->dev;
3764
3765         priv->regmap = devm_regmap_init_i2c(priv->client, &ub960_regmap_config);
3766         if (IS_ERR(priv->regmap))
3767                 return PTR_ERR(priv->regmap);
3768
3769         priv->vddio = devm_regulator_get(dev, "vddio");
3770         if (IS_ERR(priv->vddio))
3771                 return dev_err_probe(dev, PTR_ERR(priv->vddio),
3772                                      "cannot get VDDIO regulator\n");
3773
3774         /* get power-down pin from DT */
3775         priv->pd_gpio =
3776                 devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH);
3777         if (IS_ERR(priv->pd_gpio))
3778                 return dev_err_probe(dev, PTR_ERR(priv->pd_gpio),
3779                                      "Cannot get powerdown GPIO\n");
3780
3781         priv->refclk = devm_clk_get(dev, "refclk");
3782         if (IS_ERR(priv->refclk))
3783                 return dev_err_probe(dev, PTR_ERR(priv->refclk),
3784                                      "Cannot get REFCLK\n");
3785
3786         return 0;
3787 }
3788
3789 static int ub960_enable_core_hw(struct ub960_data *priv)
3790 {
3791         struct device *dev = &priv->client->dev;
3792         u8 rev_mask;
3793         int ret;
3794         u8 dev_sts;
3795         u8 refclk_freq;
3796
3797         ret = regulator_enable(priv->vddio);
3798         if (ret)
3799                 return dev_err_probe(dev, ret,
3800                                      "failed to enable VDDIO regulator\n");
3801
3802         ret = clk_prepare_enable(priv->refclk);
3803         if (ret) {
3804                 dev_err_probe(dev, ret, "Failed to enable refclk\n");
3805                 goto err_disable_vddio;
3806         }
3807
3808         if (priv->pd_gpio) {
3809                 gpiod_set_value_cansleep(priv->pd_gpio, 1);
3810                 /* wait min 2 ms for reset to complete */
3811                 fsleep(2000);
3812                 gpiod_set_value_cansleep(priv->pd_gpio, 0);
3813                 /* wait min 2 ms for power up to finish */
3814                 fsleep(2000);
3815         }
3816
3817         ub960_reset(priv, true);
3818
3819         /* Runtime check register accessibility */
3820         ret = ub960_read(priv, UB960_SR_REV_MASK, &rev_mask);
3821         if (ret) {
3822                 dev_err_probe(dev, ret, "Cannot read first register, abort\n");
3823                 goto err_pd_gpio;
3824         }
3825
3826         dev_dbg(dev, "Found %s (rev/mask %#04x)\n", priv->hw_data->model,
3827                 rev_mask);
3828
3829         ret = ub960_read(priv, UB960_SR_DEVICE_STS, &dev_sts);
3830         if (ret)
3831                 goto err_pd_gpio;
3832
3833         ret = ub960_read(priv, UB960_XR_REFCLK_FREQ, &refclk_freq);
3834         if (ret)
3835                 goto err_pd_gpio;
3836
3837         dev_dbg(dev, "refclk valid %u freq %u MHz (clk fw freq %lu MHz)\n",
3838                 !!(dev_sts & BIT(4)), refclk_freq,
3839                 clk_get_rate(priv->refclk) / 1000000);
3840
3841         /* Disable all RX ports by default */
3842         ret = ub960_write(priv, UB960_SR_RX_PORT_CTL, 0);
3843         if (ret)
3844                 goto err_pd_gpio;
3845
3846         /* release GPIO lock */
3847         if (priv->hw_data->is_ub9702) {
3848                 ret = ub960_update_bits(priv, UB960_SR_RESET,
3849                                         UB960_SR_RESET_GPIO_LOCK_RELEASE,
3850                                         UB960_SR_RESET_GPIO_LOCK_RELEASE);
3851                 if (ret)
3852                         goto err_pd_gpio;
3853         }
3854
3855         return 0;
3856
3857 err_pd_gpio:
3858         gpiod_set_value_cansleep(priv->pd_gpio, 1);
3859         clk_disable_unprepare(priv->refclk);
3860 err_disable_vddio:
3861         regulator_disable(priv->vddio);
3862
3863         return ret;
3864 }
3865
3866 static void ub960_disable_core_hw(struct ub960_data *priv)
3867 {
3868         gpiod_set_value_cansleep(priv->pd_gpio, 1);
3869         clk_disable_unprepare(priv->refclk);
3870         regulator_disable(priv->vddio);
3871 }
3872
3873 static int ub960_probe(struct i2c_client *client)
3874 {
3875         struct device *dev = &client->dev;
3876         struct ub960_data *priv;
3877         unsigned int port_lock_mask;
3878         unsigned int port_mask;
3879         unsigned int nport;
3880         int ret;
3881
3882         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
3883         if (!priv)
3884                 return -ENOMEM;
3885
3886         priv->client = client;
3887
3888         priv->hw_data = device_get_match_data(dev);
3889
3890         mutex_init(&priv->reg_lock);
3891
3892         INIT_DELAYED_WORK(&priv->poll_work, ub960_handler_work);
3893
3894         /*
3895          * Initialize these to invalid values so that the first reg writes will
3896          * configure the target.
3897          */
3898         priv->reg_current.indirect_target = 0xff;
3899         priv->reg_current.rxport = 0xff;
3900         priv->reg_current.txport = 0xff;
3901
3902         ret = ub960_get_hw_resources(priv);
3903         if (ret)
3904                 goto err_mutex_destroy;
3905
3906         ret = ub960_enable_core_hw(priv);
3907         if (ret)
3908                 goto err_mutex_destroy;
3909
3910         ret = ub960_parse_dt(priv);
3911         if (ret)
3912                 goto err_disable_core_hw;
3913
3914         ret = ub960_init_tx_ports(priv);
3915         if (ret)
3916                 goto err_free_ports;
3917
3918         ret = ub960_rxport_enable_vpocs(priv);
3919         if (ret)
3920                 goto err_free_ports;
3921
3922         ret = ub960_init_rx_ports(priv);
3923         if (ret)
3924                 goto err_disable_vpocs;
3925
3926         ub960_reset(priv, false);
3927
3928         port_mask = 0;
3929
3930         for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
3931                 struct ub960_rxport *rxport = priv->rxports[nport];
3932
3933                 if (!rxport)
3934                         continue;
3935
3936                 port_mask |= BIT(nport);
3937         }
3938
3939         ret = ub960_rxport_wait_locks(priv, port_mask, &port_lock_mask);
3940         if (ret)
3941                 goto err_disable_vpocs;
3942
3943         if (port_mask != port_lock_mask) {
3944                 ret = -EIO;
3945                 dev_err_probe(dev, ret, "Failed to lock all RX ports\n");
3946                 goto err_disable_vpocs;
3947         }
3948
3949         /*
3950          * Clear any errors caused by switching the RX port settings while
3951          * probing.
3952          */
3953         ub960_clear_rx_errors(priv);
3954
3955         ret = ub960_init_atr(priv);
3956         if (ret)
3957                 goto err_disable_vpocs;
3958
3959         ret = ub960_rxport_add_serializers(priv);
3960         if (ret)
3961                 goto err_uninit_atr;
3962
3963         ret = ub960_create_subdev(priv);
3964         if (ret)
3965                 goto err_free_sers;
3966
3967         if (client->irq)
3968                 dev_warn(dev, "irq support not implemented, using polling\n");
3969
3970         schedule_delayed_work(&priv->poll_work,
3971                               msecs_to_jiffies(UB960_POLL_TIME_MS));
3972
3973         return 0;
3974
3975 err_free_sers:
3976         ub960_rxport_remove_serializers(priv);
3977 err_uninit_atr:
3978         ub960_uninit_atr(priv);
3979 err_disable_vpocs:
3980         ub960_rxport_disable_vpocs(priv);
3981 err_free_ports:
3982         ub960_rxport_free_ports(priv);
3983         ub960_txport_free_ports(priv);
3984 err_disable_core_hw:
3985         ub960_disable_core_hw(priv);
3986 err_mutex_destroy:
3987         mutex_destroy(&priv->reg_lock);
3988         return ret;
3989 }
3990
3991 static void ub960_remove(struct i2c_client *client)
3992 {
3993         struct v4l2_subdev *sd = i2c_get_clientdata(client);
3994         struct ub960_data *priv = sd_to_ub960(sd);
3995
3996         cancel_delayed_work_sync(&priv->poll_work);
3997
3998         ub960_destroy_subdev(priv);
3999         ub960_rxport_remove_serializers(priv);
4000         ub960_uninit_atr(priv);
4001         ub960_rxport_disable_vpocs(priv);
4002         ub960_rxport_free_ports(priv);
4003         ub960_txport_free_ports(priv);
4004         ub960_disable_core_hw(priv);
4005         mutex_destroy(&priv->reg_lock);
4006 }
4007
4008 static const struct ub960_hw_data ds90ub960_hw = {
4009         .model = "ub960",
4010         .num_rxports = 4,
4011         .num_txports = 2,
4012 };
4013
4014 static const struct ub960_hw_data ds90ub9702_hw = {
4015         .model = "ub9702",
4016         .num_rxports = 4,
4017         .num_txports = 2,
4018         .is_ub9702 = true,
4019         .is_fpdlink4 = true,
4020 };
4021
4022 static const struct i2c_device_id ub960_id[] = {
4023         { "ds90ub960-q1", (kernel_ulong_t)&ds90ub960_hw },
4024         { "ds90ub9702-q1", (kernel_ulong_t)&ds90ub9702_hw },
4025         {}
4026 };
4027 MODULE_DEVICE_TABLE(i2c, ub960_id);
4028
4029 static const struct of_device_id ub960_dt_ids[] = {
4030         { .compatible = "ti,ds90ub960-q1", .data = &ds90ub960_hw },
4031         { .compatible = "ti,ds90ub9702-q1", .data = &ds90ub9702_hw },
4032         {}
4033 };
4034 MODULE_DEVICE_TABLE(of, ub960_dt_ids);
4035
4036 static struct i2c_driver ds90ub960_driver = {
4037         .probe          = ub960_probe,
4038         .remove         = ub960_remove,
4039         .id_table       = ub960_id,
4040         .driver = {
4041                 .name   = "ds90ub960",
4042                 .of_match_table = ub960_dt_ids,
4043         },
4044 };
4045 module_i2c_driver(ds90ub960_driver);
4046
4047 MODULE_LICENSE("GPL");
4048 MODULE_DESCRIPTION("Texas Instruments FPD-Link III/IV Deserializers Driver");
4049 MODULE_AUTHOR("Luca Ceresoli <luca@lucaceresoli.net>");
4050 MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>");
4051 MODULE_IMPORT_NS(I2C_ATR);