drivers/media/i2c/ccs-pll.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * drivers/media/i2c/ccs-pll.c
   4  *
   5  * Generic MIPI CCS/SMIA/SMIA++ PLL calculator
   6  *
   7  * Copyright (C) 2020 Intel Corporation
   8  * Copyright (C) 2011--2012 Nokia Corporation
   9  * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
  10  */
  11
  12 #include <linux/device.h>
  13 #include <linux/gcd.h>
  14 #include <linux/lcm.h>
  15 #include <linux/module.h>
  16
  17 #include "ccs-pll.h"
  18
  19 /* Return an even number or one. */
  20 static inline uint32_t clk_div_even(uint32_t a)
  21 {
  22         return max_t(uint32_t, 1, a & ~1);
  23 }
  24
  25 /* Return an even number or one. */
  26 static inline uint32_t clk_div_even_up(uint32_t a)
  27 {
  28         if (a == 1)
  29                 return 1;
  30         return (a + 1) & ~1;
  31 }
  32
  33 static inline uint32_t is_one_or_even(uint32_t a)
  34 {
  35         if (a == 1)
  36                 return 1;
  37         if (a & 1)
  38                 return 0;
  39
  40         return 1;
  41 }
  42
  43 static inline uint32_t one_or_more(uint32_t a)
  44 {
  45         return a ?: 1;
  46 }
  47
  48 static int bounds_check(struct device *dev, uint32_t val,
  49                         uint32_t min, uint32_t max, const char *prefix,
  50                         char *str)
  51 {
  52         if (val >= min && val <= max)
  53                 return 0;
  54
  55         dev_dbg(dev, "%s_%s out of bounds: %d (%d--%d)\n", prefix,
  56                 str, val, min, max);
  57
  58         return -EINVAL;
  59 }
  60
  61 #define PLL_OP 1
  62 #define PLL_VT 2
  63
  64 static const char *pll_string(unsigned int which)
  65 {
  66         switch (which) {
  67         case PLL_OP:
  68                 return "op";
  69         case PLL_VT:
  70                 return "vt";
  71         }
  72
  73         return NULL;
  74 }
  75
  76 #define PLL_FL(f) CCS_PLL_FLAG_##f
  77
  78 static void print_pll(struct device *dev, struct ccs_pll *pll)
  79 {
  80         const struct {
  81                 struct ccs_pll_branch_fr *fr;
  82                 struct ccs_pll_branch_bk *bk;
  83                 unsigned int which;
  84         } branches[] = {
  85                 { &pll->vt_fr, &pll->vt_bk, PLL_VT },
  86                 { &pll->op_fr, &pll->op_bk, PLL_OP }
  87         }, *br;
  88         unsigned int i;
  89
  90         dev_dbg(dev, "ext_clk_freq_hz\t\t%u\n", pll->ext_clk_freq_hz);
  91
  92         for (i = 0, br = branches; i < ARRAY_SIZE(branches); i++, br++) {
  93                 const char *s = pll_string(br->which);
  94
  95                 if (pll->flags & CCS_PLL_FLAG_DUAL_PLL ||
  96                     br->which == PLL_VT) {
  97                         dev_dbg(dev, "%s_pre_pll_clk_div\t\t%u\n",  s,
  98                                 br->fr->pre_pll_clk_div);
  99                         dev_dbg(dev, "%s_pll_multiplier\t\t%u\n",  s,
 100                                 br->fr->pll_multiplier);
 101
 102                         dev_dbg(dev, "%s_pll_ip_clk_freq_hz\t%u\n", s,
 103                                 br->fr->pll_ip_clk_freq_hz);
 104                         dev_dbg(dev, "%s_pll_op_clk_freq_hz\t%u\n", s,
 105                                 br->fr->pll_op_clk_freq_hz);
 106                 }
 107
 108                 if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) ||
 109                     br->which == PLL_VT) {
 110                         dev_dbg(dev, "%s_sys_clk_div\t\t%u\n",  s,
 111                                 br->bk->sys_clk_div);
 112                         dev_dbg(dev, "%s_pix_clk_div\t\t%u\n", s,
 113                                 br->bk->pix_clk_div);
 114
 115                         dev_dbg(dev, "%s_sys_clk_freq_hz\t%u\n", s,
 116                                 br->bk->sys_clk_freq_hz);
 117                         dev_dbg(dev, "%s_pix_clk_freq_hz\t%u\n", s,
 118                                 br->bk->pix_clk_freq_hz);
 119                 }
 120         }
 121
 122         dev_dbg(dev, "flags%s%s%s%s%s%s%s\n",
 123                 pll->flags & PLL_FL(LANE_SPEED_MODEL) ? " lane-speed" : "",
 124                 pll->flags & PLL_FL(LINK_DECOUPLED) ? " link-decoupled" : "",
 125                 pll->flags & PLL_FL(EXT_IP_PLL_DIVIDER) ?
 126                 " ext-ip-pll-divider" : "",
 127                 pll->flags & PLL_FL(FLEXIBLE_OP_PIX_CLK_DIV) ?
 128                 " flexible-op-pix-div" : "",
 129                 pll->flags & PLL_FL(FIFO_DERATING) ? " fifo-derating" : "",
 130                 pll->flags & PLL_FL(FIFO_OVERRATING) ? " fifo-overrating" : "",
 131                 pll->flags & PLL_FL(DUAL_PLL) ? " dual-pll" : "");
 132 }
 133
 134 static int check_fr_bounds(struct device *dev,
 135                            const struct ccs_pll_limits *lim,
 136                            struct ccs_pll *pll, unsigned int which)
 137 {
 138         const struct ccs_pll_branch_limits_fr *lim_fr;
 139         struct ccs_pll_branch_fr *pll_fr;
 140         const char *s = pll_string(which);
 141         int rval;
 142
 143         if (which == PLL_OP) {
 144                 lim_fr = &lim->op_fr;
 145                 pll_fr = &pll->op_fr;
 146         } else {
 147                 lim_fr = &lim->vt_fr;
 148                 pll_fr = &pll->vt_fr;
 149         }
 150
 151         rval = bounds_check(dev, pll_fr->pre_pll_clk_div,
 152                             lim_fr->min_pre_pll_clk_div,
 153                             lim_fr->max_pre_pll_clk_div, s, "pre_pll_clk_div");
 154
 155         if (!rval)
 156                 rval = bounds_check(dev, pll_fr->pll_ip_clk_freq_hz,
 157                                     lim_fr->min_pll_ip_clk_freq_hz,
 158                                     lim_fr->max_pll_ip_clk_freq_hz,
 159                                     s, "pll_ip_clk_freq_hz");
 160         if (!rval)
 161                 rval = bounds_check(dev, pll_fr->pll_multiplier,
 162                                     lim_fr->min_pll_multiplier,
 163                                     lim_fr->max_pll_multiplier,
 164                                     s, "pll_multiplier");
 165         if (!rval)
 166                 rval = bounds_check(dev, pll_fr->pll_op_clk_freq_hz,
 167                                     lim_fr->min_pll_op_clk_freq_hz,
 168                                     lim_fr->max_pll_op_clk_freq_hz,
 169                                     s, "pll_op_clk_freq_hz");
 170
 171         return rval;
 172 }
 173
 174 static int check_bk_bounds(struct device *dev,
 175                            const struct ccs_pll_limits *lim,
 176                            struct ccs_pll *pll, unsigned int which)
 177 {
 178         const struct ccs_pll_branch_limits_bk *lim_bk;
 179         struct ccs_pll_branch_bk *pll_bk;
 180         const char *s = pll_string(which);
 181         int rval;
 182
 183         if (which == PLL_OP) {
 184                 if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
 185                         return 0;
 186
 187                 lim_bk = &lim->op_bk;
 188                 pll_bk = &pll->op_bk;
 189         } else {
 190                 lim_bk = &lim->vt_bk;
 191                 pll_bk = &pll->vt_bk;
 192         }
 193
 194         rval = bounds_check(dev, pll_bk->sys_clk_div,
 195                             lim_bk->min_sys_clk_div,
 196                             lim_bk->max_sys_clk_div, s, "op_sys_clk_div");
 197         if (!rval)
 198                 rval = bounds_check(dev, pll_bk->sys_clk_freq_hz,
 199                                     lim_bk->min_sys_clk_freq_hz,
 200                                     lim_bk->max_sys_clk_freq_hz,
 201                                     s, "sys_clk_freq_hz");
 202         if (!rval)
 203                 rval = bounds_check(dev, pll_bk->sys_clk_div,
 204                                     lim_bk->min_sys_clk_div,
 205                                     lim_bk->max_sys_clk_div,
 206                                     s, "sys_clk_div");
 207         if (!rval)
 208                 rval = bounds_check(dev, pll_bk->pix_clk_freq_hz,
 209                                     lim_bk->min_pix_clk_freq_hz,
 210                                     lim_bk->max_pix_clk_freq_hz,
 211                                     s, "pix_clk_freq_hz");
 212
 213         return rval;
 214 }
 215
 216 static int check_ext_bounds(struct device *dev, struct ccs_pll *pll)
 217 {
 218         if (!(pll->flags & CCS_PLL_FLAG_FIFO_DERATING) &&
 219             pll->pixel_rate_pixel_array > pll->pixel_rate_csi) {
 220                 dev_dbg(dev, "device does not support derating\n");
 221                 return -EINVAL;
 222         }
 223
 224         if (!(pll->flags & CCS_PLL_FLAG_FIFO_OVERRATING) &&
 225             pll->pixel_rate_pixel_array < pll->pixel_rate_csi) {
 226                 dev_dbg(dev, "device does not support overrating\n");
 227                 return -EINVAL;
 228         }
 229
 230         return 0;
 231 }
 232
 233 static void
 234 ccs_pll_find_vt_sys_div(struct device *dev, const struct ccs_pll_limits *lim,
 235                         struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr,
 236                         uint16_t min_vt_div, uint16_t max_vt_div,
 237                         uint16_t *min_sys_div, uint16_t *max_sys_div)
 238 {
 239         /*
 240          * Find limits for sys_clk_div. Not all values are possible with all
 241          * values of pix_clk_div.
 242          */
 243         *min_sys_div = lim->vt_bk.min_sys_clk_div;
 244         dev_dbg(dev, "min_sys_div: %u\n", *min_sys_div);
 245         *min_sys_div = max_t(uint16_t, *min_sys_div,
 246                              DIV_ROUND_UP(min_vt_div,
 247                                           lim->vt_bk.max_pix_clk_div));
 248         dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", *min_sys_div);
 249         *min_sys_div = max_t(uint16_t, *min_sys_div,
 250                              pll_fr->pll_op_clk_freq_hz
 251                              / lim->vt_bk.max_sys_clk_freq_hz);
 252         dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", *min_sys_div);
 253         *min_sys_div = clk_div_even_up(*min_sys_div);
 254         dev_dbg(dev, "min_sys_div: one or even: %u\n", *min_sys_div);
 255
 256         *max_sys_div = lim->vt_bk.max_sys_clk_div;
 257         dev_dbg(dev, "max_sys_div: %u\n", *max_sys_div);
 258         *max_sys_div = min_t(uint16_t, *max_sys_div,
 259                              DIV_ROUND_UP(max_vt_div,
 260                                           lim->vt_bk.min_pix_clk_div));
 261         dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", *max_sys_div);
 262         *max_sys_div = min_t(uint16_t, *max_sys_div,
 263                              DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
 264                                           lim->vt_bk.min_pix_clk_freq_hz));
 265         dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", *max_sys_div);
 266 }
 267
 268 #define CPHY_CONST              7
 269 #define DPHY_CONST              16
 270 #define PHY_CONST_DIV           16
 271
 272 static inline int
 273 __ccs_pll_calculate_vt_tree(struct device *dev,
 274                             const struct ccs_pll_limits *lim,
 275                             struct ccs_pll *pll, uint32_t mul, uint32_t div)
 276 {
 277         const struct ccs_pll_branch_limits_fr *lim_fr = &lim->vt_fr;
 278         const struct ccs_pll_branch_limits_bk *lim_bk = &lim->vt_bk;
 279         struct ccs_pll_branch_fr *pll_fr = &pll->vt_fr;
 280         struct ccs_pll_branch_bk *pll_bk = &pll->vt_bk;
 281         uint32_t more_mul;
 282         uint16_t best_pix_div = SHRT_MAX >> 1, best_div;
 283         uint16_t vt_div, min_sys_div, max_sys_div, sys_div;
 284
 285         pll_fr->pll_ip_clk_freq_hz =
 286                 pll->ext_clk_freq_hz / pll_fr->pre_pll_clk_div;
 287
 288         dev_dbg(dev, "vt_pll_ip_clk_freq_hz %u\n", pll_fr->pll_ip_clk_freq_hz);
 289
 290         more_mul = one_or_more(DIV_ROUND_UP(lim_fr->min_pll_op_clk_freq_hz,
 291                                             pll_fr->pll_ip_clk_freq_hz * mul));
 292
 293         dev_dbg(dev, "more_mul: %u\n", more_mul);
 294         more_mul *= DIV_ROUND_UP(lim_fr->min_pll_multiplier, mul * more_mul);
 295         dev_dbg(dev, "more_mul2: %u\n", more_mul);
 296
 297         pll_fr->pll_multiplier = mul * more_mul;
 298
 299         if (pll_fr->pll_multiplier * pll_fr->pll_ip_clk_freq_hz >
 300             lim_fr->max_pll_op_clk_freq_hz)
 301                 return -EINVAL;
 302
 303         pll_fr->pll_op_clk_freq_hz =
 304                 pll_fr->pll_ip_clk_freq_hz * pll_fr->pll_multiplier;
 305
 306         vt_div = div * more_mul;
 307
 308         ccs_pll_find_vt_sys_div(dev, lim, pll, pll_fr, vt_div, vt_div,
 309                                 &min_sys_div, &max_sys_div);
 310
 311         max_sys_div = (vt_div & 1) ? 1 : max_sys_div;
 312
 313         dev_dbg(dev, "vt min/max_sys_div: %u,%u\n", min_sys_div, max_sys_div);
 314
 315         for (sys_div = min_sys_div; sys_div <= max_sys_div;
 316              sys_div += 2 - (sys_div & 1)) {
 317                 uint16_t pix_div;
 318
 319                 if (vt_div % sys_div)
 320                         continue;
 321
 322                 pix_div = vt_div / sys_div;
 323
 324                 if (pix_div < lim_bk->min_pix_clk_div ||
 325                     pix_div > lim_bk->max_pix_clk_div) {
 326                         dev_dbg(dev,
 327                                 "pix_div %u too small or too big (%u--%u)\n",
 328                                 pix_div,
 329                                 lim_bk->min_pix_clk_div,
 330                                 lim_bk->max_pix_clk_div);
 331                         continue;
 332                 }
 333
 334                 dev_dbg(dev, "sys/pix/best_pix: %u,%u,%u\n", sys_div, pix_div,
 335                         best_pix_div);
 336
 337                 if (pix_div * sys_div <= best_pix_div) {
 338                         best_pix_div = pix_div;
 339                         best_div = pix_div * sys_div;
 340                 }
 341         }
 342         if (best_pix_div == SHRT_MAX >> 1)
 343                 return -EINVAL;
 344
 345         pll_bk->sys_clk_div = best_div / best_pix_div;
 346         pll_bk->pix_clk_div = best_pix_div;
 347
 348         pll_bk->sys_clk_freq_hz =
 349                 pll_fr->pll_op_clk_freq_hz / pll_bk->sys_clk_div;
 350         pll_bk->pix_clk_freq_hz =
 351                 pll_bk->sys_clk_freq_hz / pll_bk->pix_clk_div;
 352
 353         pll->pixel_rate_pixel_array =
 354                 pll_bk->pix_clk_freq_hz * pll->vt_lanes;
 355
 356         return 0;
 357 }
 358
 359 static int ccs_pll_calculate_vt_tree(struct device *dev,
 360                                      const struct ccs_pll_limits *lim,
 361                                      struct ccs_pll *pll)
 362 {
 363         const struct ccs_pll_branch_limits_fr *lim_fr = &lim->vt_fr;
 364         struct ccs_pll_branch_fr *pll_fr = &pll->vt_fr;
 365         uint16_t min_pre_pll_clk_div = lim_fr->min_pre_pll_clk_div;
 366         uint16_t max_pre_pll_clk_div = lim_fr->max_pre_pll_clk_div;
 367         uint32_t pre_mul, pre_div;
 368
 369         pre_div = gcd(pll->pixel_rate_csi,
 370                       pll->ext_clk_freq_hz * pll->vt_lanes);
 371         pre_mul = pll->pixel_rate_csi / pre_div;
 372         pre_div = pll->ext_clk_freq_hz * pll->vt_lanes / pre_div;
 373
 374         /* Make sure PLL input frequency is within limits */
 375         max_pre_pll_clk_div =
 376                 min_t(uint16_t, max_pre_pll_clk_div,
 377                       DIV_ROUND_UP(pll->ext_clk_freq_hz,
 378                                    lim_fr->min_pll_ip_clk_freq_hz));
 379
 380         min_pre_pll_clk_div = max_t(uint16_t, min_pre_pll_clk_div,
 381                                     pll->ext_clk_freq_hz /
 382                                     lim_fr->max_pll_ip_clk_freq_hz);
 383
 384         dev_dbg(dev, "vt min/max_pre_pll_clk_div: %u,%u\n",
 385                 min_pre_pll_clk_div, max_pre_pll_clk_div);
 386
 387         for (pll_fr->pre_pll_clk_div = min_pre_pll_clk_div;
 388              pll_fr->pre_pll_clk_div <= max_pre_pll_clk_div;
 389              pll_fr->pre_pll_clk_div +=
 390                      (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 :
 391                      2 - (pll_fr->pre_pll_clk_div & 1)) {
 392                 uint32_t mul, div;
 393                 int rval;
 394
 395                 div = gcd(pre_mul * pll_fr->pre_pll_clk_div, pre_div);
 396                 mul = pre_mul * pll_fr->pre_pll_clk_div / div;
 397                 div = pre_div / div;
 398
 399                 dev_dbg(dev, "vt pre-div/mul/div: %u,%u,%u\n",
 400                         pll_fr->pre_pll_clk_div, mul, div);
 401
 402                 rval = __ccs_pll_calculate_vt_tree(dev, lim, pll,
 403                                                    mul, div);
 404                 if (rval)
 405                         continue;
 406
 407                 rval = check_fr_bounds(dev, lim, pll, PLL_VT);
 408                 if (rval)
 409                         continue;
 410
 411                 rval = check_bk_bounds(dev, lim, pll, PLL_VT);
 412                 if (rval)
 413                         continue;
 414
 415                 return 0;
 416         }
 417
 418         return -EINVAL;
 419 }
 420
 421 static void
 422 ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
 423                      const struct ccs_pll_branch_limits_bk *op_lim_bk,
 424                      struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr,
 425                      struct ccs_pll_branch_bk *op_pll_bk, bool cphy,
 426                      uint32_t phy_const)
 427 {
 428         uint16_t sys_div;
 429         uint16_t best_pix_div = SHRT_MAX >> 1;
 430         uint16_t vt_op_binning_div;
 431         uint16_t min_vt_div, max_vt_div, vt_div;
 432         uint16_t min_sys_div, max_sys_div;
 433
 434         if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
 435                 goto out_calc_pixel_rate;
 436
 437         /*
 438          * Find out whether a sensor supports derating. If it does not, VT and
 439          * OP domains are required to run at the same pixel rate.
 440          */
 441         if (!(pll->flags & CCS_PLL_FLAG_FIFO_DERATING)) {
 442                 min_vt_div =
 443                         op_pll_bk->sys_clk_div * op_pll_bk->pix_clk_div
 444                         * pll->vt_lanes * phy_const
 445                         / pll->op_lanes / PHY_CONST_DIV;
 446         } else {
 447                 /*
 448                  * Some sensors perform analogue binning and some do this
 449                  * digitally. The ones doing this digitally can be roughly be
 450                  * found out using this formula. The ones doing this digitally
 451                  * should run at higher clock rate, so smaller divisor is used
 452                  * on video timing side.
 453                  */
 454                 if (lim->min_line_length_pck_bin > lim->min_line_length_pck
 455                     / pll->binning_horizontal)
 456                         vt_op_binning_div = pll->binning_horizontal;
 457                 else
 458                         vt_op_binning_div = 1;
 459                 dev_dbg(dev, "vt_op_binning_div: %u\n", vt_op_binning_div);
 460
 461                 /*
 462                  * Profile 2 supports vt_pix_clk_div E [4, 10]
 463                  *
 464                  * Horizontal binning can be used as a base for difference in
 465                  * divisors. One must make sure that horizontal blanking is
 466                  * enough to accommodate the CSI-2 sync codes.
 467                  *
 468                  * Take scaling factor and number of VT lanes into account as well.
 469                  *
 470                  * Find absolute limits for the factor of vt divider.
 471                  */
 472                 dev_dbg(dev, "scale_m: %u\n", pll->scale_m);
 473                 min_vt_div =
 474                         DIV_ROUND_UP(pll->bits_per_pixel
 475                                      * op_pll_bk->sys_clk_div * pll->scale_n
 476                                      * pll->vt_lanes * phy_const,
 477                                      (pll->flags &
 478                                       CCS_PLL_FLAG_LANE_SPEED_MODEL ?
 479                                       pll->csi2.lanes : 1)
 480                                      * vt_op_binning_div * pll->scale_m
 481                                      * PHY_CONST_DIV);
 482         }
 483
 484         /* Find smallest and biggest allowed vt divisor. */
 485         dev_dbg(dev, "min_vt_div: %u\n", min_vt_div);
 486         min_vt_div = max_t(uint16_t, min_vt_div,
 487                            DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
 488                                         lim->vt_bk.max_pix_clk_freq_hz));
 489         dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n",
 490                 min_vt_div);
 491         min_vt_div = max_t(uint16_t, min_vt_div, lim->vt_bk.min_pix_clk_div
 492                                                  * lim->vt_bk.min_sys_clk_div);
 493         dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div);
 494
 495         max_vt_div = lim->vt_bk.max_sys_clk_div * lim->vt_bk.max_pix_clk_div;
 496         dev_dbg(dev, "max_vt_div: %u\n", max_vt_div);
 497         max_vt_div = min_t(uint16_t, max_vt_div,
 498                            DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
 499                                       lim->vt_bk.min_pix_clk_freq_hz));
 500         dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n",
 501                 max_vt_div);
 502
 503         ccs_pll_find_vt_sys_div(dev, lim, pll, pll_fr, min_vt_div,
 504                                 max_vt_div, &min_sys_div, &max_sys_div);
 505
 506         /*
 507          * Find pix_div such that a legal pix_div * sys_div results
 508          * into a value which is not smaller than div, the desired
 509          * divisor.
 510          */
 511         for (vt_div = min_vt_div; vt_div <= max_vt_div; vt_div++) {
 512                 uint16_t __max_sys_div = vt_div & 1 ? 1 : max_sys_div;
 513
 514                 for (sys_div = min_sys_div; sys_div <= __max_sys_div;
 515                      sys_div += 2 - (sys_div & 1)) {
 516                         uint16_t pix_div;
 517                         uint16_t rounded_div;
 518
 519                         pix_div = DIV_ROUND_UP(vt_div, sys_div);
 520
 521                         if (pix_div < lim->vt_bk.min_pix_clk_div
 522                             || pix_div > lim->vt_bk.max_pix_clk_div) {
 523                                 dev_dbg(dev,
 524                                         "pix_div %u too small or too big (%u--%u)\n",
 525                                         pix_div,
 526                                         lim->vt_bk.min_pix_clk_div,
 527                                         lim->vt_bk.max_pix_clk_div);
 528                                 continue;
 529                         }
 530
 531                         rounded_div = roundup(vt_div, best_pix_div);
 532
 533                         /* Check if this one is better. */
 534                         if (pix_div * sys_div <= rounded_div)
 535                                 best_pix_div = pix_div;
 536
 537                         /* Bail out if we've already found the best value. */
 538                         if (vt_div == rounded_div)
 539                                 break;
 540                 }
 541                 if (best_pix_div < SHRT_MAX >> 1)
 542                         break;
 543         }
 544
 545         pll->vt_bk.sys_clk_div = DIV_ROUND_UP(vt_div, best_pix_div);
 546         pll->vt_bk.pix_clk_div = best_pix_div;
 547
 548         pll->vt_bk.sys_clk_freq_hz =
 549                 pll_fr->pll_op_clk_freq_hz / pll->vt_bk.sys_clk_div;
 550         pll->vt_bk.pix_clk_freq_hz =
 551                 pll->vt_bk.sys_clk_freq_hz / pll->vt_bk.pix_clk_div;
 552
 553 out_calc_pixel_rate:
 554         pll->pixel_rate_pixel_array =
 555                 pll->vt_bk.pix_clk_freq_hz * pll->vt_lanes;
 556 }
 557
 558 /*
 559  * Heuristically guess the PLL tree for a given common multiplier and
 560  * divisor. Begin with the operational timing and continue to video
 561  * timing once operational timing has been verified.
 562  *
 563  * @mul is the PLL multiplier and @div is the common divisor
 564  * (pre_pll_clk_div and op_sys_clk_div combined). The final PLL
 565  * multiplier will be a multiple of @mul.
 566  *
 567  * @return Zero on success, error code on error.
 568  */
 569 static int
 570 ccs_pll_calculate_op(struct device *dev, const struct ccs_pll_limits *lim,
 571                      const struct ccs_pll_branch_limits_fr *op_lim_fr,
 572                      const struct ccs_pll_branch_limits_bk *op_lim_bk,
 573                      struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr,
 574                      struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul,
 575                      uint32_t div, uint32_t l, bool cphy, uint32_t phy_const)
 576 {
 577         /*
 578          * Higher multipliers (and divisors) are often required than
 579          * necessitated by the external clock and the output clocks.
 580          * There are limits for all values in the clock tree. These
 581          * are the minimum and maximum multiplier for mul.
 582          */
 583         uint32_t more_mul_min, more_mul_max;
 584         uint32_t more_mul_factor;
 585         uint32_t i;
 586
 587         /*
 588          * Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be
 589          * too high.
 590          */
 591         dev_dbg(dev, "op_pre_pll_clk_div %u\n", op_pll_fr->pre_pll_clk_div);
 592
 593         /* Don't go above max pll multiplier. */
 594         more_mul_max = op_lim_fr->max_pll_multiplier / mul;
 595         dev_dbg(dev, "more_mul_max: max_op_pll_multiplier check: %u\n",
 596                 more_mul_max);
 597         /* Don't go above max pll op frequency. */
 598         more_mul_max =
 599                 min_t(uint32_t,
 600                       more_mul_max,
 601                       op_lim_fr->max_pll_op_clk_freq_hz
 602                       / (pll->ext_clk_freq_hz /
 603                          op_pll_fr->pre_pll_clk_div * mul));
 604         dev_dbg(dev, "more_mul_max: max_pll_op_clk_freq_hz check: %u\n",
 605                 more_mul_max);
 606         /* Don't go above the division capability of op sys clock divider. */
 607         more_mul_max = min(more_mul_max,
 608                            op_lim_bk->max_sys_clk_div * op_pll_fr->pre_pll_clk_div
 609                            / div);
 610         dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n",
 611                 more_mul_max);
 612         /* Ensure we won't go above max_pll_multiplier. */
 613         more_mul_max = min(more_mul_max, op_lim_fr->max_pll_multiplier / mul);
 614         dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n",
 615                 more_mul_max);
 616
 617         /* Ensure we won't go below min_pll_op_clk_freq_hz. */
 618         more_mul_min = DIV_ROUND_UP(op_lim_fr->min_pll_op_clk_freq_hz,
 619                                     pll->ext_clk_freq_hz /
 620                                     op_pll_fr->pre_pll_clk_div * mul);
 621         dev_dbg(dev, "more_mul_min: min_op_pll_op_clk_freq_hz check: %u\n",
 622                 more_mul_min);
 623         /* Ensure we won't go below min_pll_multiplier. */
 624         more_mul_min = max(more_mul_min,
 625                            DIV_ROUND_UP(op_lim_fr->min_pll_multiplier, mul));
 626         dev_dbg(dev, "more_mul_min: min_op_pll_multiplier check: %u\n",
 627                 more_mul_min);
 628
 629         if (more_mul_min > more_mul_max) {
 630                 dev_dbg(dev,
 631                         "unable to compute more_mul_min and more_mul_max\n");
 632                 return -EINVAL;
 633         }
 634
 635         more_mul_factor = lcm(div, op_pll_fr->pre_pll_clk_div) / div;
 636         dev_dbg(dev, "more_mul_factor: %u\n", more_mul_factor);
 637         more_mul_factor = lcm(more_mul_factor, op_lim_bk->min_sys_clk_div);
 638         dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %d\n",
 639                 more_mul_factor);
 640         i = roundup(more_mul_min, more_mul_factor);
 641         if (!is_one_or_even(i))
 642                 i <<= 1;
 643
 644         dev_dbg(dev, "final more_mul: %u\n", i);
 645         if (i > more_mul_max) {
 646                 dev_dbg(dev, "final more_mul is bad, max %u\n", more_mul_max);
 647                 return -EINVAL;
 648         }
 649
 650         op_pll_fr->pll_multiplier = mul * i;
 651         op_pll_bk->sys_clk_div = div * i / op_pll_fr->pre_pll_clk_div;
 652         dev_dbg(dev, "op_sys_clk_div: %u\n", op_pll_bk->sys_clk_div);
 653
 654         op_pll_fr->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz
 655                 / op_pll_fr->pre_pll_clk_div;
 656
 657         op_pll_fr->pll_op_clk_freq_hz = op_pll_fr->pll_ip_clk_freq_hz
 658                 * op_pll_fr->pll_multiplier;
 659
 660         if (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)
 661                 op_pll_bk->pix_clk_div = pll->bits_per_pixel
 662                         * pll->op_lanes * phy_const
 663                         / PHY_CONST_DIV / pll->csi2.lanes / l;
 664         else
 665                 op_pll_bk->pix_clk_div =
 666                         pll->bits_per_pixel * phy_const / PHY_CONST_DIV / l;
 667
 668         op_pll_bk->pix_clk_freq_hz =
 669                 op_pll_bk->sys_clk_freq_hz / op_pll_bk->pix_clk_div;
 670
 671         dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div);
 672
 673         return 0;
 674 }
 675
 676 int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
 677                       struct ccs_pll *pll)
 678 {
 679         const struct ccs_pll_branch_limits_fr *op_lim_fr;
 680         const struct ccs_pll_branch_limits_bk *op_lim_bk;
 681         struct ccs_pll_branch_fr *op_pll_fr;
 682         struct ccs_pll_branch_bk *op_pll_bk;
 683         bool cphy = pll->bus_type == CCS_PLL_BUS_TYPE_CSI2_CPHY;
 684         uint32_t phy_const = cphy ? CPHY_CONST : DPHY_CONST;
 685         uint16_t min_op_pre_pll_clk_div;
 686         uint16_t max_op_pre_pll_clk_div;
 687         uint32_t mul, div;
 688         uint32_t l = (!pll->op_bits_per_lane ||
 689                       pll->op_bits_per_lane >= pll->bits_per_pixel) ? 1 : 2;
 690         uint32_t i;
 691         int rval = -EINVAL;
 692
 693         if (!(pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)) {
 694                 pll->op_lanes = 1;
 695                 pll->vt_lanes = 1;
 696         }
 697
 698         if (pll->flags & CCS_PLL_FLAG_DUAL_PLL) {
 699                 op_lim_fr = &lim->op_fr;
 700                 op_lim_bk = &lim->op_bk;
 701                 op_pll_fr = &pll->op_fr;
 702                 op_pll_bk = &pll->op_bk;
 703         } else if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) {
 704                 /*
 705                  * If there's no OP PLL at all, use the VT values
 706                  * instead. The OP values are ignored for the rest of
 707                  * the PLL calculation.
 708                  */
 709                 op_lim_fr = &lim->vt_fr;
 710                 op_lim_bk = &lim->vt_bk;
 711                 op_pll_fr = &pll->vt_fr;
 712                 op_pll_bk = &pll->vt_bk;
 713         } else {
 714                 op_lim_fr = &lim->vt_fr;
 715                 op_lim_bk = &lim->op_bk;
 716                 op_pll_fr = &pll->vt_fr;
 717                 op_pll_bk = &pll->op_bk;
 718         }
 719
 720         if (!pll->op_lanes || !pll->vt_lanes || !pll->bits_per_pixel ||
 721             !pll->ext_clk_freq_hz || !pll->link_freq || !pll->scale_m ||
 722             !op_lim_fr->min_pll_ip_clk_freq_hz ||
 723             !op_lim_fr->max_pll_ip_clk_freq_hz ||
 724             !op_lim_fr->min_pll_op_clk_freq_hz ||
 725             !op_lim_fr->max_pll_op_clk_freq_hz ||
 726             !op_lim_bk->max_sys_clk_div || !op_lim_fr->max_pll_multiplier)
 727                 return -EINVAL;
 728
 729         /*
 730          * Make sure op_pix_clk_div will be integer --- unless flexible
 731          * op_pix_clk_div is supported
 732          */
 733         if (!(pll->flags & CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV) &&
 734             (pll->bits_per_pixel * pll->op_lanes) % (pll->csi2.lanes * l)) {
 735                 dev_dbg(dev, "op_pix_clk_div not an integer (bpp %u, op lanes %u, lanes %u, l %u)\n",
 736                         pll->bits_per_pixel, pll->op_lanes, pll->csi2.lanes, l);
 737                 return -EINVAL;
 738         }
 739
 740         dev_dbg(dev, "vt_lanes: %u\n", pll->vt_lanes);
 741         dev_dbg(dev, "op_lanes: %u\n", pll->op_lanes);
 742
 743         dev_dbg(dev, "binning: %ux%u\n", pll->binning_horizontal,
 744                 pll->binning_vertical);
 745
 746         switch (pll->bus_type) {
 747         case CCS_PLL_BUS_TYPE_CSI2_DPHY:
 748                 /* CSI transfers 2 bits per clock per lane; thus times 2 */
 749                 op_pll_bk->sys_clk_freq_hz = pll->link_freq * 2
 750                         * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
 751                            1 : pll->csi2.lanes);
 752                 break;
 753         case CCS_PLL_BUS_TYPE_CSI2_CPHY:
 754                 op_pll_bk->sys_clk_freq_hz =
 755                         pll->link_freq
 756                         * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
 757                            1 : pll->csi2.lanes);
 758                 break;
 759         default:
 760                 return -EINVAL;
 761         }
 762
 763         pll->pixel_rate_csi =
 764                 div_u64((uint64_t)op_pll_bk->sys_clk_freq_hz
 765                         * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
 766                            pll->csi2.lanes : 1) * PHY_CONST_DIV,
 767                         phy_const * pll->bits_per_pixel * l);
 768
 769         /* Figure out limits for OP pre-pll divider based on extclk */
 770         dev_dbg(dev, "min / max op_pre_pll_clk_div: %u / %u\n",
 771                 op_lim_fr->min_pre_pll_clk_div, op_lim_fr->max_pre_pll_clk_div);
 772         max_op_pre_pll_clk_div =
 773                 min_t(uint16_t, op_lim_fr->max_pre_pll_clk_div,
 774                       clk_div_even(pll->ext_clk_freq_hz /
 775                                    op_lim_fr->min_pll_ip_clk_freq_hz));
 776         min_op_pre_pll_clk_div =
 777                 max_t(uint16_t, op_lim_fr->min_pre_pll_clk_div,
 778                       clk_div_even_up(
 779                               DIV_ROUND_UP(pll->ext_clk_freq_hz,
 780                                            op_lim_fr->max_pll_ip_clk_freq_hz)));
 781         dev_dbg(dev, "pre-pll check: min / max op_pre_pll_clk_div: %u / %u\n",
 782                 min_op_pre_pll_clk_div, max_op_pre_pll_clk_div);
 783
 784         i = gcd(op_pll_bk->sys_clk_freq_hz, pll->ext_clk_freq_hz);
 785         mul = op_pll_bk->sys_clk_freq_hz / i;
 786         div = pll->ext_clk_freq_hz / i;
 787         dev_dbg(dev, "mul %u / div %u\n", mul, div);
 788
 789         min_op_pre_pll_clk_div =
 790                 max_t(uint16_t, min_op_pre_pll_clk_div,
 791                       clk_div_even_up(
 792                               mul /
 793                               one_or_more(
 794                                       DIV_ROUND_UP(op_lim_fr->max_pll_op_clk_freq_hz,
 795                                                    pll->ext_clk_freq_hz))));
 796         dev_dbg(dev, "pll_op check: min / max op_pre_pll_clk_div: %u / %u\n",
 797                 min_op_pre_pll_clk_div, max_op_pre_pll_clk_div);
 798
 799         for (op_pll_fr->pre_pll_clk_div = min_op_pre_pll_clk_div;
 800              op_pll_fr->pre_pll_clk_div <= max_op_pre_pll_clk_div;
 801              op_pll_fr->pre_pll_clk_div +=
 802                      (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 :
 803                      2 - (op_pll_fr->pre_pll_clk_div & 1)) {
 804                 rval = ccs_pll_calculate_op(dev, lim, op_lim_fr, op_lim_bk, pll,
 805                                             op_pll_fr, op_pll_bk, mul, div, l,
 806                                             cphy, phy_const);
 807                 if (rval)
 808                         continue;
 809
 810                 rval = check_fr_bounds(dev, lim, pll,
 811                                        pll->flags & CCS_PLL_FLAG_DUAL_PLL ?
 812                                        PLL_OP : PLL_VT);
 813                 if (rval)
 814                         continue;
 815
 816                 rval = check_bk_bounds(dev, lim, pll, PLL_OP);
 817                 if (rval)
 818                         continue;
 819
 820                 if (pll->flags & CCS_PLL_FLAG_DUAL_PLL)
 821                         break;
 822
 823                 ccs_pll_calculate_vt(dev, lim, op_lim_bk, pll, op_pll_fr,
 824                                      op_pll_bk, cphy, phy_const);
 825
 826                 rval = check_bk_bounds(dev, lim, pll, PLL_VT);
 827                 if (rval)
 828                         continue;
 829                 rval = check_ext_bounds(dev, pll);
 830                 if (rval)
 831                         continue;
 832
 833                 break;
 834         }
 835
 836         if (rval) {
 837                 dev_dbg(dev, "unable to compute pre_pll divisor\n");
 838
 839                 return rval;
 840         }
 841
 842         if (pll->flags & CCS_PLL_FLAG_DUAL_PLL) {
 843                 rval = ccs_pll_calculate_vt_tree(dev, lim, pll);
 844
 845                 if (rval)
 846                         return rval;
 847         }
 848
 849         print_pll(dev, pll);
 850
 851         return 0;
 852 }
 853 EXPORT_SYMBOL_GPL(ccs_pll_calculate);
 854
 855 MODULE_AUTHOR("Sakari Ailus <sakari.ailus@linux.intel.com>");
 856 MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ PLL calculator");
 857 MODULE_LICENSE("GPL v2");