2 * Montage M88DS3103 demodulator driver
4 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 #include "m88ds3103_priv.h"
23 static struct dvb_frontend_ops m88ds3103_ops;
25 /* write multiple registers */
26 static int m88ds3103_wr_regs(struct m88ds3103_priv *priv,
27 u8 reg, const u8 *val, int len)
30 #define MAX_WR_XFER_LEN (MAX_WR_LEN + 1)
32 u8 buf[MAX_WR_XFER_LEN];
33 struct i2c_msg msg[1] = {
35 .addr = priv->cfg->i2c_addr,
42 if (WARN_ON(len > MAX_WR_LEN))
46 memcpy(&buf[1], val, len);
48 mutex_lock(&priv->i2c_mutex);
49 ret = i2c_transfer(priv->i2c, msg, 1);
50 mutex_unlock(&priv->i2c_mutex);
54 dev_warn(&priv->i2c->dev,
55 "%s: i2c wr failed=%d reg=%02x len=%d\n",
56 KBUILD_MODNAME, ret, reg, len);
63 /* read multiple registers */
64 static int m88ds3103_rd_regs(struct m88ds3103_priv *priv,
65 u8 reg, u8 *val, int len)
68 #define MAX_RD_XFER_LEN (MAX_RD_LEN)
70 u8 buf[MAX_RD_XFER_LEN];
71 struct i2c_msg msg[2] = {
73 .addr = priv->cfg->i2c_addr,
78 .addr = priv->cfg->i2c_addr,
85 if (WARN_ON(len > MAX_RD_LEN))
88 mutex_lock(&priv->i2c_mutex);
89 ret = i2c_transfer(priv->i2c, msg, 2);
90 mutex_unlock(&priv->i2c_mutex);
92 memcpy(val, buf, len);
95 dev_warn(&priv->i2c->dev,
96 "%s: i2c rd failed=%d reg=%02x len=%d\n",
97 KBUILD_MODNAME, ret, reg, len);
104 /* write single register */
105 static int m88ds3103_wr_reg(struct m88ds3103_priv *priv, u8 reg, u8 val)
107 return m88ds3103_wr_regs(priv, reg, &val, 1);
110 /* read single register */
111 static int m88ds3103_rd_reg(struct m88ds3103_priv *priv, u8 reg, u8 *val)
113 return m88ds3103_rd_regs(priv, reg, val, 1);
116 /* write single register with mask */
117 static int m88ds3103_wr_reg_mask(struct m88ds3103_priv *priv,
118 u8 reg, u8 val, u8 mask)
123 /* no need for read if whole reg is written */
125 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1);
134 return m88ds3103_wr_regs(priv, reg, &val, 1);
137 /* read single register with mask */
138 static int m88ds3103_rd_reg_mask(struct m88ds3103_priv *priv,
139 u8 reg, u8 *val, u8 mask)
144 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1);
150 /* find position of the first bit */
151 for (i = 0; i < 8; i++) {
152 if ((mask >> i) & 0x01)
160 /* write reg val table using reg addr auto increment */
161 static int m88ds3103_wr_reg_val_tab(struct m88ds3103_priv *priv,
162 const struct m88ds3103_reg_val *tab, int tab_len)
166 dev_dbg(&priv->i2c->dev, "%s: tab_len=%d\n", __func__, tab_len);
173 for (i = 0, j = 0; i < tab_len; i++, j++) {
176 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 ||
177 !((j + 1) % (priv->cfg->i2c_wr_max - 1))) {
178 ret = m88ds3103_wr_regs(priv, tab[i].reg - j, buf, j + 1);
188 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
192 static int m88ds3103_read_status(struct dvb_frontend *fe, fe_status_t *status)
194 struct m88ds3103_priv *priv = fe->demodulator_priv;
195 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
206 switch (c->delivery_system) {
208 ret = m88ds3103_rd_reg_mask(priv, 0xd1, &u8tmp, 0x07);
213 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
214 FE_HAS_VITERBI | FE_HAS_SYNC |
218 ret = m88ds3103_rd_reg_mask(priv, 0x0d, &u8tmp, 0x8f);
223 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
224 FE_HAS_VITERBI | FE_HAS_SYNC |
228 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
234 priv->fe_status = *status;
236 dev_dbg(&priv->i2c->dev, "%s: lock=%02x status=%02x\n",
237 __func__, u8tmp, *status);
241 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
245 static int m88ds3103_set_frontend(struct dvb_frontend *fe)
247 struct m88ds3103_priv *priv = fe->demodulator_priv;
248 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
250 const struct m88ds3103_reg_val *init;
251 u8 u8tmp, u8tmp1, u8tmp2;
253 u16 u16tmp, divide_ratio;
254 u32 tuner_frequency, target_mclk, ts_clk;
256 dev_dbg(&priv->i2c->dev,
257 "%s: delivery_system=%d modulation=%d frequency=%d symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n",
258 __func__, c->delivery_system,
259 c->modulation, c->frequency, c->symbol_rate,
260 c->inversion, c->pilot, c->rolloff);
268 if (fe->ops.tuner_ops.set_params) {
269 ret = fe->ops.tuner_ops.set_params(fe);
274 if (fe->ops.tuner_ops.get_frequency) {
275 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency);
281 ret = m88ds3103_wr_reg(priv, 0x07, 0x80);
285 ret = m88ds3103_wr_reg(priv, 0x07, 0x00);
289 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01);
293 ret = m88ds3103_wr_reg(priv, 0x00, 0x01);
297 switch (c->delivery_system) {
299 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals);
300 init = m88ds3103_dvbs_init_reg_vals;
304 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals);
305 init = m88ds3103_dvbs2_init_reg_vals;
307 switch (priv->cfg->ts_mode) {
308 case M88DS3103_TS_SERIAL:
309 case M88DS3103_TS_SERIAL_D7:
310 if (c->symbol_rate < 18000000)
313 target_mclk = 144000;
315 case M88DS3103_TS_PARALLEL:
316 case M88DS3103_TS_PARALLEL_12:
317 case M88DS3103_TS_PARALLEL_16:
318 case M88DS3103_TS_PARALLEL_19_2:
319 case M88DS3103_TS_CI:
320 if (c->symbol_rate < 18000000)
322 else if (c->symbol_rate < 28000000)
323 target_mclk = 144000;
325 target_mclk = 192000;
328 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n",
335 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
341 /* program init table */
342 if (c->delivery_system != priv->delivery_system) {
343 ret = m88ds3103_wr_reg_val_tab(priv, init, len);
348 u8tmp1 = 0; /* silence compiler warning */
349 switch (priv->cfg->ts_mode) {
350 case M88DS3103_TS_SERIAL:
355 case M88DS3103_TS_SERIAL_D7:
360 case M88DS3103_TS_PARALLEL:
364 case M88DS3103_TS_PARALLEL_12:
368 case M88DS3103_TS_PARALLEL_16:
372 case M88DS3103_TS_PARALLEL_19_2:
376 case M88DS3103_TS_CI:
381 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n", __func__);
387 ret = m88ds3103_wr_reg(priv, 0xfd, u8tmp);
391 switch (priv->cfg->ts_mode) {
392 case M88DS3103_TS_SERIAL:
393 case M88DS3103_TS_SERIAL_D7:
394 ret = m88ds3103_wr_reg_mask(priv, 0x29, u8tmp1, 0x20);
400 divide_ratio = DIV_ROUND_UP(target_mclk, ts_clk);
401 u8tmp1 = divide_ratio / 2;
402 u8tmp2 = DIV_ROUND_UP(divide_ratio, 2);
409 dev_dbg(&priv->i2c->dev,
410 "%s: target_mclk=%d ts_clk=%d divide_ratio=%d\n",
411 __func__, target_mclk, ts_clk, divide_ratio);
415 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */
417 /* u8tmp2[5:0] => ea[5:0] */
420 ret = m88ds3103_rd_reg(priv, 0xfe, &u8tmp);
424 u8tmp = ((u8tmp & 0xf0) << 0) | u8tmp1 >> 2;
425 ret = m88ds3103_wr_reg(priv, 0xfe, u8tmp);
429 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0;
430 ret = m88ds3103_wr_reg(priv, 0xea, u8tmp);
434 switch (target_mclk) {
436 u8tmp1 = 0x00; /* 0b00 */
437 u8tmp2 = 0x03; /* 0b11 */
440 u8tmp1 = 0x02; /* 0b10 */
441 u8tmp2 = 0x01; /* 0b01 */
444 u8tmp1 = 0x01; /* 0b01 */
445 u8tmp2 = 0x01; /* 0b01 */
448 u8tmp1 = 0x00; /* 0b00 */
449 u8tmp2 = 0x01; /* 0b01 */
452 u8tmp1 = 0x03; /* 0b11 */
453 u8tmp2 = 0x00; /* 0b00 */
456 dev_dbg(&priv->i2c->dev, "%s: invalid target_mclk\n", __func__);
461 ret = m88ds3103_wr_reg_mask(priv, 0x22, u8tmp1 << 6, 0xc0);
465 ret = m88ds3103_wr_reg_mask(priv, 0x24, u8tmp2 << 6, 0xc0);
469 if (c->symbol_rate <= 3000000)
471 else if (c->symbol_rate <= 10000000)
476 ret = m88ds3103_wr_reg(priv, 0xc3, 0x08);
480 ret = m88ds3103_wr_reg(priv, 0xc8, u8tmp);
484 ret = m88ds3103_wr_reg(priv, 0xc4, 0x08);
488 ret = m88ds3103_wr_reg(priv, 0xc7, 0x00);
492 u16tmp = DIV_ROUND_CLOSEST((c->symbol_rate / 1000) << 15, M88DS3103_MCLK_KHZ / 2);
493 buf[0] = (u16tmp >> 0) & 0xff;
494 buf[1] = (u16tmp >> 8) & 0xff;
495 ret = m88ds3103_wr_regs(priv, 0x61, buf, 2);
499 ret = m88ds3103_wr_reg_mask(priv, 0x4d, priv->cfg->spec_inv << 1, 0x02);
503 ret = m88ds3103_wr_reg_mask(priv, 0x30, priv->cfg->agc_inv << 4, 0x10);
507 ret = m88ds3103_wr_reg(priv, 0x33, priv->cfg->agc);
511 dev_dbg(&priv->i2c->dev, "%s: carrier offset=%d\n", __func__,
512 (tuner_frequency - c->frequency));
514 s32tmp = 0x10000 * (tuner_frequency - c->frequency);
515 s32tmp = DIV_ROUND_CLOSEST(s32tmp, M88DS3103_MCLK_KHZ);
519 buf[0] = (s32tmp >> 0) & 0xff;
520 buf[1] = (s32tmp >> 8) & 0xff;
521 ret = m88ds3103_wr_regs(priv, 0x5e, buf, 2);
525 ret = m88ds3103_wr_reg(priv, 0x00, 0x00);
529 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00);
533 priv->delivery_system = c->delivery_system;
537 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
541 static int m88ds3103_init(struct dvb_frontend *fe)
543 struct m88ds3103_priv *priv = fe->demodulator_priv;
544 int ret, len, remaining;
545 const struct firmware *fw = NULL;
546 u8 *fw_file = M88DS3103_FIRMWARE;
548 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
550 /* set cold state by default */
553 /* wake up device from sleep */
554 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x01, 0x01);
558 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x00, 0x01);
562 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x00, 0x10);
567 ret = m88ds3103_wr_reg(priv, 0x07, 0x60);
571 ret = m88ds3103_wr_reg(priv, 0x07, 0x00);
575 /* firmware status */
576 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp);
580 dev_dbg(&priv->i2c->dev, "%s: firmware=%02x\n", __func__, u8tmp);
583 goto skip_fw_download;
585 /* cold state - try to download firmware */
586 dev_info(&priv->i2c->dev, "%s: found a '%s' in cold state\n",
587 KBUILD_MODNAME, m88ds3103_ops.info.name);
589 /* request the firmware, this will block and timeout */
590 ret = request_firmware(&fw, fw_file, priv->i2c->dev.parent);
592 dev_err(&priv->i2c->dev, "%s: firmare file '%s' not found\n",
593 KBUILD_MODNAME, fw_file);
597 dev_info(&priv->i2c->dev, "%s: downloading firmware from file '%s'\n",
598 KBUILD_MODNAME, fw_file);
600 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01);
604 for (remaining = fw->size; remaining > 0;
605 remaining -= (priv->cfg->i2c_wr_max - 1)) {
607 if (len > (priv->cfg->i2c_wr_max - 1))
608 len = (priv->cfg->i2c_wr_max - 1);
610 ret = m88ds3103_wr_regs(priv, 0xb0,
611 &fw->data[fw->size - remaining], len);
613 dev_err(&priv->i2c->dev,
614 "%s: firmware download failed=%d\n",
615 KBUILD_MODNAME, ret);
620 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00);
624 release_firmware(fw);
627 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp);
632 dev_info(&priv->i2c->dev, "%s: firmware did not run\n",
638 dev_info(&priv->i2c->dev, "%s: found a '%s' in warm state\n",
639 KBUILD_MODNAME, m88ds3103_ops.info.name);
640 dev_info(&priv->i2c->dev, "%s: firmware version %X.%X\n",
641 KBUILD_MODNAME, (u8tmp >> 4) & 0xf, (u8tmp >> 0 & 0xf));
650 release_firmware(fw);
652 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
656 static int m88ds3103_sleep(struct dvb_frontend *fe)
658 struct m88ds3103_priv *priv = fe->demodulator_priv;
660 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
662 priv->delivery_system = SYS_UNDEFINED;
665 ret = m88ds3103_wr_reg_mask(priv, 0x27, 0x00, 0x01);
670 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01);
674 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01);
678 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10);
684 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
688 static int m88ds3103_get_frontend(struct dvb_frontend *fe)
690 struct m88ds3103_priv *priv = fe->demodulator_priv;
691 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
694 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
696 if (!priv->warm || !(priv->fe_status & FE_HAS_LOCK)) {
701 switch (c->delivery_system) {
703 ret = m88ds3103_rd_reg(priv, 0xe0, &buf[0]);
707 ret = m88ds3103_rd_reg(priv, 0xe6, &buf[1]);
711 switch ((buf[0] >> 2) & 0x01) {
713 c->inversion = INVERSION_OFF;
716 c->inversion = INVERSION_ON;
719 dev_dbg(&priv->i2c->dev, "%s: invalid inversion\n",
723 switch ((buf[1] >> 5) & 0x07) {
725 c->fec_inner = FEC_7_8;
728 c->fec_inner = FEC_5_6;
731 c->fec_inner = FEC_3_4;
734 c->fec_inner = FEC_2_3;
737 c->fec_inner = FEC_1_2;
740 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n",
744 c->modulation = QPSK;
748 ret = m88ds3103_rd_reg(priv, 0x7e, &buf[0]);
752 ret = m88ds3103_rd_reg(priv, 0x89, &buf[1]);
756 ret = m88ds3103_rd_reg(priv, 0xf2, &buf[2]);
760 switch ((buf[0] >> 0) & 0x0f) {
762 c->fec_inner = FEC_2_5;
765 c->fec_inner = FEC_1_2;
768 c->fec_inner = FEC_3_5;
771 c->fec_inner = FEC_2_3;
774 c->fec_inner = FEC_3_4;
777 c->fec_inner = FEC_4_5;
780 c->fec_inner = FEC_5_6;
783 c->fec_inner = FEC_8_9;
786 c->fec_inner = FEC_9_10;
789 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n",
793 switch ((buf[0] >> 5) & 0x01) {
795 c->pilot = PILOT_OFF;
801 dev_dbg(&priv->i2c->dev, "%s: invalid pilot\n",
805 switch ((buf[0] >> 6) & 0x07) {
807 c->modulation = QPSK;
810 c->modulation = PSK_8;
813 c->modulation = APSK_16;
816 c->modulation = APSK_32;
819 dev_dbg(&priv->i2c->dev, "%s: invalid modulation\n",
823 switch ((buf[1] >> 7) & 0x01) {
825 c->inversion = INVERSION_OFF;
828 c->inversion = INVERSION_ON;
831 dev_dbg(&priv->i2c->dev, "%s: invalid inversion\n",
835 switch ((buf[2] >> 0) & 0x03) {
837 c->rolloff = ROLLOFF_35;
840 c->rolloff = ROLLOFF_25;
843 c->rolloff = ROLLOFF_20;
846 dev_dbg(&priv->i2c->dev, "%s: invalid rolloff\n",
851 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
857 ret = m88ds3103_rd_regs(priv, 0x6d, buf, 2);
861 c->symbol_rate = 1ull * ((buf[1] << 8) | (buf[0] << 0)) *
862 M88DS3103_MCLK_KHZ * 1000 / 0x10000;
866 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
870 static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr)
872 struct m88ds3103_priv *priv = fe->demodulator_priv;
873 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
877 u32 noise_tot, signal_tot;
878 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
879 /* reports SNR in resolution of 0.1 dB */
881 /* more iterations for more accurate estimation */
882 #define M88DS3103_SNR_ITERATIONS 3
884 switch (c->delivery_system) {
888 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
889 ret = m88ds3103_rd_reg(priv, 0xff, &buf[0]);
896 /* use of one register limits max value to 15 dB */
897 /* SNR(X) dB = 10 * ln(X) / ln(10) dB */
898 tmp = DIV_ROUND_CLOSEST(tmp, 8 * M88DS3103_SNR_ITERATIONS);
900 *snr = 100ul * intlog2(tmp) / intlog2(10);
908 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
909 ret = m88ds3103_rd_regs(priv, 0x8c, buf, 3);
913 noise = buf[1] << 6; /* [13:6] */
914 noise |= buf[0] & 0x3f; /* [5:0] */
916 signal = buf[2] * buf[2];
920 signal_tot += signal;
923 noise = noise_tot / M88DS3103_SNR_ITERATIONS;
924 signal = signal_tot / M88DS3103_SNR_ITERATIONS;
926 /* SNR(X) dB = 10 * log10(X) dB */
927 if (signal > noise) {
928 tmp = signal / noise;
929 *snr = 100ul * intlog10(tmp) / (1 << 24);
934 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
942 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
947 static int m88ds3103_set_tone(struct dvb_frontend *fe,
948 fe_sec_tone_mode_t fe_sec_tone_mode)
950 struct m88ds3103_priv *priv = fe->demodulator_priv;
952 u8 u8tmp, tone, reg_a1_mask;
953 dev_dbg(&priv->i2c->dev, "%s: fe_sec_tone_mode=%d\n", __func__,
961 switch (fe_sec_tone_mode) {
971 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_tone_mode\n",
977 u8tmp = tone << 7 | priv->cfg->envelope_mode << 5;
978 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
983 ret = m88ds3103_wr_reg_mask(priv, 0xa1, u8tmp, reg_a1_mask);
989 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
993 static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe,
994 struct dvb_diseqc_master_cmd *diseqc_cmd)
996 struct m88ds3103_priv *priv = fe->demodulator_priv;
999 dev_dbg(&priv->i2c->dev, "%s: msg=%*ph\n", __func__,
1000 diseqc_cmd->msg_len, diseqc_cmd->msg);
1007 if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) {
1012 u8tmp = priv->cfg->envelope_mode << 5;
1013 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1017 ret = m88ds3103_wr_regs(priv, 0xa3, diseqc_cmd->msg,
1018 diseqc_cmd->msg_len);
1022 ret = m88ds3103_wr_reg(priv, 0xa1,
1023 (diseqc_cmd->msg_len - 1) << 3 | 0x07);
1027 /* DiSEqC message typical period is 54 ms */
1028 usleep_range(40000, 60000);
1030 /* wait DiSEqC TX ready */
1031 for (i = 20, u8tmp = 1; i && u8tmp; i--) {
1032 usleep_range(5000, 10000);
1034 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40);
1039 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i);
1042 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__);
1044 ret = m88ds3103_wr_reg_mask(priv, 0xa1, 0x40, 0xc0);
1049 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0);
1060 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1064 static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe,
1065 fe_sec_mini_cmd_t fe_sec_mini_cmd)
1067 struct m88ds3103_priv *priv = fe->demodulator_priv;
1070 dev_dbg(&priv->i2c->dev, "%s: fe_sec_mini_cmd=%d\n", __func__,
1078 u8tmp = priv->cfg->envelope_mode << 5;
1079 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1083 switch (fe_sec_mini_cmd) {
1091 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_mini_cmd\n",
1097 ret = m88ds3103_wr_reg(priv, 0xa1, burst);
1101 /* DiSEqC ToneBurst period is 12.5 ms */
1102 usleep_range(11000, 20000);
1104 /* wait DiSEqC TX ready */
1105 for (i = 5, u8tmp = 1; i && u8tmp; i--) {
1106 usleep_range(800, 2000);
1108 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40);
1113 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i);
1115 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0);
1120 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__);
1127 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1131 static int m88ds3103_get_tune_settings(struct dvb_frontend *fe,
1132 struct dvb_frontend_tune_settings *s)
1134 s->min_delay_ms = 3000;
1139 static void m88ds3103_release(struct dvb_frontend *fe)
1141 struct m88ds3103_priv *priv = fe->demodulator_priv;
1142 i2c_del_mux_adapter(priv->i2c_adapter);
1146 static int m88ds3103_select(struct i2c_adapter *adap, void *mux_priv, u32 chan)
1148 struct m88ds3103_priv *priv = mux_priv;
1150 struct i2c_msg gate_open_msg[1] = {
1152 .addr = priv->cfg->i2c_addr,
1159 mutex_lock(&priv->i2c_mutex);
1161 /* open tuner I2C repeater for 1 xfer, closes automatically */
1162 ret = __i2c_transfer(priv->i2c, gate_open_msg, 1);
1164 dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d\n",
1165 KBUILD_MODNAME, ret);
1175 static int m88ds3103_deselect(struct i2c_adapter *adap, void *mux_priv,
1178 struct m88ds3103_priv *priv = mux_priv;
1180 mutex_unlock(&priv->i2c_mutex);
1185 struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg,
1186 struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter)
1189 struct m88ds3103_priv *priv;
1192 /* allocate memory for the internal priv */
1193 priv = kzalloc(sizeof(struct m88ds3103_priv), GFP_KERNEL);
1196 dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME);
1202 mutex_init(&priv->i2c_mutex);
1204 ret = m88ds3103_rd_reg(priv, 0x01, &chip_id);
1208 dev_dbg(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id);
1217 switch (priv->cfg->clock_out) {
1218 case M88DS3103_CLOCK_OUT_DISABLED:
1221 case M88DS3103_CLOCK_OUT_ENABLED:
1224 case M88DS3103_CLOCK_OUT_ENABLED_DIV2:
1231 ret = m88ds3103_wr_reg(priv, 0x29, u8tmp);
1236 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01);
1240 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01);
1244 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10);
1248 /* create mux i2c adapter for tuner */
1249 priv->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, priv, 0, 0, 0,
1250 m88ds3103_select, m88ds3103_deselect);
1251 if (priv->i2c_adapter == NULL)
1254 *tuner_i2c_adapter = priv->i2c_adapter;
1256 /* create dvb_frontend */
1257 memcpy(&priv->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops));
1258 priv->fe.demodulator_priv = priv;
1262 dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
1266 EXPORT_SYMBOL(m88ds3103_attach);
1268 static struct dvb_frontend_ops m88ds3103_ops = {
1269 .delsys = { SYS_DVBS, SYS_DVBS2 },
1271 .name = "Montage M88DS3103",
1272 .frequency_min = 950000,
1273 .frequency_max = 2150000,
1274 .frequency_tolerance = 5000,
1275 .symbol_rate_min = 1000000,
1276 .symbol_rate_max = 45000000,
1277 .caps = FE_CAN_INVERSION_AUTO |
1289 FE_CAN_2G_MODULATION
1292 .release = m88ds3103_release,
1294 .get_tune_settings = m88ds3103_get_tune_settings,
1296 .init = m88ds3103_init,
1297 .sleep = m88ds3103_sleep,
1299 .set_frontend = m88ds3103_set_frontend,
1300 .get_frontend = m88ds3103_get_frontend,
1302 .read_status = m88ds3103_read_status,
1303 .read_snr = m88ds3103_read_snr,
1305 .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd,
1306 .diseqc_send_burst = m88ds3103_diseqc_send_burst,
1308 .set_tone = m88ds3103_set_tone,
1311 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1312 MODULE_DESCRIPTION("Montage M88DS3103 DVB-S/S2 demodulator driver");
1313 MODULE_LICENSE("GPL");
1314 MODULE_FIRMWARE(M88DS3103_FIRMWARE);