2 * drxk_hard: DRX-K DVB-C/T demodulator driver
4 * Copyright (C) 2010-2011 Digital Devices GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/firmware.h>
30 #include <linux/i2c.h>
31 #include <linux/hardirq.h>
32 #include <asm/div64.h>
34 #include "dvb_frontend.h"
36 #include "drxk_hard.h"
39 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode);
40 static int PowerDownQAM(struct drxk_state *state);
41 static int SetDVBTStandard(struct drxk_state *state,
42 enum OperationMode oMode);
43 static int SetQAMStandard(struct drxk_state *state,
44 enum OperationMode oMode);
45 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
47 static int SetDVBTStandard(struct drxk_state *state,
48 enum OperationMode oMode);
49 static int DVBTStart(struct drxk_state *state);
50 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
52 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus);
53 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus);
54 static int SwitchAntennaToQAM(struct drxk_state *state);
55 static int SwitchAntennaToDVBT(struct drxk_state *state);
57 static bool IsDVBT(struct drxk_state *state)
59 return state->m_OperationMode == OM_DVBT;
62 static bool IsQAM(struct drxk_state *state)
64 return state->m_OperationMode == OM_QAM_ITU_A ||
65 state->m_OperationMode == OM_QAM_ITU_B ||
66 state->m_OperationMode == OM_QAM_ITU_C;
71 #define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
72 #define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0)
74 #define DEFAULT_MER_83 165
75 #define DEFAULT_MER_93 250
77 #ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
78 #define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
81 #ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
82 #define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
85 #define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
86 #define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
88 #ifndef DRXK_KI_RAGC_ATV
89 #define DRXK_KI_RAGC_ATV 4
91 #ifndef DRXK_KI_IAGC_ATV
92 #define DRXK_KI_IAGC_ATV 6
94 #ifndef DRXK_KI_DAGC_ATV
95 #define DRXK_KI_DAGC_ATV 7
98 #ifndef DRXK_KI_RAGC_QAM
99 #define DRXK_KI_RAGC_QAM 3
101 #ifndef DRXK_KI_IAGC_QAM
102 #define DRXK_KI_IAGC_QAM 4
104 #ifndef DRXK_KI_DAGC_QAM
105 #define DRXK_KI_DAGC_QAM 7
107 #ifndef DRXK_KI_RAGC_DVBT
108 #define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
110 #ifndef DRXK_KI_IAGC_DVBT
111 #define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
113 #ifndef DRXK_KI_DAGC_DVBT
114 #define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
117 #ifndef DRXK_AGC_DAC_OFFSET
118 #define DRXK_AGC_DAC_OFFSET (0x800)
121 #ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
122 #define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
125 #ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
126 #define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
129 #ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
130 #define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
133 #ifndef DRXK_QAM_SYMBOLRATE_MAX
134 #define DRXK_QAM_SYMBOLRATE_MAX (7233000)
137 #define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56
138 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64
139 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0
140 #define DRXK_BL_ROM_OFFSET_TAPS_BG 24
141 #define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32
142 #define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40
143 #define DRXK_BL_ROM_OFFSET_TAPS_FM 48
144 #define DRXK_BL_ROM_OFFSET_UCODE 0
146 #define DRXK_BLC_TIMEOUT 100
148 #define DRXK_BLCC_NR_ELEMENTS_TAPS 2
149 #define DRXK_BLCC_NR_ELEMENTS_UCODE 6
151 #define DRXK_BLDC_NR_ELEMENTS_TAPS 28
153 #ifndef DRXK_OFDM_NE_NOTCH_WIDTH
154 #define DRXK_OFDM_NE_NOTCH_WIDTH (4)
157 #define DRXK_QAM_SL_SIG_POWER_QAM16 (40960)
158 #define DRXK_QAM_SL_SIG_POWER_QAM32 (20480)
159 #define DRXK_QAM_SL_SIG_POWER_QAM64 (43008)
160 #define DRXK_QAM_SL_SIG_POWER_QAM128 (20992)
161 #define DRXK_QAM_SL_SIG_POWER_QAM256 (43520)
163 static unsigned int debug;
164 module_param(debug, int, 0644);
165 MODULE_PARM_DESC(debug, "enable debug messages");
167 #define dprintk(level, fmt, arg...) do { \
168 if (debug >= level) \
169 printk(KERN_DEBUG "drxk: %s" fmt, __func__, ## arg); \
173 static inline u32 MulDiv32(u32 a, u32 b, u32 c)
177 tmp64 = (u64) a * (u64) b;
183 static inline u32 Frac28a(u32 a, u32 c)
189 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */
190 Q1 = a / c; /* integer part, only the 4 least significant bits
191 will be visible in the result */
193 /* division using radix 16, 7 nibbles in the result */
194 for (i = 0; i < 7; i++) {
195 Q1 = (Q1 << 4) | (R0 / c);
205 static inline u32 log10times100(u32 value)
207 return (100L * intlog10(value)) >> 24;
210 /****************************************************************************/
211 /* I2C **********************************************************************/
212 /****************************************************************************/
214 static int drxk_i2c_lock(struct drxk_state *state)
216 i2c_lock_adapter(state->i2c);
217 state->drxk_i2c_exclusive_lock = true;
222 static void drxk_i2c_unlock(struct drxk_state *state)
224 if (!state->drxk_i2c_exclusive_lock)
227 i2c_unlock_adapter(state->i2c);
228 state->drxk_i2c_exclusive_lock = false;
231 static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs,
234 if (state->drxk_i2c_exclusive_lock)
235 return __i2c_transfer(state->i2c, msgs, len);
237 return i2c_transfer(state->i2c, msgs, len);
240 static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val)
242 struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
243 .buf = val, .len = 1}
246 return drxk_i2c_transfer(state, msgs, 1);
249 static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len)
252 struct i2c_msg msg = {
253 .addr = adr, .flags = 0, .buf = data, .len = len };
258 for (i = 0; i < len; i++)
259 printk(KERN_CONT " %02x", data[i]);
260 printk(KERN_CONT "\n");
262 status = drxk_i2c_transfer(state, &msg, 1);
263 if (status >= 0 && status != 1)
267 printk(KERN_ERR "drxk: i2c write error at addr 0x%02x\n", adr);
272 static int i2c_read(struct drxk_state *state,
273 u8 adr, u8 *msg, int len, u8 *answ, int alen)
276 struct i2c_msg msgs[2] = {
277 {.addr = adr, .flags = 0,
278 .buf = msg, .len = len},
279 {.addr = adr, .flags = I2C_M_RD,
280 .buf = answ, .len = alen}
283 status = drxk_i2c_transfer(state, msgs, 2);
286 printk(KERN_CONT ": ERROR!\n");
290 printk(KERN_ERR "drxk: i2c read error at addr 0x%02x\n", adr);
295 dprintk(2, ": read from");
296 for (i = 0; i < len; i++)
297 printk(KERN_CONT " %02x", msg[i]);
298 printk(KERN_CONT ", value = ");
299 for (i = 0; i < alen; i++)
300 printk(KERN_CONT " %02x", answ[i]);
301 printk(KERN_CONT "\n");
306 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
309 u8 adr = state->demod_address, mm1[4], mm2[2], len;
311 if (state->single_master)
314 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
315 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
316 mm1[1] = ((reg >> 16) & 0xFF);
317 mm1[2] = ((reg >> 24) & 0xFF) | flags;
318 mm1[3] = ((reg >> 7) & 0xFF);
321 mm1[0] = ((reg << 1) & 0xFF);
322 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
325 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
326 status = i2c_read(state, adr, mm1, len, mm2, 2);
330 *data = mm2[0] | (mm2[1] << 8);
335 static int read16(struct drxk_state *state, u32 reg, u16 *data)
337 return read16_flags(state, reg, data, 0);
340 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
343 u8 adr = state->demod_address, mm1[4], mm2[4], len;
345 if (state->single_master)
348 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
349 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
350 mm1[1] = ((reg >> 16) & 0xFF);
351 mm1[2] = ((reg >> 24) & 0xFF) | flags;
352 mm1[3] = ((reg >> 7) & 0xFF);
355 mm1[0] = ((reg << 1) & 0xFF);
356 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
359 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
360 status = i2c_read(state, adr, mm1, len, mm2, 4);
364 *data = mm2[0] | (mm2[1] << 8) |
365 (mm2[2] << 16) | (mm2[3] << 24);
370 static int read32(struct drxk_state *state, u32 reg, u32 *data)
372 return read32_flags(state, reg, data, 0);
375 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
377 u8 adr = state->demod_address, mm[6], len;
379 if (state->single_master)
381 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
382 mm[0] = (((reg << 1) & 0xFF) | 0x01);
383 mm[1] = ((reg >> 16) & 0xFF);
384 mm[2] = ((reg >> 24) & 0xFF) | flags;
385 mm[3] = ((reg >> 7) & 0xFF);
388 mm[0] = ((reg << 1) & 0xFF);
389 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
392 mm[len] = data & 0xff;
393 mm[len + 1] = (data >> 8) & 0xff;
395 dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
396 return i2c_write(state, adr, mm, len + 2);
399 static int write16(struct drxk_state *state, u32 reg, u16 data)
401 return write16_flags(state, reg, data, 0);
404 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
406 u8 adr = state->demod_address, mm[8], len;
408 if (state->single_master)
410 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
411 mm[0] = (((reg << 1) & 0xFF) | 0x01);
412 mm[1] = ((reg >> 16) & 0xFF);
413 mm[2] = ((reg >> 24) & 0xFF) | flags;
414 mm[3] = ((reg >> 7) & 0xFF);
417 mm[0] = ((reg << 1) & 0xFF);
418 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
421 mm[len] = data & 0xff;
422 mm[len + 1] = (data >> 8) & 0xff;
423 mm[len + 2] = (data >> 16) & 0xff;
424 mm[len + 3] = (data >> 24) & 0xff;
425 dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
427 return i2c_write(state, adr, mm, len + 4);
430 static int write32(struct drxk_state *state, u32 reg, u32 data)
432 return write32_flags(state, reg, data, 0);
435 static int write_block(struct drxk_state *state, u32 Address,
436 const int BlockSize, const u8 pBlock[])
438 int status = 0, BlkSize = BlockSize;
441 if (state->single_master)
444 while (BlkSize > 0) {
445 int Chunk = BlkSize > state->m_ChunkSize ?
446 state->m_ChunkSize : BlkSize;
447 u8 *AdrBuf = &state->Chunk[0];
450 if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) {
451 AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01);
452 AdrBuf[1] = ((Address >> 16) & 0xFF);
453 AdrBuf[2] = ((Address >> 24) & 0xFF);
454 AdrBuf[3] = ((Address >> 7) & 0xFF);
457 if (Chunk == state->m_ChunkSize)
460 AdrBuf[0] = ((Address << 1) & 0xFF);
461 AdrBuf[1] = (((Address >> 16) & 0x0F) |
462 ((Address >> 18) & 0xF0));
465 memcpy(&state->Chunk[AdrLength], pBlock, Chunk);
466 dprintk(2, "(0x%08x, 0x%02x)\n", Address, Flags);
470 for (i = 0; i < Chunk; i++)
471 printk(KERN_CONT " %02x", pBlock[i]);
472 printk(KERN_CONT "\n");
474 status = i2c_write(state, state->demod_address,
475 &state->Chunk[0], Chunk + AdrLength);
477 printk(KERN_ERR "drxk: %s: i2c write error at addr 0x%02x\n",
482 Address += (Chunk >> 1);
488 #ifndef DRXK_MAX_RETRIES_POWERUP
489 #define DRXK_MAX_RETRIES_POWERUP 20
492 static int PowerUpDevice(struct drxk_state *state)
500 status = i2c_read1(state, state->demod_address, &data);
504 status = i2c_write(state, state->demod_address,
510 status = i2c_read1(state, state->demod_address,
512 } while (status < 0 &&
513 (retryCount < DRXK_MAX_RETRIES_POWERUP));
514 if (status < 0 && retryCount >= DRXK_MAX_RETRIES_POWERUP)
518 /* Make sure all clk domains are active */
519 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
522 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
525 /* Enable pll lock tests */
526 status = write16(state, SIO_CC_PLL_LOCK__A, 1);
530 state->m_currentPowerMode = DRX_POWER_UP;
534 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
540 static int init_state(struct drxk_state *state)
543 * FIXME: most (all?) of the values bellow should be moved into
544 * struct drxk_config, as they are probably board-specific
546 u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO;
547 u32 ulVSBIfAgcOutputLevel = 0;
548 u32 ulVSBIfAgcMinLevel = 0;
549 u32 ulVSBIfAgcMaxLevel = 0x7FFF;
550 u32 ulVSBIfAgcSpeed = 3;
552 u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO;
553 u32 ulVSBRfAgcOutputLevel = 0;
554 u32 ulVSBRfAgcMinLevel = 0;
555 u32 ulVSBRfAgcMaxLevel = 0x7FFF;
556 u32 ulVSBRfAgcSpeed = 3;
557 u32 ulVSBRfAgcTop = 9500;
558 u32 ulVSBRfAgcCutOffCurrent = 4000;
560 u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO;
561 u32 ulATVIfAgcOutputLevel = 0;
562 u32 ulATVIfAgcMinLevel = 0;
563 u32 ulATVIfAgcMaxLevel = 0;
564 u32 ulATVIfAgcSpeed = 3;
566 u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF;
567 u32 ulATVRfAgcOutputLevel = 0;
568 u32 ulATVRfAgcMinLevel = 0;
569 u32 ulATVRfAgcMaxLevel = 0;
570 u32 ulATVRfAgcTop = 9500;
571 u32 ulATVRfAgcCutOffCurrent = 4000;
572 u32 ulATVRfAgcSpeed = 3;
574 u32 ulQual83 = DEFAULT_MER_83;
575 u32 ulQual93 = DEFAULT_MER_93;
577 u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
578 u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
580 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
581 /* io_pad_cfg_mode output mode is drive always */
582 /* io_pad_cfg_drive is set to power 2 (23 mA) */
583 u32 ulGPIOCfg = 0x0113;
584 u32 ulInvertTSClock = 0;
585 u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
586 u32 ulDVBTBitrate = 50000000;
587 u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
589 u32 ulInsertRSByte = 0;
596 state->m_hasLNA = false;
597 state->m_hasDVBT = false;
598 state->m_hasDVBC = false;
599 state->m_hasATV = false;
600 state->m_hasOOB = false;
601 state->m_hasAudio = false;
603 if (!state->m_ChunkSize)
604 state->m_ChunkSize = 124;
606 state->m_oscClockFreq = 0;
607 state->m_smartAntInverted = false;
608 state->m_bPDownOpenBridge = false;
610 /* real system clock frequency in kHz */
611 state->m_sysClockFreq = 151875;
612 /* Timing div, 250ns/Psys */
613 /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
614 state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) *
615 HI_I2C_DELAY) / 1000;
617 if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
618 state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
619 state->m_HICfgWakeUpKey = (state->demod_address << 1);
620 /* port/bridge/power down ctrl */
621 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
623 state->m_bPowerDown = (ulPowerDown != 0);
625 state->m_DRXK_A3_PATCH_CODE = false;
627 /* Init AGC and PGA parameters */
629 state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode);
630 state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel);
631 state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel);
632 state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel);
633 state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed);
634 state->m_vsbPgaCfg = 140;
637 state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode);
638 state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel);
639 state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel);
640 state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel);
641 state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed);
642 state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop);
643 state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent);
644 state->m_vsbPreSawCfg.reference = 0x07;
645 state->m_vsbPreSawCfg.usePreSaw = true;
647 state->m_Quality83percent = DEFAULT_MER_83;
648 state->m_Quality93percent = DEFAULT_MER_93;
649 if (ulQual93 <= 500 && ulQual83 < ulQual93) {
650 state->m_Quality83percent = ulQual83;
651 state->m_Quality93percent = ulQual93;
655 state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode);
656 state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel);
657 state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel);
658 state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel);
659 state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed);
662 state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode);
663 state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel);
664 state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel);
665 state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel);
666 state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed);
667 state->m_atvRfAgcCfg.top = (ulATVRfAgcTop);
668 state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent);
669 state->m_atvPreSawCfg.reference = 0x04;
670 state->m_atvPreSawCfg.usePreSaw = true;
674 state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
675 state->m_dvbtRfAgcCfg.outputLevel = 0;
676 state->m_dvbtRfAgcCfg.minOutputLevel = 0;
677 state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF;
678 state->m_dvbtRfAgcCfg.top = 0x2100;
679 state->m_dvbtRfAgcCfg.cutOffCurrent = 4000;
680 state->m_dvbtRfAgcCfg.speed = 1;
684 state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
685 state->m_dvbtIfAgcCfg.outputLevel = 0;
686 state->m_dvbtIfAgcCfg.minOutputLevel = 0;
687 state->m_dvbtIfAgcCfg.maxOutputLevel = 9000;
688 state->m_dvbtIfAgcCfg.top = 13424;
689 state->m_dvbtIfAgcCfg.cutOffCurrent = 0;
690 state->m_dvbtIfAgcCfg.speed = 3;
691 state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30;
692 state->m_dvbtIfAgcCfg.IngainTgtMax = 30000;
693 /* state->m_dvbtPgaCfg = 140; */
695 state->m_dvbtPreSawCfg.reference = 4;
696 state->m_dvbtPreSawCfg.usePreSaw = false;
699 state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
700 state->m_qamRfAgcCfg.outputLevel = 0;
701 state->m_qamRfAgcCfg.minOutputLevel = 6023;
702 state->m_qamRfAgcCfg.maxOutputLevel = 27000;
703 state->m_qamRfAgcCfg.top = 0x2380;
704 state->m_qamRfAgcCfg.cutOffCurrent = 4000;
705 state->m_qamRfAgcCfg.speed = 3;
708 state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
709 state->m_qamIfAgcCfg.outputLevel = 0;
710 state->m_qamIfAgcCfg.minOutputLevel = 0;
711 state->m_qamIfAgcCfg.maxOutputLevel = 9000;
712 state->m_qamIfAgcCfg.top = 0x0511;
713 state->m_qamIfAgcCfg.cutOffCurrent = 0;
714 state->m_qamIfAgcCfg.speed = 3;
715 state->m_qamIfAgcCfg.IngainTgtMax = 5119;
716 state->m_qamIfAgcCfg.FastClipCtrlDelay = 50;
718 state->m_qamPgaCfg = 140;
719 state->m_qamPreSawCfg.reference = 4;
720 state->m_qamPreSawCfg.usePreSaw = false;
722 state->m_OperationMode = OM_NONE;
723 state->m_DrxkState = DRXK_UNINITIALIZED;
725 /* MPEG output configuration */
726 state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */
727 state->m_insertRSByte = false; /* If TRUE; insert RS byte */
728 state->m_invertDATA = false; /* If TRUE; invert DATA signals */
729 state->m_invertERR = false; /* If TRUE; invert ERR signal */
730 state->m_invertSTR = false; /* If TRUE; invert STR signals */
731 state->m_invertVAL = false; /* If TRUE; invert VAL signals */
732 state->m_invertCLK = (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */
734 /* If TRUE; static MPEG clockrate will be used;
735 otherwise clockrate will adapt to the bitrate of the TS */
737 state->m_DVBTBitrate = ulDVBTBitrate;
738 state->m_DVBCBitrate = ulDVBCBitrate;
740 state->m_TSDataStrength = (ulTSDataStrength & 0x07);
742 /* Maximum bitrate in b/s in case static clockrate is selected */
743 state->m_mpegTsStaticBitrate = 19392658;
744 state->m_disableTEIhandling = false;
747 state->m_insertRSByte = true;
749 state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
750 if (ulMpegLockTimeOut < 10000)
751 state->m_MpegLockTimeOut = ulMpegLockTimeOut;
752 state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
753 if (ulDemodLockTimeOut < 10000)
754 state->m_DemodLockTimeOut = ulDemodLockTimeOut;
757 state->m_Constellation = DRX_CONSTELLATION_AUTO;
758 state->m_qamInterleaveMode = DRXK_QAM_I12_J17;
759 state->m_fecRsPlen = 204 * 8; /* fecRsPlen annex A */
760 state->m_fecRsPrescale = 1;
762 state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM;
763 state->m_agcFastClipCtrlDelay = 0;
765 state->m_GPIOCfg = (ulGPIOCfg);
767 state->m_bPowerDown = false;
768 state->m_currentPowerMode = DRX_POWER_DOWN;
770 state->m_rfmirror = (ulRfMirror == 0);
771 state->m_IfAgcPol = false;
775 static int DRXX_Open(struct drxk_state *state)
783 /* stop lock indicator process */
784 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
787 /* Check device id */
788 status = read16(state, SIO_TOP_COMM_KEY__A, &key);
791 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
794 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
797 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
800 status = write16(state, SIO_TOP_COMM_KEY__A, key);
803 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
807 static int GetDeviceCapabilities(struct drxk_state *state)
809 u16 sioPdrOhwCfg = 0;
810 u32 sioTopJtagidLo = 0;
812 const char *spin = "";
817 /* stop lock indicator process */
818 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
821 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
824 status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg);
827 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
831 switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
833 /* ignore (bypass ?) */
837 state->m_oscClockFreq = 27000;
841 state->m_oscClockFreq = 20250;
845 state->m_oscClockFreq = 20250;
848 printk(KERN_ERR "drxk: Clock Frequency is unknown\n");
852 Determine device capabilities
855 status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo);
859 printk(KERN_INFO "drxk: status = 0x%08x\n", sioTopJtagidLo);
862 switch ((sioTopJtagidLo >> 29) & 0xF) {
864 state->m_deviceSpin = DRXK_SPIN_A1;
868 state->m_deviceSpin = DRXK_SPIN_A2;
872 state->m_deviceSpin = DRXK_SPIN_A3;
876 state->m_deviceSpin = DRXK_SPIN_UNKNOWN;
878 printk(KERN_ERR "drxk: Spin %d unknown\n",
879 (sioTopJtagidLo >> 29) & 0xF);
882 switch ((sioTopJtagidLo >> 12) & 0xFF) {
884 /* typeId = DRX3913K_TYPE_ID */
885 state->m_hasLNA = false;
886 state->m_hasOOB = false;
887 state->m_hasATV = false;
888 state->m_hasAudio = false;
889 state->m_hasDVBT = true;
890 state->m_hasDVBC = true;
891 state->m_hasSAWSW = true;
892 state->m_hasGPIO2 = false;
893 state->m_hasGPIO1 = false;
894 state->m_hasIRQN = false;
897 /* typeId = DRX3915K_TYPE_ID */
898 state->m_hasLNA = false;
899 state->m_hasOOB = false;
900 state->m_hasATV = true;
901 state->m_hasAudio = false;
902 state->m_hasDVBT = true;
903 state->m_hasDVBC = false;
904 state->m_hasSAWSW = true;
905 state->m_hasGPIO2 = true;
906 state->m_hasGPIO1 = true;
907 state->m_hasIRQN = false;
910 /* typeId = DRX3916K_TYPE_ID */
911 state->m_hasLNA = false;
912 state->m_hasOOB = false;
913 state->m_hasATV = true;
914 state->m_hasAudio = false;
915 state->m_hasDVBT = true;
916 state->m_hasDVBC = false;
917 state->m_hasSAWSW = true;
918 state->m_hasGPIO2 = true;
919 state->m_hasGPIO1 = true;
920 state->m_hasIRQN = false;
923 /* typeId = DRX3918K_TYPE_ID */
924 state->m_hasLNA = false;
925 state->m_hasOOB = false;
926 state->m_hasATV = true;
927 state->m_hasAudio = true;
928 state->m_hasDVBT = true;
929 state->m_hasDVBC = false;
930 state->m_hasSAWSW = true;
931 state->m_hasGPIO2 = true;
932 state->m_hasGPIO1 = true;
933 state->m_hasIRQN = false;
936 /* typeId = DRX3921K_TYPE_ID */
937 state->m_hasLNA = false;
938 state->m_hasOOB = false;
939 state->m_hasATV = true;
940 state->m_hasAudio = true;
941 state->m_hasDVBT = true;
942 state->m_hasDVBC = true;
943 state->m_hasSAWSW = true;
944 state->m_hasGPIO2 = true;
945 state->m_hasGPIO1 = true;
946 state->m_hasIRQN = false;
949 /* typeId = DRX3923K_TYPE_ID */
950 state->m_hasLNA = false;
951 state->m_hasOOB = false;
952 state->m_hasATV = true;
953 state->m_hasAudio = true;
954 state->m_hasDVBT = true;
955 state->m_hasDVBC = true;
956 state->m_hasSAWSW = true;
957 state->m_hasGPIO2 = true;
958 state->m_hasGPIO1 = true;
959 state->m_hasIRQN = false;
962 /* typeId = DRX3925K_TYPE_ID */
963 state->m_hasLNA = false;
964 state->m_hasOOB = false;
965 state->m_hasATV = true;
966 state->m_hasAudio = true;
967 state->m_hasDVBT = true;
968 state->m_hasDVBC = true;
969 state->m_hasSAWSW = true;
970 state->m_hasGPIO2 = true;
971 state->m_hasGPIO1 = true;
972 state->m_hasIRQN = false;
975 /* typeId = DRX3926K_TYPE_ID */
976 state->m_hasLNA = false;
977 state->m_hasOOB = false;
978 state->m_hasATV = true;
979 state->m_hasAudio = false;
980 state->m_hasDVBT = true;
981 state->m_hasDVBC = true;
982 state->m_hasSAWSW = true;
983 state->m_hasGPIO2 = true;
984 state->m_hasGPIO1 = true;
985 state->m_hasIRQN = false;
988 printk(KERN_ERR "drxk: DeviceID 0x%02x not supported\n",
989 ((sioTopJtagidLo >> 12) & 0xFF));
995 "drxk: detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
996 ((sioTopJtagidLo >> 12) & 0xFF), spin,
997 state->m_oscClockFreq / 1000,
998 state->m_oscClockFreq % 1000);
1002 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1008 static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)
1016 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
1019 if (cmd == SIO_HI_RA_RAM_CMD_RESET)
1023 (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
1024 ((state->m_HICfgCtrl) &
1025 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1026 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
1027 if (powerdown_cmd == false) {
1028 /* Wait until command rdy */
1035 status = read16(state, SIO_HI_RA_RAM_CMD__A,
1037 } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES)
1041 status = read16(state, SIO_HI_RA_RAM_RES__A, pResult);
1045 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1050 static int HI_CfgCommand(struct drxk_state *state)
1056 mutex_lock(&state->mutex);
1058 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout);
1061 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl);
1064 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey);
1067 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay);
1070 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv);
1073 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1076 status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
1080 state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1082 mutex_unlock(&state->mutex);
1084 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1088 static int InitHI(struct drxk_state *state)
1092 state->m_HICfgWakeUpKey = (state->demod_address << 1);
1093 state->m_HICfgTimeout = 0x96FF;
1094 /* port/bridge/power down ctrl */
1095 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1097 return HI_CfgCommand(state);
1100 static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1103 u16 sioPdrMclkCfg = 0;
1104 u16 sioPdrMdxCfg = 0;
1107 dprintk(1, ": mpeg %s, %s mode\n",
1108 mpegEnable ? "enable" : "disable",
1109 state->m_enableParallel ? "parallel" : "serial");
1111 /* stop lock indicator process */
1112 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1116 /* MPEG TS pad configuration */
1117 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
1121 if (mpegEnable == false) {
1122 /* Set MPEG TS pads to inputmode */
1123 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1126 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1129 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1132 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1135 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1138 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1141 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1144 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1147 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1150 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1153 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1156 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1160 /* Enable MPEG output */
1162 ((state->m_TSDataStrength <<
1163 SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1164 sioPdrMclkCfg = ((state->m_TSClockkStrength <<
1165 SIO_PDR_MCLK_CFG_DRIVE__B) |
1168 status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg);
1172 if (state->enable_merr_cfg)
1173 err_cfg = sioPdrMdxCfg;
1175 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
1178 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);
1182 if (state->m_enableParallel == true) {
1183 /* paralel -> enable MD1 to MD7 */
1184 status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg);
1187 status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg);
1190 status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg);
1193 status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg);
1196 status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg);
1199 status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg);
1202 status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg);
1206 sioPdrMdxCfg = ((state->m_TSDataStrength <<
1207 SIO_PDR_MD0_CFG_DRIVE__B)
1209 /* serial -> disable MD1 to MD7 */
1210 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1213 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1216 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1219 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1222 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1225 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1228 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1232 status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg);
1235 status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg);
1239 /* Enable MB output over MPEG pads and ctl input */
1240 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1243 /* Write nomagic word to enable pdr reg write */
1244 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1247 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1251 static int MPEGTSDisable(struct drxk_state *state)
1255 return MPEGTSConfigurePins(state, false);
1258 static int BLChainCmd(struct drxk_state *state,
1259 u16 romOffset, u16 nrOfElements, u32 timeOut)
1266 mutex_lock(&state->mutex);
1267 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1270 status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset);
1273 status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements);
1276 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1280 end = jiffies + msecs_to_jiffies(timeOut);
1283 status = read16(state, SIO_BL_STATUS__A, &blStatus);
1286 } while ((blStatus == 0x1) &&
1287 ((time_is_after_jiffies(end))));
1289 if (blStatus == 0x1) {
1290 printk(KERN_ERR "drxk: SIO not ready\n");
1296 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1298 mutex_unlock(&state->mutex);
1303 static int DownloadMicrocode(struct drxk_state *state,
1304 const u8 pMCImage[], u32 Length)
1306 const u8 *pSrc = pMCImage;
1316 /* down the drain (we don't care about MAGIC_WORD) */
1318 /* For future reference */
1319 Drain = (pSrc[0] << 8) | pSrc[1];
1321 pSrc += sizeof(u16);
1322 offset += sizeof(u16);
1323 nBlocks = (pSrc[0] << 8) | pSrc[1];
1324 pSrc += sizeof(u16);
1325 offset += sizeof(u16);
1327 for (i = 0; i < nBlocks; i += 1) {
1328 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
1329 (pSrc[2] << 8) | pSrc[3];
1330 pSrc += sizeof(u32);
1331 offset += sizeof(u32);
1333 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
1334 pSrc += sizeof(u16);
1335 offset += sizeof(u16);
1338 /* For future reference */
1339 Flags = (pSrc[0] << 8) | pSrc[1];
1341 pSrc += sizeof(u16);
1342 offset += sizeof(u16);
1345 /* For future reference */
1346 BlockCRC = (pSrc[0] << 8) | pSrc[1];
1348 pSrc += sizeof(u16);
1349 offset += sizeof(u16);
1351 if (offset + BlockSize > Length) {
1352 printk(KERN_ERR "drxk: Firmware is corrupted.\n");
1356 status = write_block(state, Address, BlockSize, pSrc);
1358 printk(KERN_ERR "drxk: Error %d while loading firmware\n", status);
1362 offset += BlockSize;
1367 static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable)
1371 u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
1372 u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1377 if (enable == false) {
1378 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
1379 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1382 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1383 if (status >= 0 && data == desiredStatus) {
1384 /* tokenring already has correct status */
1387 /* Disable/enable dvbt tokenring bridge */
1388 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl);
1390 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1392 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1393 if ((status >= 0 && data == desiredStatus) || time_is_after_jiffies(end))
1397 if (data != desiredStatus) {
1398 printk(KERN_ERR "drxk: SIO not ready\n");
1404 static int MPEGTSStop(struct drxk_state *state)
1407 u16 fecOcSncMode = 0;
1408 u16 fecOcIprMode = 0;
1412 /* Gracefull shutdown (byte boundaries) */
1413 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1416 fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1417 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1421 /* Suppress MCLK during absence of data */
1422 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode);
1425 fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1426 status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode);
1430 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1435 static int scu_command(struct drxk_state *state,
1436 u16 cmd, u8 parameterLen,
1437 u16 *parameter, u8 resultLen, u16 *result)
1439 #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1440 #error DRXK register mapping no longer compatible with this routine!
1443 int status = -EINVAL;
1452 if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) ||
1453 ((resultLen > 0) && (result == NULL))) {
1454 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1458 mutex_lock(&state->mutex);
1460 /* assume that the command register is ready
1461 since it is checked afterwards */
1462 for (ii = parameterLen - 1; ii >= 0; ii -= 1) {
1463 buffer[cnt++] = (parameter[ii] & 0xFF);
1464 buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1466 buffer[cnt++] = (cmd & 0xFF);
1467 buffer[cnt++] = ((cmd >> 8) & 0xFF);
1469 write_block(state, SCU_RAM_PARAM_0__A -
1470 (parameterLen - 1), cnt, buffer);
1471 /* Wait until SCU has processed command */
1472 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1475 status = read16(state, SCU_RAM_COMMAND__A, &curCmd);
1478 } while (!(curCmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1479 if (curCmd != DRX_SCU_READY) {
1480 printk(KERN_ERR "drxk: SCU not ready\n");
1485 if ((resultLen > 0) && (result != NULL)) {
1489 for (ii = resultLen - 1; ii >= 0; ii -= 1) {
1490 status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]);
1495 /* Check if an error was reported by SCU */
1496 err = (s16)result[0];
1500 /* check for the known error codes */
1502 case SCU_RESULT_UNKCMD:
1503 p = "SCU_RESULT_UNKCMD";
1505 case SCU_RESULT_UNKSTD:
1506 p = "SCU_RESULT_UNKSTD";
1508 case SCU_RESULT_SIZE:
1509 p = "SCU_RESULT_SIZE";
1511 case SCU_RESULT_INVPAR:
1512 p = "SCU_RESULT_INVPAR";
1514 default: /* Other negative values are errors */
1515 sprintf(errname, "ERROR: %d\n", err);
1518 printk(KERN_ERR "drxk: %s while sending cmd 0x%04x with params:", p, cmd);
1519 print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
1526 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1528 mutex_unlock(&state->mutex);
1532 static int SetIqmAf(struct drxk_state *state, bool active)
1540 status = read16(state, IQM_AF_STDBY__A, &data);
1545 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1546 | IQM_AF_STDBY_STDBY_AMP_STANDBY
1547 | IQM_AF_STDBY_STDBY_PD_STANDBY
1548 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1549 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1551 data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1552 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1553 & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1554 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1555 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1558 status = write16(state, IQM_AF_STDBY__A, data);
1562 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1566 static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
1569 u16 sioCcPwdMode = 0;
1573 /* Check arguments */
1579 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE;
1581 case DRXK_POWER_DOWN_OFDM:
1582 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1584 case DRXK_POWER_DOWN_CORE:
1585 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1587 case DRXK_POWER_DOWN_PLL:
1588 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL;
1590 case DRX_POWER_DOWN:
1591 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC;
1594 /* Unknow sleep mode */
1598 /* If already in requested power mode, do nothing */
1599 if (state->m_currentPowerMode == *mode)
1602 /* For next steps make sure to start from DRX_POWER_UP mode */
1603 if (state->m_currentPowerMode != DRX_POWER_UP) {
1604 status = PowerUpDevice(state);
1607 status = DVBTEnableOFDMTokenRing(state, true);
1612 if (*mode == DRX_POWER_UP) {
1613 /* Restore analog & pin configuartion */
1615 /* Power down to requested mode */
1616 /* Backup some register settings */
1617 /* Set pins with possible pull-ups connected
1618 to them in input mode */
1619 /* Analog power down */
1620 /* ADC power down */
1621 /* Power down device */
1622 /* stop all comm_exec */
1623 /* Stop and power down previous standard */
1624 switch (state->m_OperationMode) {
1626 status = MPEGTSStop(state);
1629 status = PowerDownDVBT(state, false);
1635 status = MPEGTSStop(state);
1638 status = PowerDownQAM(state);
1645 status = DVBTEnableOFDMTokenRing(state, false);
1648 status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode);
1651 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1655 if (*mode != DRXK_POWER_DOWN_OFDM) {
1656 state->m_HICfgCtrl |=
1657 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1658 status = HI_CfgCommand(state);
1663 state->m_currentPowerMode = *mode;
1667 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1672 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
1674 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
1681 status = read16(state, SCU_COMM_EXEC__A, &data);
1684 if (data == SCU_COMM_EXEC_ACTIVE) {
1685 /* Send OFDM stop command */
1686 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
1689 /* Send OFDM reset command */
1690 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
1695 /* Reset datapath for OFDM, processors first */
1696 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1699 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1702 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1707 status = SetIqmAf(state, false);
1711 /* powerdown to OFDM mode */
1713 status = CtrlPowerMode(state, &powerMode);
1719 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1723 static int SetOperationMode(struct drxk_state *state,
1724 enum OperationMode oMode)
1730 Stop and power down previous standard
1731 TODO investigate total power down instead of partial
1732 power down depending on "previous" standard.
1735 /* disable HW lock indicator */
1736 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1740 /* Device is already at the required mode */
1741 if (state->m_OperationMode == oMode)
1744 switch (state->m_OperationMode) {
1745 /* OM_NONE was added for start up */
1749 status = MPEGTSStop(state);
1752 status = PowerDownDVBT(state, true);
1755 state->m_OperationMode = OM_NONE;
1757 case OM_QAM_ITU_A: /* fallthrough */
1759 status = MPEGTSStop(state);
1762 status = PowerDownQAM(state);
1765 state->m_OperationMode = OM_NONE;
1774 Power up new standard
1778 dprintk(1, ": DVB-T\n");
1779 state->m_OperationMode = oMode;
1780 status = SetDVBTStandard(state, oMode);
1784 case OM_QAM_ITU_A: /* fallthrough */
1786 dprintk(1, ": DVB-C Annex %c\n",
1787 (state->m_OperationMode == OM_QAM_ITU_A) ? 'A' : 'C');
1788 state->m_OperationMode = oMode;
1789 status = SetQAMStandard(state, oMode);
1799 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1803 static int Start(struct drxk_state *state, s32 offsetFreq,
1804 s32 IntermediateFrequency)
1806 int status = -EINVAL;
1809 s32 OffsetkHz = offsetFreq / 1000;
1812 if (state->m_DrxkState != DRXK_STOPPED &&
1813 state->m_DrxkState != DRXK_DTV_STARTED)
1816 state->m_bMirrorFreqSpect = (state->props.inversion == INVERSION_ON);
1818 if (IntermediateFrequency < 0) {
1819 state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect;
1820 IntermediateFrequency = -IntermediateFrequency;
1823 switch (state->m_OperationMode) {
1826 IFreqkHz = (IntermediateFrequency / 1000);
1827 status = SetQAM(state, IFreqkHz, OffsetkHz);
1830 state->m_DrxkState = DRXK_DTV_STARTED;
1833 IFreqkHz = (IntermediateFrequency / 1000);
1834 status = MPEGTSStop(state);
1837 status = SetDVBT(state, IFreqkHz, OffsetkHz);
1840 status = DVBTStart(state);
1843 state->m_DrxkState = DRXK_DTV_STARTED;
1850 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1854 static int ShutDown(struct drxk_state *state)
1862 static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus)
1864 int status = -EINVAL;
1868 if (pLockStatus == NULL)
1871 *pLockStatus = NOT_LOCKED;
1873 /* define the SCU command code */
1874 switch (state->m_OperationMode) {
1878 status = GetQAMLockStatus(state, pLockStatus);
1881 status = GetDVBTLockStatus(state, pLockStatus);
1888 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1892 static int MPEGTSStart(struct drxk_state *state)
1896 u16 fecOcSncMode = 0;
1898 /* Allow OC to sync again */
1899 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1902 fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1903 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1906 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1909 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1913 static int MPEGTSDtoInit(struct drxk_state *state)
1919 /* Rate integration settings */
1920 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1923 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1926 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
1929 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
1932 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
1935 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
1938 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
1941 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
1945 /* Additional configuration */
1946 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
1949 status = write16(state, FEC_OC_SNC_LWM__A, 2);
1952 status = write16(state, FEC_OC_SNC_HWM__A, 12);
1955 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1960 static int MPEGTSDtoSetup(struct drxk_state *state,
1961 enum OperationMode oMode)
1965 u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */
1966 u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */
1967 u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */
1968 u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */
1969 u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */
1970 u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */
1971 u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */
1972 u16 fecOcTmdMode = 0;
1973 u16 fecOcTmdIntUpdRate = 0;
1975 bool staticCLK = false;
1979 /* Check insertion of the Reed-Solomon parity bytes */
1980 status = read16(state, FEC_OC_MODE__A, &fecOcRegMode);
1983 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode);
1986 fecOcRegMode &= (~FEC_OC_MODE_PARITY__M);
1987 fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
1988 if (state->m_insertRSByte == true) {
1989 /* enable parity symbol forward */
1990 fecOcRegMode |= FEC_OC_MODE_PARITY__M;
1991 /* MVAL disable during parity bytes */
1992 fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
1993 /* TS burst length to 204 */
1994 fecOcDtoBurstLen = 204;
1997 /* Check serial or parrallel output */
1998 fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
1999 if (state->m_enableParallel == false) {
2000 /* MPEG data output is serial -> set ipr_mode[0] */
2001 fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M;
2006 maxBitRate = state->m_DVBTBitrate;
2008 fecOcRcnCtlRate = 0xC00000;
2009 staticCLK = state->m_DVBTStaticCLK;
2011 case OM_QAM_ITU_A: /* fallthrough */
2013 fecOcTmdMode = 0x0004;
2014 fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */
2015 maxBitRate = state->m_DVBCBitrate;
2016 staticCLK = state->m_DVBCStaticCLK;
2020 } /* switch (standard) */
2024 /* Configure DTO's */
2028 /* Rational DTO for MCLK source (static MCLK rate),
2029 Dynamic DTO for optimal grouping
2030 (avoid intra-packet gaps),
2031 DTO offset enable to sync TS burst with MSTRT */
2032 fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2033 FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2034 fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2035 FEC_OC_FCT_MODE_VIRT_ENA__M);
2037 /* Check user defined bitrate */
2038 bitRate = maxBitRate;
2039 if (bitRate > 75900000UL) { /* max is 75.9 Mb/s */
2040 bitRate = 75900000UL;
2042 /* Rational DTO period:
2043 dto_period = (Fsys / bitrate) - 2
2045 Result should be floored,
2046 to make sure >= requested bitrate
2048 fecOcDtoPeriod = (u16) (((state->m_sysClockFreq)
2050 if (fecOcDtoPeriod <= 2)
2053 fecOcDtoPeriod -= 2;
2054 fecOcTmdIntUpdRate = 8;
2056 /* (commonAttr->staticCLK == false) => dynamic mode */
2057 fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M;
2058 fecOcFctMode = FEC_OC_FCT_MODE__PRE;
2059 fecOcTmdIntUpdRate = 5;
2062 /* Write appropriate registers with requested configuration */
2063 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen);
2066 status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod);
2069 status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode);
2072 status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode);
2075 status = write16(state, FEC_OC_MODE__A, fecOcRegMode);
2078 status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode);
2082 /* Rate integration settings */
2083 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate);
2086 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate);
2089 status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode);
2092 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2096 static int MPEGTSConfigurePolarity(struct drxk_state *state)
2098 u16 fecOcRegIprInvert = 0;
2100 /* Data mask for the output data byte */
2101 u16 InvertDataMask =
2102 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2103 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2104 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2105 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2109 /* Control selective inversion of output bits */
2110 fecOcRegIprInvert &= (~(InvertDataMask));
2111 if (state->m_invertDATA == true)
2112 fecOcRegIprInvert |= InvertDataMask;
2113 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2114 if (state->m_invertERR == true)
2115 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M;
2116 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2117 if (state->m_invertSTR == true)
2118 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M;
2119 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2120 if (state->m_invertVAL == true)
2121 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M;
2122 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2123 if (state->m_invertCLK == true)
2124 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M;
2126 return write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert);
2129 #define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2131 static int SetAgcRf(struct drxk_state *state,
2132 struct SCfgAgc *pAgcCfg, bool isDTV)
2134 int status = -EINVAL;
2136 struct SCfgAgc *pIfAgcSettings;
2140 if (pAgcCfg == NULL)
2143 switch (pAgcCfg->ctrlMode) {
2144 case DRXK_AGC_CTRL_AUTO:
2145 /* Enable RF AGC DAC */
2146 status = read16(state, IQM_AF_STDBY__A, &data);
2149 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2150 status = write16(state, IQM_AF_STDBY__A, data);
2153 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2157 /* Enable SCU RF AGC loop */
2158 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2161 if (state->m_RfAgcPol)
2162 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2164 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2165 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2169 /* Set speed (using complementary reduction value) */
2170 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2174 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2175 data |= (~(pAgcCfg->speed <<
2176 SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2177 & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2179 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2184 pIfAgcSettings = &state->m_dvbtIfAgcCfg;
2185 else if (IsQAM(state))
2186 pIfAgcSettings = &state->m_qamIfAgcCfg;
2188 pIfAgcSettings = &state->m_atvIfAgcCfg;
2189 if (pIfAgcSettings == NULL) {
2194 /* Set TOP, only if IF-AGC is in AUTO mode */
2195 if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO)
2196 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top);
2200 /* Cut-Off current */
2201 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent);
2205 /* Max. output level */
2206 status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel);
2212 case DRXK_AGC_CTRL_USER:
2213 /* Enable RF AGC DAC */
2214 status = read16(state, IQM_AF_STDBY__A, &data);
2217 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2218 status = write16(state, IQM_AF_STDBY__A, data);
2222 /* Disable SCU RF AGC loop */
2223 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2226 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2227 if (state->m_RfAgcPol)
2228 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2230 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2231 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2235 /* SCU c.o.c. to 0, enabling full control range */
2236 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2240 /* Write value to output pin */
2241 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel);
2246 case DRXK_AGC_CTRL_OFF:
2247 /* Disable RF AGC DAC */
2248 status = read16(state, IQM_AF_STDBY__A, &data);
2251 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2252 status = write16(state, IQM_AF_STDBY__A, data);
2256 /* Disable SCU RF AGC loop */
2257 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2260 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2261 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2272 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2276 #define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2278 static int SetAgcIf(struct drxk_state *state,
2279 struct SCfgAgc *pAgcCfg, bool isDTV)
2283 struct SCfgAgc *pRfAgcSettings;
2287 switch (pAgcCfg->ctrlMode) {
2288 case DRXK_AGC_CTRL_AUTO:
2290 /* Enable IF AGC DAC */
2291 status = read16(state, IQM_AF_STDBY__A, &data);
2294 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2295 status = write16(state, IQM_AF_STDBY__A, data);
2299 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2303 /* Enable SCU IF AGC loop */
2304 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2307 if (state->m_IfAgcPol)
2308 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2310 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2311 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2315 /* Set speed (using complementary reduction value) */
2316 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2319 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2320 data |= (~(pAgcCfg->speed <<
2321 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2322 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2324 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2329 pRfAgcSettings = &state->m_qamRfAgcCfg;
2331 pRfAgcSettings = &state->m_atvRfAgcCfg;
2332 if (pRfAgcSettings == NULL)
2335 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top);
2340 case DRXK_AGC_CTRL_USER:
2342 /* Enable IF AGC DAC */
2343 status = read16(state, IQM_AF_STDBY__A, &data);
2346 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2347 status = write16(state, IQM_AF_STDBY__A, data);
2351 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2355 /* Disable SCU IF AGC loop */
2356 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2359 if (state->m_IfAgcPol)
2360 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2362 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2363 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2367 /* Write value to output pin */
2368 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel);
2373 case DRXK_AGC_CTRL_OFF:
2375 /* Disable If AGC DAC */
2376 status = read16(state, IQM_AF_STDBY__A, &data);
2379 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2380 status = write16(state, IQM_AF_STDBY__A, data);
2384 /* Disable SCU IF AGC loop */
2385 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2388 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2389 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2393 } /* switch (agcSettingsIf->ctrlMode) */
2395 /* always set the top to support
2396 configurations without if-loop */
2397 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top);
2400 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2404 static int GetQAMSignalToNoise(struct drxk_state *state,
2405 s32 *pSignalToNoise)
2408 u16 qamSlErrPower = 0; /* accum. error between
2409 raw and sliced symbols */
2410 u32 qamSlSigPower = 0; /* used for MER, depends of
2412 u32 qamSlMer = 0; /* QAM MER */
2416 /* MER calculation */
2418 /* get the register value needed for MER */
2419 status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower);
2421 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2425 switch (state->props.modulation) {
2427 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2430 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2433 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2436 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2440 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2444 if (qamSlErrPower > 0) {
2445 qamSlMer = log10times100(qamSlSigPower) -
2446 log10times100((u32) qamSlErrPower);
2448 *pSignalToNoise = qamSlMer;
2453 static int GetDVBTSignalToNoise(struct drxk_state *state,
2454 s32 *pSignalToNoise)
2458 u32 EqRegTdSqrErrI = 0;
2459 u32 EqRegTdSqrErrQ = 0;
2460 u16 EqRegTdSqrErrExp = 0;
2461 u16 EqRegTdTpsPwrOfs = 0;
2462 u16 EqRegTdReqSmbCnt = 0;
2469 u16 transmissionParams = 0;
2473 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs);
2476 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt);
2479 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp);
2482 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, ®Data);
2485 /* Extend SQR_ERR_I operational range */
2486 EqRegTdSqrErrI = (u32) regData;
2487 if ((EqRegTdSqrErrExp > 11) &&
2488 (EqRegTdSqrErrI < 0x00000FFFUL)) {
2489 EqRegTdSqrErrI += 0x00010000UL;
2491 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®Data);
2494 /* Extend SQR_ERR_Q operational range */
2495 EqRegTdSqrErrQ = (u32) regData;
2496 if ((EqRegTdSqrErrExp > 11) &&
2497 (EqRegTdSqrErrQ < 0x00000FFFUL))
2498 EqRegTdSqrErrQ += 0x00010000UL;
2500 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams);
2504 /* Check input data for MER */
2506 /* MER calculation (in 0.1 dB) without math.h */
2507 if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0))
2509 else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) {
2510 /* No error at all, this must be the HW reset value
2511 * Apparently no first measurement yet
2515 SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) <<
2517 if ((transmissionParams &
2518 OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2519 == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2524 /* IMER = 100 * log10 (x)
2525 where x = (EqRegTdTpsPwrOfs^2 *
2526 EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ
2529 where a = 100 * log10 (EqRegTdTpsPwrOfs^2)
2530 b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt)
2531 c = 100 * log10 (SqrErrIQ)
2534 /* log(x) x = 9bits * 9bits->18 bits */
2535 a = log10times100(EqRegTdTpsPwrOfs *
2537 /* log(x) x = 16bits * 7bits->23 bits */
2538 b = log10times100(EqRegTdReqSmbCnt * tpsCnt);
2539 /* log(x) x = (16bits + 16bits) << 15 ->32 bits */
2540 c = log10times100(SqrErrIQ);
2544 *pSignalToNoise = iMER;
2548 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2552 static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
2556 *pSignalToNoise = 0;
2557 switch (state->m_OperationMode) {
2559 return GetDVBTSignalToNoise(state, pSignalToNoise);
2562 return GetQAMSignalToNoise(state, pSignalToNoise);
2570 static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)
2572 /* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2577 static s32 QE_SN[] = {
2583 108, /* 16-QAM 1/2 */
2584 131, /* 16-QAM 2/3 */
2585 146, /* 16-QAM 3/4 */
2586 156, /* 16-QAM 5/6 */
2587 160, /* 16-QAM 7/8 */
2588 165, /* 64-QAM 1/2 */
2589 187, /* 64-QAM 2/3 */
2590 202, /* 64-QAM 3/4 */
2591 216, /* 64-QAM 5/6 */
2592 225, /* 64-QAM 7/8 */
2598 s32 SignalToNoise = 0;
2599 u16 Constellation = 0;
2601 u32 SignalToNoiseRel;
2604 status = GetDVBTSignalToNoise(state, &SignalToNoise);
2607 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation);
2610 Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2612 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate);
2615 CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2617 if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2618 CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2620 SignalToNoiseRel = SignalToNoise -
2621 QE_SN[Constellation * 5 + CodeRate];
2624 if (SignalToNoiseRel < -70)
2626 else if (SignalToNoiseRel < 30)
2627 *pQuality = ((SignalToNoiseRel + 70) *
2630 *pQuality = BERQuality;
2635 static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)
2643 u32 SignalToNoise = 0;
2644 u32 BERQuality = 100;
2645 u32 SignalToNoiseRel = 0;
2647 status = GetQAMSignalToNoise(state, &SignalToNoise);
2651 switch (state->props.modulation) {
2653 SignalToNoiseRel = SignalToNoise - 200;
2656 SignalToNoiseRel = SignalToNoise - 230;
2657 break; /* Not in NorDig */
2659 SignalToNoiseRel = SignalToNoise - 260;
2662 SignalToNoiseRel = SignalToNoise - 290;
2666 SignalToNoiseRel = SignalToNoise - 320;
2670 if (SignalToNoiseRel < -70)
2672 else if (SignalToNoiseRel < 30)
2673 *pQuality = ((SignalToNoiseRel + 70) *
2676 *pQuality = BERQuality;
2682 static int GetQuality(struct drxk_state *state, s32 *pQuality)
2686 switch (state->m_OperationMode) {
2688 return GetDVBTQuality(state, pQuality);
2690 return GetDVBCQuality(state, pQuality);
2699 /* Free data ram in SIO HI */
2700 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2701 #define SIO_HI_RA_RAM_USR_END__A 0x420060
2703 #define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2704 #define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2705 #define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2706 #define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2708 #define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F)
2709 #define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F)
2710 #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2712 static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge)
2714 int status = -EINVAL;
2718 if (state->m_DrxkState == DRXK_UNINITIALIZED)
2720 if (state->m_DrxkState == DRXK_POWERED_DOWN)
2723 if (state->no_i2c_bridge)
2726 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2729 if (bEnableBridge) {
2730 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2734 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2739 status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0);
2743 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2747 static int SetPreSaw(struct drxk_state *state,
2748 struct SCfgPreSaw *pPreSawCfg)
2750 int status = -EINVAL;
2754 if ((pPreSawCfg == NULL)
2755 || (pPreSawCfg->reference > IQM_AF_PDREF__M))
2758 status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference);
2761 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2765 static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,
2766 u16 romOffset, u16 nrOfElements, u32 timeOut)
2769 u16 offset = (u16) ((targetAddr >> 0) & 0x00FFFF);
2770 u16 blockbank = (u16) ((targetAddr >> 16) & 0x000FFF);
2776 mutex_lock(&state->mutex);
2777 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2780 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2783 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2786 status = write16(state, SIO_BL_SRC_ADDR__A, romOffset);
2789 status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements);
2792 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2796 end = jiffies + msecs_to_jiffies(timeOut);
2798 status = read16(state, SIO_BL_STATUS__A, &blStatus);
2801 } while ((blStatus == 0x1) && time_is_after_jiffies(end));
2802 if (blStatus == 0x1) {
2803 printk(KERN_ERR "drxk: SIO not ready\n");
2809 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2811 mutex_unlock(&state->mutex);
2816 static int ADCSyncMeasurement(struct drxk_state *state, u16 *count)
2823 /* Start measurement */
2824 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2827 status = write16(state, IQM_AF_START_LOCK__A, 1);
2832 status = read16(state, IQM_AF_PHASE0__A, &data);
2836 *count = *count + 1;
2837 status = read16(state, IQM_AF_PHASE1__A, &data);
2841 *count = *count + 1;
2842 status = read16(state, IQM_AF_PHASE2__A, &data);
2846 *count = *count + 1;
2850 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2854 static int ADCSynchronization(struct drxk_state *state)
2861 status = ADCSyncMeasurement(state, &count);
2866 /* Try sampling on a diffrent edge */
2869 status = read16(state, IQM_AF_CLKNEG__A, &clkNeg);
2872 if ((clkNeg & IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2873 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2874 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2876 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2878 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2880 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
2882 status = write16(state, IQM_AF_CLKNEG__A, clkNeg);
2885 status = ADCSyncMeasurement(state, &count);
2894 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2898 static int SetFrequencyShifter(struct drxk_state *state,
2899 u16 intermediateFreqkHz,
2900 s32 tunerFreqOffset, bool isDTV)
2902 bool selectPosImage = false;
2903 u32 rfFreqResidual = tunerFreqOffset;
2904 u32 fmFrequencyShift = 0;
2905 bool tunerMirror = !state->m_bMirrorFreqSpect;
2910 u32 samplingFrequency = (u32) (state->m_sysClockFreq / 3);
2917 Program frequency shifter
2918 No need to account for mirroring on RF
2921 if ((state->m_OperationMode == OM_QAM_ITU_A) ||
2922 (state->m_OperationMode == OM_QAM_ITU_C) ||
2923 (state->m_OperationMode == OM_DVBT))
2924 selectPosImage = true;
2926 selectPosImage = false;
2929 /* tuner doesn't mirror */
2930 ifFreqActual = intermediateFreqkHz +
2931 rfFreqResidual + fmFrequencyShift;
2934 ifFreqActual = intermediateFreqkHz -
2935 rfFreqResidual - fmFrequencyShift;
2936 if (ifFreqActual > samplingFrequency / 2) {
2938 adcFreq = samplingFrequency - ifFreqActual;
2941 /* adc doesn't mirror */
2942 adcFreq = ifFreqActual;
2946 frequencyShift = adcFreq;
2947 imageToSelect = state->m_rfmirror ^ tunerMirror ^
2948 adcFlip ^ selectPosImage;
2949 state->m_IqmFsRateOfs =
2950 Frac28a((frequencyShift), samplingFrequency);
2953 state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1;
2955 /* Program frequency shifter with tuner offset compensation */
2956 /* frequencyShift += tunerFreqOffset; TODO */
2957 status = write32(state, IQM_FS_RATE_OFS_LO__A,
2958 state->m_IqmFsRateOfs);
2960 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2964 static int InitAGC(struct drxk_state *state, bool isDTV)
2967 u16 ingainTgtMin = 0;
2968 u16 ingainTgtMax = 0;
2976 u16 kiInnergainMin = 0;
2977 u16 ifIaccuHiTgt = 0;
2978 u16 ifIaccuHiTgtMin = 0;
2979 u16 ifIaccuHiTgtMax = 0;
2981 u16 fastClpCtrlDelay = 0;
2982 u16 clpCtrlMode = 0;
2987 /* Common settings */
2989 ifIaccuHiTgtMin = 2047;
2993 /* AGCInit() not available for DVBT; init done in microcode */
2994 if (!IsQAM(state)) {
2995 printk(KERN_ERR "drxk: %s: mode %d is not DVB-C\n", __func__, state->m_OperationMode);
2999 /* FIXME: Analog TV AGC require different settings */
3001 /* Standard specific settings */
3003 clpDirTo = (u16) -9;
3006 snsDirTo = (u16) -9;
3007 kiInnergainMin = (u16) -1030;
3008 ifIaccuHiTgtMax = 0x2380;
3009 ifIaccuHiTgt = 0x2380;
3010 ingainTgtMin = 0x0511;
3012 ingainTgtMax = 5119;
3013 fastClpCtrlDelay = state->m_qamIfAgcCfg.FastClipCtrlDelay;
3015 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay);
3019 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode);
3022 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt);
3025 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin);
3028 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax);
3031 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin);
3034 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax);
3037 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3040 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3043 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3046 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3049 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax);
3052 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax);
3056 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin);
3059 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt);
3062 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen);
3066 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3069 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3072 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3076 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3079 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin);
3082 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin);
3085 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo);
3088 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo);
3091 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3094 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3097 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3100 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3103 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3106 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3109 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3112 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3115 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3118 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3121 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3124 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3127 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3130 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3134 /* Initialize inner-loop KI gain factors */
3135 status = read16(state, SCU_RAM_AGC_KI__A, &data);
3140 data &= ~SCU_RAM_AGC_KI_RF__M;
3141 data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3142 data &= ~SCU_RAM_AGC_KI_IF__M;
3143 data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3145 status = write16(state, SCU_RAM_AGC_KI__A, data);
3148 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3152 static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr)
3157 if (packetErr == NULL)
3158 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3160 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr);
3162 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3166 static int DVBTScCommand(struct drxk_state *state,
3167 u16 cmd, u16 subcmd,
3168 u16 param0, u16 param1, u16 param2,
3169 u16 param3, u16 param4)
3178 status = read16(state, OFDM_SC_COMM_EXEC__A, &scExec);
3180 /* SC is not running */
3186 /* Wait until sc is ready to receive command */
3190 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3192 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3193 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3196 /* Write sub-command */
3198 /* All commands using sub-cmd */
3199 case OFDM_SC_RA_RAM_CMD_PROC_START:
3200 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3201 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3202 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3211 /* Write needed parameters and the command */
3213 /* All commands using 5 parameters */
3214 /* All commands using 4 parameters */
3215 /* All commands using 3 parameters */
3216 /* All commands using 2 parameters */
3217 case OFDM_SC_RA_RAM_CMD_PROC_START:
3218 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3219 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3220 status = write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3221 /* All commands using 1 parameters */
3222 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3223 case OFDM_SC_RA_RAM_CMD_USER_IO:
3224 status = write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3225 /* All commands using 0 parameters */
3226 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3227 case OFDM_SC_RA_RAM_CMD_NULL:
3229 status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3232 /* Unknown command */
3238 /* Wait until sc is ready processing command */
3242 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3244 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3245 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3248 /* Check for illegal cmd */
3249 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode);
3250 if (errCode == 0xFFFF) {
3251 /* illegal command */
3257 /* Retreive results parameters from SC */
3259 /* All commands yielding 5 results */
3260 /* All commands yielding 4 results */
3261 /* All commands yielding 3 results */
3262 /* All commands yielding 2 results */
3263 /* All commands yielding 1 result */
3264 case OFDM_SC_RA_RAM_CMD_USER_IO:
3265 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3266 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3267 /* All commands yielding 0 results */
3268 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3269 case OFDM_SC_RA_RAM_CMD_SET_TIMER:
3270 case OFDM_SC_RA_RAM_CMD_PROC_START:
3271 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3272 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3273 case OFDM_SC_RA_RAM_CMD_NULL:
3276 /* Unknown command */
3279 } /* switch (cmd->cmd) */
3282 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3286 static int PowerUpDVBT(struct drxk_state *state)
3288 enum DRXPowerMode powerMode = DRX_POWER_UP;
3292 status = CtrlPowerMode(state, &powerMode);
3294 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3298 static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled)
3303 if (*enabled == true)
3304 status = write16(state, IQM_CF_BYPASSDET__A, 0);
3306 status = write16(state, IQM_CF_BYPASSDET__A, 1);
3308 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3312 #define DEFAULT_FR_THRES_8K 4000
3313 static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled)
3319 if (*enabled == true) {
3320 /* write mask to 1 */
3321 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3322 DEFAULT_FR_THRES_8K);
3324 /* write mask to 0 */
3325 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3328 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3333 static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,
3334 struct DRXKCfgDvbtEchoThres_t *echoThres)
3340 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3344 switch (echoThres->fftMode) {
3345 case DRX_FFTMODE_2K:
3346 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3347 data |= ((echoThres->threshold <<
3348 OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3349 & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
3351 case DRX_FFTMODE_8K:
3352 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3353 data |= ((echoThres->threshold <<
3354 OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3355 & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
3361 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3364 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3368 static int DVBTCtrlSetSqiSpeed(struct drxk_state *state,
3369 enum DRXKCfgDvbtSqiSpeed *speed)
3371 int status = -EINVAL;
3376 case DRXK_DVBT_SQI_SPEED_FAST:
3377 case DRXK_DVBT_SQI_SPEED_MEDIUM:
3378 case DRXK_DVBT_SQI_SPEED_SLOW:
3383 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3387 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3391 /*============================================================================*/
3394 * \brief Activate DVBT specific presets
3395 * \param demod instance of demodulator.
3396 * \return DRXStatus_t.
3398 * Called in DVBTSetStandard
3401 static int DVBTActivatePresets(struct drxk_state *state)
3404 bool setincenable = false;
3405 bool setfrenable = true;
3407 struct DRXKCfgDvbtEchoThres_t echoThres2k = { 0, DRX_FFTMODE_2K };
3408 struct DRXKCfgDvbtEchoThres_t echoThres8k = { 0, DRX_FFTMODE_8K };
3411 status = DVBTCtrlSetIncEnable(state, &setincenable);
3414 status = DVBTCtrlSetFrEnable(state, &setfrenable);
3417 status = DVBTCtrlSetEchoThreshold(state, &echoThres2k);
3420 status = DVBTCtrlSetEchoThreshold(state, &echoThres8k);
3423 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax);
3426 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3430 /*============================================================================*/
3433 * \brief Initialize channelswitch-independent settings for DVBT.
3434 * \param demod instance of demodulator.
3435 * \return DRXStatus_t.
3437 * For ROM code channel filter taps are loaded from the bootloader. For microcode
3438 * the DVB-T taps from the drxk_filters.h are used.
3440 static int SetDVBTStandard(struct drxk_state *state,
3441 enum OperationMode oMode)
3450 /* added antenna switch */
3451 SwitchAntennaToDVBT(state);
3452 /* send OFDM reset command */
3453 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
3457 /* send OFDM setenv command */
3458 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmdResult);
3462 /* reset datapath for OFDM, processors first */
3463 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3466 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3469 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3474 /* synchronize on ofdstate->m_festart */
3475 status = write16(state, IQM_AF_UPD_SEL__A, 1);
3478 /* window size for clipping ADC detection */
3479 status = write16(state, IQM_AF_CLP_LEN__A, 0);
3482 /* window size for for sense pre-SAW detection */
3483 status = write16(state, IQM_AF_SNS_LEN__A, 0);
3486 /* sense threshold for sense pre-SAW detection */
3487 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3490 status = SetIqmAf(state, true);
3494 status = write16(state, IQM_AF_AGC_RF__A, 0);
3498 /* Impulse noise cruncher setup */
3499 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */
3502 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */
3505 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */
3509 status = write16(state, IQM_RC_STRETCH__A, 16);
3512 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3515 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3518 status = write16(state, IQM_CF_SCALE__A, 1600);
3521 status = write16(state, IQM_CF_SCALE_SH__A, 0);
3525 /* virtual clipping threshold for clipping ADC detection */
3526 status = write16(state, IQM_AF_CLP_TH__A, 448);
3529 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3533 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3537 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */
3540 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3543 /* enable power measurement interrupt */
3544 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3547 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3551 /* IQM will not be reset from here, sync ADC and update/init AGC */
3552 status = ADCSynchronization(state);
3555 status = SetPreSaw(state, &state->m_dvbtPreSawCfg);
3559 /* Halt SCU to enable safe non-atomic accesses */
3560 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3564 status = SetAgcRf(state, &state->m_dvbtRfAgcCfg, true);
3567 status = SetAgcIf(state, &state->m_dvbtIfAgcCfg, true);
3571 /* Set Noise Estimation notch width and enable DC fix */
3572 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3575 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3576 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3580 /* Activate SCU to enable SCU commands */
3581 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3585 if (!state->m_DRXK_A3_ROM_CODE) {
3586 /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */
3587 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDelay);
3593 #ifdef COMPILE_FOR_NONRT
3594 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3597 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3603 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */
3608 #ifdef COMPILE_FOR_NONRT
3609 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3613 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3617 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3621 /* Setup MPEG bus */
3622 status = MPEGTSDtoSetup(state, OM_DVBT);
3625 /* Set DVBT Presets */
3626 status = DVBTActivatePresets(state);
3632 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3636 /*============================================================================*/
3638 * \brief Start dvbt demodulating for channel.
3639 * \param demod instance of demodulator.
3640 * \return DRXStatus_t.
3642 static int DVBTStart(struct drxk_state *state)
3646 /* DRXKOfdmScCmd_t scCmd; */
3649 /* Start correct processes to get in lock */
3650 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
3651 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3652 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0);
3656 status = MPEGTSStart(state);
3659 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3664 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3669 /*============================================================================*/
3672 * \brief Set up dvbt demodulator for channel.
3673 * \param demod instance of demodulator.
3674 * \return DRXStatus_t.
3675 * // original DVBTSetChannel()
3677 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3678 s32 tunerFreqOffset)
3681 u16 transmissionParams = 0;
3682 u16 operationMode = 0;
3683 u32 iqmRcRateOfs = 0;
3688 dprintk(1, "IF =%d, TFO = %d\n", IntermediateFreqkHz, tunerFreqOffset);
3690 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
3694 /* Halt SCU to enable safe non-atomic accesses */
3695 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3699 /* Stop processors */
3700 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3703 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3707 /* Mandatory fix, always stop CP, required to set spl offset back to
3708 hardware default (is set to 0 by ucode during pilot detection */
3709 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3713 /*== Write channel settings to device =====================================*/
3716 switch (state->props.transmission_mode) {
3717 case TRANSMISSION_MODE_AUTO:
3719 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
3720 /* fall through , try first guess DRX_FFTMODE_8K */
3721 case TRANSMISSION_MODE_8K:
3722 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
3724 case TRANSMISSION_MODE_2K:
3725 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
3730 switch (state->props.guard_interval) {
3732 case GUARD_INTERVAL_AUTO:
3733 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
3734 /* fall through , try first guess DRX_GUARD_1DIV4 */
3735 case GUARD_INTERVAL_1_4:
3736 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
3738 case GUARD_INTERVAL_1_32:
3739 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
3741 case GUARD_INTERVAL_1_16:
3742 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
3744 case GUARD_INTERVAL_1_8:
3745 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
3750 switch (state->props.hierarchy) {
3751 case HIERARCHY_AUTO:
3752 case HIERARCHY_NONE:
3754 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
3755 /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
3756 /* transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
3759 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3762 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3765 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3771 switch (state->props.modulation) {
3774 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
3775 /* fall through , try first guess DRX_CONSTELLATION_QAM64 */
3777 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3780 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3783 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3787 /* No hierachical channels support in BDA */
3788 /* Priority (only for hierarchical channels) */
3789 switch (channel->priority) {
3790 case DRX_PRIORITY_LOW:
3791 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3792 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3793 OFDM_EC_SB_PRIOR_LO);
3795 case DRX_PRIORITY_HIGH:
3796 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3797 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3798 OFDM_EC_SB_PRIOR_HI));
3800 case DRX_PRIORITY_UNKNOWN: /* fall through */
3806 /* Set Priorty high */
3807 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3808 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3814 switch (state->props.code_rate_HP) {
3817 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
3818 /* fall through , try first guess DRX_CODERATE_2DIV3 */
3820 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3823 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3826 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3829 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3832 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3836 /* SAW filter selection: normaly not necesarry, but if wanted
3837 the application can select a SAW filter via the driver by using UIOs */
3838 /* First determine real bandwidth (Hz) */
3839 /* Also set delay for impulse noise cruncher */
3840 /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed
3841 by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC
3843 switch (state->props.bandwidth_hz) {
3845 state->props.bandwidth_hz = 8000000;
3848 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3849 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052);
3852 /* cochannel protection for PAL 8 MHz */
3853 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7);
3856 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7);
3859 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7);
3862 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3867 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3868 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491);
3871 /* cochannel protection for PAL 7 MHz */
3872 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8);
3875 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8);
3878 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4);
3881 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3886 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3887 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073);
3890 /* cochannel protection for NTSC 6 MHz */
3891 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19);
3894 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19);
3897 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14);
3900 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3909 if (iqmRcRateOfs == 0) {
3910 /* Now compute IQM_RC_RATE_OFS
3911 (((SysFreq/BandWidth)/2)/2) -1) * 2^23)
3913 ((SysFreq / BandWidth) * (2^21)) - (2^23)
3915 /* (SysFreq / BandWidth) * (2^28) */
3916 /* assert (MAX(sysClk)/MIN(bandwidth) < 16)
3917 => assert(MAX(sysClk) < 16*MIN(bandwidth))
3918 => assert(109714272 > 48000000) = true so Frac 28 can be used */
3919 iqmRcRateOfs = Frac28a((u32)
3920 ((state->m_sysClockFreq *
3921 1000) / 3), bandwidth);
3922 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */
3923 if ((iqmRcRateOfs & 0x7fL) >= 0x40)
3924 iqmRcRateOfs += 0x80L;
3925 iqmRcRateOfs = iqmRcRateOfs >> 7;
3926 /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */
3927 iqmRcRateOfs = iqmRcRateOfs - (1 << 23);
3931 ((((u32) IQM_RC_RATE_OFS_HI__M) <<
3932 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
3933 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs);
3937 /* Bandwidth setting done */
3940 status = DVBTSetFrequencyShift(demod, channel, tunerOffset);
3944 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
3948 /*== Start SC, write channel settings to SC ===============================*/
3950 /* Activate SCU to enable SCU commands */
3951 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3955 /* Enable SC after setting all other parameters */
3956 status = write16(state, OFDM_SC_COMM_STATE__A, 0);
3959 status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
3964 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
3968 /* Write SC parameter registers, set all AUTO flags in operation mode */
3969 param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
3970 OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
3971 OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
3972 OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
3973 OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
3974 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
3975 0, transmissionParams, param1, 0, 0, 0);
3979 if (!state->m_DRXK_A3_ROM_CODE)
3980 status = DVBTCtrlSetSqiSpeed(state, &state->m_sqiSpeed);
3983 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3989 /*============================================================================*/
3992 * \brief Retreive lock status .
3993 * \param demod Pointer to demodulator instance.
3994 * \param lockStat Pointer to lock status structure.
3995 * \return DRXStatus_t.
3998 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus)
4001 const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
4002 OFDM_SC_RA_RAM_LOCK_FEC__M);
4003 const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4004 const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4006 u16 ScRaRamLock = 0;
4011 *pLockStatus = NOT_LOCKED;
4013 /* Check if SC is running */
4014 status = read16(state, OFDM_SC_COMM_EXEC__A, &ScCommExec);
4017 if (ScCommExec == OFDM_SC_COMM_EXEC_STOP)
4020 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock);
4024 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask)
4025 *pLockStatus = MPEG_LOCK;
4026 else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
4027 *pLockStatus = FEC_LOCK;
4028 else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
4029 *pLockStatus = DEMOD_LOCK;
4030 else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4031 *pLockStatus = NEVER_LOCK;
4034 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4039 static int PowerUpQAM(struct drxk_state *state)
4041 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
4045 status = CtrlPowerMode(state, &powerMode);
4047 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4053 /** Power Down QAM */
4054 static int PowerDownQAM(struct drxk_state *state)
4061 status = read16(state, SCU_COMM_EXEC__A, &data);
4064 if (data == SCU_COMM_EXEC_ACTIVE) {
4069 /* stop all comstate->m_exec */
4070 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4073 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
4078 status = SetIqmAf(state, false);
4082 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4087 /*============================================================================*/
4090 * \brief Setup of the QAM Measurement intervals for signal quality
4091 * \param demod instance of demod.
4092 * \param modulation current modulation.
4093 * \return DRXStatus_t.
4096 * Take into account that for certain settings the errorcounters can overflow.
4097 * The implementation does not check this.
4100 static int SetQAMMeasurement(struct drxk_state *state,
4101 enum EDrxkConstellation modulation,
4104 u32 fecBitsDesired = 0; /* BER accounting period */
4105 u32 fecRsPeriodTotal = 0; /* Total period */
4106 u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */
4107 u16 fecRsPeriod = 0; /* Value for corresponding I2C register */
4113 /* fecBitsDesired = symbolRate [kHz] *
4119 switch (modulation) {
4120 case DRX_CONSTELLATION_QAM16:
4121 fecBitsDesired = 4 * symbolRate;
4123 case DRX_CONSTELLATION_QAM32:
4124 fecBitsDesired = 5 * symbolRate;
4126 case DRX_CONSTELLATION_QAM64:
4127 fecBitsDesired = 6 * symbolRate;
4129 case DRX_CONSTELLATION_QAM128:
4130 fecBitsDesired = 7 * symbolRate;
4132 case DRX_CONSTELLATION_QAM256:
4133 fecBitsDesired = 8 * symbolRate;
4141 fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */
4142 fecBitsDesired *= 500; /* meas. period [ms] */
4144 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
4145 /* fecRsPeriodTotal = fecBitsDesired / 1632 */
4146 fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil */
4148 /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */
4149 fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16);
4150 if (fecRsPrescale == 0) {
4151 /* Divide by zero (though impossible) */
4157 ((u16) fecRsPeriodTotal +
4158 (fecRsPrescale >> 1)) / fecRsPrescale;
4160 /* write corresponding registers */
4161 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod);
4164 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale);
4167 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod);
4170 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4174 static int SetQAM16(struct drxk_state *state)
4179 /* QAM Equalizer Setup */
4181 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4184 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4187 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4190 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4193 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4196 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4199 /* Decision Feedback Equalizer */
4200 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4203 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4206 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4209 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4212 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4215 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4219 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4222 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4225 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4229 /* QAM Slicer Settings */
4230 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16);
4234 /* QAM Loop Controller Coeficients */
4235 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4238 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4241 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4244 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4247 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4250 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4253 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4256 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4260 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4263 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4266 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4269 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4272 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4275 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4278 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4281 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4284 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4287 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4290 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4293 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4298 /* QAM State Machine (FSM) Thresholds */
4300 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4303 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4306 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4309 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4312 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4315 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4319 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4322 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4325 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4330 /* QAM FSM Tracking Parameters */
4332 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4335 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4338 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4341 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4344 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4347 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4350 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4356 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4360 /*============================================================================*/
4363 * \brief QAM32 specific setup
4364 * \param demod instance of demod.
4365 * \return DRXStatus_t.
4367 static int SetQAM32(struct drxk_state *state)
4373 /* QAM Equalizer Setup */
4375 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4378 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4381 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4384 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4387 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4390 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4394 /* Decision Feedback Equalizer */
4395 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4398 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4401 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4404 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4407 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4410 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4414 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4417 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4420 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4424 /* QAM Slicer Settings */
4426 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32);
4431 /* QAM Loop Controller Coeficients */
4433 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4436 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4439 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4442 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4445 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4448 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4451 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4454 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4458 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4461 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4464 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4467 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4470 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4473 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4476 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4479 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4482 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4485 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4488 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4491 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4496 /* QAM State Machine (FSM) Thresholds */
4498 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4501 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4504 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4507 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4510 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4513 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4517 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4520 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4523 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4528 /* QAM FSM Tracking Parameters */
4530 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4533 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4536 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4539 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4542 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4545 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4548 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4551 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4555 /*============================================================================*/
4558 * \brief QAM64 specific setup
4559 * \param demod instance of demod.
4560 * \return DRXStatus_t.
4562 static int SetQAM64(struct drxk_state *state)
4567 /* QAM Equalizer Setup */
4569 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4572 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4575 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4578 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4581 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4584 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4588 /* Decision Feedback Equalizer */
4589 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4592 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4595 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4598 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4601 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4604 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4608 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4611 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4614 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4618 /* QAM Slicer Settings */
4619 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64);
4624 /* QAM Loop Controller Coeficients */
4626 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4629 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4632 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4635 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4638 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4641 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4644 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4647 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4651 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4654 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4657 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4660 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4663 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4666 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4669 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4672 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4675 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4678 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4681 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4684 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4689 /* QAM State Machine (FSM) Thresholds */
4691 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4694 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4697 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4700 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4703 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4706 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4710 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4713 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4716 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4721 /* QAM FSM Tracking Parameters */
4723 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4726 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4729 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4732 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4735 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4738 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4741 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4744 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4749 /*============================================================================*/
4752 * \brief QAM128 specific setup
4753 * \param demod: instance of demod.
4754 * \return DRXStatus_t.
4756 static int SetQAM128(struct drxk_state *state)
4761 /* QAM Equalizer Setup */
4763 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4766 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4769 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4772 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4775 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4778 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4782 /* Decision Feedback Equalizer */
4783 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4786 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4789 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4792 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4795 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4798 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4802 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4805 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4808 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4813 /* QAM Slicer Settings */
4815 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128);
4820 /* QAM Loop Controller Coeficients */
4822 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4825 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4828 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4831 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4834 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4837 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4840 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4843 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4847 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4850 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4853 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4856 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4859 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4862 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4865 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4868 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4871 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4874 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4877 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4880 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4885 /* QAM State Machine (FSM) Thresholds */
4887 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4890 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4893 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4896 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4899 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
4902 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4906 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4909 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
4913 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
4917 /* QAM FSM Tracking Parameters */
4919 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
4922 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
4925 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
4928 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
4931 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
4934 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
4937 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
4940 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4945 /*============================================================================*/
4948 * \brief QAM256 specific setup
4949 * \param demod: instance of demod.
4950 * \return DRXStatus_t.
4952 static int SetQAM256(struct drxk_state *state)
4957 /* QAM Equalizer Setup */
4959 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
4962 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
4965 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
4968 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
4971 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
4974 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
4978 /* Decision Feedback Equalizer */
4979 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
4982 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
4985 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
4988 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
4991 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
4994 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4998 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5001 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5004 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5008 /* QAM Slicer Settings */
5010 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256);
5015 /* QAM Loop Controller Coeficients */
5017 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5020 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5023 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5026 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5029 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5032 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5035 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5038 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5042 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5045 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5048 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5051 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5054 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5057 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5060 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5063 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5066 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5069 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5072 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5075 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5080 /* QAM State Machine (FSM) Thresholds */
5082 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5085 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5088 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5091 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5094 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5097 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5101 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5104 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5107 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5112 /* QAM FSM Tracking Parameters */
5114 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5117 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5120 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5123 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5126 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5129 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5132 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5135 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5140 /*============================================================================*/
5142 * \brief Reset QAM block.
5143 * \param demod: instance of demod.
5144 * \param channel: pointer to channel data.
5145 * \return DRXStatus_t.
5147 static int QAMResetQAM(struct drxk_state *state)
5153 /* Stop QAM comstate->m_exec */
5154 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5158 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
5161 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5165 /*============================================================================*/
5168 * \brief Set QAM symbolrate.
5169 * \param demod: instance of demod.
5170 * \param channel: pointer to channel data.
5171 * \return DRXStatus_t.
5173 static int QAMSetSymbolrate(struct drxk_state *state)
5175 u32 adcFrequency = 0;
5183 /* Select & calculate correct IQM rate */
5184 adcFrequency = (state->m_sysClockFreq * 1000) / 3;
5186 /* printk(KERN_DEBUG "drxk: SR %d\n", state->props.symbol_rate); */
5187 if (state->props.symbol_rate <= 1188750)
5189 else if (state->props.symbol_rate <= 2377500)
5191 else if (state->props.symbol_rate <= 4755000)
5193 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5198 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5200 symbFreq = state->props.symbol_rate * (1 << ratesel);
5201 if (symbFreq == 0) {
5202 /* Divide by zero */
5206 iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) +
5207 (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) -
5209 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate);
5212 state->m_iqmRcRate = iqmRcRate;
5214 LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15))
5216 symbFreq = state->props.symbol_rate;
5217 if (adcFrequency == 0) {
5218 /* Divide by zero */
5222 lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) +
5223 (Frac28a((symbFreq % adcFrequency), adcFrequency) >>
5225 if (lcSymbRate > 511)
5227 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate);
5231 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5235 /*============================================================================*/
5238 * \brief Get QAM lock status.
5239 * \param demod: instance of demod.
5240 * \param channel: pointer to channel data.
5241 * \return DRXStatus_t.
5244 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus)
5247 u16 Result[2] = { 0, 0 };
5250 *pLockStatus = NOT_LOCKED;
5251 status = scu_command(state,
5252 SCU_RAM_COMMAND_STANDARD_QAM |
5253 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
5256 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5258 if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
5259 /* 0x0000 NOT LOCKED */
5260 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
5261 /* 0x4000 DEMOD LOCKED */
5262 *pLockStatus = DEMOD_LOCK;
5263 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
5264 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
5265 *pLockStatus = MPEG_LOCK;
5267 /* 0xC000 NEVER LOCKED */
5268 /* (system will never be able to lock to the signal) */
5269 /* TODO: check this, intermediate & standard specific lock states are not
5270 taken into account here */
5271 *pLockStatus = NEVER_LOCK;
5276 #define QAM_MIRROR__M 0x03
5277 #define QAM_MIRROR_NORMAL 0x00
5278 #define QAM_MIRRORED 0x01
5279 #define QAM_MIRROR_AUTO_ON 0x02
5280 #define QAM_LOCKRANGE__M 0x10
5281 #define QAM_LOCKRANGE_NORMAL 0x10
5283 static int QAMDemodulatorCommand(struct drxk_state *state,
5284 int numberOfParameters)
5288 u16 setParamParameters[4] = { 0, 0, 0, 0 };
5290 setParamParameters[0] = state->m_Constellation; /* modulation */
5291 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
5293 if (numberOfParameters == 2) {
5294 u16 setEnvParameters[1] = { 0 };
5296 if (state->m_OperationMode == OM_QAM_ITU_C)
5297 setEnvParameters[0] = QAM_TOP_ANNEX_C;
5299 setEnvParameters[0] = QAM_TOP_ANNEX_A;
5301 status = scu_command(state,
5302 SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
5303 1, setEnvParameters, 1, &cmdResult);
5307 status = scu_command(state,
5308 SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5309 numberOfParameters, setParamParameters,
5311 } else if (numberOfParameters == 4) {
5312 if (state->m_OperationMode == OM_QAM_ITU_C)
5313 setParamParameters[2] = QAM_TOP_ANNEX_C;
5315 setParamParameters[2] = QAM_TOP_ANNEX_A;
5317 setParamParameters[3] |= (QAM_MIRROR_AUTO_ON);
5318 /* Env parameters */
5319 /* check for LOCKRANGE Extented */
5320 /* setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; */
5322 status = scu_command(state,
5323 SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5324 numberOfParameters, setParamParameters,
5327 printk(KERN_WARNING "drxk: Unknown QAM demodulator parameter "
5328 "count %d\n", numberOfParameters);
5334 printk(KERN_WARNING "drxk: Warning %d on %s\n",
5339 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5340 s32 tunerFreqOffset)
5344 int qamDemodParamCount = state->qam_demod_parameter_count;
5348 * STEP 1: reset demodulator
5349 * resets FEC DI and FEC RS
5351 * resets SCU variables
5353 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5356 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5359 status = QAMResetQAM(state);
5364 * STEP 2: configure demodulator
5365 * -set params; resets IQM,QAM,FEC HW; initializes some
5368 status = QAMSetSymbolrate(state);
5373 switch (state->props.modulation) {
5375 state->m_Constellation = DRX_CONSTELLATION_QAM256;
5379 state->m_Constellation = DRX_CONSTELLATION_QAM64;
5382 state->m_Constellation = DRX_CONSTELLATION_QAM16;
5385 state->m_Constellation = DRX_CONSTELLATION_QAM32;
5388 state->m_Constellation = DRX_CONSTELLATION_QAM128;
5397 /* Use the 4-parameter if it's requested or we're probing for
5398 * the correct command. */
5399 if (state->qam_demod_parameter_count == 4
5400 || !state->qam_demod_parameter_count) {
5401 qamDemodParamCount = 4;
5402 status = QAMDemodulatorCommand(state, qamDemodParamCount);
5405 /* Use the 2-parameter command if it was requested or if we're
5406 * probing for the correct command and the 4-parameter command
5408 if (state->qam_demod_parameter_count == 2
5409 || (!state->qam_demod_parameter_count && status < 0)) {
5410 qamDemodParamCount = 2;
5411 status = QAMDemodulatorCommand(state, qamDemodParamCount);
5415 dprintk(1, "Could not set demodulator parameters. Make "
5416 "sure qam_demod_parameter_count (%d) is correct for "
5417 "your firmware (%s).\n",
5418 state->qam_demod_parameter_count,
5419 state->microcode_name);
5421 } else if (!state->qam_demod_parameter_count) {
5422 dprintk(1, "Auto-probing the correct QAM demodulator command "
5423 "parameters was successful - using %d parameters.\n",
5424 qamDemodParamCount);
5427 * One of our commands was successful. We don't need to
5428 * auto-probe anymore, now that we got the correct command.
5430 state->qam_demod_parameter_count = qamDemodParamCount;
5434 * STEP 3: enable the system in a mode where the ADC provides valid
5435 * signal setup modulation independent registers
5438 status = SetFrequency(channel, tunerFreqOffset));
5442 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
5446 /* Setup BER measurement */
5447 status = SetQAMMeasurement(state, state->m_Constellation, state->props.symbol_rate);
5451 /* Reset default values */
5452 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5455 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5459 /* Reset default LC values */
5460 status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5463 status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5466 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5469 status = write16(state, QAM_LC_MODE__A, 7);
5473 status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5476 status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5479 status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5482 status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5485 status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5488 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5491 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5494 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5497 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5500 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5503 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5506 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5509 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5512 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5515 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5519 /* Mirroring, QAM-block starting point not inverted */
5520 status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5524 /* Halt SCU to enable safe non-atomic accesses */
5525 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5529 /* STEP 4: modulation specific setup */
5530 switch (state->props.modulation) {
5532 status = SetQAM16(state);
5535 status = SetQAM32(state);
5539 status = SetQAM64(state);
5542 status = SetQAM128(state);
5545 status = SetQAM256(state);
5554 /* Activate SCU to enable SCU commands */
5555 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5559 /* Re-configure MPEG output, requires knowledge of channel bitrate */
5560 /* extAttr->currentChannel.modulation = channel->modulation; */
5561 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */
5562 status = MPEGTSDtoSetup(state, state->m_OperationMode);
5566 /* Start processes */
5567 status = MPEGTSStart(state);
5570 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5573 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5576 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5580 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
5581 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
5585 /* update global DRXK data container */
5586 /*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
5590 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5594 static int SetQAMStandard(struct drxk_state *state,
5595 enum OperationMode oMode)
5598 #ifdef DRXK_QAM_TAPS
5599 #define DRXK_QAMA_TAPS_SELECT
5600 #include "drxk_filters.h"
5601 #undef DRXK_QAMA_TAPS_SELECT
5606 /* added antenna switch */
5607 SwitchAntennaToQAM(state);
5609 /* Ensure correct power-up mode */
5610 status = PowerUpQAM(state);
5613 /* Reset QAM block */
5614 status = QAMResetQAM(state);
5620 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5623 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5627 /* Upload IQM Channel Filter settings by
5628 boot loader from ROM table */
5631 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5634 status = BLDirectCmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5637 status = BLDirectCmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5645 status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B));
5648 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5651 status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5655 status = write16(state, IQM_RC_STRETCH__A, 21);
5658 status = write16(state, IQM_AF_CLP_LEN__A, 0);
5661 status = write16(state, IQM_AF_CLP_TH__A, 448);
5664 status = write16(state, IQM_AF_SNS_LEN__A, 0);
5667 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5671 status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5674 status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5677 status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5680 status = write16(state, IQM_AF_UPD_SEL__A, 0);
5684 /* IQM Impulse Noise Processing Unit */
5685 status = write16(state, IQM_CF_CLP_VAL__A, 500);
5688 status = write16(state, IQM_CF_DATATH__A, 1000);
5691 status = write16(state, IQM_CF_BYPASSDET__A, 1);
5694 status = write16(state, IQM_CF_DET_LCT__A, 0);
5697 status = write16(state, IQM_CF_WND_LEN__A, 1);
5700 status = write16(state, IQM_CF_PKDTH__A, 1);
5703 status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5707 /* turn on IQMAF. Must be done before setAgc**() */
5708 status = SetIqmAf(state, true);
5711 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5715 /* IQM will not be reset from here, sync ADC and update/init AGC */
5716 status = ADCSynchronization(state);
5720 /* Set the FSM step period */
5721 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5725 /* Halt SCU to enable safe non-atomic accesses */
5726 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5730 /* No more resets of the IQM, current standard correctly set =>
5731 now AGCs can be configured. */
5733 status = InitAGC(state, true);
5736 status = SetPreSaw(state, &(state->m_qamPreSawCfg));
5740 /* Configure AGC's */
5741 status = SetAgcRf(state, &(state->m_qamRfAgcCfg), true);
5744 status = SetAgcIf(state, &(state->m_qamIfAgcCfg), true);
5748 /* Activate SCU to enable SCU commands */
5749 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5752 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5756 static int WriteGPIO(struct drxk_state *state)
5762 /* stop lock indicator process */
5763 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5767 /* Write magic word to enable pdr reg write */
5768 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5772 if (state->m_hasSAWSW) {
5773 if (state->UIO_mask & 0x0001) { /* UIO-1 */
5774 /* write to io pad configuration register - output mode */
5775 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5779 /* use corresponding bit in io data output registar */
5780 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5783 if ((state->m_GPIO & 0x0001) == 0)
5784 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
5786 value |= 0x8000; /* write one to 15th bit - 1st UIO */
5787 /* write back to io data output register */
5788 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5792 if (state->UIO_mask & 0x0002) { /* UIO-2 */
5793 /* write to io pad configuration register - output mode */
5794 status = write16(state, SIO_PDR_SMA_RX_CFG__A, state->m_GPIOCfg);
5798 /* use corresponding bit in io data output registar */
5799 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5802 if ((state->m_GPIO & 0x0002) == 0)
5803 value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */
5805 value |= 0x4000; /* write one to 14th bit - 2st UIO */
5806 /* write back to io data output register */
5807 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5811 if (state->UIO_mask & 0x0004) { /* UIO-3 */
5812 /* write to io pad configuration register - output mode */
5813 status = write16(state, SIO_PDR_GPIO_CFG__A, state->m_GPIOCfg);
5817 /* use corresponding bit in io data output registar */
5818 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5821 if ((state->m_GPIO & 0x0004) == 0)
5822 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
5824 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */
5825 /* write back to io data output register */
5826 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5831 /* Write magic word to disable pdr reg write */
5832 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5835 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5839 static int SwitchAntennaToQAM(struct drxk_state *state)
5846 if (!state->antenna_gpio)
5849 gpio_state = state->m_GPIO & state->antenna_gpio;
5851 if (state->antenna_dvbt ^ gpio_state) {
5852 /* Antenna is on DVB-T mode. Switch */
5853 if (state->antenna_dvbt)
5854 state->m_GPIO &= ~state->antenna_gpio;
5856 state->m_GPIO |= state->antenna_gpio;
5857 status = WriteGPIO(state);
5860 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5864 static int SwitchAntennaToDVBT(struct drxk_state *state)
5871 if (!state->antenna_gpio)
5874 gpio_state = state->m_GPIO & state->antenna_gpio;
5876 if (!(state->antenna_dvbt ^ gpio_state)) {
5877 /* Antenna is on DVB-C mode. Switch */
5878 if (state->antenna_dvbt)
5879 state->m_GPIO |= state->antenna_gpio;
5881 state->m_GPIO &= ~state->antenna_gpio;
5882 status = WriteGPIO(state);
5885 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5890 static int PowerDownDevice(struct drxk_state *state)
5892 /* Power down to requested mode */
5893 /* Backup some register settings */
5894 /* Set pins with possible pull-ups connected to them in input mode */
5895 /* Analog power down */
5896 /* ADC power down */
5897 /* Power down device */
5901 if (state->m_bPDownOpenBridge) {
5902 /* Open I2C bridge before power down of DRXK */
5903 status = ConfigureI2CBridge(state, true);
5908 status = DVBTEnableOFDMTokenRing(state, false);
5912 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK);
5915 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5918 state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
5919 status = HI_CfgCommand(state);
5922 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5927 static int init_drxk(struct drxk_state *state)
5929 int status = 0, n = 0;
5930 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
5934 if ((state->m_DrxkState == DRXK_UNINITIALIZED)) {
5935 drxk_i2c_lock(state);
5936 status = PowerUpDevice(state);
5939 status = DRXX_Open(state);
5942 /* Soft reset of OFDM-, sys- and osc-clockdomain */
5943 status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M);
5946 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5949 /* TODO is this needed, if yes how much delay in worst case scenario */
5951 state->m_DRXK_A3_PATCH_CODE = true;
5952 status = GetDeviceCapabilities(state);
5956 /* Bridge delay, uses oscilator clock */
5957 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
5958 /* SDA brdige delay */
5959 state->m_HICfgBridgeDelay =
5960 (u16) ((state->m_oscClockFreq / 1000) *
5961 HI_I2C_BRIDGE_DELAY) / 1000;
5963 if (state->m_HICfgBridgeDelay >
5964 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
5965 state->m_HICfgBridgeDelay =
5966 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
5968 /* SCL bridge delay, same as SDA for now */
5969 state->m_HICfgBridgeDelay +=
5970 state->m_HICfgBridgeDelay <<
5971 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
5973 status = InitHI(state);
5976 /* disable various processes */
5978 if (!(state->m_DRXK_A1_ROM_CODE)
5979 && !(state->m_DRXK_A2_ROM_CODE))
5982 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5987 /* disable MPEG port */
5988 status = MPEGTSDisable(state);
5992 /* Stop AUD and SCU */
5993 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
5996 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6000 /* enable token-ring bus through OFDM block for possible ucode upload */
6001 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
6005 /* include boot loader section */
6006 status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE);
6009 status = BLChainCmd(state, 0, 6, 100);
6014 status = DownloadMicrocode(state, state->fw->data,
6020 /* disable token-ring bus through OFDM block for possible ucode upload */
6021 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6025 /* Run SCU for a little while to initialize microcode version numbers */
6026 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6029 status = DRXX_Open(state);
6032 /* added for test */
6035 powerMode = DRXK_POWER_DOWN_OFDM;
6036 status = CtrlPowerMode(state, &powerMode);
6040 /* Stamp driver version number in SCU data RAM in BCD code
6041 Done to enable field application engineers to retreive drxdriver version
6042 via I2C from SCU RAM.
6043 Not using SCU command interface for SCU register access since no
6044 microcode may be present.
6047 (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6048 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6049 ((DRXK_VERSION_MAJOR % 10) << 4) +
6050 (DRXK_VERSION_MINOR % 10);
6051 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion);
6055 (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6056 (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6057 (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6058 (DRXK_VERSION_PATCH % 10);
6059 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion);
6063 printk(KERN_INFO "DRXK driver version %d.%d.%d\n",
6064 DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6065 DRXK_VERSION_PATCH);
6067 /* Dirty fix of default values for ROM/PATCH microcode
6068 Dirty because this fix makes it impossible to setup suitable values
6069 before calling DRX_Open. This solution requires changes to RF AGC speed
6070 to be done via the CTRL function after calling DRX_Open */
6072 /* m_dvbtRfAgcCfg.speed = 3; */
6074 /* Reset driver debug flags to 0 */
6075 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6080 NOTE: No more full FEC resets allowed afterwards!! */
6081 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6084 /* MPEGTS functions are still the same */
6085 status = MPEGTSDtoInit(state);
6088 status = MPEGTSStop(state);
6091 status = MPEGTSConfigurePolarity(state);
6094 status = MPEGTSConfigurePins(state, state->m_enableMPEGOutput);
6097 /* added: configure GPIO */
6098 status = WriteGPIO(state);
6102 state->m_DrxkState = DRXK_STOPPED;
6104 if (state->m_bPowerDown) {
6105 status = PowerDownDevice(state);
6108 state->m_DrxkState = DRXK_POWERED_DOWN;
6110 state->m_DrxkState = DRXK_STOPPED;
6112 /* Initialize the supported delivery systems */
6114 if (state->m_hasDVBC) {
6115 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
6116 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
6117 strlcat(state->frontend.ops.info.name, " DVB-C",
6118 sizeof(state->frontend.ops.info.name));
6120 if (state->m_hasDVBT) {
6121 state->frontend.ops.delsys[n++] = SYS_DVBT;
6122 strlcat(state->frontend.ops.info.name, " DVB-T",
6123 sizeof(state->frontend.ops.info.name));
6125 drxk_i2c_unlock(state);
6129 state->m_DrxkState = DRXK_NO_DEV;
6130 drxk_i2c_unlock(state);
6131 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
6137 static void load_firmware_cb(const struct firmware *fw,
6140 struct drxk_state *state = context;
6142 dprintk(1, ": %s\n", fw ? "firmware loaded" : "firmware not loaded");
6145 "drxk: Could not load firmware file %s.\n",
6146 state->microcode_name);
6148 "drxk: Copy %s to your hotplug directory!\n",
6149 state->microcode_name);
6150 state->microcode_name = NULL;
6153 * As firmware is now load asynchronous, it is not possible
6154 * anymore to fail at frontend attach. We might silently
6155 * return here, and hope that the driver won't crash.
6156 * We might also change all DVB callbacks to return -ENODEV
6157 * if the device is not initialized.
6158 * As the DRX-K devices have their own internal firmware,
6159 * let's just hope that it will match a firmware revision
6160 * compatible with this driver and proceed.
6168 static void drxk_release(struct dvb_frontend *fe)
6170 struct drxk_state *state = fe->demodulator_priv;
6174 release_firmware(state->fw);
6179 static int drxk_sleep(struct dvb_frontend *fe)
6181 struct drxk_state *state = fe->demodulator_priv;
6185 if (state->m_DrxkState == DRXK_NO_DEV)
6187 if (state->m_DrxkState == DRXK_UNINITIALIZED)
6194 static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
6196 struct drxk_state *state = fe->demodulator_priv;
6198 dprintk(1, ": %s\n", enable ? "enable" : "disable");
6200 if (state->m_DrxkState == DRXK_NO_DEV)
6203 return ConfigureI2CBridge(state, enable ? true : false);
6206 static int drxk_set_parameters(struct dvb_frontend *fe)
6208 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6209 u32 delsys = p->delivery_system, old_delsys;
6210 struct drxk_state *state = fe->demodulator_priv;
6215 if (state->m_DrxkState == DRXK_NO_DEV)
6218 if (state->m_DrxkState == DRXK_UNINITIALIZED)
6221 if (!fe->ops.tuner_ops.get_if_frequency) {
6223 "drxk: Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
6227 if (fe->ops.i2c_gate_ctrl)
6228 fe->ops.i2c_gate_ctrl(fe, 1);
6229 if (fe->ops.tuner_ops.set_params)
6230 fe->ops.tuner_ops.set_params(fe);
6231 if (fe->ops.i2c_gate_ctrl)
6232 fe->ops.i2c_gate_ctrl(fe, 0);
6234 old_delsys = state->props.delivery_system;
6237 if (old_delsys != delsys) {
6240 case SYS_DVBC_ANNEX_A:
6241 case SYS_DVBC_ANNEX_C:
6242 if (!state->m_hasDVBC)
6244 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? true : false;
6245 if (state->m_itut_annex_c)
6246 SetOperationMode(state, OM_QAM_ITU_C);
6248 SetOperationMode(state, OM_QAM_ITU_A);
6251 if (!state->m_hasDVBT)
6253 SetOperationMode(state, OM_DVBT);
6260 fe->ops.tuner_ops.get_if_frequency(fe, &IF);
6261 Start(state, 0, IF);
6263 /* After set_frontend, stats aren't avaliable */
6264 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
6265 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6266 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6267 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6268 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6269 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6270 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6271 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6273 /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */
6278 static int get_strength(struct drxk_state *state, u64 *strength)
6281 struct SCfgAgc rfAgc, ifAgc;
6287 /* FIXME: those are part of the tuner presets */
6288 u16 tunerRfGain = 50; /* Default value on az6007 driver */
6289 u16 tunerIfGain = 40; /* Default value on az6007 driver */
6293 if (IsDVBT(state)) {
6294 rfAgc = state->m_dvbtRfAgcCfg;
6295 ifAgc = state->m_dvbtIfAgcCfg;
6296 } else if (IsQAM(state)) {
6297 rfAgc = state->m_qamRfAgcCfg;
6298 ifAgc = state->m_qamIfAgcCfg;
6300 rfAgc = state->m_atvRfAgcCfg;
6301 ifAgc = state->m_atvIfAgcCfg;
6304 if (rfAgc.ctrlMode == DRXK_AGC_CTRL_AUTO) {
6305 /* SCU outputLevel */
6306 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);
6311 read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc);
6315 if (((u32) scu_lvl + (u32) scu_coc) < 0xffff)
6316 rfAgc.outputLevel = scu_lvl + scu_coc;
6318 rfAgc.outputLevel = 0xffff;
6320 /* Take RF gain into account */
6321 totalGain += tunerRfGain;
6323 /* clip output value */
6324 if (rfAgc.outputLevel < rfAgc.minOutputLevel)
6325 rfAgc.outputLevel = rfAgc.minOutputLevel;
6326 if (rfAgc.outputLevel > rfAgc.maxOutputLevel)
6327 rfAgc.outputLevel = rfAgc.maxOutputLevel;
6329 agcRange = (u32) (rfAgc.maxOutputLevel - rfAgc.minOutputLevel);
6332 ((u32)(tunerRfGain)) *
6333 ((u32)(rfAgc.outputLevel - rfAgc.minOutputLevel))
6338 if (ifAgc.ctrlMode == DRXK_AGC_CTRL_AUTO) {
6339 status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,
6340 &ifAgc.outputLevel);
6344 status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,
6349 /* Take IF gain into account */
6350 totalGain += (u32) tunerIfGain;
6352 /* clip output value */
6353 if (ifAgc.outputLevel < ifAgc.minOutputLevel)
6354 ifAgc.outputLevel = ifAgc.minOutputLevel;
6355 if (ifAgc.outputLevel > ifAgc.maxOutputLevel)
6356 ifAgc.outputLevel = ifAgc.maxOutputLevel;
6358 agcRange = (u32) (ifAgc.maxOutputLevel - ifAgc.minOutputLevel);
6361 ((u32)(tunerIfGain)) *
6362 ((u32)(ifAgc.outputLevel - ifAgc.minOutputLevel))
6368 * Convert to 0..65535 scale.
6369 * If it can't be measured (AGC is disabled), just show 100%.
6372 *strength = (65535UL * atten / totalGain / 100);
6379 static int drxk_get_stats(struct dvb_frontend *fe)
6381 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
6382 struct drxk_state *state = fe->demodulator_priv;
6387 u32 post_bit_err_count;
6388 u32 post_bit_error_scale;
6389 u32 pre_bit_err_count;
6392 u32 pkt_error_count;
6395 if (state->m_DrxkState == DRXK_NO_DEV)
6397 if (state->m_DrxkState == DRXK_UNINITIALIZED)
6401 state->fe_status = 0;
6402 GetLockStatus(state, &stat);
6403 if (stat == MPEG_LOCK)
6404 state->fe_status |= 0x1f;
6405 if (stat == FEC_LOCK)
6406 state->fe_status |= 0x0f;
6407 if (stat == DEMOD_LOCK)
6408 state->fe_status |= 0x07;
6411 * Estimate signal strength from AGC
6413 get_strength(state, &c->strength.stat[0].uvalue);
6414 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
6417 if (stat >= DEMOD_LOCK) {
6418 GetSignalToNoise(state, &cnr);
6419 c->cnr.stat[0].svalue = cnr * 100;
6420 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
6422 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6425 if (stat < FEC_LOCK) {
6426 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6427 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6428 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6429 c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6430 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6431 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6437 /* BER measurement is valid if at least FEC lock is achieved */
6439 /* OFDM_EC_VD_REQ_SMB_CNT__A and/or OFDM_EC_VD_REQ_BIT_CNT can be written
6440 to set nr of symbols or bits over which
6441 to measure EC_VD_REG_ERR_BIT_CNT__A . See CtrlSetCfg(). */
6443 /* Read registers for post/preViterbi BER calculation */
6444 status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, ®16);
6447 pre_bit_err_count = reg16;
6449 status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , ®16);
6452 pre_bit_count = reg16;
6454 /* Number of bit-errors */
6455 status = read16(state, FEC_RS_NR_BIT_ERRORS__A, ®16);
6458 post_bit_err_count = reg16;
6460 status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, ®16);
6463 post_bit_error_scale = reg16;
6465 status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, ®16);
6470 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, ®16);
6473 pkt_error_count = reg16;
6474 write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
6476 post_bit_err_count *= post_bit_error_scale;
6478 post_bit_count = pkt_count * 204 * 8;
6480 /* Store the results */
6481 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
6482 c->block_error.stat[0].uvalue += pkt_error_count;
6483 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
6484 c->block_count.stat[0].uvalue += pkt_count;
6486 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
6487 c->pre_bit_error.stat[0].uvalue += pre_bit_err_count;
6488 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
6489 c->pre_bit_count.stat[0].uvalue += pre_bit_count;
6491 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
6492 c->post_bit_error.stat[0].uvalue += post_bit_err_count;
6493 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
6494 c->post_bit_count.stat[0].uvalue += post_bit_count;
6501 static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status)
6503 struct drxk_state *state = fe->demodulator_priv;
6508 rc = drxk_get_stats(fe);
6512 *status = state->fe_status;
6517 static int drxk_read_signal_strength(struct dvb_frontend *fe,
6520 struct drxk_state *state = fe->demodulator_priv;
6521 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
6525 if (state->m_DrxkState == DRXK_NO_DEV)
6527 if (state->m_DrxkState == DRXK_UNINITIALIZED)
6530 *strength = c->strength.stat[0].uvalue;
6534 static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
6536 struct drxk_state *state = fe->demodulator_priv;
6541 if (state->m_DrxkState == DRXK_NO_DEV)
6543 if (state->m_DrxkState == DRXK_UNINITIALIZED)
6546 GetSignalToNoise(state, &snr2);
6548 /* No negative SNR, clip to zero */
6551 *snr = snr2 & 0xffff;
6555 static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6557 struct drxk_state *state = fe->demodulator_priv;
6562 if (state->m_DrxkState == DRXK_NO_DEV)
6564 if (state->m_DrxkState == DRXK_UNINITIALIZED)
6567 DVBTQAMGetAccPktErr(state, &err);
6568 *ucblocks = (u32) err;
6572 static int drxk_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings
6575 struct drxk_state *state = fe->demodulator_priv;
6576 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6580 if (state->m_DrxkState == DRXK_NO_DEV)
6582 if (state->m_DrxkState == DRXK_UNINITIALIZED)
6585 switch (p->delivery_system) {
6586 case SYS_DVBC_ANNEX_A:
6587 case SYS_DVBC_ANNEX_C:
6589 sets->min_delay_ms = 3000;
6590 sets->max_drift = 0;
6591 sets->step_size = 0;
6598 static struct dvb_frontend_ops drxk_ops = {
6599 /* .delsys will be filled dynamically */
6602 .frequency_min = 47000000,
6603 .frequency_max = 865000000,
6605 .symbol_rate_min = 870000,
6606 .symbol_rate_max = 11700000,
6608 .frequency_stepsize = 166667,
6610 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
6611 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO |
6612 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
6613 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS |
6614 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
6615 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO
6618 .release = drxk_release,
6619 .sleep = drxk_sleep,
6620 .i2c_gate_ctrl = drxk_gate_ctrl,
6622 .set_frontend = drxk_set_parameters,
6623 .get_tune_settings = drxk_get_tune_settings,
6625 .read_status = drxk_read_status,
6626 .read_signal_strength = drxk_read_signal_strength,
6627 .read_snr = drxk_read_snr,
6628 .read_ucblocks = drxk_read_ucblocks,
6631 struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6632 struct i2c_adapter *i2c)
6634 struct dtv_frontend_properties *p;
6635 struct drxk_state *state = NULL;
6636 u8 adr = config->adr;
6640 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
6645 state->demod_address = adr;
6646 state->single_master = config->single_master;
6647 state->microcode_name = config->microcode_name;
6648 state->qam_demod_parameter_count = config->qam_demod_parameter_count;
6649 state->no_i2c_bridge = config->no_i2c_bridge;
6650 state->antenna_gpio = config->antenna_gpio;
6651 state->antenna_dvbt = config->antenna_dvbt;
6652 state->m_ChunkSize = config->chunk_size;
6653 state->enable_merr_cfg = config->enable_merr_cfg;
6655 if (config->dynamic_clk) {
6656 state->m_DVBTStaticCLK = 0;
6657 state->m_DVBCStaticCLK = 0;
6659 state->m_DVBTStaticCLK = 1;
6660 state->m_DVBCStaticCLK = 1;
6664 if (config->mpeg_out_clk_strength)
6665 state->m_TSClockkStrength = config->mpeg_out_clk_strength & 0x07;
6667 state->m_TSClockkStrength = 0x06;
6669 if (config->parallel_ts)
6670 state->m_enableParallel = true;
6672 state->m_enableParallel = false;
6674 /* NOTE: as more UIO bits will be used, add them to the mask */
6675 state->UIO_mask = config->antenna_gpio;
6677 /* Default gpio to DVB-C */
6678 if (!state->antenna_dvbt && state->antenna_gpio)
6679 state->m_GPIO |= state->antenna_gpio;
6681 state->m_GPIO &= ~state->antenna_gpio;
6683 mutex_init(&state->mutex);
6685 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));
6686 state->frontend.demodulator_priv = state;
6690 /* Load firmware and initialize DRX-K */
6691 if (state->microcode_name) {
6692 if (config->load_firmware_sync) {
6693 const struct firmware *fw = NULL;
6695 status = request_firmware(&fw, state->microcode_name,
6696 state->i2c->dev.parent);
6699 load_firmware_cb(fw, state);
6701 status = request_firmware_nowait(THIS_MODULE, 1,
6702 state->microcode_name,
6703 state->i2c->dev.parent,
6705 state, load_firmware_cb);
6708 "drxk: failed to request a firmware\n");
6712 } else if (init_drxk(state) < 0)
6716 /* Initialize stats */
6717 p = &state->frontend.dtv_property_cache;
6718 p->strength.len = 1;
6720 p->block_error.len = 1;
6721 p->block_count.len = 1;
6722 p->pre_bit_error.len = 1;
6723 p->pre_bit_count.len = 1;
6724 p->post_bit_error.len = 1;
6725 p->post_bit_count.len = 1;
6727 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
6728 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6729 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6730 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6731 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6732 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6733 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6734 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6736 printk(KERN_INFO "drxk: frontend initialized.\n");
6737 return &state->frontend;
6740 printk(KERN_ERR "drxk: not found\n");
6744 EXPORT_SYMBOL(drxk_attach);
6746 MODULE_DESCRIPTION("DRX-K driver");
6747 MODULE_AUTHOR("Ralph Metzler");
6748 MODULE_LICENSE("GPL");