2 * Sony CXD2820R demodulator driver
4 * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 #include "cxd2820r_priv.h"
24 int cxd2820r_set_frontend_t(struct dvb_frontend *fe)
26 struct cxd2820r_priv *priv = fe->demodulator_priv;
27 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
32 u8 bw_params1[][5] = {
33 { 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
34 { 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
35 { 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
37 u8 bw_params2[][2] = {
38 { 0x1f, 0xdc }, /* 6 MHz */
39 { 0x12, 0xf8 }, /* 7 MHz */
40 { 0x01, 0xe0 }, /* 8 MHz */
42 struct reg_val_mask tab[] = {
43 { 0x00080, 0x00, 0xff },
44 { 0x00081, 0x03, 0xff },
45 { 0x00085, 0x07, 0xff },
46 { 0x00088, 0x01, 0xff },
48 { 0x00070, priv->cfg.ts_mode, 0xff },
49 { 0x000cb, priv->cfg.if_agc_polarity << 6, 0x40 },
50 { 0x000a5, 0x00, 0x01 },
51 { 0x00082, 0x20, 0x60 },
52 { 0x000c2, 0xc3, 0xff },
53 { 0x0016a, 0x50, 0xff },
54 { 0x00427, 0x41, 0xff },
57 dev_dbg(&priv->i2c->dev, "%s: frequency=%d bandwidth_hz=%d\n", __func__,
58 c->frequency, c->bandwidth_hz);
60 switch (c->bandwidth_hz) {
78 if (fe->ops.tuner_ops.set_params)
79 fe->ops.tuner_ops.set_params(fe);
81 if (priv->delivery_system != SYS_DVBT) {
82 for (i = 0; i < ARRAY_SIZE(tab); i++) {
83 ret = cxd2820r_wr_reg_mask(priv, tab[i].reg,
84 tab[i].val, tab[i].mask);
90 priv->delivery_system = SYS_DVBT;
91 priv->ber_running = 0; /* tune stops BER counter */
93 /* program IF frequency */
94 if (fe->ops.tuner_ops.get_if_frequency) {
95 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
101 dev_dbg(&priv->i2c->dev, "%s: if_freq=%d\n", __func__, if_freq);
103 num = if_freq / 1000; /* Hz => kHz */
105 if_ctl = cxd2820r_div_u64_round_closest(num, 41000);
106 buf[0] = ((if_ctl >> 16) & 0xff);
107 buf[1] = ((if_ctl >> 8) & 0xff);
108 buf[2] = ((if_ctl >> 0) & 0xff);
110 ret = cxd2820r_wr_regs(priv, 0x000b6, buf, 3);
114 ret = cxd2820r_wr_regs(priv, 0x0009f, bw_params1[bw_i], 5);
118 ret = cxd2820r_wr_reg_mask(priv, 0x000d7, bw_param << 6, 0xc0);
122 ret = cxd2820r_wr_regs(priv, 0x000d9, bw_params2[bw_i], 2);
126 ret = cxd2820r_wr_reg(priv, 0x000ff, 0x08);
130 ret = cxd2820r_wr_reg(priv, 0x000fe, 0x01);
136 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
140 int cxd2820r_get_frontend_t(struct dvb_frontend *fe)
142 struct cxd2820r_priv *priv = fe->demodulator_priv;
143 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
147 ret = cxd2820r_rd_regs(priv, 0x0002f, buf, sizeof(buf));
151 switch ((buf[0] >> 6) & 0x03) {
153 c->modulation = QPSK;
156 c->modulation = QAM_16;
159 c->modulation = QAM_64;
163 switch ((buf[1] >> 1) & 0x03) {
165 c->transmission_mode = TRANSMISSION_MODE_2K;
168 c->transmission_mode = TRANSMISSION_MODE_8K;
172 switch ((buf[1] >> 3) & 0x03) {
174 c->guard_interval = GUARD_INTERVAL_1_32;
177 c->guard_interval = GUARD_INTERVAL_1_16;
180 c->guard_interval = GUARD_INTERVAL_1_8;
183 c->guard_interval = GUARD_INTERVAL_1_4;
187 switch ((buf[0] >> 3) & 0x07) {
189 c->hierarchy = HIERARCHY_NONE;
192 c->hierarchy = HIERARCHY_1;
195 c->hierarchy = HIERARCHY_2;
198 c->hierarchy = HIERARCHY_4;
202 switch ((buf[0] >> 0) & 0x07) {
204 c->code_rate_HP = FEC_1_2;
207 c->code_rate_HP = FEC_2_3;
210 c->code_rate_HP = FEC_3_4;
213 c->code_rate_HP = FEC_5_6;
216 c->code_rate_HP = FEC_7_8;
220 switch ((buf[1] >> 5) & 0x07) {
222 c->code_rate_LP = FEC_1_2;
225 c->code_rate_LP = FEC_2_3;
228 c->code_rate_LP = FEC_3_4;
231 c->code_rate_LP = FEC_5_6;
234 c->code_rate_LP = FEC_7_8;
238 ret = cxd2820r_rd_reg(priv, 0x007c6, &buf[0]);
242 switch ((buf[0] >> 0) & 0x01) {
244 c->inversion = INVERSION_OFF;
247 c->inversion = INVERSION_ON;
253 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
257 int cxd2820r_read_ber_t(struct dvb_frontend *fe, u32 *ber)
259 struct cxd2820r_priv *priv = fe->demodulator_priv;
261 u8 buf[3], start_ber = 0;
264 if (priv->ber_running) {
265 ret = cxd2820r_rd_regs(priv, 0x00076, buf, sizeof(buf));
269 if ((buf[2] >> 7) & 0x01 || (buf[2] >> 4) & 0x01) {
270 *ber = (buf[2] & 0x0f) << 16 | buf[1] << 8 | buf[0];
274 priv->ber_running = 1;
280 ret = cxd2820r_wr_reg(priv, 0x00079, 0x01);
287 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
291 int cxd2820r_read_signal_strength_t(struct dvb_frontend *fe,
294 struct cxd2820r_priv *priv = fe->demodulator_priv;
299 ret = cxd2820r_rd_regs(priv, 0x00026, buf, sizeof(buf));
303 tmp = (buf[0] & 0x0f) << 8 | buf[1];
306 /* scale value to 0x0000-0xffff from 0x0000-0x0fff */
307 *strength = tmp * 0xffff / 0x0fff;
311 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
315 int cxd2820r_read_snr_t(struct dvb_frontend *fe, u16 *snr)
317 struct cxd2820r_priv *priv = fe->demodulator_priv;
321 /* report SNR in dB * 10 */
323 ret = cxd2820r_rd_regs(priv, 0x00028, buf, sizeof(buf));
327 tmp = (buf[0] & 0x1f) << 8 | buf[1];
328 #define CXD2820R_LOG10_8_24 15151336 /* log10(8) << 24 */
330 *snr = (intlog10(tmp) - CXD2820R_LOG10_8_24) / ((1 << 24)
335 dev_dbg(&priv->i2c->dev, "%s: dBx10=%d val=%04x\n", __func__, *snr,
340 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
344 int cxd2820r_read_ucblocks_t(struct dvb_frontend *fe, u32 *ucblocks)
347 /* no way to read ? */
351 int cxd2820r_read_status_t(struct dvb_frontend *fe, fe_status_t *status)
353 struct cxd2820r_priv *priv = fe->demodulator_priv;
358 ret = cxd2820r_rd_reg(priv, 0x00010, &buf[0]);
362 if ((buf[0] & 0x07) == 6) {
363 ret = cxd2820r_rd_reg(priv, 0x00073, &buf[1]);
367 if (((buf[1] >> 3) & 0x01) == 1) {
368 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
369 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
371 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
372 FE_HAS_VITERBI | FE_HAS_SYNC;
375 ret = cxd2820r_rd_reg(priv, 0x00014, &buf[2]);
379 if ((buf[2] & 0x0f) >= 4) {
380 ret = cxd2820r_rd_reg(priv, 0x00a14, &buf[3]);
384 if (((buf[3] >> 4) & 0x01) == 1)
385 *status |= FE_HAS_SIGNAL;
389 dev_dbg(&priv->i2c->dev, "%s: lock=%*ph\n", __func__, 4, buf);
393 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
397 int cxd2820r_init_t(struct dvb_frontend *fe)
399 struct cxd2820r_priv *priv = fe->demodulator_priv;
402 ret = cxd2820r_wr_reg(priv, 0x00085, 0x07);
408 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
412 int cxd2820r_sleep_t(struct dvb_frontend *fe)
414 struct cxd2820r_priv *priv = fe->demodulator_priv;
416 struct reg_val_mask tab[] = {
417 { 0x000ff, 0x1f, 0xff },
418 { 0x00085, 0x00, 0xff },
419 { 0x00088, 0x01, 0xff },
420 { 0x00081, 0x00, 0xff },
421 { 0x00080, 0x00, 0xff },
424 dev_dbg(&priv->i2c->dev, "%s\n", __func__);
426 priv->delivery_system = SYS_UNDEFINED;
428 for (i = 0; i < ARRAY_SIZE(tab); i++) {
429 ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, tab[i].val,
437 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
441 int cxd2820r_get_tune_settings_t(struct dvb_frontend *fe,
442 struct dvb_frontend_tune_settings *s)
444 s->min_delay_ms = 500;
445 s->step_size = fe->ops.info.frequency_stepsize * 2;
446 s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;