drivers/media/dvb/frontends/lgdt3305.c

   1 /*
   2  *    Support for LG Electronics LGDT3304 and LGDT3305 - VSB/QAM
   3  *
   4  *    Copyright (C) 2008, 2009 Michael Krufky <mkrufky@linuxtv.org>
   5  *
   6  *    This program is free software; you can redistribute it and/or modify
   7  *    it under the terms of the GNU General Public License as published by
   8  *    the Free Software Foundation; either version 2 of the License, or
   9  *    (at your option) any later version.
  10  *
  11  *    This program is distributed in the hope that it will be useful,
  12  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *    GNU General Public License for more details.
  15  *
  16  *    You should have received a copy of the GNU General Public License
  17  *    along with this program; if not, write to the Free Software
  18  *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  *
  20  */
  21
  22 #include <asm/div64.h>
  23 #include <linux/dvb/frontend.h>
  24 #include <linux/slab.h>
  25 #include "dvb_math.h"
  26 #include "lgdt3305.h"
  27
  28 static int debug;
  29 module_param(debug, int, 0644);
  30 MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
  31
  32 #define DBG_INFO 1
  33 #define DBG_REG  2
  34
  35 #define lg_printk(kern, fmt, arg...)                                    \
  36         printk(kern "%s: " fmt, __func__, ##arg)
  37
  38 #define lg_info(fmt, arg...)    printk(KERN_INFO "lgdt3305: " fmt, ##arg)
  39 #define lg_warn(fmt, arg...)    lg_printk(KERN_WARNING,       fmt, ##arg)
  40 #define lg_err(fmt, arg...)     lg_printk(KERN_ERR,           fmt, ##arg)
  41 #define lg_dbg(fmt, arg...) if (debug & DBG_INFO)                       \
  42                                 lg_printk(KERN_DEBUG,         fmt, ##arg)
  43 #define lg_reg(fmt, arg...) if (debug & DBG_REG)                        \
  44                                 lg_printk(KERN_DEBUG,         fmt, ##arg)
  45
  46 #define lg_fail(ret)                                                    \
  47 ({                                                                      \
  48         int __ret;                                                      \
  49         __ret = (ret < 0);                                              \
  50         if (__ret)                                                      \
  51                 lg_err("error %d on line %d\n", ret, __LINE__);         \
  52         __ret;                                                          \
  53 })
  54
  55 struct lgdt3305_state {
  56         struct i2c_adapter *i2c_adap;
  57         const struct lgdt3305_config *cfg;
  58
  59         struct dvb_frontend frontend;
  60
  61         fe_modulation_t current_modulation;
  62         u32 current_frequency;
  63         u32 snr;
  64 };
  65
  66 /* ------------------------------------------------------------------------ */
  67
  68 /* FIXME: verify & document the LGDT3304 registers */
  69
  70 #define LGDT3305_GEN_CTRL_1                   0x0000
  71 #define LGDT3305_GEN_CTRL_2                   0x0001
  72 #define LGDT3305_GEN_CTRL_3                   0x0002
  73 #define LGDT3305_GEN_STATUS                   0x0003
  74 #define LGDT3305_GEN_CONTROL                  0x0007
  75 #define LGDT3305_GEN_CTRL_4                   0x000a
  76 #define LGDT3305_DGTL_AGC_REF_1               0x0012
  77 #define LGDT3305_DGTL_AGC_REF_2               0x0013
  78 #define LGDT3305_CR_CTR_FREQ_1                0x0106
  79 #define LGDT3305_CR_CTR_FREQ_2                0x0107
  80 #define LGDT3305_CR_CTR_FREQ_3                0x0108
  81 #define LGDT3305_CR_CTR_FREQ_4                0x0109
  82 #define LGDT3305_CR_MSE_1                     0x011b
  83 #define LGDT3305_CR_MSE_2                     0x011c
  84 #define LGDT3305_CR_LOCK_STATUS               0x011d
  85 #define LGDT3305_CR_CTRL_7                    0x0126
  86 #define LGDT3305_AGC_POWER_REF_1              0x0300
  87 #define LGDT3305_AGC_POWER_REF_2              0x0301
  88 #define LGDT3305_AGC_DELAY_PT_1               0x0302
  89 #define LGDT3305_AGC_DELAY_PT_2               0x0303
  90 #define LGDT3305_RFAGC_LOOP_FLTR_BW_1         0x0306
  91 #define LGDT3305_RFAGC_LOOP_FLTR_BW_2         0x0307
  92 #define LGDT3305_IFBW_1                       0x0308
  93 #define LGDT3305_IFBW_2                       0x0309
  94 #define LGDT3305_AGC_CTRL_1                   0x030c
  95 #define LGDT3305_AGC_CTRL_4                   0x0314
  96 #define LGDT3305_EQ_MSE_1                     0x0413
  97 #define LGDT3305_EQ_MSE_2                     0x0414
  98 #define LGDT3305_EQ_MSE_3                     0x0415
  99 #define LGDT3305_PT_MSE_1                     0x0417
 100 #define LGDT3305_PT_MSE_2                     0x0418
 101 #define LGDT3305_PT_MSE_3                     0x0419
 102 #define LGDT3305_FEC_BLOCK_CTRL               0x0504
 103 #define LGDT3305_FEC_LOCK_STATUS              0x050a
 104 #define LGDT3305_FEC_PKT_ERR_1                0x050c
 105 #define LGDT3305_FEC_PKT_ERR_2                0x050d
 106 #define LGDT3305_TP_CTRL_1                    0x050e
 107 #define LGDT3305_BERT_PERIOD                  0x0801
 108 #define LGDT3305_BERT_ERROR_COUNT_1           0x080a
 109 #define LGDT3305_BERT_ERROR_COUNT_2           0x080b
 110 #define LGDT3305_BERT_ERROR_COUNT_3           0x080c
 111 #define LGDT3305_BERT_ERROR_COUNT_4           0x080d
 112
 113 static int lgdt3305_write_reg(struct lgdt3305_state *state, u16 reg, u8 val)
 114 {
 115         int ret;
 116         u8 buf[] = { reg >> 8, reg & 0xff, val };
 117         struct i2c_msg msg = {
 118                 .addr = state->cfg->i2c_addr, .flags = 0,
 119                 .buf = buf, .len = 3,
 120         };
 121
 122         lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
 123
 124         ret = i2c_transfer(state->i2c_adap, &msg, 1);
 125
 126         if (ret != 1) {
 127                 lg_err("error (addr %02x %02x <- %02x, err = %i)\n",
 128                        msg.buf[0], msg.buf[1], msg.buf[2], ret);
 129                 if (ret < 0)
 130                         return ret;
 131                 else
 132                         return -EREMOTEIO;
 133         }
 134         return 0;
 135 }
 136
 137 static int lgdt3305_read_reg(struct lgdt3305_state *state, u16 reg, u8 *val)
 138 {
 139         int ret;
 140         u8 reg_buf[] = { reg >> 8, reg & 0xff };
 141         struct i2c_msg msg[] = {
 142                 { .addr = state->cfg->i2c_addr,
 143                   .flags = 0, .buf = reg_buf, .len = 2 },
 144                 { .addr = state->cfg->i2c_addr,
 145                   .flags = I2C_M_RD, .buf = val, .len = 1 },
 146         };
 147
 148         lg_reg("reg: 0x%04x\n", reg);
 149
 150         ret = i2c_transfer(state->i2c_adap, msg, 2);
 151
 152         if (ret != 2) {
 153                 lg_err("error (addr %02x reg %04x error (ret == %i)\n",
 154                        state->cfg->i2c_addr, reg, ret);
 155                 if (ret < 0)
 156                         return ret;
 157                 else
 158                         return -EREMOTEIO;
 159         }
 160         return 0;
 161 }
 162
 163 #define read_reg(state, reg)                                            \
 164 ({                                                                      \
 165         u8 __val;                                                       \
 166         int ret = lgdt3305_read_reg(state, reg, &__val);                \
 167         if (lg_fail(ret))                                               \
 168                 __val = 0;                                              \
 169         __val;                                                          \
 170 })
 171
 172 static int lgdt3305_set_reg_bit(struct lgdt3305_state *state,
 173                                 u16 reg, int bit, int onoff)
 174 {
 175         u8 val;
 176         int ret;
 177
 178         lg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
 179
 180         ret = lgdt3305_read_reg(state, reg, &val);
 181         if (lg_fail(ret))
 182                 goto fail;
 183
 184         val &= ~(1 << bit);
 185         val |= (onoff & 1) << bit;
 186
 187         ret = lgdt3305_write_reg(state, reg, val);
 188 fail:
 189         return ret;
 190 }
 191
 192 struct lgdt3305_reg {
 193         u16 reg;
 194         u8 val;
 195 };
 196
 197 static int lgdt3305_write_regs(struct lgdt3305_state *state,
 198                                struct lgdt3305_reg *regs, int len)
 199 {
 200         int i, ret;
 201
 202         lg_reg("writing %d registers...\n", len);
 203
 204         for (i = 0; i < len - 1; i++) {
 205                 ret = lgdt3305_write_reg(state, regs[i].reg, regs[i].val);
 206                 if (lg_fail(ret))
 207                         return ret;
 208         }
 209         return 0;
 210 }
 211
 212 /* ------------------------------------------------------------------------ */
 213
 214 static int lgdt3305_soft_reset(struct lgdt3305_state *state)
 215 {
 216         int ret;
 217
 218         lg_dbg("\n");
 219
 220         ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 0);
 221         if (lg_fail(ret))
 222                 goto fail;
 223
 224         msleep(20);
 225         ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 1);
 226 fail:
 227         return ret;
 228 }
 229
 230 static inline int lgdt3305_mpeg_mode(struct lgdt3305_state *state,
 231                                      enum lgdt3305_mpeg_mode mode)
 232 {
 233         lg_dbg("(%d)\n", mode);
 234         return lgdt3305_set_reg_bit(state, LGDT3305_TP_CTRL_1, 5, mode);
 235 }
 236
 237 static int lgdt3305_mpeg_mode_polarity(struct lgdt3305_state *state,
 238                                        enum lgdt3305_tp_clock_edge edge,
 239                                        enum lgdt3305_tp_valid_polarity valid)
 240 {
 241         u8 val;
 242         int ret;
 243
 244         lg_dbg("edge = %d, valid = %d\n", edge, valid);
 245
 246         ret = lgdt3305_read_reg(state, LGDT3305_TP_CTRL_1, &val);
 247         if (lg_fail(ret))
 248                 goto fail;
 249
 250         val &= ~0x09;
 251
 252         if (edge)
 253                 val |= 0x08;
 254         if (valid)
 255                 val |= 0x01;
 256
 257         ret = lgdt3305_write_reg(state, LGDT3305_TP_CTRL_1, val);
 258         if (lg_fail(ret))
 259                 goto fail;
 260
 261         ret = lgdt3305_soft_reset(state);
 262 fail:
 263         return ret;
 264 }
 265
 266 static int lgdt3305_set_modulation(struct lgdt3305_state *state,
 267                                    struct dvb_frontend_parameters *param)
 268 {
 269         u8 opermode;
 270         int ret;
 271
 272         lg_dbg("\n");
 273
 274         ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_1, &opermode);
 275         if (lg_fail(ret))
 276                 goto fail;
 277
 278         opermode &= ~0x03;
 279
 280         switch (param->u.vsb.modulation) {
 281         case VSB_8:
 282                 opermode |= 0x03;
 283                 break;
 284         case QAM_64:
 285                 opermode |= 0x00;
 286                 break;
 287         case QAM_256:
 288                 opermode |= 0x01;
 289                 break;
 290         default:
 291                 return -EINVAL;
 292         }
 293         ret = lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_1, opermode);
 294 fail:
 295         return ret;
 296 }
 297
 298 static int lgdt3305_set_filter_extension(struct lgdt3305_state *state,
 299                                          struct dvb_frontend_parameters *param)
 300 {
 301         int val;
 302
 303         switch (param->u.vsb.modulation) {
 304         case VSB_8:
 305                 val = 0;
 306                 break;
 307         case QAM_64:
 308         case QAM_256:
 309                 val = 1;
 310                 break;
 311         default:
 312                 return -EINVAL;
 313         }
 314         lg_dbg("val = %d\n", val);
 315
 316         return lgdt3305_set_reg_bit(state, 0x043f, 2, val);
 317 }
 318
 319 /* ------------------------------------------------------------------------ */
 320
 321 static int lgdt3305_passband_digital_agc(struct lgdt3305_state *state,
 322                                          struct dvb_frontend_parameters *param)
 323 {
 324         u16 agc_ref;
 325
 326         switch (param->u.vsb.modulation) {
 327         case VSB_8:
 328                 agc_ref = 0x32c4;
 329                 break;
 330         case QAM_64:
 331                 agc_ref = 0x2a00;
 332                 break;
 333         case QAM_256:
 334                 agc_ref = 0x2a80;
 335                 break;
 336         default:
 337                 return -EINVAL;
 338         }
 339
 340         lg_dbg("agc ref: 0x%04x\n", agc_ref);
 341
 342         lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_1, agc_ref >> 8);
 343         lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_2, agc_ref & 0xff);
 344
 345         return 0;
 346 }
 347
 348 static int lgdt3305_rfagc_loop(struct lgdt3305_state *state,
 349                                struct dvb_frontend_parameters *param)
 350 {
 351         u16 ifbw, rfbw, agcdelay;
 352
 353         switch (param->u.vsb.modulation) {
 354         case VSB_8:
 355                 agcdelay = 0x04c0;
 356                 rfbw     = 0x8000;
 357                 ifbw     = 0x8000;
 358                 break;
 359         case QAM_64:
 360         case QAM_256:
 361                 agcdelay = 0x046b;
 362                 rfbw     = 0x8889;
 363                 /* FIXME: investigate optimal ifbw & rfbw values for the
 364                  *        DT3304 and re-write this switch..case block */
 365                 if (state->cfg->demod_chip == LGDT3304)
 366                         ifbw = 0x6666;
 367                 else /* (state->cfg->demod_chip == LGDT3305) */
 368                         ifbw = 0x8888;
 369                 break;
 370         default:
 371                 return -EINVAL;
 372         }
 373
 374         if (state->cfg->rf_agc_loop) {
 375                 lg_dbg("agcdelay: 0x%04x, rfbw: 0x%04x\n", agcdelay, rfbw);
 376
 377                 /* rf agc loop filter bandwidth */
 378                 lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_1,
 379                                    agcdelay >> 8);
 380                 lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_2,
 381                                    agcdelay & 0xff);
 382
 383                 lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_1,
 384                                    rfbw >> 8);
 385                 lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_2,
 386                                    rfbw & 0xff);
 387         } else {
 388                 lg_dbg("ifbw: 0x%04x\n", ifbw);
 389
 390                 /* if agc loop filter bandwidth */
 391                 lgdt3305_write_reg(state, LGDT3305_IFBW_1, ifbw >> 8);
 392                 lgdt3305_write_reg(state, LGDT3305_IFBW_2, ifbw & 0xff);
 393         }
 394
 395         return 0;
 396 }
 397
 398 static int lgdt3305_agc_setup(struct lgdt3305_state *state,
 399                               struct dvb_frontend_parameters *param)
 400 {
 401         int lockdten, acqen;
 402
 403         switch (param->u.vsb.modulation) {
 404         case VSB_8:
 405                 lockdten = 0;
 406                 acqen = 0;
 407                 break;
 408         case QAM_64:
 409         case QAM_256:
 410                 lockdten = 1;
 411                 acqen = 1;
 412                 break;
 413         default:
 414                 return -EINVAL;
 415         }
 416
 417         lg_dbg("lockdten = %d, acqen = %d\n", lockdten, acqen);
 418
 419         /* control agc function */
 420         switch (state->cfg->demod_chip) {
 421         case LGDT3304:
 422                 lgdt3305_write_reg(state, 0x0314, 0xe1 | lockdten << 1);
 423                 lgdt3305_set_reg_bit(state, 0x030e, 2, acqen);
 424                 break;
 425         case LGDT3305:
 426                 lgdt3305_write_reg(state, LGDT3305_AGC_CTRL_4, 0xe1 | lockdten << 1);
 427                 lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 2, acqen);
 428                 break;
 429         default:
 430                 return -EINVAL;
 431         }
 432
 433         return lgdt3305_rfagc_loop(state, param);
 434 }
 435
 436 static int lgdt3305_set_agc_power_ref(struct lgdt3305_state *state,
 437                                       struct dvb_frontend_parameters *param)
 438 {
 439         u16 usref = 0;
 440
 441         switch (param->u.vsb.modulation) {
 442         case VSB_8:
 443                 if (state->cfg->usref_8vsb)
 444                         usref = state->cfg->usref_8vsb;
 445                 break;
 446         case QAM_64:
 447                 if (state->cfg->usref_qam64)
 448                         usref = state->cfg->usref_qam64;
 449                 break;
 450         case QAM_256:
 451                 if (state->cfg->usref_qam256)
 452                         usref = state->cfg->usref_qam256;
 453                 break;
 454         default:
 455                 return -EINVAL;
 456         }
 457
 458         if (usref) {
 459                 lg_dbg("set manual mode: 0x%04x\n", usref);
 460
 461                 lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 3, 1);
 462
 463                 lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_1,
 464                                    0xff & (usref >> 8));
 465                 lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_2,
 466                                    0xff & (usref >> 0));
 467         }
 468         return 0;
 469 }
 470
 471 /* ------------------------------------------------------------------------ */
 472
 473 static int lgdt3305_spectral_inversion(struct lgdt3305_state *state,
 474                                        struct dvb_frontend_parameters *param,
 475                                        int inversion)
 476 {
 477         int ret;
 478
 479         lg_dbg("(%d)\n", inversion);
 480
 481         switch (param->u.vsb.modulation) {
 482         case VSB_8:
 483                 ret = lgdt3305_write_reg(state, LGDT3305_CR_CTRL_7,
 484                                          inversion ? 0xf9 : 0x79);
 485                 break;
 486         case QAM_64:
 487         case QAM_256:
 488                 ret = lgdt3305_write_reg(state, LGDT3305_FEC_BLOCK_CTRL,
 489                                          inversion ? 0xfd : 0xff);
 490                 break;
 491         default:
 492                 ret = -EINVAL;
 493         }
 494         return ret;
 495 }
 496
 497 static int lgdt3305_set_if(struct lgdt3305_state *state,
 498                            struct dvb_frontend_parameters *param)
 499 {
 500         u16 if_freq_khz;
 501         u8 nco1, nco2, nco3, nco4;
 502         u64 nco;
 503
 504         switch (param->u.vsb.modulation) {
 505         case VSB_8:
 506                 if_freq_khz = state->cfg->vsb_if_khz;
 507                 break;
 508         case QAM_64:
 509         case QAM_256:
 510                 if_freq_khz = state->cfg->qam_if_khz;
 511                 break;
 512         default:
 513                 return -EINVAL;
 514         }
 515
 516         nco = if_freq_khz / 10;
 517
 518         switch (param->u.vsb.modulation) {
 519         case VSB_8:
 520                 nco <<= 24;
 521                 do_div(nco, 625);
 522                 break;
 523         case QAM_64:
 524         case QAM_256:
 525                 nco <<= 28;
 526                 do_div(nco, 625);
 527                 break;
 528         default:
 529                 return -EINVAL;
 530         }
 531
 532         nco1 = (nco >> 24) & 0x3f;
 533         nco1 |= 0x40;
 534         nco2 = (nco >> 16) & 0xff;
 535         nco3 = (nco >> 8) & 0xff;
 536         nco4 = nco & 0xff;
 537
 538         lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, nco1);
 539         lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, nco2);
 540         lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, nco3);
 541         lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, nco4);
 542
 543         lg_dbg("%d KHz -> [%02x%02x%02x%02x]\n",
 544                if_freq_khz, nco1, nco2, nco3, nco4);
 545
 546         return 0;
 547 }
 548
 549 /* ------------------------------------------------------------------------ */
 550
 551 static int lgdt3305_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 552 {
 553         struct lgdt3305_state *state = fe->demodulator_priv;
 554
 555         if (state->cfg->deny_i2c_rptr)
 556                 return 0;
 557
 558         lg_dbg("(%d)\n", enable);
 559
 560         return lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_2, 5,
 561                                     enable ? 0 : 1);
 562 }
 563
 564 static int lgdt3305_sleep(struct dvb_frontend *fe)
 565 {
 566         struct lgdt3305_state *state = fe->demodulator_priv;
 567         u8 gen_ctrl_3, gen_ctrl_4;
 568
 569         lg_dbg("\n");
 570
 571         gen_ctrl_3 = read_reg(state, LGDT3305_GEN_CTRL_3);
 572         gen_ctrl_4 = read_reg(state, LGDT3305_GEN_CTRL_4);
 573
 574         /* hold in software reset while sleeping */
 575         gen_ctrl_3 &= ~0x01;
 576         /* tristate the IF-AGC pin */
 577         gen_ctrl_3 |=  0x02;
 578         /* tristate the RF-AGC pin */
 579         gen_ctrl_3 |=  0x04;
 580
 581         /* disable vsb/qam module */
 582         gen_ctrl_4 &= ~0x01;
 583         /* disable adc module */
 584         gen_ctrl_4 &= ~0x02;
 585
 586         lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_3, gen_ctrl_3);
 587         lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_4, gen_ctrl_4);
 588
 589         return 0;
 590 }
 591
 592 static int lgdt3305_init(struct dvb_frontend *fe)
 593 {
 594         struct lgdt3305_state *state = fe->demodulator_priv;
 595         int ret;
 596
 597         static struct lgdt3305_reg lgdt3304_init_data[] = {
 598                 { .reg = LGDT3305_GEN_CTRL_1,           .val = 0x03, },
 599                 { .reg = 0x000d,                        .val = 0x02, },
 600                 { .reg = 0x000e,                        .val = 0x02, },
 601                 { .reg = LGDT3305_DGTL_AGC_REF_1,       .val = 0x32, },
 602                 { .reg = LGDT3305_DGTL_AGC_REF_2,       .val = 0xc4, },
 603                 { .reg = LGDT3305_CR_CTR_FREQ_1,        .val = 0x00, },
 604                 { .reg = LGDT3305_CR_CTR_FREQ_2,        .val = 0x00, },
 605                 { .reg = LGDT3305_CR_CTR_FREQ_3,        .val = 0x00, },
 606                 { .reg = LGDT3305_CR_CTR_FREQ_4,        .val = 0x00, },
 607                 { .reg = LGDT3305_CR_CTRL_7,            .val = 0xf9, },
 608                 { .reg = 0x0112,                        .val = 0x17, },
 609                 { .reg = 0x0113,                        .val = 0x15, },
 610                 { .reg = 0x0114,                        .val = 0x18, },
 611                 { .reg = 0x0115,                        .val = 0xff, },
 612                 { .reg = 0x0116,                        .val = 0x3c, },
 613                 { .reg = 0x0214,                        .val = 0x67, },
 614                 { .reg = 0x0424,                        .val = 0x8d, },
 615                 { .reg = 0x0427,                        .val = 0x12, },
 616                 { .reg = 0x0428,                        .val = 0x4f, },
 617                 { .reg = LGDT3305_IFBW_1,               .val = 0x80, },
 618                 { .reg = LGDT3305_IFBW_2,               .val = 0x00, },
 619                 { .reg = 0x030a,                        .val = 0x08, },
 620                 { .reg = 0x030b,                        .val = 0x9b, },
 621                 { .reg = 0x030d,                        .val = 0x00, },
 622                 { .reg = 0x030e,                        .val = 0x1c, },
 623                 { .reg = 0x0314,                        .val = 0xe1, },
 624                 { .reg = 0x000d,                        .val = 0x82, },
 625                 { .reg = LGDT3305_TP_CTRL_1,            .val = 0x5b, },
 626                 { .reg = LGDT3305_TP_CTRL_1,            .val = 0x5b, },
 627         };
 628
 629         static struct lgdt3305_reg lgdt3305_init_data[] = {
 630                 { .reg = LGDT3305_GEN_CTRL_1,           .val = 0x03, },
 631                 { .reg = LGDT3305_GEN_CTRL_2,           .val = 0xb0, },
 632                 { .reg = LGDT3305_GEN_CTRL_3,           .val = 0x01, },
 633                 { .reg = LGDT3305_GEN_CONTROL,          .val = 0x6f, },
 634                 { .reg = LGDT3305_GEN_CTRL_4,           .val = 0x03, },
 635                 { .reg = LGDT3305_DGTL_AGC_REF_1,       .val = 0x32, },
 636                 { .reg = LGDT3305_DGTL_AGC_REF_2,       .val = 0xc4, },
 637                 { .reg = LGDT3305_CR_CTR_FREQ_1,        .val = 0x00, },
 638                 { .reg = LGDT3305_CR_CTR_FREQ_2,        .val = 0x00, },
 639                 { .reg = LGDT3305_CR_CTR_FREQ_3,        .val = 0x00, },
 640                 { .reg = LGDT3305_CR_CTR_FREQ_4,        .val = 0x00, },
 641                 { .reg = LGDT3305_CR_CTRL_7,            .val = 0x79, },
 642                 { .reg = LGDT3305_AGC_POWER_REF_1,      .val = 0x32, },
 643                 { .reg = LGDT3305_AGC_POWER_REF_2,      .val = 0xc4, },
 644                 { .reg = LGDT3305_AGC_DELAY_PT_1,       .val = 0x0d, },
 645                 { .reg = LGDT3305_AGC_DELAY_PT_2,       .val = 0x30, },
 646                 { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_1, .val = 0x80, },
 647                 { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_2, .val = 0x00, },
 648                 { .reg = LGDT3305_IFBW_1,               .val = 0x80, },
 649                 { .reg = LGDT3305_IFBW_2,               .val = 0x00, },
 650                 { .reg = LGDT3305_AGC_CTRL_1,           .val = 0x30, },
 651                 { .reg = LGDT3305_AGC_CTRL_4,           .val = 0x61, },
 652                 { .reg = LGDT3305_FEC_BLOCK_CTRL,       .val = 0xff, },
 653                 { .reg = LGDT3305_TP_CTRL_1,            .val = 0x1b, },
 654         };
 655
 656         lg_dbg("\n");
 657
 658         switch (state->cfg->demod_chip) {
 659         case LGDT3304:
 660                 ret = lgdt3305_write_regs(state, lgdt3304_init_data,
 661                                           ARRAY_SIZE(lgdt3304_init_data));
 662                 break;
 663         case LGDT3305:
 664                 ret = lgdt3305_write_regs(state, lgdt3305_init_data,
 665                                           ARRAY_SIZE(lgdt3305_init_data));
 666                 break;
 667         default:
 668                 ret = -EINVAL;
 669         }
 670         if (lg_fail(ret))
 671                 goto fail;
 672
 673         ret = lgdt3305_soft_reset(state);
 674 fail:
 675         return ret;
 676 }
 677
 678 static int lgdt3304_set_parameters(struct dvb_frontend *fe,
 679                                    struct dvb_frontend_parameters *param)
 680 {
 681         struct lgdt3305_state *state = fe->demodulator_priv;
 682         int ret;
 683
 684         lg_dbg("(%d, %d)\n", param->frequency, param->u.vsb.modulation);
 685
 686         if (fe->ops.tuner_ops.set_params) {
 687                 ret = fe->ops.tuner_ops.set_params(fe, param);
 688                 if (fe->ops.i2c_gate_ctrl)
 689                         fe->ops.i2c_gate_ctrl(fe, 0);
 690                 if (lg_fail(ret))
 691                         goto fail;
 692                 state->current_frequency = param->frequency;
 693         }
 694
 695         ret = lgdt3305_set_modulation(state, param);
 696         if (lg_fail(ret))
 697                 goto fail;
 698
 699         ret = lgdt3305_passband_digital_agc(state, param);
 700         if (lg_fail(ret))
 701                 goto fail;
 702
 703         ret = lgdt3305_agc_setup(state, param);
 704         if (lg_fail(ret))
 705                 goto fail;
 706
 707         /* reg 0x030d is 3304-only... seen in vsb and qam usbsnoops... */
 708         switch (param->u.vsb.modulation) {
 709         case VSB_8:
 710                 lgdt3305_write_reg(state, 0x030d, 0x00);
 711                 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, 0x4f);
 712                 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, 0x0c);
 713                 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, 0xac);
 714                 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, 0xba);
 715                 break;
 716         case QAM_64:
 717         case QAM_256:
 718                 lgdt3305_write_reg(state, 0x030d, 0x14);
 719                 ret = lgdt3305_set_if(state, param);
 720                 if (lg_fail(ret))
 721                         goto fail;
 722                 break;
 723         default:
 724                 return -EINVAL;
 725         }
 726
 727
 728         ret = lgdt3305_spectral_inversion(state, param,
 729                                           state->cfg->spectral_inversion
 730                                           ? 1 : 0);
 731         if (lg_fail(ret))
 732                 goto fail;
 733
 734         state->current_modulation = param->u.vsb.modulation;
 735
 736         ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode);
 737         if (lg_fail(ret))
 738                 goto fail;
 739
 740         /* lgdt3305_mpeg_mode_polarity calls lgdt3305_soft_reset */
 741         ret = lgdt3305_mpeg_mode_polarity(state,
 742                                           state->cfg->tpclk_edge,
 743                                           state->cfg->tpvalid_polarity);
 744 fail:
 745         return ret;
 746 }
 747
 748 static int lgdt3305_set_parameters(struct dvb_frontend *fe,
 749                                    struct dvb_frontend_parameters *param)
 750 {
 751         struct lgdt3305_state *state = fe->demodulator_priv;
 752         int ret;
 753
 754         lg_dbg("(%d, %d)\n", param->frequency, param->u.vsb.modulation);
 755
 756         if (fe->ops.tuner_ops.set_params) {
 757                 ret = fe->ops.tuner_ops.set_params(fe, param);
 758                 if (fe->ops.i2c_gate_ctrl)
 759                         fe->ops.i2c_gate_ctrl(fe, 0);
 760                 if (lg_fail(ret))
 761                         goto fail;
 762                 state->current_frequency = param->frequency;
 763         }
 764
 765         ret = lgdt3305_set_modulation(state, param);
 766         if (lg_fail(ret))
 767                 goto fail;
 768
 769         ret = lgdt3305_passband_digital_agc(state, param);
 770         if (lg_fail(ret))
 771                 goto fail;
 772         ret = lgdt3305_set_agc_power_ref(state, param);
 773         if (lg_fail(ret))
 774                 goto fail;
 775         ret = lgdt3305_agc_setup(state, param);
 776         if (lg_fail(ret))
 777                 goto fail;
 778
 779         /* low if */
 780         ret = lgdt3305_write_reg(state, LGDT3305_GEN_CONTROL, 0x2f);
 781         if (lg_fail(ret))
 782                 goto fail;
 783         ret = lgdt3305_set_reg_bit(state, LGDT3305_CR_CTR_FREQ_1, 6, 1);
 784         if (lg_fail(ret))
 785                 goto fail;
 786
 787         ret = lgdt3305_set_if(state, param);
 788         if (lg_fail(ret))
 789                 goto fail;
 790         ret = lgdt3305_spectral_inversion(state, param,
 791                                           state->cfg->spectral_inversion
 792                                           ? 1 : 0);
 793         if (lg_fail(ret))
 794                 goto fail;
 795
 796         ret = lgdt3305_set_filter_extension(state, param);
 797         if (lg_fail(ret))
 798                 goto fail;
 799
 800         state->current_modulation = param->u.vsb.modulation;
 801
 802         ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode);
 803         if (lg_fail(ret))
 804                 goto fail;
 805
 806         /* lgdt3305_mpeg_mode_polarity calls lgdt3305_soft_reset */
 807         ret = lgdt3305_mpeg_mode_polarity(state,
 808                                           state->cfg->tpclk_edge,
 809                                           state->cfg->tpvalid_polarity);
 810 fail:
 811         return ret;
 812 }
 813
 814 static int lgdt3305_get_frontend(struct dvb_frontend *fe,
 815                                  struct dvb_frontend_parameters *param)
 816 {
 817         struct lgdt3305_state *state = fe->demodulator_priv;
 818
 819         lg_dbg("\n");
 820
 821         param->u.vsb.modulation = state->current_modulation;
 822         param->frequency = state->current_frequency;
 823         return 0;
 824 }
 825
 826 /* ------------------------------------------------------------------------ */
 827
 828 static int lgdt3305_read_cr_lock_status(struct lgdt3305_state *state,
 829                                         int *locked)
 830 {
 831         u8 val;
 832         int ret;
 833         char *cr_lock_state = "";
 834
 835         *locked = 0;
 836
 837         ret = lgdt3305_read_reg(state, LGDT3305_CR_LOCK_STATUS, &val);
 838         if (lg_fail(ret))
 839                 goto fail;
 840
 841         switch (state->current_modulation) {
 842         case QAM_256:
 843         case QAM_64:
 844                 if (val & (1 << 1))
 845                         *locked = 1;
 846
 847                 switch (val & 0x07) {
 848                 case 0:
 849                         cr_lock_state = "QAM UNLOCK";
 850                         break;
 851                 case 4:
 852                         cr_lock_state = "QAM 1stLock";
 853                         break;
 854                 case 6:
 855                         cr_lock_state = "QAM 2ndLock";
 856                         break;
 857                 case 7:
 858                         cr_lock_state = "QAM FinalLock";
 859                         break;
 860                 default:
 861                         cr_lock_state = "CLOCKQAM-INVALID!";
 862                         break;
 863                 }
 864                 break;
 865         case VSB_8:
 866                 if (val & (1 << 7)) {
 867                         *locked = 1;
 868                         cr_lock_state = "CLOCKVSB";
 869                 }
 870                 break;
 871         default:
 872                 ret = -EINVAL;
 873         }
 874         lg_dbg("(%d) %s\n", *locked, cr_lock_state);
 875 fail:
 876         return ret;
 877 }
 878
 879 static int lgdt3305_read_fec_lock_status(struct lgdt3305_state *state,
 880                                          int *locked)
 881 {
 882         u8 val;
 883         int ret, mpeg_lock, fec_lock, viterbi_lock;
 884
 885         *locked = 0;
 886
 887         switch (state->current_modulation) {
 888         case QAM_256:
 889         case QAM_64:
 890                 ret = lgdt3305_read_reg(state,
 891                                         LGDT3305_FEC_LOCK_STATUS, &val);
 892                 if (lg_fail(ret))
 893                         goto fail;
 894
 895                 mpeg_lock    = (val & (1 << 0)) ? 1 : 0;
 896                 fec_lock     = (val & (1 << 2)) ? 1 : 0;
 897                 viterbi_lock = (val & (1 << 3)) ? 1 : 0;
 898
 899                 *locked = mpeg_lock && fec_lock && viterbi_lock;
 900
 901                 lg_dbg("(%d) %s%s%s\n", *locked,
 902                        mpeg_lock    ? "mpeg lock  "  : "",
 903                        fec_lock     ? "fec lock  "   : "",
 904                        viterbi_lock ? "viterbi lock" : "");
 905                 break;
 906         case VSB_8:
 907         default:
 908                 ret = -EINVAL;
 909         }
 910 fail:
 911         return ret;
 912 }
 913
 914 static int lgdt3305_read_status(struct dvb_frontend *fe, fe_status_t *status)
 915 {
 916         struct lgdt3305_state *state = fe->demodulator_priv;
 917         u8 val;
 918         int ret, signal, inlock, nofecerr, snrgood,
 919                 cr_lock, fec_lock, sync_lock;
 920
 921         *status = 0;
 922
 923         ret = lgdt3305_read_reg(state, LGDT3305_GEN_STATUS, &val);
 924         if (lg_fail(ret))
 925                 goto fail;
 926
 927         signal    = (val & (1 << 4)) ? 1 : 0;
 928         inlock    = (val & (1 << 3)) ? 0 : 1;
 929         sync_lock = (val & (1 << 2)) ? 1 : 0;
 930         nofecerr  = (val & (1 << 1)) ? 1 : 0;
 931         snrgood   = (val & (1 << 0)) ? 1 : 0;
 932
 933         lg_dbg("%s%s%s%s%s\n",
 934                signal    ? "SIGNALEXIST " : "",
 935                inlock    ? "INLOCK "      : "",
 936                sync_lock ? "SYNCLOCK "    : "",
 937                nofecerr  ? "NOFECERR "    : "",
 938                snrgood   ? "SNRGOOD "     : "");
 939
 940         ret = lgdt3305_read_cr_lock_status(state, &cr_lock);
 941         if (lg_fail(ret))
 942                 goto fail;
 943
 944         if (signal)
 945                 *status |= FE_HAS_SIGNAL;
 946         if (cr_lock)
 947                 *status |= FE_HAS_CARRIER;
 948         if (nofecerr)
 949                 *status |= FE_HAS_VITERBI;
 950         if (sync_lock)
 951                 *status |= FE_HAS_SYNC;
 952
 953         switch (state->current_modulation) {
 954         case QAM_256:
 955         case QAM_64:
 956                 ret = lgdt3305_read_fec_lock_status(state, &fec_lock);
 957                 if (lg_fail(ret))
 958                         goto fail;
 959
 960                 if (fec_lock)
 961                         *status |= FE_HAS_LOCK;
 962                 break;
 963         case VSB_8:
 964                 if (inlock)
 965                         *status |= FE_HAS_LOCK;
 966                 break;
 967         default:
 968                 ret = -EINVAL;
 969         }
 970 fail:
 971         return ret;
 972 }
 973
 974 /* ------------------------------------------------------------------------ */
 975
 976 /* borrowed from lgdt330x.c */
 977 static u32 calculate_snr(u32 mse, u32 c)
 978 {
 979         if (mse == 0) /* no signal */
 980                 return 0;
 981
 982         mse = intlog10(mse);
 983         if (mse > c) {
 984                 /* Negative SNR, which is possible, but realisticly the
 985                 demod will lose lock before the signal gets this bad.  The
 986                 API only allows for unsigned values, so just return 0 */
 987                 return 0;
 988         }
 989         return 10*(c - mse);
 990 }
 991
 992 static int lgdt3305_read_snr(struct dvb_frontend *fe, u16 *snr)
 993 {
 994         struct lgdt3305_state *state = fe->demodulator_priv;
 995         u32 noise;      /* noise value */
 996         u32 c;          /* per-modulation SNR calculation constant */
 997
 998         switch (state->current_modulation) {
 999         case VSB_8:
1000 #ifdef USE_PTMSE
1001                 /* Use Phase Tracker Mean-Square Error Register */
1002                 /* SNR for ranges from -13.11 to +44.08 */
1003                 noise = ((read_reg(state, LGDT3305_PT_MSE_1) & 0x07) << 16) |
1004                         (read_reg(state, LGDT3305_PT_MSE_2) << 8) |
1005                         (read_reg(state, LGDT3305_PT_MSE_3) & 0xff);
1006                 c = 73957994; /* log10(25*32^2)*2^24 */
1007 #else
1008                 /* Use Equalizer Mean-Square Error Register */
1009                 /* SNR for ranges from -16.12 to +44.08 */
1010                 noise = ((read_reg(state, LGDT3305_EQ_MSE_1) & 0x0f) << 16) |
1011                         (read_reg(state, LGDT3305_EQ_MSE_2) << 8) |
1012                         (read_reg(state, LGDT3305_EQ_MSE_3) & 0xff);
1013                 c = 73957994; /* log10(25*32^2)*2^24 */
1014 #endif
1015                 break;
1016         case QAM_64:
1017         case QAM_256:
1018                 noise = (read_reg(state, LGDT3305_CR_MSE_1) << 8) |
1019                         (read_reg(state, LGDT3305_CR_MSE_2) & 0xff);
1020
1021                 c = (state->current_modulation == QAM_64) ?
1022                         97939837 : 98026066;
1023                 /* log10(688128)*2^24 and log10(696320)*2^24 */
1024                 break;
1025         default:
1026                 return -EINVAL;
1027         }
1028         state->snr = calculate_snr(noise, c);
1029         /* report SNR in dB * 10 */
1030         *snr = (state->snr / ((1 << 24) / 10));
1031         lg_dbg("noise = 0x%08x, snr = %d.%02d dB\n", noise,
1032                state->snr >> 24, (((state->snr >> 8) & 0xffff) * 100) >> 16);
1033
1034         return 0;
1035 }
1036
1037 static int lgdt3305_read_signal_strength(struct dvb_frontend *fe,
1038                                          u16 *strength)
1039 {
1040         /* borrowed from lgdt330x.c
1041          *
1042          * Calculate strength from SNR up to 35dB
1043          * Even though the SNR can go higher than 35dB,
1044          * there is some comfort factor in having a range of
1045          * strong signals that can show at 100%
1046          */
1047         struct lgdt3305_state *state = fe->demodulator_priv;
1048         u16 snr;
1049         int ret;
1050
1051         *strength = 0;
1052
1053         ret = fe->ops.read_snr(fe, &snr);
1054         if (lg_fail(ret))
1055                 goto fail;
1056         /* Rather than use the 8.8 value snr, use state->snr which is 8.24 */
1057         /* scale the range 0 - 35*2^24 into 0 - 65535 */
1058         if (state->snr >= 8960 * 0x10000)
1059                 *strength = 0xffff;
1060         else
1061                 *strength = state->snr / 8960;
1062 fail:
1063         return ret;
1064 }
1065
1066 /* ------------------------------------------------------------------------ */
1067
1068 static int lgdt3305_read_ber(struct dvb_frontend *fe, u32 *ber)
1069 {
1070         *ber = 0;
1071         return 0;
1072 }
1073
1074 static int lgdt3305_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1075 {
1076         struct lgdt3305_state *state = fe->demodulator_priv;
1077
1078         *ucblocks =
1079                 (read_reg(state, LGDT3305_FEC_PKT_ERR_1) << 8) |
1080                 (read_reg(state, LGDT3305_FEC_PKT_ERR_2) & 0xff);
1081
1082         return 0;
1083 }
1084
1085 static int lgdt3305_get_tune_settings(struct dvb_frontend *fe,
1086                                       struct dvb_frontend_tune_settings
1087                                         *fe_tune_settings)
1088 {
1089         fe_tune_settings->min_delay_ms = 500;
1090         lg_dbg("\n");
1091         return 0;
1092 }
1093
1094 static void lgdt3305_release(struct dvb_frontend *fe)
1095 {
1096         struct lgdt3305_state *state = fe->demodulator_priv;
1097         lg_dbg("\n");
1098         kfree(state);
1099 }
1100
1101 static struct dvb_frontend_ops lgdt3304_ops;
1102 static struct dvb_frontend_ops lgdt3305_ops;
1103
1104 struct dvb_frontend *lgdt3305_attach(const struct lgdt3305_config *config,
1105                                      struct i2c_adapter *i2c_adap)
1106 {
1107         struct lgdt3305_state *state = NULL;
1108         int ret;
1109         u8 val;
1110
1111         lg_dbg("(%d-%04x)\n",
1112                i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
1113                config ? config->i2c_addr : 0);
1114
1115         state = kzalloc(sizeof(struct lgdt3305_state), GFP_KERNEL);
1116         if (state == NULL)
1117                 goto fail;
1118
1119         state->cfg = config;
1120         state->i2c_adap = i2c_adap;
1121
1122         switch (config->demod_chip) {
1123         case LGDT3304:
1124                 memcpy(&state->frontend.ops, &lgdt3304_ops,
1125                        sizeof(struct dvb_frontend_ops));
1126                 break;
1127         case LGDT3305:
1128                 memcpy(&state->frontend.ops, &lgdt3305_ops,
1129                        sizeof(struct dvb_frontend_ops));
1130                 break;
1131         default:
1132                 goto fail;
1133         }
1134         state->frontend.demodulator_priv = state;
1135
1136         /* verify that we're talking to a lg dt3304/5 */
1137         ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_2, &val);
1138         if ((lg_fail(ret)) | (val == 0))
1139                 goto fail;
1140         ret = lgdt3305_write_reg(state, 0x0808, 0x80);
1141         if (lg_fail(ret))
1142                 goto fail;
1143         ret = lgdt3305_read_reg(state, 0x0808, &val);
1144         if ((lg_fail(ret)) | (val != 0x80))
1145                 goto fail;
1146         ret = lgdt3305_write_reg(state, 0x0808, 0x00);
1147         if (lg_fail(ret))
1148                 goto fail;
1149
1150         state->current_frequency = -1;
1151         state->current_modulation = -1;
1152
1153         return &state->frontend;
1154 fail:
1155         lg_warn("unable to detect %s hardware\n",
1156                 config->demod_chip ? "LGDT3304" : "LGDT3305");
1157         kfree(state);
1158         return NULL;
1159 }
1160 EXPORT_SYMBOL(lgdt3305_attach);
1161
1162 static struct dvb_frontend_ops lgdt3304_ops = {
1163         .info = {
1164                 .name = "LG Electronics LGDT3304 VSB/QAM Frontend",
1165                 .type               = FE_ATSC,
1166                 .frequency_min      = 54000000,
1167                 .frequency_max      = 858000000,
1168                 .frequency_stepsize = 62500,
1169                 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
1170         },
1171         .i2c_gate_ctrl        = lgdt3305_i2c_gate_ctrl,
1172         .init                 = lgdt3305_init,
1173         .set_frontend         = lgdt3304_set_parameters,
1174         .get_frontend         = lgdt3305_get_frontend,
1175         .get_tune_settings    = lgdt3305_get_tune_settings,
1176         .read_status          = lgdt3305_read_status,
1177         .read_ber             = lgdt3305_read_ber,
1178         .read_signal_strength = lgdt3305_read_signal_strength,
1179         .read_snr             = lgdt3305_read_snr,
1180         .read_ucblocks        = lgdt3305_read_ucblocks,
1181         .release              = lgdt3305_release,
1182 };
1183
1184 static struct dvb_frontend_ops lgdt3305_ops = {
1185         .info = {
1186                 .name = "LG Electronics LGDT3305 VSB/QAM Frontend",
1187                 .type               = FE_ATSC,
1188                 .frequency_min      = 54000000,
1189                 .frequency_max      = 858000000,
1190                 .frequency_stepsize = 62500,
1191                 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
1192         },
1193         .i2c_gate_ctrl        = lgdt3305_i2c_gate_ctrl,
1194         .init                 = lgdt3305_init,
1195         .sleep                = lgdt3305_sleep,
1196         .set_frontend         = lgdt3305_set_parameters,
1197         .get_frontend         = lgdt3305_get_frontend,
1198         .get_tune_settings    = lgdt3305_get_tune_settings,
1199         .read_status          = lgdt3305_read_status,
1200         .read_ber             = lgdt3305_read_ber,
1201         .read_signal_strength = lgdt3305_read_signal_strength,
1202         .read_snr             = lgdt3305_read_snr,
1203         .read_ucblocks        = lgdt3305_read_ucblocks,
1204         .release              = lgdt3305_release,
1205 };
1206
1207 MODULE_DESCRIPTION("LG Electronics LGDT3304/5 ATSC/QAM-B Demodulator Driver");
1208 MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
1209 MODULE_LICENSE("GPL");
1210 MODULE_VERSION("0.1");
1211
1212 /*
1213  * Local variables:
1214  * c-basic-offset: 8
1215  * End:
1216  */