2 * drxk_hard: DRX-K DVB-C/T demodulator driver
4 * Copyright (C) 2010-2011 Digital Devices GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/firmware.h>
30 #include <linux/i2c.h>
31 #include <asm/div64.h>
33 #include "dvb_frontend.h"
35 #include "drxk_hard.h"
37 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode);
38 static int PowerDownQAM(struct drxk_state *state);
39 static int SetDVBTStandard(struct drxk_state *state,
40 enum OperationMode oMode);
41 static int SetQAMStandard(struct drxk_state *state,
42 enum OperationMode oMode);
43 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
45 static int SetDVBTStandard(struct drxk_state *state,
46 enum OperationMode oMode);
47 static int DVBTStart(struct drxk_state *state);
48 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
50 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus);
51 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus);
52 static int SwitchAntennaToQAM(struct drxk_state *state);
53 static int SwitchAntennaToDVBT(struct drxk_state *state);
55 static bool IsDVBT(struct drxk_state *state)
57 return state->m_OperationMode == OM_DVBT;
60 static bool IsQAM(struct drxk_state *state)
62 return state->m_OperationMode == OM_QAM_ITU_A ||
63 state->m_OperationMode == OM_QAM_ITU_B ||
64 state->m_OperationMode == OM_QAM_ITU_C;
67 bool IsA1WithPatchCode(struct drxk_state *state)
69 return state->m_DRXK_A1_PATCH_CODE;
72 bool IsA1WithRomCode(struct drxk_state *state)
74 return state->m_DRXK_A1_ROM_CODE;
79 #define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
80 #define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0)
82 #define DEFAULT_MER_83 165
83 #define DEFAULT_MER_93 250
85 #ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
86 #define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
89 #ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
90 #define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
93 #ifndef DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH
94 #define DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH (0x06)
97 #define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
98 #define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
100 #ifndef DRXK_KI_RAGC_ATV
101 #define DRXK_KI_RAGC_ATV 4
103 #ifndef DRXK_KI_IAGC_ATV
104 #define DRXK_KI_IAGC_ATV 6
106 #ifndef DRXK_KI_DAGC_ATV
107 #define DRXK_KI_DAGC_ATV 7
110 #ifndef DRXK_KI_RAGC_QAM
111 #define DRXK_KI_RAGC_QAM 3
113 #ifndef DRXK_KI_IAGC_QAM
114 #define DRXK_KI_IAGC_QAM 4
116 #ifndef DRXK_KI_DAGC_QAM
117 #define DRXK_KI_DAGC_QAM 7
119 #ifndef DRXK_KI_RAGC_DVBT
120 #define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
122 #ifndef DRXK_KI_IAGC_DVBT
123 #define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
125 #ifndef DRXK_KI_DAGC_DVBT
126 #define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
129 #ifndef DRXK_AGC_DAC_OFFSET
130 #define DRXK_AGC_DAC_OFFSET (0x800)
133 #ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
134 #define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
137 #ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
138 #define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
141 #ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
142 #define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
145 #ifndef DRXK_QAM_SYMBOLRATE_MAX
146 #define DRXK_QAM_SYMBOLRATE_MAX (7233000)
149 #define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56
150 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64
151 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0
152 #define DRXK_BL_ROM_OFFSET_TAPS_BG 24
153 #define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32
154 #define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40
155 #define DRXK_BL_ROM_OFFSET_TAPS_FM 48
156 #define DRXK_BL_ROM_OFFSET_UCODE 0
158 #define DRXK_BLC_TIMEOUT 100
160 #define DRXK_BLCC_NR_ELEMENTS_TAPS 2
161 #define DRXK_BLCC_NR_ELEMENTS_UCODE 6
163 #define DRXK_BLDC_NR_ELEMENTS_TAPS 28
165 #ifndef DRXK_OFDM_NE_NOTCH_WIDTH
166 #define DRXK_OFDM_NE_NOTCH_WIDTH (4)
169 #define DRXK_QAM_SL_SIG_POWER_QAM16 (40960)
170 #define DRXK_QAM_SL_SIG_POWER_QAM32 (20480)
171 #define DRXK_QAM_SL_SIG_POWER_QAM64 (43008)
172 #define DRXK_QAM_SL_SIG_POWER_QAM128 (20992)
173 #define DRXK_QAM_SL_SIG_POWER_QAM256 (43520)
175 static unsigned int debug;
176 module_param(debug, int, 0644);
177 MODULE_PARM_DESC(debug, "enable debug messages");
179 #define dprintk(level, fmt, arg...) do { \
180 if (debug >= level) \
181 printk(KERN_DEBUG "drxk: %s" fmt, __func__, ## arg); \
185 static inline u32 MulDiv32(u32 a, u32 b, u32 c)
189 tmp64 = (u64) a * (u64) b;
195 inline u32 Frac28a(u32 a, u32 c)
201 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */
202 Q1 = a / c; /* integer part, only the 4 least significant bits
203 will be visible in the result */
205 /* division using radix 16, 7 nibbles in the result */
206 for (i = 0; i < 7; i++) {
207 Q1 = (Q1 << 4) | (R0 / c);
217 static u32 Log10Times100(u32 x)
219 static const u8 scale = 15;
220 static const u8 indexWidth = 5;
227 log2lut[n] = (1<<scale) * 200 * log2(1.0 + ((1.0/(1<<INDEXWIDTH)) * n))
228 0 <= n < ((1<<INDEXWIDTH)+1)
231 static const u32 log2lut[] = {
233 290941, /* 290941.300628 */
234 573196, /* 573196.476418 */
235 847269, /* 847269.179851 */
236 1113620, /* 1113620.489452 */
237 1372674, /* 1372673.576986 */
238 1624818, /* 1624817.752104 */
239 1870412, /* 1870411.981536 */
240 2109788, /* 2109787.962654 */
241 2343253, /* 2343252.817465 */
242 2571091, /* 2571091.461923 */
243 2793569, /* 2793568.696416 */
244 3010931, /* 3010931.055901 */
245 3223408, /* 3223408.452106 */
246 3431216, /* 3431215.635215 */
247 3634553, /* 3634553.498355 */
248 3833610, /* 3833610.244726 */
249 4028562, /* 4028562.434393 */
250 4219576, /* 4219575.925308 */
251 4406807, /* 4406806.721144 */
252 4590402, /* 4590401.736809 */
253 4770499, /* 4770499.491025 */
254 4947231, /* 4947230.734179 */
255 5120719, /* 5120719.018555 */
256 5291081, /* 5291081.217197 */
257 5458428, /* 5458427.996830 */
258 5622864, /* 5622864.249668 */
259 5784489, /* 5784489.488298 */
260 5943398, /* 5943398.207380 */
261 6099680, /* 6099680.215452 */
262 6253421, /* 6253420.939751 */
263 6404702, /* 6404701.706649 */
264 6553600, /* 6553600.000000 */
271 /* Scale x (normalize) */
272 /* computing y in log(x/y) = log(x) - log(y) */
273 if ((x & ((0xffffffff) << (scale + 1))) == 0) {
274 for (k = scale; k > 0; k--) {
275 if (x & (((u32) 1) << scale))
280 for (k = scale; k < 31; k++) {
281 if ((x & (((u32) (-1)) << (scale + 1))) == 0)
287 Now x has binary point between bit[scale] and bit[scale-1]
288 and 1.0 <= x < 2.0 */
290 /* correction for divison: log(x) = log(x/y)+log(y) */
291 y = k * ((((u32) 1) << scale) * 200);
293 /* remove integer part */
294 x &= ((((u32) 1) << scale) - 1);
296 i = (u8) (x >> (scale - indexWidth));
297 /* compute delta (x - a) */
298 d = x & ((((u32) 1) << (scale - indexWidth)) - 1);
299 /* compute log, multiplication (d* (..)) must be within range ! */
301 ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth));
302 /* Conver to log10() */
303 y /= 108853; /* (log2(10) << scale) */
311 /****************************************************************************/
312 /* I2C **********************************************************************/
313 /****************************************************************************/
315 static int i2c_read1(struct i2c_adapter *adapter, u8 adr, u8 *val)
317 struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
318 .buf = val, .len = 1}
321 return i2c_transfer(adapter, msgs, 1);
324 static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
327 struct i2c_msg msg = {
328 .addr = adr, .flags = 0, .buf = data, .len = len };
333 for (i = 0; i < len; i++)
334 printk(KERN_CONT " %02x", data[i]);
335 printk(KERN_CONT "\n");
337 status = i2c_transfer(adap, &msg, 1);
338 if (status >= 0 && status != 1)
342 printk(KERN_ERR "drxk: i2c write error at addr 0x%02x\n", adr);
347 static int i2c_read(struct i2c_adapter *adap,
348 u8 adr, u8 *msg, int len, u8 *answ, int alen)
351 struct i2c_msg msgs[2] = {
352 {.addr = adr, .flags = 0,
353 .buf = msg, .len = len},
354 {.addr = adr, .flags = I2C_M_RD,
355 .buf = answ, .len = alen}
358 status = i2c_transfer(adap, msgs, 2);
361 printk(KERN_CONT ": ERROR!\n");
365 printk(KERN_ERR "drxk: i2c read error at addr 0x%02x\n", adr);
370 dprintk(2, ": read from");
371 for (i = 0; i < len; i++)
372 printk(KERN_CONT " %02x", msg[i]);
373 printk(KERN_CONT ", value = ");
374 for (i = 0; i < alen; i++)
375 printk(KERN_CONT " %02x", answ[i]);
376 printk(KERN_CONT "\n");
381 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
384 u8 adr = state->demod_address, mm1[4], mm2[2], len;
386 if (state->single_master)
389 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
390 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
391 mm1[1] = ((reg >> 16) & 0xFF);
392 mm1[2] = ((reg >> 24) & 0xFF) | flags;
393 mm1[3] = ((reg >> 7) & 0xFF);
396 mm1[0] = ((reg << 1) & 0xFF);
397 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
400 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
401 status = i2c_read(state->i2c, adr, mm1, len, mm2, 2);
405 *data = mm2[0] | (mm2[1] << 8);
410 static int read16(struct drxk_state *state, u32 reg, u16 *data)
412 return read16_flags(state, reg, data, 0);
415 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
418 u8 adr = state->demod_address, mm1[4], mm2[4], len;
420 if (state->single_master)
423 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
424 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
425 mm1[1] = ((reg >> 16) & 0xFF);
426 mm1[2] = ((reg >> 24) & 0xFF) | flags;
427 mm1[3] = ((reg >> 7) & 0xFF);
430 mm1[0] = ((reg << 1) & 0xFF);
431 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
434 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
435 status = i2c_read(state->i2c, adr, mm1, len, mm2, 4);
439 *data = mm2[0] | (mm2[1] << 8) |
440 (mm2[2] << 16) | (mm2[3] << 24);
445 static int read32(struct drxk_state *state, u32 reg, u32 *data)
447 return read32_flags(state, reg, data, 0);
450 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
452 u8 adr = state->demod_address, mm[6], len;
454 if (state->single_master)
456 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
457 mm[0] = (((reg << 1) & 0xFF) | 0x01);
458 mm[1] = ((reg >> 16) & 0xFF);
459 mm[2] = ((reg >> 24) & 0xFF) | flags;
460 mm[3] = ((reg >> 7) & 0xFF);
463 mm[0] = ((reg << 1) & 0xFF);
464 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
467 mm[len] = data & 0xff;
468 mm[len + 1] = (data >> 8) & 0xff;
470 dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
471 return i2c_write(state->i2c, adr, mm, len + 2);
474 static int write16(struct drxk_state *state, u32 reg, u16 data)
476 return write16_flags(state, reg, data, 0);
479 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
481 u8 adr = state->demod_address, mm[8], len;
483 if (state->single_master)
485 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
486 mm[0] = (((reg << 1) & 0xFF) | 0x01);
487 mm[1] = ((reg >> 16) & 0xFF);
488 mm[2] = ((reg >> 24) & 0xFF) | flags;
489 mm[3] = ((reg >> 7) & 0xFF);
492 mm[0] = ((reg << 1) & 0xFF);
493 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
496 mm[len] = data & 0xff;
497 mm[len + 1] = (data >> 8) & 0xff;
498 mm[len + 2] = (data >> 16) & 0xff;
499 mm[len + 3] = (data >> 24) & 0xff;
500 dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
502 return i2c_write(state->i2c, adr, mm, len + 4);
505 static int write32(struct drxk_state *state, u32 reg, u32 data)
507 return write32_flags(state, reg, data, 0);
510 static int write_block(struct drxk_state *state, u32 Address,
511 const int BlockSize, const u8 pBlock[])
513 int status = 0, BlkSize = BlockSize;
516 if (state->single_master)
519 while (BlkSize > 0) {
520 int Chunk = BlkSize > state->m_ChunkSize ?
521 state->m_ChunkSize : BlkSize;
522 u8 *AdrBuf = &state->Chunk[0];
525 if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) {
526 AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01);
527 AdrBuf[1] = ((Address >> 16) & 0xFF);
528 AdrBuf[2] = ((Address >> 24) & 0xFF);
529 AdrBuf[3] = ((Address >> 7) & 0xFF);
532 if (Chunk == state->m_ChunkSize)
535 AdrBuf[0] = ((Address << 1) & 0xFF);
536 AdrBuf[1] = (((Address >> 16) & 0x0F) |
537 ((Address >> 18) & 0xF0));
540 memcpy(&state->Chunk[AdrLength], pBlock, Chunk);
541 dprintk(2, "(0x%08x, 0x%02x)\n", Address, Flags);
545 for (i = 0; i < Chunk; i++)
546 printk(KERN_CONT " %02x", pBlock[i]);
547 printk(KERN_CONT "\n");
549 status = i2c_write(state->i2c, state->demod_address,
550 &state->Chunk[0], Chunk + AdrLength);
552 printk(KERN_ERR "drxk: %s: i2c write error at addr 0x%02x\n",
557 Address += (Chunk >> 1);
563 #ifndef DRXK_MAX_RETRIES_POWERUP
564 #define DRXK_MAX_RETRIES_POWERUP 20
567 int PowerUpDevice(struct drxk_state *state)
575 status = i2c_read1(state->i2c, state->demod_address, &data);
579 status = i2c_write(state->i2c, state->demod_address,
585 status = i2c_read1(state->i2c, state->demod_address,
587 } while (status < 0 &&
588 (retryCount < DRXK_MAX_RETRIES_POWERUP));
589 if (status < 0 && retryCount >= DRXK_MAX_RETRIES_POWERUP)
593 /* Make sure all clk domains are active */
594 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
597 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
600 /* Enable pll lock tests */
601 status = write16(state, SIO_CC_PLL_LOCK__A, 1);
605 state->m_currentPowerMode = DRX_POWER_UP;
609 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
615 static int init_state(struct drxk_state *state)
618 * FIXME: most (all?) of the values bellow should be moved into
619 * struct drxk_config, as they are probably board-specific
621 u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO;
622 u32 ulVSBIfAgcOutputLevel = 0;
623 u32 ulVSBIfAgcMinLevel = 0;
624 u32 ulVSBIfAgcMaxLevel = 0x7FFF;
625 u32 ulVSBIfAgcSpeed = 3;
627 u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO;
628 u32 ulVSBRfAgcOutputLevel = 0;
629 u32 ulVSBRfAgcMinLevel = 0;
630 u32 ulVSBRfAgcMaxLevel = 0x7FFF;
631 u32 ulVSBRfAgcSpeed = 3;
632 u32 ulVSBRfAgcTop = 9500;
633 u32 ulVSBRfAgcCutOffCurrent = 4000;
635 u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO;
636 u32 ulATVIfAgcOutputLevel = 0;
637 u32 ulATVIfAgcMinLevel = 0;
638 u32 ulATVIfAgcMaxLevel = 0;
639 u32 ulATVIfAgcSpeed = 3;
641 u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF;
642 u32 ulATVRfAgcOutputLevel = 0;
643 u32 ulATVRfAgcMinLevel = 0;
644 u32 ulATVRfAgcMaxLevel = 0;
645 u32 ulATVRfAgcTop = 9500;
646 u32 ulATVRfAgcCutOffCurrent = 4000;
647 u32 ulATVRfAgcSpeed = 3;
649 u32 ulQual83 = DEFAULT_MER_83;
650 u32 ulQual93 = DEFAULT_MER_93;
652 u32 ulDVBTStaticTSClock = 1;
653 u32 ulDVBCStaticTSClock = 1;
655 u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
656 u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
658 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
659 /* io_pad_cfg_mode output mode is drive always */
660 /* io_pad_cfg_drive is set to power 2 (23 mA) */
661 u32 ulGPIOCfg = 0x0113;
662 u32 ulInvertTSClock = 0;
663 u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
664 u32 ulTSClockkStrength = DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH;
665 u32 ulDVBTBitrate = 50000000;
666 u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
668 u32 ulInsertRSByte = 0;
675 state->m_hasLNA = false;
676 state->m_hasDVBT = false;
677 state->m_hasDVBC = false;
678 state->m_hasATV = false;
679 state->m_hasOOB = false;
680 state->m_hasAudio = false;
682 if (!state->m_ChunkSize)
683 state->m_ChunkSize = 124;
685 state->m_oscClockFreq = 0;
686 state->m_smartAntInverted = false;
687 state->m_bPDownOpenBridge = false;
689 /* real system clock frequency in kHz */
690 state->m_sysClockFreq = 151875;
691 /* Timing div, 250ns/Psys */
692 /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
693 state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) *
694 HI_I2C_DELAY) / 1000;
696 if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
697 state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
698 state->m_HICfgWakeUpKey = (state->demod_address << 1);
699 /* port/bridge/power down ctrl */
700 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
702 state->m_bPowerDown = (ulPowerDown != 0);
704 state->m_DRXK_A1_PATCH_CODE = false;
705 state->m_DRXK_A1_ROM_CODE = false;
706 state->m_DRXK_A2_ROM_CODE = false;
707 state->m_DRXK_A3_ROM_CODE = false;
708 state->m_DRXK_A2_PATCH_CODE = false;
709 state->m_DRXK_A3_PATCH_CODE = false;
711 /* Init AGC and PGA parameters */
713 state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode);
714 state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel);
715 state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel);
716 state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel);
717 state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed);
718 state->m_vsbPgaCfg = 140;
721 state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode);
722 state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel);
723 state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel);
724 state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel);
725 state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed);
726 state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop);
727 state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent);
728 state->m_vsbPreSawCfg.reference = 0x07;
729 state->m_vsbPreSawCfg.usePreSaw = true;
731 state->m_Quality83percent = DEFAULT_MER_83;
732 state->m_Quality93percent = DEFAULT_MER_93;
733 if (ulQual93 <= 500 && ulQual83 < ulQual93) {
734 state->m_Quality83percent = ulQual83;
735 state->m_Quality93percent = ulQual93;
739 state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode);
740 state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel);
741 state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel);
742 state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel);
743 state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed);
746 state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode);
747 state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel);
748 state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel);
749 state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel);
750 state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed);
751 state->m_atvRfAgcCfg.top = (ulATVRfAgcTop);
752 state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent);
753 state->m_atvPreSawCfg.reference = 0x04;
754 state->m_atvPreSawCfg.usePreSaw = true;
758 state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
759 state->m_dvbtRfAgcCfg.outputLevel = 0;
760 state->m_dvbtRfAgcCfg.minOutputLevel = 0;
761 state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF;
762 state->m_dvbtRfAgcCfg.top = 0x2100;
763 state->m_dvbtRfAgcCfg.cutOffCurrent = 4000;
764 state->m_dvbtRfAgcCfg.speed = 1;
768 state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
769 state->m_dvbtIfAgcCfg.outputLevel = 0;
770 state->m_dvbtIfAgcCfg.minOutputLevel = 0;
771 state->m_dvbtIfAgcCfg.maxOutputLevel = 9000;
772 state->m_dvbtIfAgcCfg.top = 13424;
773 state->m_dvbtIfAgcCfg.cutOffCurrent = 0;
774 state->m_dvbtIfAgcCfg.speed = 3;
775 state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30;
776 state->m_dvbtIfAgcCfg.IngainTgtMax = 30000;
777 /* state->m_dvbtPgaCfg = 140; */
779 state->m_dvbtPreSawCfg.reference = 4;
780 state->m_dvbtPreSawCfg.usePreSaw = false;
783 state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
784 state->m_qamRfAgcCfg.outputLevel = 0;
785 state->m_qamRfAgcCfg.minOutputLevel = 6023;
786 state->m_qamRfAgcCfg.maxOutputLevel = 27000;
787 state->m_qamRfAgcCfg.top = 0x2380;
788 state->m_qamRfAgcCfg.cutOffCurrent = 4000;
789 state->m_qamRfAgcCfg.speed = 3;
792 state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
793 state->m_qamIfAgcCfg.outputLevel = 0;
794 state->m_qamIfAgcCfg.minOutputLevel = 0;
795 state->m_qamIfAgcCfg.maxOutputLevel = 9000;
796 state->m_qamIfAgcCfg.top = 0x0511;
797 state->m_qamIfAgcCfg.cutOffCurrent = 0;
798 state->m_qamIfAgcCfg.speed = 3;
799 state->m_qamIfAgcCfg.IngainTgtMax = 5119;
800 state->m_qamIfAgcCfg.FastClipCtrlDelay = 50;
802 state->m_qamPgaCfg = 140;
803 state->m_qamPreSawCfg.reference = 4;
804 state->m_qamPreSawCfg.usePreSaw = false;
806 state->m_OperationMode = OM_NONE;
807 state->m_DrxkState = DRXK_UNINITIALIZED;
809 /* MPEG output configuration */
810 state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */
811 state->m_insertRSByte = false; /* If TRUE; insert RS byte */
812 state->m_invertDATA = false; /* If TRUE; invert DATA signals */
813 state->m_invertERR = false; /* If TRUE; invert ERR signal */
814 state->m_invertSTR = false; /* If TRUE; invert STR signals */
815 state->m_invertVAL = false; /* If TRUE; invert VAL signals */
816 state->m_invertCLK = (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */
817 state->m_DVBTStaticCLK = (ulDVBTStaticTSClock != 0);
818 state->m_DVBCStaticCLK = (ulDVBCStaticTSClock != 0);
819 /* If TRUE; static MPEG clockrate will be used;
820 otherwise clockrate will adapt to the bitrate of the TS */
822 state->m_DVBTBitrate = ulDVBTBitrate;
823 state->m_DVBCBitrate = ulDVBCBitrate;
825 state->m_TSDataStrength = (ulTSDataStrength & 0x07);
826 state->m_TSClockkStrength = (ulTSClockkStrength & 0x07);
828 /* Maximum bitrate in b/s in case static clockrate is selected */
829 state->m_mpegTsStaticBitrate = 19392658;
830 state->m_disableTEIhandling = false;
833 state->m_insertRSByte = true;
835 state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
836 if (ulMpegLockTimeOut < 10000)
837 state->m_MpegLockTimeOut = ulMpegLockTimeOut;
838 state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
839 if (ulDemodLockTimeOut < 10000)
840 state->m_DemodLockTimeOut = ulDemodLockTimeOut;
843 state->m_Constellation = DRX_CONSTELLATION_AUTO;
844 state->m_qamInterleaveMode = DRXK_QAM_I12_J17;
845 state->m_fecRsPlen = 204 * 8; /* fecRsPlen annex A */
846 state->m_fecRsPrescale = 1;
848 state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM;
849 state->m_agcFastClipCtrlDelay = 0;
851 state->m_GPIOCfg = (ulGPIOCfg);
853 state->m_bPowerDown = false;
854 state->m_currentPowerMode = DRX_POWER_DOWN;
856 state->m_rfmirror = (ulRfMirror == 0);
857 state->m_IfAgcPol = false;
861 static int DRXX_Open(struct drxk_state *state)
869 /* stop lock indicator process */
870 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
873 /* Check device id */
874 status = read16(state, SIO_TOP_COMM_KEY__A, &key);
877 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
880 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
883 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
886 status = write16(state, SIO_TOP_COMM_KEY__A, key);
889 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
893 static int GetDeviceCapabilities(struct drxk_state *state)
895 u16 sioPdrOhwCfg = 0;
896 u32 sioTopJtagidLo = 0;
898 const char *spin = "";
903 /* stop lock indicator process */
904 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
907 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
910 status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg);
913 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
917 switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
919 /* ignore (bypass ?) */
923 state->m_oscClockFreq = 27000;
927 state->m_oscClockFreq = 20250;
931 state->m_oscClockFreq = 20250;
934 printk(KERN_ERR "drxk: Clock Frequency is unkonwn\n");
938 Determine device capabilities
941 status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo);
945 printk(KERN_ERR "drxk: status = 0x%08x\n", sioTopJtagidLo);
948 switch ((sioTopJtagidLo >> 29) & 0xF) {
950 state->m_deviceSpin = DRXK_SPIN_A1;
954 state->m_deviceSpin = DRXK_SPIN_A2;
958 state->m_deviceSpin = DRXK_SPIN_A3;
962 state->m_deviceSpin = DRXK_SPIN_UNKNOWN;
964 printk(KERN_ERR "drxk: Spin %d unknown\n",
965 (sioTopJtagidLo >> 29) & 0xF);
968 switch ((sioTopJtagidLo >> 12) & 0xFF) {
970 /* typeId = DRX3913K_TYPE_ID */
971 state->m_hasLNA = false;
972 state->m_hasOOB = false;
973 state->m_hasATV = false;
974 state->m_hasAudio = false;
975 state->m_hasDVBT = true;
976 state->m_hasDVBC = true;
977 state->m_hasSAWSW = true;
978 state->m_hasGPIO2 = false;
979 state->m_hasGPIO1 = false;
980 state->m_hasIRQN = false;
983 /* typeId = DRX3915K_TYPE_ID */
984 state->m_hasLNA = false;
985 state->m_hasOOB = false;
986 state->m_hasATV = true;
987 state->m_hasAudio = false;
988 state->m_hasDVBT = true;
989 state->m_hasDVBC = false;
990 state->m_hasSAWSW = true;
991 state->m_hasGPIO2 = true;
992 state->m_hasGPIO1 = true;
993 state->m_hasIRQN = false;
996 /* typeId = DRX3916K_TYPE_ID */
997 state->m_hasLNA = false;
998 state->m_hasOOB = false;
999 state->m_hasATV = true;
1000 state->m_hasAudio = false;
1001 state->m_hasDVBT = true;
1002 state->m_hasDVBC = false;
1003 state->m_hasSAWSW = true;
1004 state->m_hasGPIO2 = true;
1005 state->m_hasGPIO1 = true;
1006 state->m_hasIRQN = false;
1009 /* typeId = DRX3918K_TYPE_ID */
1010 state->m_hasLNA = false;
1011 state->m_hasOOB = false;
1012 state->m_hasATV = true;
1013 state->m_hasAudio = true;
1014 state->m_hasDVBT = true;
1015 state->m_hasDVBC = false;
1016 state->m_hasSAWSW = true;
1017 state->m_hasGPIO2 = true;
1018 state->m_hasGPIO1 = true;
1019 state->m_hasIRQN = false;
1022 /* typeId = DRX3921K_TYPE_ID */
1023 state->m_hasLNA = false;
1024 state->m_hasOOB = false;
1025 state->m_hasATV = true;
1026 state->m_hasAudio = true;
1027 state->m_hasDVBT = true;
1028 state->m_hasDVBC = true;
1029 state->m_hasSAWSW = true;
1030 state->m_hasGPIO2 = true;
1031 state->m_hasGPIO1 = true;
1032 state->m_hasIRQN = false;
1035 /* typeId = DRX3923K_TYPE_ID */
1036 state->m_hasLNA = false;
1037 state->m_hasOOB = false;
1038 state->m_hasATV = true;
1039 state->m_hasAudio = true;
1040 state->m_hasDVBT = true;
1041 state->m_hasDVBC = true;
1042 state->m_hasSAWSW = true;
1043 state->m_hasGPIO2 = true;
1044 state->m_hasGPIO1 = true;
1045 state->m_hasIRQN = false;
1048 /* typeId = DRX3925K_TYPE_ID */
1049 state->m_hasLNA = false;
1050 state->m_hasOOB = false;
1051 state->m_hasATV = true;
1052 state->m_hasAudio = true;
1053 state->m_hasDVBT = true;
1054 state->m_hasDVBC = true;
1055 state->m_hasSAWSW = true;
1056 state->m_hasGPIO2 = true;
1057 state->m_hasGPIO1 = true;
1058 state->m_hasIRQN = false;
1061 /* typeId = DRX3926K_TYPE_ID */
1062 state->m_hasLNA = false;
1063 state->m_hasOOB = false;
1064 state->m_hasATV = true;
1065 state->m_hasAudio = false;
1066 state->m_hasDVBT = true;
1067 state->m_hasDVBC = true;
1068 state->m_hasSAWSW = true;
1069 state->m_hasGPIO2 = true;
1070 state->m_hasGPIO1 = true;
1071 state->m_hasIRQN = false;
1074 printk(KERN_ERR "drxk: DeviceID 0x%02x not supported\n",
1075 ((sioTopJtagidLo >> 12) & 0xFF));
1081 "drxk: detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
1082 ((sioTopJtagidLo >> 12) & 0xFF), spin,
1083 state->m_oscClockFreq / 1000,
1084 state->m_oscClockFreq % 1000);
1088 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1094 static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)
1102 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
1105 if (cmd == SIO_HI_RA_RAM_CMD_RESET)
1109 (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
1110 ((state->m_HICfgCtrl) &
1111 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1112 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
1113 if (powerdown_cmd == false) {
1114 /* Wait until command rdy */
1121 status = read16(state, SIO_HI_RA_RAM_CMD__A,
1123 } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES)
1127 status = read16(state, SIO_HI_RA_RAM_RES__A, pResult);
1131 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1136 static int HI_CfgCommand(struct drxk_state *state)
1142 mutex_lock(&state->mutex);
1144 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout);
1147 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl);
1150 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey);
1153 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay);
1156 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv);
1159 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1162 status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
1166 state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1168 mutex_unlock(&state->mutex);
1170 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1174 static int InitHI(struct drxk_state *state)
1178 state->m_HICfgWakeUpKey = (state->demod_address << 1);
1179 state->m_HICfgTimeout = 0x96FF;
1180 /* port/bridge/power down ctrl */
1181 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1183 return HI_CfgCommand(state);
1186 static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1189 u16 sioPdrMclkCfg = 0;
1190 u16 sioPdrMdxCfg = 0;
1192 dprintk(1, ": mpeg %s, %s mode\n",
1193 mpegEnable ? "enable" : "disable",
1194 state->m_enableParallel ? "parallel" : "serial");
1196 /* stop lock indicator process */
1197 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1201 /* MPEG TS pad configuration */
1202 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
1206 if (mpegEnable == false) {
1207 /* Set MPEG TS pads to inputmode */
1208 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1211 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1214 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1217 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1220 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1223 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1226 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1229 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1232 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1235 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1238 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1241 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1245 /* Enable MPEG output */
1247 ((state->m_TSDataStrength <<
1248 SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1249 sioPdrMclkCfg = ((state->m_TSClockkStrength <<
1250 SIO_PDR_MCLK_CFG_DRIVE__B) |
1253 status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg);
1256 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000); /* Disable */
1259 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000); /* Disable */
1262 if (state->m_enableParallel == true) {
1263 /* paralel -> enable MD1 to MD7 */
1264 status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg);
1267 status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg);
1270 status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg);
1273 status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg);
1276 status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg);
1279 status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg);
1282 status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg);
1286 sioPdrMdxCfg = ((state->m_TSDataStrength <<
1287 SIO_PDR_MD0_CFG_DRIVE__B)
1289 /* serial -> disable MD1 to MD7 */
1290 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1293 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1296 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1299 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1302 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1305 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1308 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1312 status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg);
1315 status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg);
1319 /* Enable MB output over MPEG pads and ctl input */
1320 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1323 /* Write nomagic word to enable pdr reg write */
1324 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1327 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1331 static int MPEGTSDisable(struct drxk_state *state)
1335 return MPEGTSConfigurePins(state, false);
1338 static int BLChainCmd(struct drxk_state *state,
1339 u16 romOffset, u16 nrOfElements, u32 timeOut)
1346 mutex_lock(&state->mutex);
1347 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1350 status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset);
1353 status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements);
1356 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1360 end = jiffies + msecs_to_jiffies(timeOut);
1363 status = read16(state, SIO_BL_STATUS__A, &blStatus);
1366 } while ((blStatus == 0x1) &&
1367 ((time_is_after_jiffies(end))));
1369 if (blStatus == 0x1) {
1370 printk(KERN_ERR "drxk: SIO not ready\n");
1376 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1378 mutex_unlock(&state->mutex);
1383 static int DownloadMicrocode(struct drxk_state *state,
1384 const u8 pMCImage[], u32 Length)
1386 const u8 *pSrc = pMCImage;
1399 /* down the drain (we don care about MAGIC_WORD) */
1400 Drain = (pSrc[0] << 8) | pSrc[1];
1401 pSrc += sizeof(u16);
1402 offset += sizeof(u16);
1403 nBlocks = (pSrc[0] << 8) | pSrc[1];
1404 pSrc += sizeof(u16);
1405 offset += sizeof(u16);
1407 for (i = 0; i < nBlocks; i += 1) {
1408 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
1409 (pSrc[2] << 8) | pSrc[3];
1410 pSrc += sizeof(u32);
1411 offset += sizeof(u32);
1413 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
1414 pSrc += sizeof(u16);
1415 offset += sizeof(u16);
1417 Flags = (pSrc[0] << 8) | pSrc[1];
1418 pSrc += sizeof(u16);
1419 offset += sizeof(u16);
1421 BlockCRC = (pSrc[0] << 8) | pSrc[1];
1422 pSrc += sizeof(u16);
1423 offset += sizeof(u16);
1425 if (offset + BlockSize > Length) {
1426 printk(KERN_ERR "drxk: Firmware is corrupted.\n");
1430 status = write_block(state, Address, BlockSize, pSrc);
1432 printk(KERN_ERR "drxk: Error %d while loading firmware\n", status);
1436 offset += BlockSize;
1441 static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable)
1445 u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
1446 u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1451 if (enable == false) {
1452 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
1453 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1456 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1457 if (status >= 0 && data == desiredStatus) {
1458 /* tokenring already has correct status */
1461 /* Disable/enable dvbt tokenring bridge */
1462 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl);
1464 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1466 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1467 if ((status >= 0 && data == desiredStatus) || time_is_after_jiffies(end))
1471 if (data != desiredStatus) {
1472 printk(KERN_ERR "drxk: SIO not ready\n");
1478 static int MPEGTSStop(struct drxk_state *state)
1481 u16 fecOcSncMode = 0;
1482 u16 fecOcIprMode = 0;
1486 /* Gracefull shutdown (byte boundaries) */
1487 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1490 fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1491 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1495 /* Suppress MCLK during absence of data */
1496 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode);
1499 fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1500 status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode);
1504 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1509 static int scu_command(struct drxk_state *state,
1510 u16 cmd, u8 parameterLen,
1511 u16 *parameter, u8 resultLen, u16 *result)
1513 #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1514 #error DRXK register mapping no longer compatible with this routine!
1517 int status = -EINVAL;
1526 if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) ||
1527 ((resultLen > 0) && (result == NULL)))
1530 mutex_lock(&state->mutex);
1532 /* assume that the command register is ready
1533 since it is checked afterwards */
1534 for (ii = parameterLen - 1; ii >= 0; ii -= 1) {
1535 buffer[cnt++] = (parameter[ii] & 0xFF);
1536 buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1538 buffer[cnt++] = (cmd & 0xFF);
1539 buffer[cnt++] = ((cmd >> 8) & 0xFF);
1541 write_block(state, SCU_RAM_PARAM_0__A -
1542 (parameterLen - 1), cnt, buffer);
1543 /* Wait until SCU has processed command */
1544 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1547 status = read16(state, SCU_RAM_COMMAND__A, &curCmd);
1550 } while (!(curCmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1551 if (curCmd != DRX_SCU_READY) {
1552 printk(KERN_ERR "drxk: SCU not ready\n");
1557 if ((resultLen > 0) && (result != NULL)) {
1561 for (ii = resultLen - 1; ii >= 0; ii -= 1) {
1562 status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]);
1567 /* Check if an error was reported by SCU */
1568 err = (s16)result[0];
1572 /* check for the known error codes */
1574 case SCU_RESULT_UNKCMD:
1575 p = "SCU_RESULT_UNKCMD";
1577 case SCU_RESULT_UNKSTD:
1578 p = "SCU_RESULT_UNKSTD";
1580 case SCU_RESULT_SIZE:
1581 p = "SCU_RESULT_SIZE";
1583 case SCU_RESULT_INVPAR:
1584 p = "SCU_RESULT_INVPAR";
1586 default: /* Other negative values are errors */
1587 sprintf(errname, "ERROR: %d\n", err);
1590 printk(KERN_ERR "drxk: %s while sending cmd 0x%04x with params:", p, cmd);
1591 print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
1598 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1600 mutex_unlock(&state->mutex);
1604 static int SetIqmAf(struct drxk_state *state, bool active)
1612 status = read16(state, IQM_AF_STDBY__A, &data);
1617 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1618 | IQM_AF_STDBY_STDBY_AMP_STANDBY
1619 | IQM_AF_STDBY_STDBY_PD_STANDBY
1620 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1621 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1623 data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1624 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1625 & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1626 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1627 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1630 status = write16(state, IQM_AF_STDBY__A, data);
1634 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1638 static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
1641 u16 sioCcPwdMode = 0;
1645 /* Check arguments */
1651 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE;
1653 case DRXK_POWER_DOWN_OFDM:
1654 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1656 case DRXK_POWER_DOWN_CORE:
1657 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1659 case DRXK_POWER_DOWN_PLL:
1660 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL;
1662 case DRX_POWER_DOWN:
1663 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC;
1666 /* Unknow sleep mode */
1670 /* If already in requested power mode, do nothing */
1671 if (state->m_currentPowerMode == *mode)
1674 /* For next steps make sure to start from DRX_POWER_UP mode */
1675 if (state->m_currentPowerMode != DRX_POWER_UP) {
1676 status = PowerUpDevice(state);
1679 status = DVBTEnableOFDMTokenRing(state, true);
1684 if (*mode == DRX_POWER_UP) {
1685 /* Restore analog & pin configuartion */
1687 /* Power down to requested mode */
1688 /* Backup some register settings */
1689 /* Set pins with possible pull-ups connected
1690 to them in input mode */
1691 /* Analog power down */
1692 /* ADC power down */
1693 /* Power down device */
1694 /* stop all comm_exec */
1695 /* Stop and power down previous standard */
1696 switch (state->m_OperationMode) {
1698 status = MPEGTSStop(state);
1701 status = PowerDownDVBT(state, false);
1707 status = MPEGTSStop(state);
1710 status = PowerDownQAM(state);
1717 status = DVBTEnableOFDMTokenRing(state, false);
1720 status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode);
1723 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1727 if (*mode != DRXK_POWER_DOWN_OFDM) {
1728 state->m_HICfgCtrl |=
1729 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1730 status = HI_CfgCommand(state);
1735 state->m_currentPowerMode = *mode;
1739 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1744 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
1746 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
1753 status = read16(state, SCU_COMM_EXEC__A, &data);
1756 if (data == SCU_COMM_EXEC_ACTIVE) {
1757 /* Send OFDM stop command */
1758 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
1761 /* Send OFDM reset command */
1762 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
1767 /* Reset datapath for OFDM, processors first */
1768 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1771 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1774 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1779 status = SetIqmAf(state, false);
1783 /* powerdown to OFDM mode */
1785 status = CtrlPowerMode(state, &powerMode);
1791 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1795 static int SetOperationMode(struct drxk_state *state,
1796 enum OperationMode oMode)
1802 Stop and power down previous standard
1803 TODO investigate total power down instead of partial
1804 power down depending on "previous" standard.
1807 /* disable HW lock indicator */
1808 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1812 /* Device is already at the required mode */
1813 if (state->m_OperationMode == oMode)
1816 switch (state->m_OperationMode) {
1817 /* OM_NONE was added for start up */
1821 status = MPEGTSStop(state);
1824 status = PowerDownDVBT(state, true);
1827 state->m_OperationMode = OM_NONE;
1829 case OM_QAM_ITU_A: /* fallthrough */
1831 status = MPEGTSStop(state);
1834 status = PowerDownQAM(state);
1837 state->m_OperationMode = OM_NONE;
1846 Power up new standard
1850 dprintk(1, ": DVB-T\n");
1851 state->m_OperationMode = oMode;
1852 status = SetDVBTStandard(state, oMode);
1856 case OM_QAM_ITU_A: /* fallthrough */
1858 dprintk(1, ": DVB-C Annex %c\n",
1859 (state->m_OperationMode == OM_QAM_ITU_A) ? 'A' : 'C');
1860 state->m_OperationMode = oMode;
1861 status = SetQAMStandard(state, oMode);
1871 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1875 static int Start(struct drxk_state *state, s32 offsetFreq,
1876 s32 IntermediateFrequency)
1878 int status = -EINVAL;
1881 s32 OffsetkHz = offsetFreq / 1000;
1884 if (state->m_DrxkState != DRXK_STOPPED &&
1885 state->m_DrxkState != DRXK_DTV_STARTED)
1888 state->m_bMirrorFreqSpect = (state->props.inversion == INVERSION_ON);
1890 if (IntermediateFrequency < 0) {
1891 state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect;
1892 IntermediateFrequency = -IntermediateFrequency;
1895 switch (state->m_OperationMode) {
1898 IFreqkHz = (IntermediateFrequency / 1000);
1899 status = SetQAM(state, IFreqkHz, OffsetkHz);
1902 state->m_DrxkState = DRXK_DTV_STARTED;
1905 IFreqkHz = (IntermediateFrequency / 1000);
1906 status = MPEGTSStop(state);
1909 status = SetDVBT(state, IFreqkHz, OffsetkHz);
1912 status = DVBTStart(state);
1915 state->m_DrxkState = DRXK_DTV_STARTED;
1922 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1926 static int ShutDown(struct drxk_state *state)
1934 static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus,
1937 int status = -EINVAL;
1941 if (pLockStatus == NULL)
1944 *pLockStatus = NOT_LOCKED;
1946 /* define the SCU command code */
1947 switch (state->m_OperationMode) {
1951 status = GetQAMLockStatus(state, pLockStatus);
1954 status = GetDVBTLockStatus(state, pLockStatus);
1961 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1965 static int MPEGTSStart(struct drxk_state *state)
1969 u16 fecOcSncMode = 0;
1971 /* Allow OC to sync again */
1972 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1975 fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1976 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1979 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1982 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1986 static int MPEGTSDtoInit(struct drxk_state *state)
1992 /* Rate integration settings */
1993 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1996 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1999 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
2002 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
2005 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
2008 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
2011 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
2014 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
2018 /* Additional configuration */
2019 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
2022 status = write16(state, FEC_OC_SNC_LWM__A, 2);
2025 status = write16(state, FEC_OC_SNC_HWM__A, 12);
2028 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2033 static int MPEGTSDtoSetup(struct drxk_state *state,
2034 enum OperationMode oMode)
2038 u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */
2039 u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */
2040 u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */
2041 u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */
2042 u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */
2043 u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */
2044 u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */
2045 u16 fecOcTmdMode = 0;
2046 u16 fecOcTmdIntUpdRate = 0;
2048 bool staticCLK = false;
2052 /* Check insertion of the Reed-Solomon parity bytes */
2053 status = read16(state, FEC_OC_MODE__A, &fecOcRegMode);
2056 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode);
2059 fecOcRegMode &= (~FEC_OC_MODE_PARITY__M);
2060 fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2061 if (state->m_insertRSByte == true) {
2062 /* enable parity symbol forward */
2063 fecOcRegMode |= FEC_OC_MODE_PARITY__M;
2064 /* MVAL disable during parity bytes */
2065 fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2066 /* TS burst length to 204 */
2067 fecOcDtoBurstLen = 204;
2070 /* Check serial or parrallel output */
2071 fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2072 if (state->m_enableParallel == false) {
2073 /* MPEG data output is serial -> set ipr_mode[0] */
2074 fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M;
2079 maxBitRate = state->m_DVBTBitrate;
2081 fecOcRcnCtlRate = 0xC00000;
2082 staticCLK = state->m_DVBTStaticCLK;
2084 case OM_QAM_ITU_A: /* fallthrough */
2086 fecOcTmdMode = 0x0004;
2087 fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */
2088 maxBitRate = state->m_DVBCBitrate;
2089 staticCLK = state->m_DVBCStaticCLK;
2093 } /* switch (standard) */
2097 /* Configure DTO's */
2101 /* Rational DTO for MCLK source (static MCLK rate),
2102 Dynamic DTO for optimal grouping
2103 (avoid intra-packet gaps),
2104 DTO offset enable to sync TS burst with MSTRT */
2105 fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2106 FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2107 fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2108 FEC_OC_FCT_MODE_VIRT_ENA__M);
2110 /* Check user defined bitrate */
2111 bitRate = maxBitRate;
2112 if (bitRate > 75900000UL) { /* max is 75.9 Mb/s */
2113 bitRate = 75900000UL;
2115 /* Rational DTO period:
2116 dto_period = (Fsys / bitrate) - 2
2118 Result should be floored,
2119 to make sure >= requested bitrate
2121 fecOcDtoPeriod = (u16) (((state->m_sysClockFreq)
2123 if (fecOcDtoPeriod <= 2)
2126 fecOcDtoPeriod -= 2;
2127 fecOcTmdIntUpdRate = 8;
2129 /* (commonAttr->staticCLK == false) => dynamic mode */
2130 fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M;
2131 fecOcFctMode = FEC_OC_FCT_MODE__PRE;
2132 fecOcTmdIntUpdRate = 5;
2135 /* Write appropriate registers with requested configuration */
2136 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen);
2139 status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod);
2142 status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode);
2145 status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode);
2148 status = write16(state, FEC_OC_MODE__A, fecOcRegMode);
2151 status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode);
2155 /* Rate integration settings */
2156 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate);
2159 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate);
2162 status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode);
2165 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2169 static int MPEGTSConfigurePolarity(struct drxk_state *state)
2171 u16 fecOcRegIprInvert = 0;
2173 /* Data mask for the output data byte */
2174 u16 InvertDataMask =
2175 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2176 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2177 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2178 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2182 /* Control selective inversion of output bits */
2183 fecOcRegIprInvert &= (~(InvertDataMask));
2184 if (state->m_invertDATA == true)
2185 fecOcRegIprInvert |= InvertDataMask;
2186 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2187 if (state->m_invertERR == true)
2188 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M;
2189 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2190 if (state->m_invertSTR == true)
2191 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M;
2192 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2193 if (state->m_invertVAL == true)
2194 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M;
2195 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2196 if (state->m_invertCLK == true)
2197 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M;
2199 return write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert);
2202 #define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2204 static int SetAgcRf(struct drxk_state *state,
2205 struct SCfgAgc *pAgcCfg, bool isDTV)
2207 int status = -EINVAL;
2209 struct SCfgAgc *pIfAgcSettings;
2213 if (pAgcCfg == NULL)
2216 switch (pAgcCfg->ctrlMode) {
2217 case DRXK_AGC_CTRL_AUTO:
2218 /* Enable RF AGC DAC */
2219 status = read16(state, IQM_AF_STDBY__A, &data);
2222 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2223 status = write16(state, IQM_AF_STDBY__A, data);
2226 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2230 /* Enable SCU RF AGC loop */
2231 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2234 if (state->m_RfAgcPol)
2235 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2237 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2238 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2242 /* Set speed (using complementary reduction value) */
2243 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2247 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2248 data |= (~(pAgcCfg->speed <<
2249 SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2250 & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2252 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2257 pIfAgcSettings = &state->m_dvbtIfAgcCfg;
2258 else if (IsQAM(state))
2259 pIfAgcSettings = &state->m_qamIfAgcCfg;
2261 pIfAgcSettings = &state->m_atvIfAgcCfg;
2262 if (pIfAgcSettings == NULL) {
2267 /* Set TOP, only if IF-AGC is in AUTO mode */
2268 if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO)
2269 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top);
2273 /* Cut-Off current */
2274 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent);
2278 /* Max. output level */
2279 status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel);
2285 case DRXK_AGC_CTRL_USER:
2286 /* Enable RF AGC DAC */
2287 status = read16(state, IQM_AF_STDBY__A, &data);
2290 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2291 status = write16(state, IQM_AF_STDBY__A, data);
2295 /* Disable SCU RF AGC loop */
2296 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2299 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2300 if (state->m_RfAgcPol)
2301 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2303 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2304 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2308 /* SCU c.o.c. to 0, enabling full control range */
2309 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2313 /* Write value to output pin */
2314 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel);
2319 case DRXK_AGC_CTRL_OFF:
2320 /* Disable RF AGC DAC */
2321 status = read16(state, IQM_AF_STDBY__A, &data);
2324 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2325 status = write16(state, IQM_AF_STDBY__A, data);
2329 /* Disable SCU RF AGC loop */
2330 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2333 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2334 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2345 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2349 #define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2351 static int SetAgcIf(struct drxk_state *state,
2352 struct SCfgAgc *pAgcCfg, bool isDTV)
2356 struct SCfgAgc *pRfAgcSettings;
2360 switch (pAgcCfg->ctrlMode) {
2361 case DRXK_AGC_CTRL_AUTO:
2363 /* Enable IF AGC DAC */
2364 status = read16(state, IQM_AF_STDBY__A, &data);
2367 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2368 status = write16(state, IQM_AF_STDBY__A, data);
2372 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2376 /* Enable SCU IF AGC loop */
2377 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2380 if (state->m_IfAgcPol)
2381 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2383 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2384 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2388 /* Set speed (using complementary reduction value) */
2389 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2392 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2393 data |= (~(pAgcCfg->speed <<
2394 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2395 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2397 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2402 pRfAgcSettings = &state->m_qamRfAgcCfg;
2404 pRfAgcSettings = &state->m_atvRfAgcCfg;
2405 if (pRfAgcSettings == NULL)
2408 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top);
2413 case DRXK_AGC_CTRL_USER:
2415 /* Enable IF AGC DAC */
2416 status = read16(state, IQM_AF_STDBY__A, &data);
2419 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2420 status = write16(state, IQM_AF_STDBY__A, data);
2424 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2428 /* Disable SCU IF AGC loop */
2429 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2432 if (state->m_IfAgcPol)
2433 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2435 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2436 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2440 /* Write value to output pin */
2441 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel);
2446 case DRXK_AGC_CTRL_OFF:
2448 /* Disable If AGC DAC */
2449 status = read16(state, IQM_AF_STDBY__A, &data);
2452 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2453 status = write16(state, IQM_AF_STDBY__A, data);
2457 /* Disable SCU IF AGC loop */
2458 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2461 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2462 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2466 } /* switch (agcSettingsIf->ctrlMode) */
2468 /* always set the top to support
2469 configurations without if-loop */
2470 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top);
2473 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2477 static int ReadIFAgc(struct drxk_state *state, u32 *pValue)
2485 status = read16(state, IQM_AF_AGC_IF__A, &agcDacLvl);
2487 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2493 if (agcDacLvl > DRXK_AGC_DAC_OFFSET)
2494 Level = agcDacLvl - DRXK_AGC_DAC_OFFSET;
2496 *pValue = (14000 - Level) / 4;
2503 static int GetQAMSignalToNoise(struct drxk_state *state,
2504 s32 *pSignalToNoise)
2507 u16 qamSlErrPower = 0; /* accum. error between
2508 raw and sliced symbols */
2509 u32 qamSlSigPower = 0; /* used for MER, depends of
2511 u32 qamSlMer = 0; /* QAM MER */
2515 /* MER calculation */
2517 /* get the register value needed for MER */
2518 status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower);
2520 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2524 switch (state->props.modulation) {
2526 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2529 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2532 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2535 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2539 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2543 if (qamSlErrPower > 0) {
2544 qamSlMer = Log10Times100(qamSlSigPower) -
2545 Log10Times100((u32) qamSlErrPower);
2547 *pSignalToNoise = qamSlMer;
2552 static int GetDVBTSignalToNoise(struct drxk_state *state,
2553 s32 *pSignalToNoise)
2557 u32 EqRegTdSqrErrI = 0;
2558 u32 EqRegTdSqrErrQ = 0;
2559 u16 EqRegTdSqrErrExp = 0;
2560 u16 EqRegTdTpsPwrOfs = 0;
2561 u16 EqRegTdReqSmbCnt = 0;
2568 u16 transmissionParams = 0;
2572 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs);
2575 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt);
2578 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp);
2581 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, ®Data);
2584 /* Extend SQR_ERR_I operational range */
2585 EqRegTdSqrErrI = (u32) regData;
2586 if ((EqRegTdSqrErrExp > 11) &&
2587 (EqRegTdSqrErrI < 0x00000FFFUL)) {
2588 EqRegTdSqrErrI += 0x00010000UL;
2590 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®Data);
2593 /* Extend SQR_ERR_Q operational range */
2594 EqRegTdSqrErrQ = (u32) regData;
2595 if ((EqRegTdSqrErrExp > 11) &&
2596 (EqRegTdSqrErrQ < 0x00000FFFUL))
2597 EqRegTdSqrErrQ += 0x00010000UL;
2599 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams);
2603 /* Check input data for MER */
2605 /* MER calculation (in 0.1 dB) without math.h */
2606 if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0))
2608 else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) {
2609 /* No error at all, this must be the HW reset value
2610 * Apparently no first measurement yet
2614 SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) <<
2616 if ((transmissionParams &
2617 OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2618 == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2623 /* IMER = 100 * log10 (x)
2624 where x = (EqRegTdTpsPwrOfs^2 *
2625 EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ
2628 where a = 100 * log10 (EqRegTdTpsPwrOfs^2)
2629 b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt)
2630 c = 100 * log10 (SqrErrIQ)
2633 /* log(x) x = 9bits * 9bits->18 bits */
2634 a = Log10Times100(EqRegTdTpsPwrOfs *
2636 /* log(x) x = 16bits * 7bits->23 bits */
2637 b = Log10Times100(EqRegTdReqSmbCnt * tpsCnt);
2638 /* log(x) x = (16bits + 16bits) << 15 ->32 bits */
2639 c = Log10Times100(SqrErrIQ);
2642 /* No negative MER, clip to zero */
2648 *pSignalToNoise = iMER;
2652 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2656 static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
2660 *pSignalToNoise = 0;
2661 switch (state->m_OperationMode) {
2663 return GetDVBTSignalToNoise(state, pSignalToNoise);
2666 return GetQAMSignalToNoise(state, pSignalToNoise);
2674 static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)
2676 /* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2681 static s32 QE_SN[] = {
2687 108, /* 16-QAM 1/2 */
2688 131, /* 16-QAM 2/3 */
2689 146, /* 16-QAM 3/4 */
2690 156, /* 16-QAM 5/6 */
2691 160, /* 16-QAM 7/8 */
2692 165, /* 64-QAM 1/2 */
2693 187, /* 64-QAM 2/3 */
2694 202, /* 64-QAM 3/4 */
2695 216, /* 64-QAM 5/6 */
2696 225, /* 64-QAM 7/8 */
2702 s32 SignalToNoise = 0;
2703 u16 Constellation = 0;
2705 u32 SignalToNoiseRel;
2708 status = GetDVBTSignalToNoise(state, &SignalToNoise);
2711 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation);
2714 Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2716 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate);
2719 CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2721 if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2722 CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2724 SignalToNoiseRel = SignalToNoise -
2725 QE_SN[Constellation * 5 + CodeRate];
2728 if (SignalToNoiseRel < -70)
2730 else if (SignalToNoiseRel < 30)
2731 *pQuality = ((SignalToNoiseRel + 70) *
2734 *pQuality = BERQuality;
2739 static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)
2747 u32 SignalToNoise = 0;
2748 u32 BERQuality = 100;
2749 u32 SignalToNoiseRel = 0;
2751 status = GetQAMSignalToNoise(state, &SignalToNoise);
2755 switch (state->props.modulation) {
2757 SignalToNoiseRel = SignalToNoise - 200;
2760 SignalToNoiseRel = SignalToNoise - 230;
2761 break; /* Not in NorDig */
2763 SignalToNoiseRel = SignalToNoise - 260;
2766 SignalToNoiseRel = SignalToNoise - 290;
2770 SignalToNoiseRel = SignalToNoise - 320;
2774 if (SignalToNoiseRel < -70)
2776 else if (SignalToNoiseRel < 30)
2777 *pQuality = ((SignalToNoiseRel + 70) *
2780 *pQuality = BERQuality;
2786 static int GetQuality(struct drxk_state *state, s32 *pQuality)
2790 switch (state->m_OperationMode) {
2792 return GetDVBTQuality(state, pQuality);
2794 return GetDVBCQuality(state, pQuality);
2803 /* Free data ram in SIO HI */
2804 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2805 #define SIO_HI_RA_RAM_USR_END__A 0x420060
2807 #define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2808 #define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2809 #define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2810 #define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2812 #define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F)
2813 #define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F)
2814 #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2816 static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge)
2818 int status = -EINVAL;
2822 if (state->m_DrxkState == DRXK_UNINITIALIZED)
2824 if (state->m_DrxkState == DRXK_POWERED_DOWN)
2827 if (state->no_i2c_bridge)
2830 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2833 if (bEnableBridge) {
2834 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2838 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2843 status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0);
2847 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2851 static int SetPreSaw(struct drxk_state *state,
2852 struct SCfgPreSaw *pPreSawCfg)
2854 int status = -EINVAL;
2858 if ((pPreSawCfg == NULL)
2859 || (pPreSawCfg->reference > IQM_AF_PDREF__M))
2862 status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference);
2865 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2869 static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,
2870 u16 romOffset, u16 nrOfElements, u32 timeOut)
2873 u16 offset = (u16) ((targetAddr >> 0) & 0x00FFFF);
2874 u16 blockbank = (u16) ((targetAddr >> 16) & 0x000FFF);
2880 mutex_lock(&state->mutex);
2881 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2884 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2887 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2890 status = write16(state, SIO_BL_SRC_ADDR__A, romOffset);
2893 status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements);
2896 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2900 end = jiffies + msecs_to_jiffies(timeOut);
2902 status = read16(state, SIO_BL_STATUS__A, &blStatus);
2905 } while ((blStatus == 0x1) && time_is_after_jiffies(end));
2906 if (blStatus == 0x1) {
2907 printk(KERN_ERR "drxk: SIO not ready\n");
2913 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2915 mutex_unlock(&state->mutex);
2920 static int ADCSyncMeasurement(struct drxk_state *state, u16 *count)
2927 /* Start measurement */
2928 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2931 status = write16(state, IQM_AF_START_LOCK__A, 1);
2936 status = read16(state, IQM_AF_PHASE0__A, &data);
2940 *count = *count + 1;
2941 status = read16(state, IQM_AF_PHASE1__A, &data);
2945 *count = *count + 1;
2946 status = read16(state, IQM_AF_PHASE2__A, &data);
2950 *count = *count + 1;
2954 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2958 static int ADCSynchronization(struct drxk_state *state)
2965 status = ADCSyncMeasurement(state, &count);
2970 /* Try sampling on a diffrent edge */
2973 status = read16(state, IQM_AF_CLKNEG__A, &clkNeg);
2976 if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2977 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2978 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2980 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2982 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2984 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
2986 status = write16(state, IQM_AF_CLKNEG__A, clkNeg);
2989 status = ADCSyncMeasurement(state, &count);
2998 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3002 static int SetFrequencyShifter(struct drxk_state *state,
3003 u16 intermediateFreqkHz,
3004 s32 tunerFreqOffset, bool isDTV)
3006 bool selectPosImage = false;
3007 u32 rfFreqResidual = tunerFreqOffset;
3008 u32 fmFrequencyShift = 0;
3009 bool tunerMirror = !state->m_bMirrorFreqSpect;
3014 u32 samplingFrequency = (u32) (state->m_sysClockFreq / 3);
3021 Program frequency shifter
3022 No need to account for mirroring on RF
3025 if ((state->m_OperationMode == OM_QAM_ITU_A) ||
3026 (state->m_OperationMode == OM_QAM_ITU_C) ||
3027 (state->m_OperationMode == OM_DVBT))
3028 selectPosImage = true;
3030 selectPosImage = false;
3033 /* tuner doesn't mirror */
3034 ifFreqActual = intermediateFreqkHz +
3035 rfFreqResidual + fmFrequencyShift;
3038 ifFreqActual = intermediateFreqkHz -
3039 rfFreqResidual - fmFrequencyShift;
3040 if (ifFreqActual > samplingFrequency / 2) {
3042 adcFreq = samplingFrequency - ifFreqActual;
3045 /* adc doesn't mirror */
3046 adcFreq = ifFreqActual;
3050 frequencyShift = adcFreq;
3051 imageToSelect = state->m_rfmirror ^ tunerMirror ^
3052 adcFlip ^ selectPosImage;
3053 state->m_IqmFsRateOfs =
3054 Frac28a((frequencyShift), samplingFrequency);
3057 state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1;
3059 /* Program frequency shifter with tuner offset compensation */
3060 /* frequencyShift += tunerFreqOffset; TODO */
3061 status = write32(state, IQM_FS_RATE_OFS_LO__A,
3062 state->m_IqmFsRateOfs);
3064 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3068 static int InitAGC(struct drxk_state *state, bool isDTV)
3071 u16 ingainTgtMin = 0;
3072 u16 ingainTgtMax = 0;
3080 u16 kiInnergainMin = 0;
3081 u16 ifIaccuHiTgt = 0;
3082 u16 ifIaccuHiTgtMin = 0;
3083 u16 ifIaccuHiTgtMax = 0;
3085 u16 fastClpCtrlDelay = 0;
3086 u16 clpCtrlMode = 0;
3091 /* Common settings */
3093 ifIaccuHiTgtMin = 2047;
3097 /* AGCInit() not available for DVBT; init done in microcode */
3098 if (!IsQAM(state)) {
3099 printk(KERN_ERR "drxk: %s: mode %d is not DVB-C\n", __func__, state->m_OperationMode);
3103 /* FIXME: Analog TV AGC require different settings */
3105 /* Standard specific settings */
3107 clpDirTo = (u16) -9;
3110 snsDirTo = (u16) -9;
3111 kiInnergainMin = (u16) -1030;
3112 ifIaccuHiTgtMax = 0x2380;
3113 ifIaccuHiTgt = 0x2380;
3114 ingainTgtMin = 0x0511;
3116 ingainTgtMax = 5119;
3117 fastClpCtrlDelay = state->m_qamIfAgcCfg.FastClipCtrlDelay;
3119 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay);
3123 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode);
3126 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt);
3129 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin);
3132 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax);
3135 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin);
3138 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax);
3141 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3144 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3147 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3150 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3153 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax);
3156 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax);
3160 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin);
3163 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt);
3166 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen);
3170 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3173 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3176 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3180 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3183 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin);
3186 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin);
3189 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo);
3192 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo);
3195 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3198 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3201 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3204 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3207 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3210 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3213 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3216 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3219 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3222 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3225 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3228 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3231 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3234 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3238 /* Initialize inner-loop KI gain factors */
3239 status = read16(state, SCU_RAM_AGC_KI__A, &data);
3244 data &= ~SCU_RAM_AGC_KI_RF__M;
3245 data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3246 data &= ~SCU_RAM_AGC_KI_IF__M;
3247 data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3249 status = write16(state, SCU_RAM_AGC_KI__A, data);
3252 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3256 static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr)
3261 if (packetErr == NULL)
3262 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3264 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr);
3266 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3270 static int DVBTScCommand(struct drxk_state *state,
3271 u16 cmd, u16 subcmd,
3272 u16 param0, u16 param1, u16 param2,
3273 u16 param3, u16 param4)
3282 status = read16(state, OFDM_SC_COMM_EXEC__A, &scExec);
3284 /* SC is not running */
3290 /* Wait until sc is ready to receive command */
3294 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3296 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3297 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3300 /* Write sub-command */
3302 /* All commands using sub-cmd */
3303 case OFDM_SC_RA_RAM_CMD_PROC_START:
3304 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3305 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3306 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3315 /* Write needed parameters and the command */
3317 /* All commands using 5 parameters */
3318 /* All commands using 4 parameters */
3319 /* All commands using 3 parameters */
3320 /* All commands using 2 parameters */
3321 case OFDM_SC_RA_RAM_CMD_PROC_START:
3322 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3323 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3324 status = write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3325 /* All commands using 1 parameters */
3326 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3327 case OFDM_SC_RA_RAM_CMD_USER_IO:
3328 status = write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3329 /* All commands using 0 parameters */
3330 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3331 case OFDM_SC_RA_RAM_CMD_NULL:
3333 status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3336 /* Unknown command */
3342 /* Wait until sc is ready processing command */
3346 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3348 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3349 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3352 /* Check for illegal cmd */
3353 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode);
3354 if (errCode == 0xFFFF) {
3355 /* illegal command */
3361 /* Retreive results parameters from SC */
3363 /* All commands yielding 5 results */
3364 /* All commands yielding 4 results */
3365 /* All commands yielding 3 results */
3366 /* All commands yielding 2 results */
3367 /* All commands yielding 1 result */
3368 case OFDM_SC_RA_RAM_CMD_USER_IO:
3369 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3370 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3371 /* All commands yielding 0 results */
3372 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3373 case OFDM_SC_RA_RAM_CMD_SET_TIMER:
3374 case OFDM_SC_RA_RAM_CMD_PROC_START:
3375 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3376 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3377 case OFDM_SC_RA_RAM_CMD_NULL:
3380 /* Unknown command */
3383 } /* switch (cmd->cmd) */
3386 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3390 static int PowerUpDVBT(struct drxk_state *state)
3392 enum DRXPowerMode powerMode = DRX_POWER_UP;
3396 status = CtrlPowerMode(state, &powerMode);
3398 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3402 static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled)
3407 if (*enabled == true)
3408 status = write16(state, IQM_CF_BYPASSDET__A, 0);
3410 status = write16(state, IQM_CF_BYPASSDET__A, 1);
3412 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3416 #define DEFAULT_FR_THRES_8K 4000
3417 static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled)
3423 if (*enabled == true) {
3424 /* write mask to 1 */
3425 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3426 DEFAULT_FR_THRES_8K);
3428 /* write mask to 0 */
3429 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3432 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3437 static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,
3438 struct DRXKCfgDvbtEchoThres_t *echoThres)
3444 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3448 switch (echoThres->fftMode) {
3449 case DRX_FFTMODE_2K:
3450 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3451 data |= ((echoThres->threshold <<
3452 OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3453 & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
3455 case DRX_FFTMODE_8K:
3456 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3457 data |= ((echoThres->threshold <<
3458 OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3459 & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
3465 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3468 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3472 static int DVBTCtrlSetSqiSpeed(struct drxk_state *state,
3473 enum DRXKCfgDvbtSqiSpeed *speed)
3475 int status = -EINVAL;
3480 case DRXK_DVBT_SQI_SPEED_FAST:
3481 case DRXK_DVBT_SQI_SPEED_MEDIUM:
3482 case DRXK_DVBT_SQI_SPEED_SLOW:
3487 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3491 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3495 /*============================================================================*/
3498 * \brief Activate DVBT specific presets
3499 * \param demod instance of demodulator.
3500 * \return DRXStatus_t.
3502 * Called in DVBTSetStandard
3505 static int DVBTActivatePresets(struct drxk_state *state)
3508 bool setincenable = false;
3509 bool setfrenable = true;
3511 struct DRXKCfgDvbtEchoThres_t echoThres2k = { 0, DRX_FFTMODE_2K };
3512 struct DRXKCfgDvbtEchoThres_t echoThres8k = { 0, DRX_FFTMODE_8K };
3515 status = DVBTCtrlSetIncEnable(state, &setincenable);
3518 status = DVBTCtrlSetFrEnable(state, &setfrenable);
3521 status = DVBTCtrlSetEchoThreshold(state, &echoThres2k);
3524 status = DVBTCtrlSetEchoThreshold(state, &echoThres8k);
3527 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax);
3530 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3534 /*============================================================================*/
3537 * \brief Initialize channelswitch-independent settings for DVBT.
3538 * \param demod instance of demodulator.
3539 * \return DRXStatus_t.
3541 * For ROM code channel filter taps are loaded from the bootloader. For microcode
3542 * the DVB-T taps from the drxk_filters.h are used.
3544 static int SetDVBTStandard(struct drxk_state *state,
3545 enum OperationMode oMode)
3554 /* added antenna switch */
3555 SwitchAntennaToDVBT(state);
3556 /* send OFDM reset command */
3557 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
3561 /* send OFDM setenv command */
3562 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmdResult);
3566 /* reset datapath for OFDM, processors first */
3567 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3570 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3573 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3578 /* synchronize on ofdstate->m_festart */
3579 status = write16(state, IQM_AF_UPD_SEL__A, 1);
3582 /* window size for clipping ADC detection */
3583 status = write16(state, IQM_AF_CLP_LEN__A, 0);
3586 /* window size for for sense pre-SAW detection */
3587 status = write16(state, IQM_AF_SNS_LEN__A, 0);
3590 /* sense threshold for sense pre-SAW detection */
3591 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3594 status = SetIqmAf(state, true);
3598 status = write16(state, IQM_AF_AGC_RF__A, 0);
3602 /* Impulse noise cruncher setup */
3603 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */
3606 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */
3609 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */
3613 status = write16(state, IQM_RC_STRETCH__A, 16);
3616 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3619 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3622 status = write16(state, IQM_CF_SCALE__A, 1600);
3625 status = write16(state, IQM_CF_SCALE_SH__A, 0);
3629 /* virtual clipping threshold for clipping ADC detection */
3630 status = write16(state, IQM_AF_CLP_TH__A, 448);
3633 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3637 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3641 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */
3644 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3647 /* enable power measurement interrupt */
3648 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3651 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3655 /* IQM will not be reset from here, sync ADC and update/init AGC */
3656 status = ADCSynchronization(state);
3659 status = SetPreSaw(state, &state->m_dvbtPreSawCfg);
3663 /* Halt SCU to enable safe non-atomic accesses */
3664 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3668 status = SetAgcRf(state, &state->m_dvbtRfAgcCfg, true);
3671 status = SetAgcIf(state, &state->m_dvbtIfAgcCfg, true);
3675 /* Set Noise Estimation notch width and enable DC fix */
3676 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3679 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3680 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3684 /* Activate SCU to enable SCU commands */
3685 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3689 if (!state->m_DRXK_A3_ROM_CODE) {
3690 /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */
3691 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDelay);
3697 #ifdef COMPILE_FOR_NONRT
3698 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3701 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3707 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */
3712 #ifdef COMPILE_FOR_NONRT
3713 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3717 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3721 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3725 /* Setup MPEG bus */
3726 status = MPEGTSDtoSetup(state, OM_DVBT);
3729 /* Set DVBT Presets */
3730 status = DVBTActivatePresets(state);
3736 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3740 /*============================================================================*/
3742 * \brief Start dvbt demodulating for channel.
3743 * \param demod instance of demodulator.
3744 * \return DRXStatus_t.
3746 static int DVBTStart(struct drxk_state *state)
3750 /* DRXKOfdmScCmd_t scCmd; */
3753 /* Start correct processes to get in lock */
3754 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
3755 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3756 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0);
3760 status = MPEGTSStart(state);
3763 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3768 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3773 /*============================================================================*/
3776 * \brief Set up dvbt demodulator for channel.
3777 * \param demod instance of demodulator.
3778 * \return DRXStatus_t.
3779 * // original DVBTSetChannel()
3781 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3782 s32 tunerFreqOffset)
3785 u16 transmissionParams = 0;
3786 u16 operationMode = 0;
3787 u32 iqmRcRateOfs = 0;
3792 dprintk(1, "IF =%d, TFO = %d\n", IntermediateFreqkHz, tunerFreqOffset);
3794 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
3798 /* Halt SCU to enable safe non-atomic accesses */
3799 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3803 /* Stop processors */
3804 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3807 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3811 /* Mandatory fix, always stop CP, required to set spl offset back to
3812 hardware default (is set to 0 by ucode during pilot detection */
3813 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3817 /*== Write channel settings to device =====================================*/
3820 switch (state->props.transmission_mode) {
3821 case TRANSMISSION_MODE_AUTO:
3823 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
3824 /* fall through , try first guess DRX_FFTMODE_8K */
3825 case TRANSMISSION_MODE_8K:
3826 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
3828 case TRANSMISSION_MODE_2K:
3829 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
3834 switch (state->props.guard_interval) {
3836 case GUARD_INTERVAL_AUTO:
3837 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
3838 /* fall through , try first guess DRX_GUARD_1DIV4 */
3839 case GUARD_INTERVAL_1_4:
3840 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
3842 case GUARD_INTERVAL_1_32:
3843 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
3845 case GUARD_INTERVAL_1_16:
3846 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
3848 case GUARD_INTERVAL_1_8:
3849 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
3854 switch (state->props.hierarchy) {
3855 case HIERARCHY_AUTO:
3856 case HIERARCHY_NONE:
3858 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
3859 /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
3860 /* transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
3863 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3866 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3869 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3875 switch (state->props.modulation) {
3878 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
3879 /* fall through , try first guess DRX_CONSTELLATION_QAM64 */
3881 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3884 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3887 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3891 /* No hierachical channels support in BDA */
3892 /* Priority (only for hierarchical channels) */
3893 switch (channel->priority) {
3894 case DRX_PRIORITY_LOW:
3895 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3896 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3897 OFDM_EC_SB_PRIOR_LO);
3899 case DRX_PRIORITY_HIGH:
3900 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3901 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3902 OFDM_EC_SB_PRIOR_HI));
3904 case DRX_PRIORITY_UNKNOWN: /* fall through */
3910 /* Set Priorty high */
3911 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3912 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3918 switch (state->props.code_rate_HP) {
3921 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
3922 /* fall through , try first guess DRX_CODERATE_2DIV3 */
3924 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3927 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3930 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3933 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3936 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3940 /* SAW filter selection: normaly not necesarry, but if wanted
3941 the application can select a SAW filter via the driver by using UIOs */
3942 /* First determine real bandwidth (Hz) */
3943 /* Also set delay for impulse noise cruncher */
3944 /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed
3945 by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC
3947 switch (state->props.bandwidth_hz) {
3949 state->props.bandwidth_hz = 8000000;
3952 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3953 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052);
3956 /* cochannel protection for PAL 8 MHz */
3957 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7);
3960 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7);
3963 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7);
3966 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3971 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3972 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491);
3975 /* cochannel protection for PAL 7 MHz */
3976 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8);
3979 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8);
3982 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4);
3985 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3990 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3991 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073);
3994 /* cochannel protection for NTSC 6 MHz */
3995 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19);
3998 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19);
4001 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14);
4004 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
4013 if (iqmRcRateOfs == 0) {
4014 /* Now compute IQM_RC_RATE_OFS
4015 (((SysFreq/BandWidth)/2)/2) -1) * 2^23)
4017 ((SysFreq / BandWidth) * (2^21)) - (2^23)
4019 /* (SysFreq / BandWidth) * (2^28) */
4020 /* assert (MAX(sysClk)/MIN(bandwidth) < 16)
4021 => assert(MAX(sysClk) < 16*MIN(bandwidth))
4022 => assert(109714272 > 48000000) = true so Frac 28 can be used */
4023 iqmRcRateOfs = Frac28a((u32)
4024 ((state->m_sysClockFreq *
4025 1000) / 3), bandwidth);
4026 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */
4027 if ((iqmRcRateOfs & 0x7fL) >= 0x40)
4028 iqmRcRateOfs += 0x80L;
4029 iqmRcRateOfs = iqmRcRateOfs >> 7;
4030 /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */
4031 iqmRcRateOfs = iqmRcRateOfs - (1 << 23);
4035 ((((u32) IQM_RC_RATE_OFS_HI__M) <<
4036 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
4037 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs);
4041 /* Bandwidth setting done */
4044 status = DVBTSetFrequencyShift(demod, channel, tunerOffset);
4048 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
4052 /*== Start SC, write channel settings to SC ===============================*/
4054 /* Activate SCU to enable SCU commands */
4055 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4059 /* Enable SC after setting all other parameters */
4060 status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4063 status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4068 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
4072 /* Write SC parameter registers, set all AUTO flags in operation mode */
4073 param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
4074 OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
4075 OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
4076 OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
4077 OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
4078 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4079 0, transmissionParams, param1, 0, 0, 0);
4083 if (!state->m_DRXK_A3_ROM_CODE)
4084 status = DVBTCtrlSetSqiSpeed(state, &state->m_sqiSpeed);
4087 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4093 /*============================================================================*/
4096 * \brief Retreive lock status .
4097 * \param demod Pointer to demodulator instance.
4098 * \param lockStat Pointer to lock status structure.
4099 * \return DRXStatus_t.
4102 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus)
4105 const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
4106 OFDM_SC_RA_RAM_LOCK_FEC__M);
4107 const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4108 const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4110 u16 ScRaRamLock = 0;
4115 *pLockStatus = NOT_LOCKED;
4117 /* Check if SC is running */
4118 status = read16(state, OFDM_SC_COMM_EXEC__A, &ScCommExec);
4121 if (ScCommExec == OFDM_SC_COMM_EXEC_STOP)
4124 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock);
4128 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask)
4129 *pLockStatus = MPEG_LOCK;
4130 else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
4131 *pLockStatus = FEC_LOCK;
4132 else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
4133 *pLockStatus = DEMOD_LOCK;
4134 else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4135 *pLockStatus = NEVER_LOCK;
4138 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4143 static int PowerUpQAM(struct drxk_state *state)
4145 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
4149 status = CtrlPowerMode(state, &powerMode);
4151 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4157 /** Power Down QAM */
4158 static int PowerDownQAM(struct drxk_state *state)
4165 status = read16(state, SCU_COMM_EXEC__A, &data);
4168 if (data == SCU_COMM_EXEC_ACTIVE) {
4173 /* stop all comstate->m_exec */
4174 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4177 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
4182 status = SetIqmAf(state, false);
4186 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4191 /*============================================================================*/
4194 * \brief Setup of the QAM Measurement intervals for signal quality
4195 * \param demod instance of demod.
4196 * \param modulation current modulation.
4197 * \return DRXStatus_t.
4200 * Take into account that for certain settings the errorcounters can overflow.
4201 * The implementation does not check this.
4204 static int SetQAMMeasurement(struct drxk_state *state,
4205 enum EDrxkConstellation modulation,
4208 u32 fecBitsDesired = 0; /* BER accounting period */
4209 u32 fecRsPeriodTotal = 0; /* Total period */
4210 u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */
4211 u16 fecRsPeriod = 0; /* Value for corresponding I2C register */
4217 /* fecBitsDesired = symbolRate [kHz] *
4223 switch (modulation) {
4224 case DRX_CONSTELLATION_QAM16:
4225 fecBitsDesired = 4 * symbolRate;
4227 case DRX_CONSTELLATION_QAM32:
4228 fecBitsDesired = 5 * symbolRate;
4230 case DRX_CONSTELLATION_QAM64:
4231 fecBitsDesired = 6 * symbolRate;
4233 case DRX_CONSTELLATION_QAM128:
4234 fecBitsDesired = 7 * symbolRate;
4236 case DRX_CONSTELLATION_QAM256:
4237 fecBitsDesired = 8 * symbolRate;
4245 fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */
4246 fecBitsDesired *= 500; /* meas. period [ms] */
4248 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
4249 /* fecRsPeriodTotal = fecBitsDesired / 1632 */
4250 fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil */
4252 /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */
4253 fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16);
4254 if (fecRsPrescale == 0) {
4255 /* Divide by zero (though impossible) */
4261 ((u16) fecRsPeriodTotal +
4262 (fecRsPrescale >> 1)) / fecRsPrescale;
4264 /* write corresponding registers */
4265 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod);
4268 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale);
4271 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod);
4274 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4278 static int SetQAM16(struct drxk_state *state)
4283 /* QAM Equalizer Setup */
4285 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4288 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4291 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4294 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4297 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4300 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4303 /* Decision Feedback Equalizer */
4304 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4307 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4310 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4313 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4316 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4319 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4323 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4326 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4329 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4333 /* QAM Slicer Settings */
4334 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16);
4338 /* QAM Loop Controller Coeficients */
4339 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4342 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4345 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4348 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4351 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4354 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4357 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4360 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4364 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4367 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4370 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4373 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4376 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4379 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4382 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4385 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4388 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4391 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4394 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4397 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4402 /* QAM State Machine (FSM) Thresholds */
4404 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4407 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4410 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4413 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4416 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4419 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4423 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4426 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4429 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4434 /* QAM FSM Tracking Parameters */
4436 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4439 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4442 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4445 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4448 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4451 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4454 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4460 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4464 /*============================================================================*/
4467 * \brief QAM32 specific setup
4468 * \param demod instance of demod.
4469 * \return DRXStatus_t.
4471 static int SetQAM32(struct drxk_state *state)
4477 /* QAM Equalizer Setup */
4479 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4482 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4485 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4488 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4491 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4494 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4498 /* Decision Feedback Equalizer */
4499 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4502 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4505 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4508 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4511 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4514 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4518 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4521 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4524 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4528 /* QAM Slicer Settings */
4530 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32);
4535 /* QAM Loop Controller Coeficients */
4537 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4540 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4543 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4546 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4549 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4552 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4555 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4558 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4562 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4565 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4568 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4571 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4574 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4577 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4580 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4583 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4586 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4589 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4592 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4595 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4600 /* QAM State Machine (FSM) Thresholds */
4602 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4605 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4608 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4611 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4614 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4617 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4621 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4624 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4627 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4632 /* QAM FSM Tracking Parameters */
4634 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4637 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4640 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4643 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4646 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4649 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4652 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4655 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4659 /*============================================================================*/
4662 * \brief QAM64 specific setup
4663 * \param demod instance of demod.
4664 * \return DRXStatus_t.
4666 static int SetQAM64(struct drxk_state *state)
4671 /* QAM Equalizer Setup */
4673 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4676 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4679 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4682 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4685 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4688 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4692 /* Decision Feedback Equalizer */
4693 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4696 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4699 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4702 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4705 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4708 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4712 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4715 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4718 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4722 /* QAM Slicer Settings */
4723 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64);
4728 /* QAM Loop Controller Coeficients */
4730 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4733 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4736 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4739 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4742 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4745 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4748 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4751 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4755 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4758 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4761 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4764 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4767 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4770 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4773 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4776 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4779 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4782 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4785 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4788 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4793 /* QAM State Machine (FSM) Thresholds */
4795 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4798 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4801 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4804 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4807 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4810 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4814 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4817 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4820 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4825 /* QAM FSM Tracking Parameters */
4827 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4830 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4833 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4836 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4839 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4842 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4845 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4848 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4853 /*============================================================================*/
4856 * \brief QAM128 specific setup
4857 * \param demod: instance of demod.
4858 * \return DRXStatus_t.
4860 static int SetQAM128(struct drxk_state *state)
4865 /* QAM Equalizer Setup */
4867 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4870 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4873 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4876 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4879 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4882 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4886 /* Decision Feedback Equalizer */
4887 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4890 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4893 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4896 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4899 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4902 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4906 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4909 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4912 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4917 /* QAM Slicer Settings */
4919 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128);
4924 /* QAM Loop Controller Coeficients */
4926 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4929 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4932 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4935 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4938 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4941 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4944 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4947 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4951 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4954 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4957 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4960 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4963 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4966 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4969 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4972 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4975 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4978 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4981 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4984 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4989 /* QAM State Machine (FSM) Thresholds */
4991 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4994 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4997 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5000 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5003 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
5006 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
5010 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5013 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
5017 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5021 /* QAM FSM Tracking Parameters */
5023 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5026 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
5029 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
5032 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
5035 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
5038 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5041 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5044 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5049 /*============================================================================*/
5052 * \brief QAM256 specific setup
5053 * \param demod: instance of demod.
5054 * \return DRXStatus_t.
5056 static int SetQAM256(struct drxk_state *state)
5061 /* QAM Equalizer Setup */
5063 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5066 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5069 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5072 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5075 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5078 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5082 /* Decision Feedback Equalizer */
5083 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5086 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5089 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5092 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5095 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5098 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5102 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5105 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5108 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5112 /* QAM Slicer Settings */
5114 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256);
5119 /* QAM Loop Controller Coeficients */
5121 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5124 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5127 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5130 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5133 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5136 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5139 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5142 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5146 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5149 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5152 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5155 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5158 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5161 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5164 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5167 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5170 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5173 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5176 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5179 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5184 /* QAM State Machine (FSM) Thresholds */
5186 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5189 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5192 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5195 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5198 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5201 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5205 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5208 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5211 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5216 /* QAM FSM Tracking Parameters */
5218 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5221 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5224 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5227 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5230 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5233 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5236 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5239 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5244 /*============================================================================*/
5246 * \brief Reset QAM block.
5247 * \param demod: instance of demod.
5248 * \param channel: pointer to channel data.
5249 * \return DRXStatus_t.
5251 static int QAMResetQAM(struct drxk_state *state)
5257 /* Stop QAM comstate->m_exec */
5258 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5262 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
5265 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5269 /*============================================================================*/
5272 * \brief Set QAM symbolrate.
5273 * \param demod: instance of demod.
5274 * \param channel: pointer to channel data.
5275 * \return DRXStatus_t.
5277 static int QAMSetSymbolrate(struct drxk_state *state)
5279 u32 adcFrequency = 0;
5287 /* Select & calculate correct IQM rate */
5288 adcFrequency = (state->m_sysClockFreq * 1000) / 3;
5290 /* printk(KERN_DEBUG "drxk: SR %d\n", state->props.symbol_rate); */
5291 if (state->props.symbol_rate <= 1188750)
5293 else if (state->props.symbol_rate <= 2377500)
5295 else if (state->props.symbol_rate <= 4755000)
5297 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5302 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5304 symbFreq = state->props.symbol_rate * (1 << ratesel);
5305 if (symbFreq == 0) {
5306 /* Divide by zero */
5310 iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) +
5311 (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) -
5313 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate);
5316 state->m_iqmRcRate = iqmRcRate;
5318 LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15))
5320 symbFreq = state->props.symbol_rate;
5321 if (adcFrequency == 0) {
5322 /* Divide by zero */
5326 lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) +
5327 (Frac28a((symbFreq % adcFrequency), adcFrequency) >>
5329 if (lcSymbRate > 511)
5331 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate);
5335 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5339 /*============================================================================*/
5342 * \brief Get QAM lock status.
5343 * \param demod: instance of demod.
5344 * \param channel: pointer to channel data.
5345 * \return DRXStatus_t.
5348 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus)
5351 u16 Result[2] = { 0, 0 };
5354 *pLockStatus = NOT_LOCKED;
5355 status = scu_command(state,
5356 SCU_RAM_COMMAND_STANDARD_QAM |
5357 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
5360 printk(KERN_ERR "drxk: %s status = %08x\n", __func__, status);
5362 if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
5363 /* 0x0000 NOT LOCKED */
5364 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
5365 /* 0x4000 DEMOD LOCKED */
5366 *pLockStatus = DEMOD_LOCK;
5367 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
5368 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
5369 *pLockStatus = MPEG_LOCK;
5371 /* 0xC000 NEVER LOCKED */
5372 /* (system will never be able to lock to the signal) */
5373 /* TODO: check this, intermediate & standard specific lock states are not
5374 taken into account here */
5375 *pLockStatus = NEVER_LOCK;
5380 #define QAM_MIRROR__M 0x03
5381 #define QAM_MIRROR_NORMAL 0x00
5382 #define QAM_MIRRORED 0x01
5383 #define QAM_MIRROR_AUTO_ON 0x02
5384 #define QAM_LOCKRANGE__M 0x10
5385 #define QAM_LOCKRANGE_NORMAL 0x10
5387 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5388 s32 tunerFreqOffset)
5391 u16 setParamParameters[4] = { 0, 0, 0, 0 };
5396 * STEP 1: reset demodulator
5397 * resets FEC DI and FEC RS
5399 * resets SCU variables
5401 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5404 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5407 status = QAMResetQAM(state);
5412 * STEP 2: configure demodulator
5413 * -set params; resets IQM,QAM,FEC HW; initializes some
5416 status = QAMSetSymbolrate(state);
5421 switch (state->props.modulation) {
5423 state->m_Constellation = DRX_CONSTELLATION_QAM256;
5427 state->m_Constellation = DRX_CONSTELLATION_QAM64;
5430 state->m_Constellation = DRX_CONSTELLATION_QAM16;
5433 state->m_Constellation = DRX_CONSTELLATION_QAM32;
5436 state->m_Constellation = DRX_CONSTELLATION_QAM128;
5444 setParamParameters[0] = state->m_Constellation; /* modulation */
5445 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
5446 if (state->m_OperationMode == OM_QAM_ITU_C)
5447 setParamParameters[2] = QAM_TOP_ANNEX_C;
5449 setParamParameters[2] = QAM_TOP_ANNEX_A;
5450 setParamParameters[3] |= (QAM_MIRROR_AUTO_ON);
5451 /* Env parameters */
5452 /* check for LOCKRANGE Extented */
5453 /* setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; */
5455 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 4, setParamParameters, 1, &cmdResult);
5457 /* Fall-back to the simpler call */
5458 if (state->m_OperationMode == OM_QAM_ITU_C)
5459 setParamParameters[0] = QAM_TOP_ANNEX_C;
5461 setParamParameters[0] = QAM_TOP_ANNEX_A;
5462 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 1, setParamParameters, 1, &cmdResult);
5466 setParamParameters[0] = state->m_Constellation; /* modulation */
5467 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
5468 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 2, setParamParameters, 1, &cmdResult);
5474 * STEP 3: enable the system in a mode where the ADC provides valid
5475 * signal setup modulation independent registers
5478 status = SetFrequency(channel, tunerFreqOffset));
5482 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
5486 /* Setup BER measurement */
5487 status = SetQAMMeasurement(state, state->m_Constellation, state->props.symbol_rate);
5491 /* Reset default values */
5492 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5495 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5499 /* Reset default LC values */
5500 status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5503 status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5506 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5509 status = write16(state, QAM_LC_MODE__A, 7);
5513 status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5516 status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5519 status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5522 status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5525 status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5528 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5531 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5534 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5537 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5540 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5543 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5546 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5549 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5552 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5555 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5559 /* Mirroring, QAM-block starting point not inverted */
5560 status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5564 /* Halt SCU to enable safe non-atomic accesses */
5565 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5569 /* STEP 4: modulation specific setup */
5570 switch (state->props.modulation) {
5572 status = SetQAM16(state);
5575 status = SetQAM32(state);
5579 status = SetQAM64(state);
5582 status = SetQAM128(state);
5585 status = SetQAM256(state);
5594 /* Activate SCU to enable SCU commands */
5595 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5599 /* Re-configure MPEG output, requires knowledge of channel bitrate */
5600 /* extAttr->currentChannel.modulation = channel->modulation; */
5601 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */
5602 status = MPEGTSDtoSetup(state, state->m_OperationMode);
5606 /* Start processes */
5607 status = MPEGTSStart(state);
5610 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5613 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5616 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5620 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
5621 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
5625 /* update global DRXK data container */
5626 /*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
5630 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5634 static int SetQAMStandard(struct drxk_state *state,
5635 enum OperationMode oMode)
5638 #ifdef DRXK_QAM_TAPS
5639 #define DRXK_QAMA_TAPS_SELECT
5640 #include "drxk_filters.h"
5641 #undef DRXK_QAMA_TAPS_SELECT
5646 /* added antenna switch */
5647 SwitchAntennaToQAM(state);
5649 /* Ensure correct power-up mode */
5650 status = PowerUpQAM(state);
5653 /* Reset QAM block */
5654 status = QAMResetQAM(state);
5660 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5663 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5667 /* Upload IQM Channel Filter settings by
5668 boot loader from ROM table */
5671 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5674 status = BLDirectCmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5677 status = BLDirectCmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5685 status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B));
5688 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5691 status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5695 status = write16(state, IQM_RC_STRETCH__A, 21);
5698 status = write16(state, IQM_AF_CLP_LEN__A, 0);
5701 status = write16(state, IQM_AF_CLP_TH__A, 448);
5704 status = write16(state, IQM_AF_SNS_LEN__A, 0);
5707 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5711 status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5714 status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5717 status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5720 status = write16(state, IQM_AF_UPD_SEL__A, 0);
5724 /* IQM Impulse Noise Processing Unit */
5725 status = write16(state, IQM_CF_CLP_VAL__A, 500);
5728 status = write16(state, IQM_CF_DATATH__A, 1000);
5731 status = write16(state, IQM_CF_BYPASSDET__A, 1);
5734 status = write16(state, IQM_CF_DET_LCT__A, 0);
5737 status = write16(state, IQM_CF_WND_LEN__A, 1);
5740 status = write16(state, IQM_CF_PKDTH__A, 1);
5743 status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5747 /* turn on IQMAF. Must be done before setAgc**() */
5748 status = SetIqmAf(state, true);
5751 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5755 /* IQM will not be reset from here, sync ADC and update/init AGC */
5756 status = ADCSynchronization(state);
5760 /* Set the FSM step period */
5761 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5765 /* Halt SCU to enable safe non-atomic accesses */
5766 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5770 /* No more resets of the IQM, current standard correctly set =>
5771 now AGCs can be configured. */
5773 status = InitAGC(state, true);
5776 status = SetPreSaw(state, &(state->m_qamPreSawCfg));
5780 /* Configure AGC's */
5781 status = SetAgcRf(state, &(state->m_qamRfAgcCfg), true);
5784 status = SetAgcIf(state, &(state->m_qamIfAgcCfg), true);
5788 /* Activate SCU to enable SCU commands */
5789 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5792 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5796 static int WriteGPIO(struct drxk_state *state)
5802 /* stop lock indicator process */
5803 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5807 /* Write magic word to enable pdr reg write */
5808 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5812 if (state->m_hasSAWSW) {
5813 if (state->UIO_mask & 0x0001) { /* UIO-1 */
5814 /* write to io pad configuration register - output mode */
5815 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5819 /* use corresponding bit in io data output registar */
5820 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5823 if ((state->m_GPIO & 0x0001) == 0)
5824 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
5826 value |= 0x8000; /* write one to 15th bit - 1st UIO */
5827 /* write back to io data output register */
5828 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5832 if (state->UIO_mask & 0x0002) { /* UIO-2 */
5833 /* write to io pad configuration register - output mode */
5834 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5838 /* use corresponding bit in io data output registar */
5839 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5842 if ((state->m_GPIO & 0x0002) == 0)
5843 value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */
5845 value |= 0x4000; /* write one to 14th bit - 2st UIO */
5846 /* write back to io data output register */
5847 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5851 if (state->UIO_mask & 0x0004) { /* UIO-3 */
5852 /* write to io pad configuration register - output mode */
5853 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5857 /* use corresponding bit in io data output registar */
5858 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5861 if ((state->m_GPIO & 0x0004) == 0)
5862 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
5864 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */
5865 /* write back to io data output register */
5866 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5871 /* Write magic word to disable pdr reg write */
5872 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5875 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5879 static int SwitchAntennaToQAM(struct drxk_state *state)
5886 if (!state->antenna_gpio)
5889 gpio_state = state->m_GPIO & state->antenna_gpio;
5891 if (state->antenna_dvbt ^ gpio_state) {
5892 /* Antenna is on DVB-T mode. Switch */
5893 if (state->antenna_dvbt)
5894 state->m_GPIO &= ~state->antenna_gpio;
5896 state->m_GPIO |= state->antenna_gpio;
5897 status = WriteGPIO(state);
5900 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5904 static int SwitchAntennaToDVBT(struct drxk_state *state)
5911 if (!state->antenna_gpio)
5914 gpio_state = state->m_GPIO & state->antenna_gpio;
5916 if (!(state->antenna_dvbt ^ gpio_state)) {
5917 /* Antenna is on DVB-C mode. Switch */
5918 if (state->antenna_dvbt)
5919 state->m_GPIO |= state->antenna_gpio;
5921 state->m_GPIO &= ~state->antenna_gpio;
5922 status = WriteGPIO(state);
5925 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5930 static int PowerDownDevice(struct drxk_state *state)
5932 /* Power down to requested mode */
5933 /* Backup some register settings */
5934 /* Set pins with possible pull-ups connected to them in input mode */
5935 /* Analog power down */
5936 /* ADC power down */
5937 /* Power down device */
5941 if (state->m_bPDownOpenBridge) {
5942 /* Open I2C bridge before power down of DRXK */
5943 status = ConfigureI2CBridge(state, true);
5948 status = DVBTEnableOFDMTokenRing(state, false);
5952 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK);
5955 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5958 state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
5959 status = HI_CfgCommand(state);
5962 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5967 static int load_microcode(struct drxk_state *state, const char *mc_name)
5969 const struct firmware *fw = NULL;
5974 err = request_firmware(&fw, mc_name, state->i2c->dev.parent);
5977 "drxk: Could not load firmware file %s.\n", mc_name);
5979 "drxk: Copy %s to your hotplug directory!\n", mc_name);
5982 err = DownloadMicrocode(state, fw->data, fw->size);
5983 release_firmware(fw);
5987 static int init_drxk(struct drxk_state *state)
5990 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
5994 if ((state->m_DrxkState == DRXK_UNINITIALIZED)) {
5995 status = PowerUpDevice(state);
5998 status = DRXX_Open(state);
6001 /* Soft reset of OFDM-, sys- and osc-clockdomain */
6002 status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M);
6005 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6008 /* TODO is this needed, if yes how much delay in worst case scenario */
6010 state->m_DRXK_A3_PATCH_CODE = true;
6011 status = GetDeviceCapabilities(state);
6015 /* Bridge delay, uses oscilator clock */
6016 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
6017 /* SDA brdige delay */
6018 state->m_HICfgBridgeDelay =
6019 (u16) ((state->m_oscClockFreq / 1000) *
6020 HI_I2C_BRIDGE_DELAY) / 1000;
6022 if (state->m_HICfgBridgeDelay >
6023 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
6024 state->m_HICfgBridgeDelay =
6025 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
6027 /* SCL bridge delay, same as SDA for now */
6028 state->m_HICfgBridgeDelay +=
6029 state->m_HICfgBridgeDelay <<
6030 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
6032 status = InitHI(state);
6035 /* disable various processes */
6037 if (!(state->m_DRXK_A1_ROM_CODE)
6038 && !(state->m_DRXK_A2_ROM_CODE))
6041 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
6046 /* disable MPEG port */
6047 status = MPEGTSDisable(state);
6051 /* Stop AUD and SCU */
6052 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6055 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6059 /* enable token-ring bus through OFDM block for possible ucode upload */
6060 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
6064 /* include boot loader section */
6065 status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE);
6068 status = BLChainCmd(state, 0, 6, 100);
6072 if (!state->microcode_name)
6073 load_microcode(state, "drxk_a3.mc");
6075 load_microcode(state, state->microcode_name);
6077 /* disable token-ring bus through OFDM block for possible ucode upload */
6078 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6082 /* Run SCU for a little while to initialize microcode version numbers */
6083 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6086 status = DRXX_Open(state);
6089 /* added for test */
6092 powerMode = DRXK_POWER_DOWN_OFDM;
6093 status = CtrlPowerMode(state, &powerMode);
6097 /* Stamp driver version number in SCU data RAM in BCD code
6098 Done to enable field application engineers to retreive drxdriver version
6099 via I2C from SCU RAM.
6100 Not using SCU command interface for SCU register access since no
6101 microcode may be present.
6104 (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6105 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6106 ((DRXK_VERSION_MAJOR % 10) << 4) +
6107 (DRXK_VERSION_MINOR % 10);
6108 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion);
6112 (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6113 (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6114 (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6115 (DRXK_VERSION_PATCH % 10);
6116 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion);
6120 printk(KERN_INFO "DRXK driver version %d.%d.%d\n",
6121 DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6122 DRXK_VERSION_PATCH);
6124 /* Dirty fix of default values for ROM/PATCH microcode
6125 Dirty because this fix makes it impossible to setup suitable values
6126 before calling DRX_Open. This solution requires changes to RF AGC speed
6127 to be done via the CTRL function after calling DRX_Open */
6129 /* m_dvbtRfAgcCfg.speed = 3; */
6131 /* Reset driver debug flags to 0 */
6132 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6137 NOTE: No more full FEC resets allowed afterwards!! */
6138 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6141 /* MPEGTS functions are still the same */
6142 status = MPEGTSDtoInit(state);
6145 status = MPEGTSStop(state);
6148 status = MPEGTSConfigurePolarity(state);
6151 status = MPEGTSConfigurePins(state, state->m_enableMPEGOutput);
6154 /* added: configure GPIO */
6155 status = WriteGPIO(state);
6159 state->m_DrxkState = DRXK_STOPPED;
6161 if (state->m_bPowerDown) {
6162 status = PowerDownDevice(state);
6165 state->m_DrxkState = DRXK_POWERED_DOWN;
6167 state->m_DrxkState = DRXK_STOPPED;
6171 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
6176 static void drxk_release(struct dvb_frontend *fe)
6178 struct drxk_state *state = fe->demodulator_priv;
6184 static int drxk_sleep(struct dvb_frontend *fe)
6186 struct drxk_state *state = fe->demodulator_priv;
6193 static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
6195 struct drxk_state *state = fe->demodulator_priv;
6197 dprintk(1, "%s\n", enable ? "enable" : "disable");
6198 return ConfigureI2CBridge(state, enable ? true : false);
6201 static int drxk_set_parameters(struct dvb_frontend *fe)
6203 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6204 u32 delsys = p->delivery_system, old_delsys;
6205 struct drxk_state *state = fe->demodulator_priv;
6210 if (!fe->ops.tuner_ops.get_if_frequency) {
6212 "drxk: Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
6216 if (fe->ops.i2c_gate_ctrl)
6217 fe->ops.i2c_gate_ctrl(fe, 1);
6218 if (fe->ops.tuner_ops.set_params)
6219 fe->ops.tuner_ops.set_params(fe);
6220 if (fe->ops.i2c_gate_ctrl)
6221 fe->ops.i2c_gate_ctrl(fe, 0);
6223 old_delsys = state->props.delivery_system;
6226 if (old_delsys != delsys) {
6229 case SYS_DVBC_ANNEX_A:
6230 case SYS_DVBC_ANNEX_C:
6231 if (!state->m_hasDVBC)
6233 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? true : false;
6234 if (state->m_itut_annex_c)
6235 SetOperationMode(state, OM_QAM_ITU_C);
6237 SetOperationMode(state, OM_QAM_ITU_A);
6240 if (!state->m_hasDVBT)
6242 SetOperationMode(state, OM_DVBT);
6249 fe->ops.tuner_ops.get_if_frequency(fe, &IF);
6250 Start(state, 0, IF);
6252 /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */
6257 static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status)
6259 struct drxk_state *state = fe->demodulator_priv;
6264 GetLockStatus(state, &stat, 0);
6265 if (stat == MPEG_LOCK)
6267 if (stat == FEC_LOCK)
6269 if (stat == DEMOD_LOCK)
6274 static int drxk_read_ber(struct dvb_frontend *fe, u32 *ber)
6282 static int drxk_read_signal_strength(struct dvb_frontend *fe,
6285 struct drxk_state *state = fe->demodulator_priv;
6289 ReadIFAgc(state, &val);
6290 *strength = val & 0xffff;
6294 static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
6296 struct drxk_state *state = fe->demodulator_priv;
6300 GetSignalToNoise(state, &snr2);
6301 *snr = snr2 & 0xffff;
6305 static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6307 struct drxk_state *state = fe->demodulator_priv;
6311 DVBTQAMGetAccPktErr(state, &err);
6312 *ucblocks = (u32) err;
6316 static int drxk_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings
6319 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6322 switch (p->delivery_system) {
6323 case SYS_DVBC_ANNEX_A:
6324 case SYS_DVBC_ANNEX_C:
6325 sets->min_delay_ms = 3000;
6326 sets->max_drift = 0;
6327 sets->step_size = 0;
6331 * For DVB-T, let it use the default DVB core way, that is:
6332 * fepriv->step_size = fe->ops.info.frequency_stepsize * 2
6338 static struct dvb_frontend_ops drxk_ops = {
6339 /* .delsys will be filled dynamically */
6342 .frequency_min = 47000000,
6343 .frequency_max = 865000000,
6345 .symbol_rate_min = 870000,
6346 .symbol_rate_max = 11700000,
6348 .frequency_stepsize = 166667,
6350 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
6351 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO |
6352 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
6353 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS |
6354 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
6355 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO
6358 .release = drxk_release,
6359 .sleep = drxk_sleep,
6360 .i2c_gate_ctrl = drxk_gate_ctrl,
6362 .set_frontend = drxk_set_parameters,
6363 .get_tune_settings = drxk_get_tune_settings,
6365 .read_status = drxk_read_status,
6366 .read_ber = drxk_read_ber,
6367 .read_signal_strength = drxk_read_signal_strength,
6368 .read_snr = drxk_read_snr,
6369 .read_ucblocks = drxk_read_ucblocks,
6372 struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6373 struct i2c_adapter *i2c)
6377 struct drxk_state *state = NULL;
6378 u8 adr = config->adr;
6381 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
6386 state->demod_address = adr;
6387 state->single_master = config->single_master;
6388 state->microcode_name = config->microcode_name;
6389 state->no_i2c_bridge = config->no_i2c_bridge;
6390 state->antenna_gpio = config->antenna_gpio;
6391 state->antenna_dvbt = config->antenna_dvbt;
6392 state->m_ChunkSize = config->chunk_size;
6394 if (config->parallel_ts)
6395 state->m_enableParallel = true;
6397 state->m_enableParallel = false;
6399 /* NOTE: as more UIO bits will be used, add them to the mask */
6400 state->UIO_mask = config->antenna_gpio;
6402 /* Default gpio to DVB-C */
6403 if (!state->antenna_dvbt && state->antenna_gpio)
6404 state->m_GPIO |= state->antenna_gpio;
6406 state->m_GPIO &= ~state->antenna_gpio;
6408 mutex_init(&state->mutex);
6410 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));
6411 state->frontend.demodulator_priv = state;
6414 if (init_drxk(state) < 0)
6417 /* Initialize the supported delivery systems */
6419 if (state->m_hasDVBC) {
6420 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
6421 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
6422 strlcat(state->frontend.ops.info.name, " DVB-C",
6423 sizeof(state->frontend.ops.info.name));
6425 if (state->m_hasDVBT) {
6426 state->frontend.ops.delsys[n++] = SYS_DVBT;
6427 strlcat(state->frontend.ops.info.name, " DVB-T",
6428 sizeof(state->frontend.ops.info.name));
6431 printk(KERN_INFO "drxk: frontend initialized.\n");
6432 return &state->frontend;
6435 printk(KERN_ERR "drxk: not found\n");
6439 EXPORT_SYMBOL(drxk_attach);
6441 MODULE_DESCRIPTION("DRX-K driver");
6442 MODULE_AUTHOR("Ralph Metzler");
6443 MODULE_LICENSE("GPL");