1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (c) 2018 MediaTek Inc.
5 #include <linux/bitops.h>
7 #include <linux/clk-provider.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/errno.h>
10 #include <linux/interrupt.h>
12 #include <linux/iopoll.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/mailbox_controller.h>
17 #include <linux/mailbox/mtk-cmdq-mailbox.h>
18 #include <linux/of_device.h>
20 #define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT)
21 #define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE)
22 #define CMDQ_GCE_NUM_MAX (2)
24 #define CMDQ_CURR_IRQ_STATUS 0x10
25 #define CMDQ_SYNC_TOKEN_UPDATE 0x68
26 #define CMDQ_THR_SLOT_CYCLES 0x30
27 #define CMDQ_THR_BASE 0x100
28 #define CMDQ_THR_SIZE 0x80
29 #define CMDQ_THR_WARM_RESET 0x00
30 #define CMDQ_THR_ENABLE_TASK 0x04
31 #define CMDQ_THR_SUSPEND_TASK 0x08
32 #define CMDQ_THR_CURR_STATUS 0x0c
33 #define CMDQ_THR_IRQ_STATUS 0x10
34 #define CMDQ_THR_IRQ_ENABLE 0x14
35 #define CMDQ_THR_CURR_ADDR 0x20
36 #define CMDQ_THR_END_ADDR 0x24
37 #define CMDQ_THR_WAIT_TOKEN 0x30
38 #define CMDQ_THR_PRIORITY 0x40
40 #define GCE_GCTL_VALUE 0x48
42 #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200
43 #define CMDQ_THR_ENABLED 0x1
44 #define CMDQ_THR_DISABLED 0x0
45 #define CMDQ_THR_SUSPEND 0x1
46 #define CMDQ_THR_RESUME 0x0
47 #define CMDQ_THR_STATUS_SUSPENDED BIT(1)
48 #define CMDQ_THR_DO_WARM_RESET BIT(0)
49 #define CMDQ_THR_IRQ_DONE 0x1
50 #define CMDQ_THR_IRQ_ERROR 0x12
51 #define CMDQ_THR_IRQ_EN (CMDQ_THR_IRQ_ERROR | CMDQ_THR_IRQ_DONE)
52 #define CMDQ_THR_IS_WAITING BIT(31)
54 #define CMDQ_JUMP_BY_OFFSET 0x10000000
55 #define CMDQ_JUMP_BY_PA 0x10000001
58 struct mbox_chan *chan;
60 struct list_head task_busy_list;
66 struct list_head list_entry;
68 struct cmdq_thread *thread;
69 struct cmdq_pkt *pkt; /* the packet sent from mailbox client */
73 struct mbox_controller mbox;
78 struct cmdq_thread *thread;
79 struct clk_bulk_data clocks[CMDQ_GCE_NUM_MAX];
93 u8 cmdq_get_shift_pa(struct mbox_chan *chan)
95 struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
97 return cmdq->shift_pa;
99 EXPORT_SYMBOL(cmdq_get_shift_pa);
101 static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread)
105 writel(CMDQ_THR_SUSPEND, thread->base + CMDQ_THR_SUSPEND_TASK);
107 /* If already disabled, treat as suspended successful. */
108 if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
111 if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_STATUS,
112 status, status & CMDQ_THR_STATUS_SUSPENDED, 0, 10)) {
113 dev_err(cmdq->mbox.dev, "suspend GCE thread 0x%x failed\n",
114 (u32)(thread->base - cmdq->base));
121 static void cmdq_thread_resume(struct cmdq_thread *thread)
123 writel(CMDQ_THR_RESUME, thread->base + CMDQ_THR_SUSPEND_TASK);
126 static void cmdq_init(struct cmdq *cmdq)
130 WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
131 if (cmdq->control_by_sw)
132 writel(0x7, cmdq->base + GCE_GCTL_VALUE);
133 writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
134 for (i = 0; i <= CMDQ_MAX_EVENT; i++)
135 writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
136 clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
139 static int cmdq_thread_reset(struct cmdq *cmdq, struct cmdq_thread *thread)
143 writel(CMDQ_THR_DO_WARM_RESET, thread->base + CMDQ_THR_WARM_RESET);
144 if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_WARM_RESET,
145 warm_reset, !(warm_reset & CMDQ_THR_DO_WARM_RESET),
147 dev_err(cmdq->mbox.dev, "reset GCE thread 0x%x failed\n",
148 (u32)(thread->base - cmdq->base));
155 static void cmdq_thread_disable(struct cmdq *cmdq, struct cmdq_thread *thread)
157 cmdq_thread_reset(cmdq, thread);
158 writel(CMDQ_THR_DISABLED, thread->base + CMDQ_THR_ENABLE_TASK);
161 /* notify GCE to re-fetch commands by setting GCE thread PC */
162 static void cmdq_thread_invalidate_fetched_data(struct cmdq_thread *thread)
164 writel(readl(thread->base + CMDQ_THR_CURR_ADDR),
165 thread->base + CMDQ_THR_CURR_ADDR);
168 static void cmdq_task_insert_into_thread(struct cmdq_task *task)
170 struct device *dev = task->cmdq->mbox.dev;
171 struct cmdq_thread *thread = task->thread;
172 struct cmdq_task *prev_task = list_last_entry(
173 &thread->task_busy_list, typeof(*task), list_entry);
174 u64 *prev_task_base = prev_task->pkt->va_base;
176 /* let previous task jump to this task */
177 dma_sync_single_for_cpu(dev, prev_task->pa_base,
178 prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
179 prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] =
180 (u64)CMDQ_JUMP_BY_PA << 32 |
181 (task->pa_base >> task->cmdq->shift_pa);
182 dma_sync_single_for_device(dev, prev_task->pa_base,
183 prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
185 cmdq_thread_invalidate_fetched_data(thread);
188 static bool cmdq_thread_is_in_wfe(struct cmdq_thread *thread)
190 return readl(thread->base + CMDQ_THR_WAIT_TOKEN) & CMDQ_THR_IS_WAITING;
193 static void cmdq_task_exec_done(struct cmdq_task *task, int sta)
195 struct cmdq_task_cb *cb = &task->pkt->async_cb;
196 struct cmdq_cb_data data;
199 data.data = cb->data;
200 data.pkt = task->pkt;
204 mbox_chan_received_data(task->thread->chan, &data);
206 list_del(&task->list_entry);
209 static void cmdq_task_handle_error(struct cmdq_task *task)
211 struct cmdq_thread *thread = task->thread;
212 struct cmdq_task *next_task;
213 struct cmdq *cmdq = task->cmdq;
215 dev_err(cmdq->mbox.dev, "task 0x%p error\n", task);
216 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
217 next_task = list_first_entry_or_null(&thread->task_busy_list,
218 struct cmdq_task, list_entry);
220 writel(next_task->pa_base >> cmdq->shift_pa,
221 thread->base + CMDQ_THR_CURR_ADDR);
222 cmdq_thread_resume(thread);
225 static void cmdq_thread_irq_handler(struct cmdq *cmdq,
226 struct cmdq_thread *thread)
228 struct cmdq_task *task, *tmp, *curr_task = NULL;
229 u32 curr_pa, irq_flag, task_end_pa;
232 irq_flag = readl(thread->base + CMDQ_THR_IRQ_STATUS);
233 writel(~irq_flag, thread->base + CMDQ_THR_IRQ_STATUS);
236 * When ISR call this function, another CPU core could run
237 * "release task" right before we acquire the spin lock, and thus
238 * reset / disable this GCE thread, so we need to check the enable
239 * bit of this GCE thread.
241 if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
244 if (irq_flag & CMDQ_THR_IRQ_ERROR)
246 else if (irq_flag & CMDQ_THR_IRQ_DONE)
251 curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->shift_pa;
253 list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
255 task_end_pa = task->pa_base + task->pkt->cmd_buf_size;
256 if (curr_pa >= task->pa_base && curr_pa < task_end_pa)
259 if (!curr_task || curr_pa == task_end_pa - CMDQ_INST_SIZE) {
260 cmdq_task_exec_done(task, 0);
263 cmdq_task_exec_done(task, -ENOEXEC);
264 cmdq_task_handle_error(curr_task);
272 if (list_empty(&thread->task_busy_list)) {
273 cmdq_thread_disable(cmdq, thread);
274 clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
278 static irqreturn_t cmdq_irq_handler(int irq, void *dev)
280 struct cmdq *cmdq = dev;
281 unsigned long irq_status, flags = 0L;
284 irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & cmdq->irq_mask;
285 if (!(irq_status ^ cmdq->irq_mask))
288 for_each_clear_bit(bit, &irq_status, cmdq->thread_nr) {
289 struct cmdq_thread *thread = &cmdq->thread[bit];
291 spin_lock_irqsave(&thread->chan->lock, flags);
292 cmdq_thread_irq_handler(cmdq, thread);
293 spin_unlock_irqrestore(&thread->chan->lock, flags);
299 static int cmdq_suspend(struct device *dev)
301 struct cmdq *cmdq = dev_get_drvdata(dev);
302 struct cmdq_thread *thread;
304 bool task_running = false;
306 cmdq->suspended = true;
308 for (i = 0; i < cmdq->thread_nr; i++) {
309 thread = &cmdq->thread[i];
310 if (!list_empty(&thread->task_busy_list)) {
317 dev_warn(dev, "exist running task(s) in suspend\n");
319 clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
324 static int cmdq_resume(struct device *dev)
326 struct cmdq *cmdq = dev_get_drvdata(dev);
328 WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks));
329 cmdq->suspended = false;
333 static int cmdq_remove(struct platform_device *pdev)
335 struct cmdq *cmdq = platform_get_drvdata(pdev);
337 clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
341 static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
343 struct cmdq_pkt *pkt = (struct cmdq_pkt *)data;
344 struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
345 struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
346 struct cmdq_task *task;
347 unsigned long curr_pa, end_pa;
349 /* Client should not flush new tasks if suspended. */
350 WARN_ON(cmdq->suspended);
352 task = kzalloc(sizeof(*task), GFP_ATOMIC);
357 INIT_LIST_HEAD(&task->list_entry);
358 task->pa_base = pkt->pa_base;
359 task->thread = thread;
362 if (list_empty(&thread->task_busy_list)) {
363 WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
366 * The thread reset will clear thread related register to 0,
367 * including pc, end, priority, irq, suspend and enable. Thus
368 * set CMDQ_THR_ENABLED to CMDQ_THR_ENABLE_TASK will enable
369 * thread and make it running.
371 WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
373 writel(task->pa_base >> cmdq->shift_pa,
374 thread->base + CMDQ_THR_CURR_ADDR);
375 writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
376 thread->base + CMDQ_THR_END_ADDR);
378 writel(thread->priority, thread->base + CMDQ_THR_PRIORITY);
379 writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE);
380 writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK);
382 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
383 curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) <<
385 end_pa = readl(thread->base + CMDQ_THR_END_ADDR) <<
388 if (curr_pa == end_pa - CMDQ_INST_SIZE ||
390 /* set to this task directly */
391 writel(task->pa_base >> cmdq->shift_pa,
392 thread->base + CMDQ_THR_CURR_ADDR);
394 cmdq_task_insert_into_thread(task);
395 smp_mb(); /* modify jump before enable thread */
397 writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
398 thread->base + CMDQ_THR_END_ADDR);
399 cmdq_thread_resume(thread);
401 list_move_tail(&task->list_entry, &thread->task_busy_list);
406 static int cmdq_mbox_startup(struct mbox_chan *chan)
411 static void cmdq_mbox_shutdown(struct mbox_chan *chan)
413 struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
414 struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
415 struct cmdq_task *task, *tmp;
418 spin_lock_irqsave(&thread->chan->lock, flags);
419 if (list_empty(&thread->task_busy_list))
422 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
424 /* make sure executed tasks have success callback */
425 cmdq_thread_irq_handler(cmdq, thread);
426 if (list_empty(&thread->task_busy_list))
429 list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
431 cmdq_task_exec_done(task, -ECONNABORTED);
435 cmdq_thread_disable(cmdq, thread);
436 clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
440 * The thread->task_busy_list empty means thread already disable. The
441 * cmdq_mbox_send_data() always reset thread which clear disable and
442 * suspend statue when first pkt send to channel, so there is no need
443 * to do any operation here, only unlock and leave.
445 spin_unlock_irqrestore(&thread->chan->lock, flags);
448 static int cmdq_mbox_flush(struct mbox_chan *chan, unsigned long timeout)
450 struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
451 struct cmdq_task_cb *cb;
452 struct cmdq_cb_data data;
453 struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
454 struct cmdq_task *task, *tmp;
458 spin_lock_irqsave(&thread->chan->lock, flags);
459 if (list_empty(&thread->task_busy_list))
462 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
463 if (!cmdq_thread_is_in_wfe(thread))
466 list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
468 cb = &task->pkt->async_cb;
469 data.sta = -ECONNABORTED;
470 data.data = cb->data;
471 data.pkt = task->pkt;
475 mbox_chan_received_data(task->thread->chan, &data);
476 list_del(&task->list_entry);
480 cmdq_thread_resume(thread);
481 cmdq_thread_disable(cmdq, thread);
482 clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
485 spin_unlock_irqrestore(&thread->chan->lock, flags);
489 cmdq_thread_resume(thread);
490 spin_unlock_irqrestore(&thread->chan->lock, flags);
491 if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_ENABLE_TASK,
492 enable, enable == 0, 1, timeout)) {
493 dev_err(cmdq->mbox.dev, "Fail to wait GCE thread 0x%x done\n",
494 (u32)(thread->base - cmdq->base));
501 static const struct mbox_chan_ops cmdq_mbox_chan_ops = {
502 .send_data = cmdq_mbox_send_data,
503 .startup = cmdq_mbox_startup,
504 .shutdown = cmdq_mbox_shutdown,
505 .flush = cmdq_mbox_flush,
508 static struct mbox_chan *cmdq_xlate(struct mbox_controller *mbox,
509 const struct of_phandle_args *sp)
511 int ind = sp->args[0];
512 struct cmdq_thread *thread;
514 if (ind >= mbox->num_chans)
515 return ERR_PTR(-EINVAL);
517 thread = (struct cmdq_thread *)mbox->chans[ind].con_priv;
518 thread->priority = sp->args[1];
519 thread->chan = &mbox->chans[ind];
521 return &mbox->chans[ind];
524 static int cmdq_probe(struct platform_device *pdev)
526 struct device *dev = &pdev->dev;
527 struct resource *res;
530 struct gce_plat *plat_data;
531 struct device_node *phandle = dev->of_node;
532 struct device_node *node;
534 static const char * const clk_name = "gce";
535 static const char * const clk_names[] = { "gce0", "gce1" };
537 cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL);
541 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
542 cmdq->base = devm_ioremap_resource(dev, res);
543 if (IS_ERR(cmdq->base))
544 return PTR_ERR(cmdq->base);
546 cmdq->irq = platform_get_irq(pdev, 0);
550 plat_data = (struct gce_plat *)of_device_get_match_data(dev);
552 dev_err(dev, "failed to get match data\n");
556 cmdq->thread_nr = plat_data->thread_nr;
557 cmdq->shift_pa = plat_data->shift;
558 cmdq->control_by_sw = plat_data->control_by_sw;
559 cmdq->gce_num = plat_data->gce_num;
560 cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
561 err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
564 dev_err(dev, "failed to register ISR (%d)\n", err);
568 dev_dbg(dev, "cmdq device: addr:0x%p, va:0x%p, irq:%d\n",
569 dev, cmdq->base, cmdq->irq);
571 if (cmdq->gce_num > 1) {
572 for_each_child_of_node(phandle->parent, node) {
573 alias_id = of_alias_get_id(node, clk_name);
574 if (alias_id >= 0 && alias_id < cmdq->gce_num) {
575 cmdq->clocks[alias_id].id = clk_names[alias_id];
576 cmdq->clocks[alias_id].clk = of_clk_get(node, 0);
577 if (IS_ERR(cmdq->clocks[alias_id].clk)) {
578 dev_err(dev, "failed to get gce clk: %d\n", alias_id);
579 return PTR_ERR(cmdq->clocks[alias_id].clk);
584 cmdq->clocks[alias_id].id = clk_name;
585 cmdq->clocks[alias_id].clk = devm_clk_get(&pdev->dev, clk_name);
586 if (IS_ERR(cmdq->clocks[alias_id].clk)) {
587 dev_err(dev, "failed to get gce clk\n");
588 return PTR_ERR(cmdq->clocks[alias_id].clk);
592 cmdq->mbox.dev = dev;
593 cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr,
594 sizeof(*cmdq->mbox.chans), GFP_KERNEL);
595 if (!cmdq->mbox.chans)
598 cmdq->mbox.num_chans = cmdq->thread_nr;
599 cmdq->mbox.ops = &cmdq_mbox_chan_ops;
600 cmdq->mbox.of_xlate = cmdq_xlate;
602 /* make use of TXDONE_BY_ACK */
603 cmdq->mbox.txdone_irq = false;
604 cmdq->mbox.txdone_poll = false;
606 cmdq->thread = devm_kcalloc(dev, cmdq->thread_nr,
607 sizeof(*cmdq->thread), GFP_KERNEL);
611 for (i = 0; i < cmdq->thread_nr; i++) {
612 cmdq->thread[i].base = cmdq->base + CMDQ_THR_BASE +
614 INIT_LIST_HEAD(&cmdq->thread[i].task_busy_list);
615 cmdq->mbox.chans[i].con_priv = (void *)&cmdq->thread[i];
618 err = devm_mbox_controller_register(dev, &cmdq->mbox);
620 dev_err(dev, "failed to register mailbox: %d\n", err);
624 platform_set_drvdata(pdev, cmdq);
626 WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks));
633 static const struct dev_pm_ops cmdq_pm_ops = {
634 .suspend = cmdq_suspend,
635 .resume = cmdq_resume,
638 static const struct gce_plat gce_plat_v2 = {
641 .control_by_sw = false,
645 static const struct gce_plat gce_plat_v3 = {
648 .control_by_sw = false,
652 static const struct gce_plat gce_plat_v4 = {
655 .control_by_sw = false,
659 static const struct gce_plat gce_plat_v5 = {
662 .control_by_sw = true,
666 static const struct gce_plat gce_plat_v6 = {
669 .control_by_sw = false,
673 static const struct of_device_id cmdq_of_ids[] = {
674 {.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2},
675 {.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3},
676 {.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4},
677 {.compatible = "mediatek,mt8192-gce", .data = (void *)&gce_plat_v5},
678 {.compatible = "mediatek,mt8195-gce", .data = (void *)&gce_plat_v6},
682 static struct platform_driver cmdq_drv = {
684 .remove = cmdq_remove,
688 .of_match_table = cmdq_of_ids,
692 static int __init cmdq_drv_init(void)
694 return platform_driver_register(&cmdq_drv);
697 static void __exit cmdq_drv_exit(void)
699 platform_driver_unregister(&cmdq_drv);
702 subsys_initcall(cmdq_drv_init);
703 module_exit(cmdq_drv_exit);
705 MODULE_LICENSE("GPL v2");