drivers/mailbox/imx-mailbox.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/firmware/imx/ipc.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/io.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/kernel.h>
  12 #include <linux/mailbox_controller.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/suspend.h>
  17 #include <linux/slab.h>
  18
  19 #define IMX_MU_CHANS            16
  20 /* TX0/RX0/RXDB[0-3] */
  21 #define IMX_MU_SCU_CHANS        6
  22 #define IMX_MU_CHAN_NAME_SIZE   20
  23
  24 enum imx_mu_chan_type {
  25         IMX_MU_TYPE_TX,         /* Tx */
  26         IMX_MU_TYPE_RX,         /* Rx */
  27         IMX_MU_TYPE_TXDB,       /* Tx doorbell */
  28         IMX_MU_TYPE_RXDB,       /* Rx doorbell */
  29 };
  30
  31 enum imx_mu_xcr {
  32         IMX_MU_GIER,
  33         IMX_MU_GCR,
  34         IMX_MU_TCR,
  35         IMX_MU_RCR,
  36         IMX_MU_xCR_MAX,
  37 };
  38
  39 enum imx_mu_xsr {
  40         IMX_MU_SR,
  41         IMX_MU_GSR,
  42         IMX_MU_TSR,
  43         IMX_MU_RSR,
  44 };
  45
  46 struct imx_sc_rpc_msg_max {
  47         struct imx_sc_rpc_msg hdr;
  48         u32 data[7];
  49 };
  50
  51 struct imx_mu_con_priv {
  52         unsigned int            idx;
  53         char                    irq_desc[IMX_MU_CHAN_NAME_SIZE];
  54         enum imx_mu_chan_type   type;
  55         struct mbox_chan        *chan;
  56         struct tasklet_struct   txdb_tasklet;
  57 };
  58
  59 struct imx_mu_priv {
  60         struct device           *dev;
  61         void __iomem            *base;
  62         spinlock_t              xcr_lock; /* control register lock */
  63
  64         struct mbox_controller  mbox;
  65         struct mbox_chan        mbox_chans[IMX_MU_CHANS];
  66
  67         struct imx_mu_con_priv  con_priv[IMX_MU_CHANS];
  68         const struct imx_mu_dcfg        *dcfg;
  69         struct clk              *clk;
  70         int                     irq;
  71         bool                    suspend;
  72
  73         u32 xcr[4];
  74
  75         bool                    side_b;
  76 };
  77
  78 enum imx_mu_type {
  79         IMX_MU_V1,
  80         IMX_MU_V2,
  81 };
  82
  83 struct imx_mu_dcfg {
  84         int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
  85         int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
  86         void (*init)(struct imx_mu_priv *priv);
  87         enum imx_mu_type type;
  88         u32     xTR;            /* Transmit Register0 */
  89         u32     xRR;            /* Receive Register0 */
  90         u32     xSR[4];         /* Status Registers */
  91         u32     xCR[4];         /* Control Registers */
  92 };
  93
  94 #define IMX_MU_xSR_GIPn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
  95 #define IMX_MU_xSR_RFn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
  96 #define IMX_MU_xSR_TEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
  97
  98 /* General Purpose Interrupt Enable */
  99 #define IMX_MU_xCR_GIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
 100 /* Receive Interrupt Enable */
 101 #define IMX_MU_xCR_RIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
 102 /* Transmit Interrupt Enable */
 103 #define IMX_MU_xCR_TIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
 104 /* General Purpose Interrupt Request */
 105 #define IMX_MU_xCR_GIRn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
 106
 107
 108 static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
 109 {
 110         return container_of(mbox, struct imx_mu_priv, mbox);
 111 }
 112
 113 static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs)
 114 {
 115         iowrite32(val, priv->base + offs);
 116 }
 117
 118 static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
 119 {
 120         return ioread32(priv->base + offs);
 121 }
 122
 123 static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, enum imx_mu_xcr type, u32 set, u32 clr)
 124 {
 125         unsigned long flags;
 126         u32 val;
 127
 128         spin_lock_irqsave(&priv->xcr_lock, flags);
 129         val = imx_mu_read(priv, priv->dcfg->xCR[type]);
 130         val &= ~clr;
 131         val |= set;
 132         imx_mu_write(priv, val, priv->dcfg->xCR[type]);
 133         spin_unlock_irqrestore(&priv->xcr_lock, flags);
 134
 135         return val;
 136 }
 137
 138 static int imx_mu_generic_tx(struct imx_mu_priv *priv,
 139                              struct imx_mu_con_priv *cp,
 140                              void *data)
 141 {
 142         u32 *arg = data;
 143
 144         switch (cp->type) {
 145         case IMX_MU_TYPE_TX:
 146                 imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);
 147                 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
 148                 break;
 149         case IMX_MU_TYPE_TXDB:
 150                 imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
 151                 tasklet_schedule(&cp->txdb_tasklet);
 152                 break;
 153         default:
 154                 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
 155                 return -EINVAL;
 156         }
 157
 158         return 0;
 159 }
 160
 161 static int imx_mu_generic_rx(struct imx_mu_priv *priv,
 162                              struct imx_mu_con_priv *cp)
 163 {
 164         u32 dat;
 165
 166         dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4);
 167         mbox_chan_received_data(cp->chan, (void *)&dat);
 168
 169         return 0;
 170 }
 171
 172 static int imx_mu_scu_tx(struct imx_mu_priv *priv,
 173                          struct imx_mu_con_priv *cp,
 174                          void *data)
 175 {
 176         struct imx_sc_rpc_msg_max *msg = data;
 177         u32 *arg = data;
 178         int i, ret;
 179         u32 xsr;
 180
 181         switch (cp->type) {
 182         case IMX_MU_TYPE_TX:
 183                 /*
 184                  * msg->hdr.size specifies the number of u32 words while
 185                  * sizeof yields bytes.
 186                  */
 187
 188                 if (msg->hdr.size > sizeof(*msg) / 4) {
 189                         /*
 190                          * The real message size can be different to
 191                          * struct imx_sc_rpc_msg_max size
 192                          */
 193                         dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on TX; got: %i bytes\n", sizeof(*msg), msg->hdr.size << 2);
 194                         return -EINVAL;
 195                 }
 196
 197                 for (i = 0; i < 4 && i < msg->hdr.size; i++)
 198                         imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
 199                 for (; i < msg->hdr.size; i++) {
 200                         ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR],
 201                                                  xsr,
 202                                                  xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % 4),
 203                                                  0, 100);
 204                         if (ret) {
 205                                 dev_err(priv->dev, "Send data index: %d timeout\n", i);
 206                                 return ret;
 207                         }
 208                         imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
 209                 }
 210
 211                 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
 212                 break;
 213         default:
 214                 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
 215                 return -EINVAL;
 216         }
 217
 218         return 0;
 219 }
 220
 221 static int imx_mu_scu_rx(struct imx_mu_priv *priv,
 222                          struct imx_mu_con_priv *cp)
 223 {
 224         struct imx_sc_rpc_msg_max msg;
 225         u32 *data = (u32 *)&msg;
 226         int i, ret;
 227         u32 xsr;
 228
 229         imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0));
 230         *data++ = imx_mu_read(priv, priv->dcfg->xRR);
 231
 232         if (msg.hdr.size > sizeof(msg) / 4) {
 233                 dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on RX; got: %i bytes\n", sizeof(msg), msg.hdr.size << 2);
 234                 return -EINVAL;
 235         }
 236
 237         for (i = 1; i < msg.hdr.size; i++) {
 238                 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,
 239                                          xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0, 100);
 240                 if (ret) {
 241                         dev_err(priv->dev, "timeout read idx %d\n", i);
 242                         return ret;
 243                 }
 244                 *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
 245         }
 246
 247         imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);
 248         mbox_chan_received_data(cp->chan, (void *)&msg);
 249
 250         return 0;
 251 }
 252
 253 static void imx_mu_txdb_tasklet(unsigned long data)
 254 {
 255         struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data;
 256
 257         mbox_chan_txdone(cp->chan, 0);
 258 }
 259
 260 static irqreturn_t imx_mu_isr(int irq, void *p)
 261 {
 262         struct mbox_chan *chan = p;
 263         struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
 264         struct imx_mu_con_priv *cp = chan->con_priv;
 265         u32 val, ctrl;
 266
 267         switch (cp->type) {
 268         case IMX_MU_TYPE_TX:
 269                 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]);
 270                 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
 271                 val &= IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx) &
 272                         (ctrl & IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
 273                 break;
 274         case IMX_MU_TYPE_RX:
 275                 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]);
 276                 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
 277                 val &= IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx) &
 278                         (ctrl & IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
 279                 break;
 280         case IMX_MU_TYPE_RXDB:
 281                 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GIER]);
 282                 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
 283                 val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) &
 284                         (ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
 285                 break;
 286         default:
 287                 dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n",
 288                                      cp->type);
 289                 return IRQ_NONE;
 290         }
 291
 292         if (!val)
 293                 return IRQ_NONE;
 294
 295         if ((val == IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx)) &&
 296             (cp->type == IMX_MU_TYPE_TX)) {
 297                 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
 298                 mbox_chan_txdone(chan, 0);
 299         } else if ((val == IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx)) &&
 300                    (cp->type == IMX_MU_TYPE_RX)) {
 301                 priv->dcfg->rx(priv, cp);
 302         } else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) &&
 303                    (cp->type == IMX_MU_TYPE_RXDB)) {
 304                 imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
 305                              priv->dcfg->xSR[IMX_MU_GSR]);
 306                 mbox_chan_received_data(chan, NULL);
 307         } else {
 308                 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
 309                 return IRQ_NONE;
 310         }
 311
 312         if (priv->suspend)
 313                 pm_system_wakeup();
 314
 315         return IRQ_HANDLED;
 316 }
 317
 318 static int imx_mu_send_data(struct mbox_chan *chan, void *data)
 319 {
 320         struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
 321         struct imx_mu_con_priv *cp = chan->con_priv;
 322
 323         return priv->dcfg->tx(priv, cp, data);
 324 }
 325
 326 static int imx_mu_startup(struct mbox_chan *chan)
 327 {
 328         struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
 329         struct imx_mu_con_priv *cp = chan->con_priv;
 330         unsigned long irq_flag = IRQF_SHARED;
 331         int ret;
 332
 333         pm_runtime_get_sync(priv->dev);
 334         if (cp->type == IMX_MU_TYPE_TXDB) {
 335                 /* Tx doorbell don't have ACK support */
 336                 tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet,
 337                              (unsigned long)cp);
 338                 return 0;
 339         }
 340
 341         /* IPC MU should be with IRQF_NO_SUSPEND set */
 342         if (!priv->dev->pm_domain)
 343                 irq_flag |= IRQF_NO_SUSPEND;
 344
 345         ret = request_irq(priv->irq, imx_mu_isr, irq_flag,
 346                           cp->irq_desc, chan);
 347         if (ret) {
 348                 dev_err(priv->dev,
 349                         "Unable to acquire IRQ %d\n", priv->irq);
 350                 return ret;
 351         }
 352
 353         switch (cp->type) {
 354         case IMX_MU_TYPE_RX:
 355                 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0);
 356                 break;
 357         case IMX_MU_TYPE_RXDB:
 358                 imx_mu_xcr_rmw(priv, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx), 0);
 359                 break;
 360         default:
 361                 break;
 362         }
 363
 364         return 0;
 365 }
 366
 367 static void imx_mu_shutdown(struct mbox_chan *chan)
 368 {
 369         struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
 370         struct imx_mu_con_priv *cp = chan->con_priv;
 371
 372         if (cp->type == IMX_MU_TYPE_TXDB) {
 373                 tasklet_kill(&cp->txdb_tasklet);
 374                 pm_runtime_put_sync(priv->dev);
 375                 return;
 376         }
 377
 378         switch (cp->type) {
 379         case IMX_MU_TYPE_TX:
 380                 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
 381                 break;
 382         case IMX_MU_TYPE_RX:
 383                 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
 384                 break;
 385         case IMX_MU_TYPE_RXDB:
 386                 imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
 387                 break;
 388         default:
 389                 break;
 390         }
 391
 392         free_irq(priv->irq, chan);
 393         pm_runtime_put_sync(priv->dev);
 394 }
 395
 396 static const struct mbox_chan_ops imx_mu_ops = {
 397         .send_data = imx_mu_send_data,
 398         .startup = imx_mu_startup,
 399         .shutdown = imx_mu_shutdown,
 400 };
 401
 402 static struct mbox_chan *imx_mu_scu_xlate(struct mbox_controller *mbox,
 403                                           const struct of_phandle_args *sp)
 404 {
 405         u32 type, idx, chan;
 406
 407         if (sp->args_count != 2) {
 408                 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
 409                 return ERR_PTR(-EINVAL);
 410         }
 411
 412         type = sp->args[0]; /* channel type */
 413         idx = sp->args[1]; /* index */
 414
 415         switch (type) {
 416         case IMX_MU_TYPE_TX:
 417         case IMX_MU_TYPE_RX:
 418                 if (idx != 0)
 419                         dev_err(mbox->dev, "Invalid chan idx: %d\n", idx);
 420                 chan = type;
 421                 break;
 422         case IMX_MU_TYPE_RXDB:
 423                 chan = 2 + idx;
 424                 break;
 425         default:
 426                 dev_err(mbox->dev, "Invalid chan type: %d\n", type);
 427                 return ERR_PTR(-EINVAL);
 428         }
 429
 430         if (chan >= mbox->num_chans) {
 431                 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
 432                 return ERR_PTR(-EINVAL);
 433         }
 434
 435         return &mbox->chans[chan];
 436 }
 437
 438 static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
 439                                        const struct of_phandle_args *sp)
 440 {
 441         u32 type, idx, chan;
 442
 443         if (sp->args_count != 2) {
 444                 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
 445                 return ERR_PTR(-EINVAL);
 446         }
 447
 448         type = sp->args[0]; /* channel type */
 449         idx = sp->args[1]; /* index */
 450         chan = type * 4 + idx;
 451
 452         if (chan >= mbox->num_chans) {
 453                 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
 454                 return ERR_PTR(-EINVAL);
 455         }
 456
 457         return &mbox->chans[chan];
 458 }
 459
 460 static void imx_mu_init_generic(struct imx_mu_priv *priv)
 461 {
 462         unsigned int i;
 463
 464         for (i = 0; i < IMX_MU_CHANS; i++) {
 465                 struct imx_mu_con_priv *cp = &priv->con_priv[i];
 466
 467                 cp->idx = i % 4;
 468                 cp->type = i >> 2;
 469                 cp->chan = &priv->mbox_chans[i];
 470                 priv->mbox_chans[i].con_priv = cp;
 471                 snprintf(cp->irq_desc, sizeof(cp->irq_desc),
 472                          "imx_mu_chan[%i-%i]", cp->type, cp->idx);
 473         }
 474
 475         priv->mbox.num_chans = IMX_MU_CHANS;
 476         priv->mbox.of_xlate = imx_mu_xlate;
 477
 478         if (priv->side_b)
 479                 return;
 480
 481         /* Set default MU configuration */
 482         for (i = 0; i < IMX_MU_xCR_MAX; i++)
 483                 imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
 484 }
 485
 486 static void imx_mu_init_scu(struct imx_mu_priv *priv)
 487 {
 488         unsigned int i;
 489
 490         for (i = 0; i < IMX_MU_SCU_CHANS; i++) {
 491                 struct imx_mu_con_priv *cp = &priv->con_priv[i];
 492
 493                 cp->idx = i < 2 ? 0 : i - 2;
 494                 cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB;
 495                 cp->chan = &priv->mbox_chans[i];
 496                 priv->mbox_chans[i].con_priv = cp;
 497                 snprintf(cp->irq_desc, sizeof(cp->irq_desc),
 498                          "imx_mu_chan[%i-%i]", cp->type, cp->idx);
 499         }
 500
 501         priv->mbox.num_chans = IMX_MU_SCU_CHANS;
 502         priv->mbox.of_xlate = imx_mu_scu_xlate;
 503
 504         /* Set default MU configuration */
 505         for (i = 0; i < IMX_MU_xCR_MAX; i++)
 506                 imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
 507 }
 508
 509 static int imx_mu_probe(struct platform_device *pdev)
 510 {
 511         struct device *dev = &pdev->dev;
 512         struct device_node *np = dev->of_node;
 513         struct imx_mu_priv *priv;
 514         const struct imx_mu_dcfg *dcfg;
 515         int ret;
 516
 517         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 518         if (!priv)
 519                 return -ENOMEM;
 520
 521         priv->dev = dev;
 522
 523         priv->base = devm_platform_ioremap_resource(pdev, 0);
 524         if (IS_ERR(priv->base))
 525                 return PTR_ERR(priv->base);
 526
 527         priv->irq = platform_get_irq(pdev, 0);
 528         if (priv->irq < 0)
 529                 return priv->irq;
 530
 531         dcfg = of_device_get_match_data(dev);
 532         if (!dcfg)
 533                 return -EINVAL;
 534         priv->dcfg = dcfg;
 535
 536         priv->clk = devm_clk_get(dev, NULL);
 537         if (IS_ERR(priv->clk)) {
 538                 if (PTR_ERR(priv->clk) != -ENOENT)
 539                         return PTR_ERR(priv->clk);
 540
 541                 priv->clk = NULL;
 542         }
 543
 544         ret = clk_prepare_enable(priv->clk);
 545         if (ret) {
 546                 dev_err(dev, "Failed to enable clock\n");
 547                 return ret;
 548         }
 549
 550         priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
 551
 552         priv->dcfg->init(priv);
 553
 554         spin_lock_init(&priv->xcr_lock);
 555
 556         priv->mbox.dev = dev;
 557         priv->mbox.ops = &imx_mu_ops;
 558         priv->mbox.chans = priv->mbox_chans;
 559         priv->mbox.txdone_irq = true;
 560
 561         platform_set_drvdata(pdev, priv);
 562
 563         ret = devm_mbox_controller_register(dev, &priv->mbox);
 564         if (ret) {
 565                 clk_disable_unprepare(priv->clk);
 566                 return ret;
 567         }
 568
 569         pm_runtime_enable(dev);
 570
 571         ret = pm_runtime_get_sync(dev);
 572         if (ret < 0) {
 573                 pm_runtime_put_noidle(dev);
 574                 goto disable_runtime_pm;
 575         }
 576
 577         ret = pm_runtime_put_sync(dev);
 578         if (ret < 0)
 579                 goto disable_runtime_pm;
 580
 581         clk_disable_unprepare(priv->clk);
 582
 583         return 0;
 584
 585 disable_runtime_pm:
 586         pm_runtime_disable(dev);
 587         clk_disable_unprepare(priv->clk);
 588         return ret;
 589 }
 590
 591 static int imx_mu_remove(struct platform_device *pdev)
 592 {
 593         struct imx_mu_priv *priv = platform_get_drvdata(pdev);
 594
 595         pm_runtime_disable(priv->dev);
 596
 597         return 0;
 598 }
 599
 600 static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
 601         .tx     = imx_mu_generic_tx,
 602         .rx     = imx_mu_generic_rx,
 603         .init   = imx_mu_init_generic,
 604         .xTR    = 0x0,
 605         .xRR    = 0x10,
 606         .xSR    = {0x20, 0x20, 0x20, 0x20},
 607         .xCR    = {0x24, 0x24, 0x24, 0x24},
 608 };
 609
 610 static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
 611         .tx     = imx_mu_generic_tx,
 612         .rx     = imx_mu_generic_rx,
 613         .init   = imx_mu_init_generic,
 614         .xTR    = 0x20,
 615         .xRR    = 0x40,
 616         .xSR    = {0x60, 0x60, 0x60, 0x60},
 617         .xCR    = {0x64, 0x64, 0x64, 0x64},
 618 };
 619
 620 static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {
 621         .tx     = imx_mu_generic_tx,
 622         .rx     = imx_mu_generic_rx,
 623         .init   = imx_mu_init_generic,
 624         .type   = IMX_MU_V2,
 625         .xTR    = 0x200,
 626         .xRR    = 0x280,
 627         .xSR    = {0xC, 0x118, 0x124, 0x12C},
 628         .xCR    = {0x110, 0x114, 0x120, 0x128},
 629 };
 630
 631 static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
 632         .tx     = imx_mu_scu_tx,
 633         .rx     = imx_mu_scu_rx,
 634         .init   = imx_mu_init_scu,
 635         .xTR    = 0x0,
 636         .xRR    = 0x10,
 637         .xSR    = {0x20, 0x20, 0x20, 0x20},
 638         .xCR    = {0x24, 0x24, 0x24, 0x24},
 639 };
 640
 641 static const struct of_device_id imx_mu_dt_ids[] = {
 642         { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
 643         { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
 644         { .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp },
 645         { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
 646         { },
 647 };
 648 MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
 649
 650 static int __maybe_unused imx_mu_suspend_noirq(struct device *dev)
 651 {
 652         struct imx_mu_priv *priv = dev_get_drvdata(dev);
 653         int i;
 654
 655         if (!priv->clk) {
 656                 for (i = 0; i < IMX_MU_xCR_MAX; i++)
 657                         priv->xcr[i] = imx_mu_read(priv, priv->dcfg->xCR[i]);
 658         }
 659
 660         priv->suspend = true;
 661
 662         return 0;
 663 }
 664
 665 static int __maybe_unused imx_mu_resume_noirq(struct device *dev)
 666 {
 667         struct imx_mu_priv *priv = dev_get_drvdata(dev);
 668         int i;
 669
 670         /*
 671          * ONLY restore MU when context lost, the TIE could
 672          * be set during noirq resume as there is MU data
 673          * communication going on, and restore the saved
 674          * value will overwrite the TIE and cause MU data
 675          * send failed, may lead to system freeze. This issue
 676          * is observed by testing freeze mode suspend.
 677          */
 678         if (!priv->clk && !imx_mu_read(priv, priv->dcfg->xCR[0])) {
 679                 for (i = 0; i < IMX_MU_xCR_MAX; i++)
 680                         imx_mu_write(priv, priv->xcr[i], priv->dcfg->xCR[i]);
 681         }
 682
 683         priv->suspend = false;
 684
 685         return 0;
 686 }
 687
 688 static int __maybe_unused imx_mu_runtime_suspend(struct device *dev)
 689 {
 690         struct imx_mu_priv *priv = dev_get_drvdata(dev);
 691
 692         clk_disable_unprepare(priv->clk);
 693
 694         return 0;
 695 }
 696
 697 static int __maybe_unused imx_mu_runtime_resume(struct device *dev)
 698 {
 699         struct imx_mu_priv *priv = dev_get_drvdata(dev);
 700         int ret;
 701
 702         ret = clk_prepare_enable(priv->clk);
 703         if (ret)
 704                 dev_err(dev, "failed to enable clock\n");
 705
 706         return ret;
 707 }
 708
 709 static const struct dev_pm_ops imx_mu_pm_ops = {
 710         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_mu_suspend_noirq,
 711                                       imx_mu_resume_noirq)
 712         SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend,
 713                            imx_mu_runtime_resume, NULL)
 714 };
 715
 716 static struct platform_driver imx_mu_driver = {
 717         .probe          = imx_mu_probe,
 718         .remove         = imx_mu_remove,
 719         .driver = {
 720                 .name   = "imx_mu",
 721                 .of_match_table = imx_mu_dt_ids,
 722                 .pm = &imx_mu_pm_ops,
 723         },
 724 };
 725 module_platform_driver(imx_mu_driver);
 726
 727 MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
 728 MODULE_DESCRIPTION("Message Unit driver for i.MX");
 729 MODULE_LICENSE("GPL v2");