drivers/mailbox/imx-mailbox.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
   4  * Copyright 2022 NXP, Peng Fan <peng.fan@nxp.com>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/firmware/imx/ipc.h>
   9 #include <linux/firmware/imx/s4.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/io.h>
  12 #include <linux/iopoll.h>
  13 #include <linux/jiffies.h>
  14 #include <linux/kernel.h>
  15 #include <linux/mailbox_controller.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/suspend.h>
  21 #include <linux/slab.h>
  22
  23 #define IMX_MU_CHANS            17
  24 /* TX0/RX0/RXDB[0-3] */
  25 #define IMX_MU_SCU_CHANS        6
  26 /* TX0/RX0 */
  27 #define IMX_MU_S4_CHANS         2
  28 #define IMX_MU_CHAN_NAME_SIZE   20
  29
  30 #define IMX_MU_NUM_RR           4
  31
  32 #define IMX_MU_SECO_TX_TOUT (msecs_to_jiffies(3000))
  33 #define IMX_MU_SECO_RX_TOUT (msecs_to_jiffies(3000))
  34
  35 /* Please not change TX & RX */
  36 enum imx_mu_chan_type {
  37         IMX_MU_TYPE_TX          = 0, /* Tx */
  38         IMX_MU_TYPE_RX          = 1, /* Rx */
  39         IMX_MU_TYPE_TXDB        = 2, /* Tx doorbell */
  40         IMX_MU_TYPE_RXDB        = 3, /* Rx doorbell */
  41         IMX_MU_TYPE_RST         = 4, /* Reset */
  42 };
  43
  44 enum imx_mu_xcr {
  45         IMX_MU_CR,
  46         IMX_MU_GIER,
  47         IMX_MU_GCR,
  48         IMX_MU_TCR,
  49         IMX_MU_RCR,
  50         IMX_MU_xCR_MAX,
  51 };
  52
  53 enum imx_mu_xsr {
  54         IMX_MU_SR,
  55         IMX_MU_GSR,
  56         IMX_MU_TSR,
  57         IMX_MU_RSR,
  58         IMX_MU_xSR_MAX,
  59 };
  60
  61 struct imx_sc_rpc_msg_max {
  62         struct imx_sc_rpc_msg hdr;
  63         u32 data[30];
  64 };
  65
  66 struct imx_s4_rpc_msg_max {
  67         struct imx_s4_rpc_msg hdr;
  68         u32 data[254];
  69 };
  70
  71 struct imx_mu_con_priv {
  72         unsigned int            idx;
  73         char                    irq_desc[IMX_MU_CHAN_NAME_SIZE];
  74         enum imx_mu_chan_type   type;
  75         struct mbox_chan        *chan;
  76         struct tasklet_struct   txdb_tasklet;
  77 };
  78
  79 struct imx_mu_priv {
  80         struct device           *dev;
  81         void __iomem            *base;
  82         void                    *msg;
  83         spinlock_t              xcr_lock; /* control register lock */
  84
  85         struct mbox_controller  mbox;
  86         struct mbox_chan        mbox_chans[IMX_MU_CHANS];
  87
  88         struct imx_mu_con_priv  con_priv[IMX_MU_CHANS];
  89         const struct imx_mu_dcfg        *dcfg;
  90         struct clk              *clk;
  91         int                     irq[IMX_MU_CHANS];
  92         bool                    suspend;
  93
  94         u32 xcr[IMX_MU_xCR_MAX];
  95
  96         bool                    side_b;
  97 };
  98
  99 enum imx_mu_type {
 100         IMX_MU_V1,
 101         IMX_MU_V2 = BIT(1),
 102         IMX_MU_V2_S4 = BIT(15),
 103         IMX_MU_V2_IRQ = BIT(16),
 104 };
 105
 106 struct imx_mu_dcfg {
 107         int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
 108         int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
 109         int (*rxdb)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
 110         void (*init)(struct imx_mu_priv *priv);
 111         enum imx_mu_type type;
 112         u32     xTR;            /* Transmit Register0 */
 113         u32     xRR;            /* Receive Register0 */
 114         u32     xSR[IMX_MU_xSR_MAX];    /* Status Registers */
 115         u32     xCR[IMX_MU_xCR_MAX];    /* Control Registers */
 116 };
 117
 118 #define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
 119 #define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
 120 #define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
 121
 122 /* General Purpose Interrupt Enable */
 123 #define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
 124 /* Receive Interrupt Enable */
 125 #define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
 126 /* Transmit Interrupt Enable */
 127 #define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
 128 /* General Purpose Interrupt Request */
 129 #define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
 130 /* MU reset */
 131 #define IMX_MU_xCR_RST(type)    (type & IMX_MU_V2 ? BIT(0) : BIT(5))
 132 #define IMX_MU_xSR_RST(type)    (type & IMX_MU_V2 ? BIT(0) : BIT(7))
 133
 134
 135 static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
 136 {
 137         return container_of(mbox, struct imx_mu_priv, mbox);
 138 }
 139
 140 static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs)
 141 {
 142         iowrite32(val, priv->base + offs);
 143 }
 144
 145 static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
 146 {
 147         return ioread32(priv->base + offs);
 148 }
 149
 150 static int imx_mu_tx_waiting_write(struct imx_mu_priv *priv, u32 val, u32 idx)
 151 {
 152         u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_TX_TOUT;
 153         u32 status;
 154         u32 can_write;
 155
 156         dev_dbg(priv->dev, "Trying to write %.8x to idx %d\n", val, idx);
 157
 158         do {
 159                 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
 160                 can_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4);
 161         } while (!can_write && time_is_after_jiffies64(timeout_time));
 162
 163         if (!can_write) {
 164                 dev_err(priv->dev, "timeout trying to write %.8x at %d(%.8x)\n",
 165                         val, idx, status);
 166                 return -ETIME;
 167         }
 168
 169         imx_mu_write(priv, val, priv->dcfg->xTR + (idx % 4) * 4);
 170
 171         return 0;
 172 }
 173
 174 static int imx_mu_rx_waiting_read(struct imx_mu_priv *priv, u32 *val, u32 idx)
 175 {
 176         u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_RX_TOUT;
 177         u32 status;
 178         u32 can_read;
 179
 180         dev_dbg(priv->dev, "Trying to read from idx %d\n", idx);
 181
 182         do {
 183                 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
 184                 can_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4);
 185         } while (!can_read && time_is_after_jiffies64(timeout_time));
 186
 187         if (!can_read) {
 188                 dev_err(priv->dev, "timeout trying to read idx %d (%.8x)\n",
 189                         idx, status);
 190                 return -ETIME;
 191         }
 192
 193         *val = imx_mu_read(priv, priv->dcfg->xRR + (idx % 4) * 4);
 194         dev_dbg(priv->dev, "Read %.8x\n", *val);
 195
 196         return 0;
 197 }
 198
 199 static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, enum imx_mu_xcr type, u32 set, u32 clr)
 200 {
 201         unsigned long flags;
 202         u32 val;
 203
 204         spin_lock_irqsave(&priv->xcr_lock, flags);
 205         val = imx_mu_read(priv, priv->dcfg->xCR[type]);
 206         val &= ~clr;
 207         val |= set;
 208         imx_mu_write(priv, val, priv->dcfg->xCR[type]);
 209         spin_unlock_irqrestore(&priv->xcr_lock, flags);
 210
 211         return val;
 212 }
 213
 214 static int imx_mu_generic_tx(struct imx_mu_priv *priv,
 215                              struct imx_mu_con_priv *cp,
 216                              void *data)
 217 {
 218         u32 *arg = data;
 219
 220         switch (cp->type) {
 221         case IMX_MU_TYPE_TX:
 222                 imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);
 223                 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
 224                 break;
 225         case IMX_MU_TYPE_TXDB:
 226                 imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
 227                 tasklet_schedule(&cp->txdb_tasklet);
 228                 break;
 229         default:
 230                 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
 231                 return -EINVAL;
 232         }
 233
 234         return 0;
 235 }
 236
 237 static int imx_mu_generic_rx(struct imx_mu_priv *priv,
 238                              struct imx_mu_con_priv *cp)
 239 {
 240         u32 dat;
 241
 242         dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4);
 243         mbox_chan_received_data(cp->chan, (void *)&dat);
 244
 245         return 0;
 246 }
 247
 248 static int imx_mu_generic_rxdb(struct imx_mu_priv *priv,
 249                                struct imx_mu_con_priv *cp)
 250 {
 251         imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
 252                      priv->dcfg->xSR[IMX_MU_GSR]);
 253         mbox_chan_received_data(cp->chan, NULL);
 254
 255         return 0;
 256 }
 257
 258 static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data)
 259 {
 260         u32 *arg = data;
 261         int i, ret;
 262         u32 xsr;
 263         u32 size, max_size, num_tr;
 264
 265         if (priv->dcfg->type & IMX_MU_V2_S4) {
 266                 size = ((struct imx_s4_rpc_msg_max *)data)->hdr.size;
 267                 max_size = sizeof(struct imx_s4_rpc_msg_max);
 268                 num_tr = 8;
 269         } else {
 270                 size = ((struct imx_sc_rpc_msg_max *)data)->hdr.size;
 271                 max_size = sizeof(struct imx_sc_rpc_msg_max);
 272                 num_tr = 4;
 273         }
 274
 275         switch (cp->type) {
 276         case IMX_MU_TYPE_TX:
 277                 /*
 278                  * msg->hdr.size specifies the number of u32 words while
 279                  * sizeof yields bytes.
 280                  */
 281
 282                 if (size > max_size / 4) {
 283                         /*
 284                          * The real message size can be different to
 285                          * struct imx_sc_rpc_msg_max/imx_s4_rpc_msg_max size
 286                          */
 287                         dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on TX; got: %i bytes\n", max_size, size << 2);
 288                         return -EINVAL;
 289                 }
 290
 291                 for (i = 0; i < num_tr && i < size; i++)
 292                         imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);
 293                 for (; i < size; i++) {
 294                         ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR],
 295                                                  xsr,
 296                                                  xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % num_tr),
 297                                                  0, 5 * USEC_PER_SEC);
 298                         if (ret) {
 299                                 dev_err(priv->dev, "Send data index: %d timeout\n", i);
 300                                 return ret;
 301                         }
 302                         imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);
 303                 }
 304
 305                 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
 306                 break;
 307         default:
 308                 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
 309                 return -EINVAL;
 310         }
 311
 312         return 0;
 313 }
 314
 315 static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp)
 316 {
 317         u32 *data;
 318         int i, ret;
 319         u32 xsr;
 320         u32 size, max_size;
 321
 322         data = (u32 *)priv->msg;
 323
 324         imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0));
 325         *data++ = imx_mu_read(priv, priv->dcfg->xRR);
 326
 327         if (priv->dcfg->type & IMX_MU_V2_S4) {
 328                 size = ((struct imx_s4_rpc_msg_max *)priv->msg)->hdr.size;
 329                 max_size = sizeof(struct imx_s4_rpc_msg_max);
 330         } else {
 331                 size = ((struct imx_sc_rpc_msg_max *)priv->msg)->hdr.size;
 332                 max_size = sizeof(struct imx_sc_rpc_msg_max);
 333         }
 334
 335         if (size > max_size / 4) {
 336                 dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on RX; got: %i bytes\n", max_size, size << 2);
 337                 return -EINVAL;
 338         }
 339
 340         for (i = 1; i < size; i++) {
 341                 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,
 342                                          xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0,
 343                                          5 * USEC_PER_SEC);
 344                 if (ret) {
 345                         dev_err(priv->dev, "timeout read idx %d\n", i);
 346                         return ret;
 347                 }
 348                 *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
 349         }
 350
 351         imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);
 352         mbox_chan_received_data(cp->chan, (void *)priv->msg);
 353
 354         return 0;
 355 }
 356
 357 static int imx_mu_seco_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp,
 358                           void *data)
 359 {
 360         struct imx_sc_rpc_msg_max *msg = data;
 361         u32 *arg = data;
 362         u32 byte_size;
 363         int err;
 364         int i;
 365
 366         dev_dbg(priv->dev, "Sending message\n");
 367
 368         switch (cp->type) {
 369         case IMX_MU_TYPE_TXDB:
 370                 byte_size = msg->hdr.size * sizeof(u32);
 371                 if (byte_size > sizeof(*msg)) {
 372                         /*
 373                          * The real message size can be different to
 374                          * struct imx_sc_rpc_msg_max size
 375                          */
 376                         dev_err(priv->dev,
 377                                 "Exceed max msg size (%zu) on TX, got: %i\n",
 378                                 sizeof(*msg), byte_size);
 379                         return -EINVAL;
 380                 }
 381
 382                 print_hex_dump_debug("from client ", DUMP_PREFIX_OFFSET, 4, 4,
 383                                      data, byte_size, false);
 384
 385                 /* Send first word */
 386                 dev_dbg(priv->dev, "Sending header\n");
 387                 imx_mu_write(priv, *arg++, priv->dcfg->xTR);
 388
 389                 /* Send signaling */
 390                 dev_dbg(priv->dev, "Sending signaling\n");
 391                 imx_mu_xcr_rmw(priv, IMX_MU_GCR,
 392                                IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
 393
 394                 /* Send words to fill the mailbox */
 395                 for (i = 1; i < 4 && i < msg->hdr.size; i++) {
 396                         dev_dbg(priv->dev, "Sending word %d\n", i);
 397                         imx_mu_write(priv, *arg++,
 398                                      priv->dcfg->xTR + (i % 4) * 4);
 399                 }
 400
 401                 /* Send rest of message waiting for remote read */
 402                 for (; i < msg->hdr.size; i++) {
 403                         dev_dbg(priv->dev, "Sending word %d\n", i);
 404                         err = imx_mu_tx_waiting_write(priv, *arg++, i);
 405                         if (err) {
 406                                 dev_err(priv->dev, "Timeout tx %d\n", i);
 407                                 return err;
 408                         }
 409                 }
 410
 411                 /* Simulate hack for mbox framework */
 412                 tasklet_schedule(&cp->txdb_tasklet);
 413
 414                 break;
 415         default:
 416                 dev_warn_ratelimited(priv->dev,
 417                                      "Send data on wrong channel type: %d\n",
 418                                      cp->type);
 419                 return -EINVAL;
 420         }
 421
 422         return 0;
 423 }
 424
 425 static int imx_mu_seco_rxdb(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp)
 426 {
 427         struct imx_sc_rpc_msg_max msg;
 428         u32 *data = (u32 *)&msg;
 429         u32 byte_size;
 430         int err = 0;
 431         int i;
 432
 433         dev_dbg(priv->dev, "Receiving message\n");
 434
 435         /* Read header */
 436         dev_dbg(priv->dev, "Receiving header\n");
 437         *data++ = imx_mu_read(priv, priv->dcfg->xRR);
 438         byte_size = msg.hdr.size * sizeof(u32);
 439         if (byte_size > sizeof(msg)) {
 440                 dev_err(priv->dev, "Exceed max msg size (%zu) on RX, got: %i\n",
 441                         sizeof(msg), byte_size);
 442                 err = -EINVAL;
 443                 goto error;
 444         }
 445
 446         /* Read message waiting they are written */
 447         for (i = 1; i < msg.hdr.size; i++) {
 448                 dev_dbg(priv->dev, "Receiving word %d\n", i);
 449                 err = imx_mu_rx_waiting_read(priv, data++, i);
 450                 if (err) {
 451                         dev_err(priv->dev, "Timeout rx %d\n", i);
 452                         goto error;
 453                 }
 454         }
 455
 456         /* Clear GIP */
 457         imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
 458                      priv->dcfg->xSR[IMX_MU_GSR]);
 459
 460         print_hex_dump_debug("to client ", DUMP_PREFIX_OFFSET, 4, 4,
 461                              &msg, byte_size, false);
 462
 463         /* send data to client */
 464         dev_dbg(priv->dev, "Sending message to client\n");
 465         mbox_chan_received_data(cp->chan, (void *)&msg);
 466
 467         goto exit;
 468
 469 error:
 470         mbox_chan_received_data(cp->chan, ERR_PTR(err));
 471
 472 exit:
 473         return err;
 474 }
 475
 476 static void imx_mu_txdb_tasklet(unsigned long data)
 477 {
 478         struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data;
 479
 480         mbox_chan_txdone(cp->chan, 0);
 481 }
 482
 483 static irqreturn_t imx_mu_isr(int irq, void *p)
 484 {
 485         struct mbox_chan *chan = p;
 486         struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
 487         struct imx_mu_con_priv *cp = chan->con_priv;
 488         u32 val, ctrl;
 489
 490         switch (cp->type) {
 491         case IMX_MU_TYPE_TX:
 492                 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]);
 493                 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
 494                 val &= IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx) &
 495                         (ctrl & IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
 496                 break;
 497         case IMX_MU_TYPE_RX:
 498                 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]);
 499                 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
 500                 val &= IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx) &
 501                         (ctrl & IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
 502                 break;
 503         case IMX_MU_TYPE_RXDB:
 504                 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GIER]);
 505                 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
 506                 val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) &
 507                         (ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
 508                 break;
 509         case IMX_MU_TYPE_RST:
 510                 return IRQ_NONE;
 511         default:
 512                 dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n",
 513                                      cp->type);
 514                 return IRQ_NONE;
 515         }
 516
 517         if (!val)
 518                 return IRQ_NONE;
 519
 520         if ((val == IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx)) &&
 521             (cp->type == IMX_MU_TYPE_TX)) {
 522                 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
 523                 mbox_chan_txdone(chan, 0);
 524         } else if ((val == IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx)) &&
 525                    (cp->type == IMX_MU_TYPE_RX)) {
 526                 priv->dcfg->rx(priv, cp);
 527         } else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) &&
 528                    (cp->type == IMX_MU_TYPE_RXDB)) {
 529                 priv->dcfg->rxdb(priv, cp);
 530         } else {
 531                 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
 532                 return IRQ_NONE;
 533         }
 534
 535         if (priv->suspend)
 536                 pm_system_wakeup();
 537
 538         return IRQ_HANDLED;
 539 }
 540
 541 static int imx_mu_send_data(struct mbox_chan *chan, void *data)
 542 {
 543         struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
 544         struct imx_mu_con_priv *cp = chan->con_priv;
 545
 546         return priv->dcfg->tx(priv, cp, data);
 547 }
 548
 549 static int imx_mu_startup(struct mbox_chan *chan)
 550 {
 551         struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
 552         struct imx_mu_con_priv *cp = chan->con_priv;
 553         unsigned long irq_flag = 0;
 554         int ret;
 555
 556         pm_runtime_get_sync(priv->dev);
 557         if (cp->type == IMX_MU_TYPE_TXDB) {
 558                 /* Tx doorbell don't have ACK support */
 559                 tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet,
 560                              (unsigned long)cp);
 561                 return 0;
 562         }
 563
 564         /* IPC MU should be with IRQF_NO_SUSPEND set */
 565         if (!priv->dev->pm_domain)
 566                 irq_flag |= IRQF_NO_SUSPEND;
 567
 568         if (!(priv->dcfg->type & IMX_MU_V2_IRQ))
 569                 irq_flag |= IRQF_SHARED;
 570
 571         ret = request_irq(priv->irq[cp->type], imx_mu_isr, irq_flag, cp->irq_desc, chan);
 572         if (ret) {
 573                 dev_err(priv->dev, "Unable to acquire IRQ %d\n", priv->irq[cp->type]);
 574                 return ret;
 575         }
 576
 577         switch (cp->type) {
 578         case IMX_MU_TYPE_RX:
 579                 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0);
 580                 break;
 581         case IMX_MU_TYPE_RXDB:
 582                 imx_mu_xcr_rmw(priv, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx), 0);
 583                 break;
 584         default:
 585                 break;
 586         }
 587
 588         return 0;
 589 }
 590
 591 static void imx_mu_shutdown(struct mbox_chan *chan)
 592 {
 593         struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
 594         struct imx_mu_con_priv *cp = chan->con_priv;
 595         int ret;
 596         u32 sr;
 597
 598         if (cp->type == IMX_MU_TYPE_TXDB) {
 599                 tasklet_kill(&cp->txdb_tasklet);
 600                 pm_runtime_put_sync(priv->dev);
 601                 return;
 602         }
 603
 604         switch (cp->type) {
 605         case IMX_MU_TYPE_TX:
 606                 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
 607                 break;
 608         case IMX_MU_TYPE_RX:
 609                 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
 610                 break;
 611         case IMX_MU_TYPE_RXDB:
 612                 imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
 613                 break;
 614         case IMX_MU_TYPE_RST:
 615                 imx_mu_xcr_rmw(priv, IMX_MU_CR, IMX_MU_xCR_RST(priv->dcfg->type), 0);
 616                 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_SR], sr,
 617                                          !(sr & IMX_MU_xSR_RST(priv->dcfg->type)), 1, 5);
 618                 if (ret)
 619                         dev_warn(priv->dev, "RST channel timeout\n");
 620                 break;
 621         default:
 622                 break;
 623         }
 624
 625         free_irq(priv->irq[cp->type], chan);
 626         pm_runtime_put_sync(priv->dev);
 627 }
 628
 629 static const struct mbox_chan_ops imx_mu_ops = {
 630         .send_data = imx_mu_send_data,
 631         .startup = imx_mu_startup,
 632         .shutdown = imx_mu_shutdown,
 633 };
 634
 635 static struct mbox_chan *imx_mu_specific_xlate(struct mbox_controller *mbox,
 636                                                const struct of_phandle_args *sp)
 637 {
 638         u32 type, idx, chan;
 639
 640         if (sp->args_count != 2) {
 641                 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
 642                 return ERR_PTR(-EINVAL);
 643         }
 644
 645         type = sp->args[0]; /* channel type */
 646         idx = sp->args[1]; /* index */
 647
 648         switch (type) {
 649         case IMX_MU_TYPE_TX:
 650         case IMX_MU_TYPE_RX:
 651                 if (idx != 0)
 652                         dev_err(mbox->dev, "Invalid chan idx: %d\n", idx);
 653                 chan = type;
 654                 break;
 655         case IMX_MU_TYPE_RXDB:
 656                 chan = 2 + idx;
 657                 break;
 658         default:
 659                 dev_err(mbox->dev, "Invalid chan type: %d\n", type);
 660                 return ERR_PTR(-EINVAL);
 661         }
 662
 663         if (chan >= mbox->num_chans) {
 664                 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
 665                 return ERR_PTR(-EINVAL);
 666         }
 667
 668         return &mbox->chans[chan];
 669 }
 670
 671 static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
 672                                        const struct of_phandle_args *sp)
 673 {
 674         u32 type, idx, chan;
 675
 676         if (sp->args_count != 2) {
 677                 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
 678                 return ERR_PTR(-EINVAL);
 679         }
 680
 681         type = sp->args[0]; /* channel type */
 682         idx = sp->args[1]; /* index */
 683         chan = type * 4 + idx;
 684
 685         if (chan >= mbox->num_chans) {
 686                 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
 687                 return ERR_PTR(-EINVAL);
 688         }
 689
 690         return &mbox->chans[chan];
 691 }
 692
 693 static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox,
 694                                            const struct of_phandle_args *sp)
 695 {
 696         u32 type;
 697
 698         if (sp->args_count < 1) {
 699                 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
 700                 return ERR_PTR(-EINVAL);
 701         }
 702
 703         type = sp->args[0]; /* channel type */
 704
 705         /* Only supports TXDB and RXDB */
 706         if (type == IMX_MU_TYPE_TX || type == IMX_MU_TYPE_RX) {
 707                 dev_err(mbox->dev, "Invalid type: %d\n", type);
 708                 return ERR_PTR(-EINVAL);
 709         }
 710
 711         return imx_mu_xlate(mbox, sp);
 712 }
 713
 714 static void imx_mu_init_generic(struct imx_mu_priv *priv)
 715 {
 716         unsigned int i;
 717         unsigned int val;
 718
 719         for (i = 0; i < IMX_MU_CHANS; i++) {
 720                 struct imx_mu_con_priv *cp = &priv->con_priv[i];
 721
 722                 cp->idx = i % 4;
 723                 cp->type = i >> 2;
 724                 cp->chan = &priv->mbox_chans[i];
 725                 priv->mbox_chans[i].con_priv = cp;
 726                 snprintf(cp->irq_desc, sizeof(cp->irq_desc),
 727                          "imx_mu_chan[%i-%i]", cp->type, cp->idx);
 728         }
 729
 730         priv->mbox.num_chans = IMX_MU_CHANS;
 731         priv->mbox.of_xlate = imx_mu_xlate;
 732
 733         if (priv->side_b)
 734                 return;
 735
 736         /* Set default MU configuration */
 737         for (i = 0; i < IMX_MU_xCR_MAX; i++)
 738                 imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
 739
 740         /* Clear any pending GIP */
 741         val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
 742         imx_mu_write(priv, val, priv->dcfg->xSR[IMX_MU_GSR]);
 743
 744         /* Clear any pending RSR */
 745         for (i = 0; i < IMX_MU_NUM_RR; i++)
 746                 imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
 747 }
 748
 749 static void imx_mu_init_specific(struct imx_mu_priv *priv)
 750 {
 751         unsigned int i;
 752         int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS;
 753
 754         for (i = 0; i < num_chans; i++) {
 755                 struct imx_mu_con_priv *cp = &priv->con_priv[i];
 756
 757                 cp->idx = i < 2 ? 0 : i - 2;
 758                 cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB;
 759                 cp->chan = &priv->mbox_chans[i];
 760                 priv->mbox_chans[i].con_priv = cp;
 761                 snprintf(cp->irq_desc, sizeof(cp->irq_desc),
 762                          "imx_mu_chan[%i-%i]", cp->type, cp->idx);
 763         }
 764
 765         priv->mbox.num_chans = num_chans;
 766         priv->mbox.of_xlate = imx_mu_specific_xlate;
 767
 768         /* Set default MU configuration */
 769         for (i = 0; i < IMX_MU_xCR_MAX; i++)
 770                 imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
 771 }
 772
 773 static void imx_mu_init_seco(struct imx_mu_priv *priv)
 774 {
 775         imx_mu_init_generic(priv);
 776         priv->mbox.of_xlate = imx_mu_seco_xlate;
 777 }
 778
 779 static int imx_mu_probe(struct platform_device *pdev)
 780 {
 781         struct device *dev = &pdev->dev;
 782         struct device_node *np = dev->of_node;
 783         struct imx_mu_priv *priv;
 784         const struct imx_mu_dcfg *dcfg;
 785         int i, ret;
 786         u32 size;
 787
 788         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 789         if (!priv)
 790                 return -ENOMEM;
 791
 792         priv->dev = dev;
 793
 794         priv->base = devm_platform_ioremap_resource(pdev, 0);
 795         if (IS_ERR(priv->base))
 796                 return PTR_ERR(priv->base);
 797
 798         dcfg = of_device_get_match_data(dev);
 799         if (!dcfg)
 800                 return -EINVAL;
 801         priv->dcfg = dcfg;
 802         if (priv->dcfg->type & IMX_MU_V2_IRQ) {
 803                 priv->irq[IMX_MU_TYPE_TX] = platform_get_irq_byname(pdev, "tx");
 804                 if (priv->irq[IMX_MU_TYPE_TX] < 0)
 805                         return priv->irq[IMX_MU_TYPE_TX];
 806                 priv->irq[IMX_MU_TYPE_RX] = platform_get_irq_byname(pdev, "rx");
 807                 if (priv->irq[IMX_MU_TYPE_RX] < 0)
 808                         return priv->irq[IMX_MU_TYPE_RX];
 809         } else {
 810                 ret = platform_get_irq(pdev, 0);
 811                 if (ret < 0)
 812                         return ret;
 813
 814                 for (i = 0; i < IMX_MU_CHANS; i++)
 815                         priv->irq[i] = ret;
 816         }
 817
 818         if (priv->dcfg->type & IMX_MU_V2_S4)
 819                 size = sizeof(struct imx_s4_rpc_msg_max);
 820         else
 821                 size = sizeof(struct imx_sc_rpc_msg_max);
 822
 823         priv->msg = devm_kzalloc(dev, size, GFP_KERNEL);
 824         if (!priv->msg)
 825                 return -ENOMEM;
 826
 827         priv->clk = devm_clk_get(dev, NULL);
 828         if (IS_ERR(priv->clk)) {
 829                 if (PTR_ERR(priv->clk) != -ENOENT)
 830                         return PTR_ERR(priv->clk);
 831
 832                 priv->clk = NULL;
 833         }
 834
 835         ret = clk_prepare_enable(priv->clk);
 836         if (ret) {
 837                 dev_err(dev, "Failed to enable clock\n");
 838                 return ret;
 839         }
 840
 841         priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
 842
 843         priv->dcfg->init(priv);
 844
 845         spin_lock_init(&priv->xcr_lock);
 846
 847         priv->mbox.dev = dev;
 848         priv->mbox.ops = &imx_mu_ops;
 849         priv->mbox.chans = priv->mbox_chans;
 850         priv->mbox.txdone_irq = true;
 851
 852         platform_set_drvdata(pdev, priv);
 853
 854         ret = devm_mbox_controller_register(dev, &priv->mbox);
 855         if (ret) {
 856                 clk_disable_unprepare(priv->clk);
 857                 return ret;
 858         }
 859
 860         pm_runtime_enable(dev);
 861
 862         ret = pm_runtime_resume_and_get(dev);
 863         if (ret < 0)
 864                 goto disable_runtime_pm;
 865
 866         ret = pm_runtime_put_sync(dev);
 867         if (ret < 0)
 868                 goto disable_runtime_pm;
 869
 870         clk_disable_unprepare(priv->clk);
 871
 872         return 0;
 873
 874 disable_runtime_pm:
 875         pm_runtime_disable(dev);
 876         clk_disable_unprepare(priv->clk);
 877         return ret;
 878 }
 879
 880 static int imx_mu_remove(struct platform_device *pdev)
 881 {
 882         struct imx_mu_priv *priv = platform_get_drvdata(pdev);
 883
 884         pm_runtime_disable(priv->dev);
 885
 886         return 0;
 887 }
 888
 889 static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
 890         .tx     = imx_mu_generic_tx,
 891         .rx     = imx_mu_generic_rx,
 892         .rxdb   = imx_mu_generic_rxdb,
 893         .init   = imx_mu_init_generic,
 894         .xTR    = 0x0,
 895         .xRR    = 0x10,
 896         .xSR    = {0x20, 0x20, 0x20, 0x20},
 897         .xCR    = {0x24, 0x24, 0x24, 0x24, 0x24},
 898 };
 899
 900 static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
 901         .tx     = imx_mu_generic_tx,
 902         .rx     = imx_mu_generic_rx,
 903         .rxdb   = imx_mu_generic_rxdb,
 904         .init   = imx_mu_init_generic,
 905         .xTR    = 0x20,
 906         .xRR    = 0x40,
 907         .xSR    = {0x60, 0x60, 0x60, 0x60},
 908         .xCR    = {0x64, 0x64, 0x64, 0x64, 0x64},
 909 };
 910
 911 static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {
 912         .tx     = imx_mu_generic_tx,
 913         .rx     = imx_mu_generic_rx,
 914         .rxdb   = imx_mu_generic_rxdb,
 915         .init   = imx_mu_init_generic,
 916         .type   = IMX_MU_V2,
 917         .xTR    = 0x200,
 918         .xRR    = 0x280,
 919         .xSR    = {0xC, 0x118, 0x124, 0x12C},
 920         .xCR    = {0x8, 0x110, 0x114, 0x120, 0x128},
 921 };
 922
 923 static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = {
 924         .tx     = imx_mu_specific_tx,
 925         .rx     = imx_mu_specific_rx,
 926         .init   = imx_mu_init_specific,
 927         .type   = IMX_MU_V2 | IMX_MU_V2_S4,
 928         .xTR    = 0x200,
 929         .xRR    = 0x280,
 930         .xSR    = {0xC, 0x118, 0x124, 0x12C},
 931         .xCR    = {0x8, 0x110, 0x114, 0x120, 0x128},
 932 };
 933
 934 static const struct imx_mu_dcfg imx_mu_cfg_imx93_s4 = {
 935         .tx     = imx_mu_specific_tx,
 936         .rx     = imx_mu_specific_rx,
 937         .init   = imx_mu_init_specific,
 938         .type   = IMX_MU_V2 | IMX_MU_V2_S4 | IMX_MU_V2_IRQ,
 939         .xTR    = 0x200,
 940         .xRR    = 0x280,
 941         .xSR    = {0xC, 0x118, 0x124, 0x12C},
 942         .xCR    = {0x8, 0x110, 0x114, 0x120, 0x128},
 943 };
 944
 945 static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
 946         .tx     = imx_mu_specific_tx,
 947         .rx     = imx_mu_specific_rx,
 948         .init   = imx_mu_init_specific,
 949         .rxdb   = imx_mu_generic_rxdb,
 950         .xTR    = 0x0,
 951         .xRR    = 0x10,
 952         .xSR    = {0x20, 0x20, 0x20, 0x20},
 953         .xCR    = {0x24, 0x24, 0x24, 0x24, 0x24},
 954 };
 955
 956 static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco = {
 957         .tx     = imx_mu_seco_tx,
 958         .rx     = imx_mu_generic_rx,
 959         .rxdb   = imx_mu_seco_rxdb,
 960         .init   = imx_mu_init_seco,
 961         .xTR    = 0x0,
 962         .xRR    = 0x10,
 963         .xSR    = {0x20, 0x20, 0x20, 0x20},
 964         .xCR    = {0x24, 0x24, 0x24, 0x24, 0x24},
 965 };
 966
 967 static const struct of_device_id imx_mu_dt_ids[] = {
 968         { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
 969         { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
 970         { .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp },
 971         { .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 },
 972         { .compatible = "fsl,imx93-mu-s4", .data = &imx_mu_cfg_imx93_s4 },
 973         { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
 974         { .compatible = "fsl,imx8-mu-seco", .data = &imx_mu_cfg_imx8_seco },
 975         { },
 976 };
 977 MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
 978
 979 static int __maybe_unused imx_mu_suspend_noirq(struct device *dev)
 980 {
 981         struct imx_mu_priv *priv = dev_get_drvdata(dev);
 982         int i;
 983
 984         if (!priv->clk) {
 985                 for (i = 0; i < IMX_MU_xCR_MAX; i++)
 986                         priv->xcr[i] = imx_mu_read(priv, priv->dcfg->xCR[i]);
 987         }
 988
 989         priv->suspend = true;
 990
 991         return 0;
 992 }
 993
 994 static int __maybe_unused imx_mu_resume_noirq(struct device *dev)
 995 {
 996         struct imx_mu_priv *priv = dev_get_drvdata(dev);
 997         int i;
 998
 999         /*
1000          * ONLY restore MU when context lost, the TIE could
1001          * be set during noirq resume as there is MU data
1002          * communication going on, and restore the saved
1003          * value will overwrite the TIE and cause MU data
1004          * send failed, may lead to system freeze. This issue
1005          * is observed by testing freeze mode suspend.
1006          */
1007         if (!priv->clk && !imx_mu_read(priv, priv->dcfg->xCR[0])) {
1008                 for (i = 0; i < IMX_MU_xCR_MAX; i++)
1009                         imx_mu_write(priv, priv->xcr[i], priv->dcfg->xCR[i]);
1010         }
1011
1012         priv->suspend = false;
1013
1014         return 0;
1015 }
1016
1017 static int __maybe_unused imx_mu_runtime_suspend(struct device *dev)
1018 {
1019         struct imx_mu_priv *priv = dev_get_drvdata(dev);
1020
1021         clk_disable_unprepare(priv->clk);
1022
1023         return 0;
1024 }
1025
1026 static int __maybe_unused imx_mu_runtime_resume(struct device *dev)
1027 {
1028         struct imx_mu_priv *priv = dev_get_drvdata(dev);
1029         int ret;
1030
1031         ret = clk_prepare_enable(priv->clk);
1032         if (ret)
1033                 dev_err(dev, "failed to enable clock\n");
1034
1035         return ret;
1036 }
1037
1038 static const struct dev_pm_ops imx_mu_pm_ops = {
1039         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_mu_suspend_noirq,
1040                                       imx_mu_resume_noirq)
1041         SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend,
1042                            imx_mu_runtime_resume, NULL)
1043 };
1044
1045 static struct platform_driver imx_mu_driver = {
1046         .probe          = imx_mu_probe,
1047         .remove         = imx_mu_remove,
1048         .driver = {
1049                 .name   = "imx_mu",
1050                 .of_match_table = imx_mu_dt_ids,
1051                 .pm = &imx_mu_pm_ops,
1052         },
1053 };
1054 module_platform_driver(imx_mu_driver);
1055
1056 MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
1057 MODULE_DESCRIPTION("Message Unit driver for i.MX");
1058 MODULE_LICENSE("GPL v2");