2 * Copyright (C) 2005-2006 Atmel Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #if defined(CONFIG_MACB) && (CONFIG_COMMANDS & (CFG_CMD_NET | CFG_CMD_MII))
23 * The u-boot networking stack is a little weird. It seems like the
24 * networking core allocates receive buffers up front without any
25 * regard to the hardware that's supposed to actually receive those
28 * The MACB receives packets into 128-byte receive buffers, so the
29 * buffers allocated by the core isn't very practical to use. We'll
30 * allocate our own, but we need one such buffer in case a packet
31 * wraps around the DMA ring so that we have to copy it.
33 * Therefore, define CFG_RX_ETH_BUFFER to 1 in the board-specific
34 * configuration header. This way, the core allocates one RX buffer
35 * and one TX buffer, each of which can hold a ethernet packet of
38 * For some reason, the networking core unconditionally specifies a
39 * 32-byte packet "alignment" (which really should be called
40 * "padding"). MACB shouldn't need that, but we'll refrain from any
41 * core modifications here...
47 #include <linux/mii.h>
49 #include <asm/dma-mapping.h>
50 #include <asm/arch/clk.h>
54 #define barrier() asm volatile("" ::: "memory")
56 #define CFG_MACB_RX_BUFFER_SIZE 4096
57 #define CFG_MACB_RX_RING_SIZE (CFG_MACB_RX_BUFFER_SIZE / 128)
58 #define CFG_MACB_TX_RING_SIZE 16
59 #define CFG_MACB_TX_TIMEOUT 1000
60 #define CFG_MACB_AUTONEG_TIMEOUT 5000000
62 struct macb_dma_desc {
67 #define RXADDR_USED 0x00000001
68 #define RXADDR_WRAP 0x00000002
70 #define RXBUF_FRMLEN_MASK 0x00000fff
71 #define RXBUF_FRAME_START 0x00004000
72 #define RXBUF_FRAME_END 0x00008000
73 #define RXBUF_TYPEID_MATCH 0x00400000
74 #define RXBUF_ADDR4_MATCH 0x00800000
75 #define RXBUF_ADDR3_MATCH 0x01000000
76 #define RXBUF_ADDR2_MATCH 0x02000000
77 #define RXBUF_ADDR1_MATCH 0x04000000
78 #define RXBUF_BROADCAST 0x80000000
80 #define TXBUF_FRMLEN_MASK 0x000007ff
81 #define TXBUF_FRAME_END 0x00008000
82 #define TXBUF_NOCRC 0x00010000
83 #define TXBUF_EXHAUSTED 0x08000000
84 #define TXBUF_UNDERRUN 0x10000000
85 #define TXBUF_MAXRETRY 0x20000000
86 #define TXBUF_WRAP 0x40000000
87 #define TXBUF_USED 0x80000000
98 struct macb_dma_desc *rx_ring;
99 struct macb_dma_desc *tx_ring;
101 unsigned long rx_buffer_dma;
102 unsigned long rx_ring_dma;
103 unsigned long tx_ring_dma;
105 const struct device *dev;
106 struct eth_device netdev;
107 unsigned short phy_addr;
109 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
111 static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value)
113 unsigned long netctl;
114 unsigned long netstat;
117 netctl = macb_readl(macb, NCR);
118 netctl |= MACB_BIT(MPE);
119 macb_writel(macb, NCR, netctl);
121 frame = (MACB_BF(SOF, 1)
123 | MACB_BF(PHYA, macb->phy_addr)
126 | MACB_BF(DATA, value));
127 macb_writel(macb, MAN, frame);
130 netstat = macb_readl(macb, NSR);
131 } while (!(netstat & MACB_BIT(IDLE)));
133 netctl = macb_readl(macb, NCR);
134 netctl &= ~MACB_BIT(MPE);
135 macb_writel(macb, NCR, netctl);
138 static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
140 unsigned long netctl;
141 unsigned long netstat;
144 netctl = macb_readl(macb, NCR);
145 netctl |= MACB_BIT(MPE);
146 macb_writel(macb, NCR, netctl);
148 frame = (MACB_BF(SOF, 1)
150 | MACB_BF(PHYA, macb->phy_addr)
153 macb_writel(macb, MAN, frame);
156 netstat = macb_readl(macb, NSR);
157 } while (!(netstat & MACB_BIT(IDLE)));
159 frame = macb_readl(macb, MAN);
161 netctl = macb_readl(macb, NCR);
162 netctl &= ~MACB_BIT(MPE);
163 macb_writel(macb, NCR, netctl);
165 return MACB_BFEXT(DATA, frame);
168 #if (CONFIG_COMMANDS & CFG_CMD_NET)
170 static int macb_send(struct eth_device *netdev, volatile void *packet,
173 struct macb_device *macb = to_macb(netdev);
174 unsigned long paddr, ctrl;
175 unsigned int tx_head = macb->tx_head;
178 paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
180 ctrl = length & TXBUF_FRMLEN_MASK;
181 ctrl |= TXBUF_FRAME_END;
182 if (tx_head == (CFG_MACB_TX_RING_SIZE - 1)) {
188 macb->tx_ring[tx_head].ctrl = ctrl;
189 macb->tx_ring[tx_head].addr = paddr;
191 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
194 * I guess this is necessary because the networking core may
195 * re-use the transmit buffer as soon as we return...
197 for (i = 0; i <= CFG_MACB_TX_TIMEOUT; i++) {
199 ctrl = macb->tx_ring[tx_head].ctrl;
200 if (ctrl & TXBUF_USED)
205 dma_unmap_single(packet, length, paddr);
207 if (i <= CFG_MACB_TX_TIMEOUT) {
208 if (ctrl & TXBUF_UNDERRUN)
209 printf("%s: TX underrun\n", netdev->name);
210 if (ctrl & TXBUF_EXHAUSTED)
211 printf("%s: TX buffers exhausted in mid frame\n",
214 printf("%s: TX timeout\n", netdev->name);
217 /* No one cares anyway */
221 static void reclaim_rx_buffers(struct macb_device *macb,
222 unsigned int new_tail)
227 while (i > new_tail) {
228 macb->rx_ring[i].addr &= ~RXADDR_USED;
230 if (i > CFG_MACB_RX_RING_SIZE)
234 while (i < new_tail) {
235 macb->rx_ring[i].addr &= ~RXADDR_USED;
240 macb->rx_tail = new_tail;
243 static int macb_recv(struct eth_device *netdev)
245 struct macb_device *macb = to_macb(netdev);
246 unsigned int rx_tail = macb->rx_tail;
253 if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED))
256 status = macb->rx_ring[rx_tail].ctrl;
257 if (status & RXBUF_FRAME_START) {
258 if (rx_tail != macb->rx_tail)
259 reclaim_rx_buffers(macb, rx_tail);
263 if (status & RXBUF_FRAME_END) {
264 buffer = macb->rx_buffer + 128 * macb->rx_tail;
265 length = status & RXBUF_FRMLEN_MASK;
267 unsigned int headlen, taillen;
269 headlen = 128 * (CFG_MACB_RX_RING_SIZE
271 taillen = length - headlen;
272 memcpy((void *)NetRxPackets[0],
274 memcpy((void *)NetRxPackets[0] + headlen,
275 macb->rx_buffer, taillen);
276 buffer = (void *)NetRxPackets[0];
279 NetReceive(buffer, length);
280 if (++rx_tail >= CFG_MACB_RX_RING_SIZE)
282 reclaim_rx_buffers(macb, rx_tail);
284 if (++rx_tail >= CFG_MACB_RX_RING_SIZE) {
295 static void macb_phy_reset(struct macb_device *macb)
297 struct eth_device *netdev = &macb->netdev;
301 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
302 macb_mdio_write(macb, MII_ADVERTISE, adv);
303 printf("%s: Starting autonegotiation...\n", netdev->name);
304 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
307 for (i = 0; i < CFG_MACB_AUTONEG_TIMEOUT / 100; i++) {
308 status = macb_mdio_read(macb, MII_BMSR);
309 if (status & BMSR_ANEGCOMPLETE)
314 if (status & BMSR_ANEGCOMPLETE)
315 printf("%s: Autonegotiation complete\n", netdev->name);
317 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
318 netdev->name, status);
321 static int macb_phy_init(struct macb_device *macb)
323 struct eth_device *netdev = &macb->netdev;
325 u16 phy_id, status, adv, lpa;
326 int media, speed, duplex;
329 /* Check if the PHY is up to snuff... */
330 phy_id = macb_mdio_read(macb, MII_PHYSID1);
331 if (phy_id == 0xffff) {
332 printf("%s: No PHY present\n", netdev->name);
336 status = macb_mdio_read(macb, MII_BMSR);
337 if (!(status & BMSR_LSTATUS)) {
338 /* Try to re-negotiate if we don't have link already. */
339 macb_phy_reset(macb);
341 for (i = 0; i < CFG_MACB_AUTONEG_TIMEOUT / 100; i++) {
342 status = macb_mdio_read(macb, MII_BMSR);
343 if (status & BMSR_LSTATUS)
349 if (!(status & BMSR_LSTATUS)) {
350 printf("%s: link down (status: 0x%04x)\n",
351 netdev->name, status);
354 adv = macb_mdio_read(macb, MII_ADVERTISE);
355 lpa = macb_mdio_read(macb, MII_LPA);
356 media = mii_nway_result(lpa & adv);
357 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
359 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
360 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
362 speed ? "100" : "10",
363 duplex ? "full" : "half",
366 ncfgr = macb_readl(macb, NCFGR);
367 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
369 ncfgr |= MACB_BIT(SPD);
371 ncfgr |= MACB_BIT(FD);
372 macb_writel(macb, NCFGR, ncfgr);
377 static int macb_init(struct eth_device *netdev, bd_t *bd)
379 struct macb_device *macb = to_macb(netdev);
386 * macb_halt should have been called at some point before now,
387 * so we'll assume the controller is idle.
390 /* initialize DMA descriptors */
391 paddr = macb->rx_buffer_dma;
392 for (i = 0; i < CFG_MACB_RX_RING_SIZE; i++) {
393 if (i == (CFG_MACB_RX_RING_SIZE - 1))
394 paddr |= RXADDR_WRAP;
395 macb->rx_ring[i].addr = paddr;
396 macb->rx_ring[i].ctrl = 0;
399 for (i = 0; i < CFG_MACB_TX_RING_SIZE; i++) {
400 macb->tx_ring[i].addr = 0;
401 if (i == (CFG_MACB_TX_RING_SIZE - 1))
402 macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
404 macb->tx_ring[i].ctrl = TXBUF_USED;
406 macb->rx_tail = macb->tx_head = macb->tx_tail = 0;
408 macb_writel(macb, RBQP, macb->rx_ring_dma);
409 macb_writel(macb, TBQP, macb->tx_ring_dma);
411 /* set hardware address */
412 hwaddr_bottom = cpu_to_le32(*((u32 *)netdev->enetaddr));
413 macb_writel(macb, SA1B, hwaddr_bottom);
414 hwaddr_top = cpu_to_le16(*((u16 *)(netdev->enetaddr + 4)));
415 macb_writel(macb, SA1T, hwaddr_top);
417 /* choose RMII or MII mode. This depends on the board */
419 macb_writel(macb, USRIO, 0);
421 macb_writel(macb, USRIO, MACB_BIT(MII));
424 if (!macb_phy_init(macb))
427 /* Enable TX and RX */
428 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
433 static void macb_halt(struct eth_device *netdev)
435 struct macb_device *macb = to_macb(netdev);
438 /* Halt the controller and wait for any ongoing transmission to end. */
439 ncr = macb_readl(macb, NCR);
440 ncr |= MACB_BIT(THALT);
441 macb_writel(macb, NCR, ncr);
444 tsr = macb_readl(macb, TSR);
445 } while (tsr & MACB_BIT(TGO));
447 /* Disable TX and RX, and clear statistics */
448 macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
451 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
453 struct macb_device *macb;
454 struct eth_device *netdev;
455 unsigned long macb_hz;
458 macb = malloc(sizeof(struct macb_device));
460 printf("Error: Failed to allocate memory for MACB%d\n", id);
463 memset(macb, 0, sizeof(struct macb_device));
465 netdev = &macb->netdev;
467 macb->rx_buffer = dma_alloc_coherent(CFG_MACB_RX_BUFFER_SIZE,
468 &macb->rx_buffer_dma);
469 macb->rx_ring = dma_alloc_coherent(CFG_MACB_RX_RING_SIZE
470 * sizeof(struct macb_dma_desc),
472 macb->tx_ring = dma_alloc_coherent(CFG_MACB_TX_RING_SIZE
473 * sizeof(struct macb_dma_desc),
477 macb->phy_addr = phy_addr;
479 sprintf(netdev->name, "macb%d", id);
480 netdev->init = macb_init;
481 netdev->halt = macb_halt;
482 netdev->send = macb_send;
483 netdev->recv = macb_recv;
486 * Do some basic initialization so that we at least can talk
489 macb_hz = get_macb_pclk_rate(id);
490 if (macb_hz < 20000000)
491 ncfgr = MACB_BF(CLK, MACB_CLK_DIV8);
492 else if (macb_hz < 40000000)
493 ncfgr = MACB_BF(CLK, MACB_CLK_DIV16);
494 else if (macb_hz < 80000000)
495 ncfgr = MACB_BF(CLK, MACB_CLK_DIV32);
497 ncfgr = MACB_BF(CLK, MACB_CLK_DIV64);
499 macb_writel(macb, NCFGR, ncfgr);
501 eth_register(netdev);
506 #endif /* (CONFIG_COMMANDS & CFG_CMD_NET) */
508 #if (CONFIG_COMMANDS & CFG_CMD_MII)
510 int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
512 unsigned long netctl;
513 unsigned long netstat;
517 iflag = disable_interrupts();
518 netctl = macb_readl(&macb, EMACB_NCR);
519 netctl |= MACB_BIT(MPE);
520 macb_writel(&macb, EMACB_NCR, netctl);
524 frame = (MACB_BF(SOF, 1)
526 | MACB_BF(PHYA, addr)
529 macb_writel(&macb, EMACB_MAN, frame);
532 netstat = macb_readl(&macb, EMACB_NSR);
533 } while (!(netstat & MACB_BIT(IDLE)));
535 frame = macb_readl(&macb, EMACB_MAN);
536 *value = MACB_BFEXT(DATA, frame);
538 iflag = disable_interrupts();
539 netctl = macb_readl(&macb, EMACB_NCR);
540 netctl &= ~MACB_BIT(MPE);
541 macb_writel(&macb, EMACB_NCR, netctl);
548 int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
550 unsigned long netctl;
551 unsigned long netstat;
555 iflag = disable_interrupts();
556 netctl = macb_readl(&macb, EMACB_NCR);
557 netctl |= MACB_BIT(MPE);
558 macb_writel(&macb, EMACB_NCR, netctl);
562 frame = (MACB_BF(SOF, 1)
564 | MACB_BF(PHYA, addr)
567 | MACB_BF(DATA, value));
568 macb_writel(&macb, EMACB_MAN, frame);
571 netstat = macb_readl(&macb, EMACB_NSR);
572 } while (!(netstat & MACB_BIT(IDLE)));
574 iflag = disable_interrupts();
575 netctl = macb_readl(&macb, EMACB_NCR);
576 netctl &= ~MACB_BIT(MPE);
577 macb_writel(&macb, EMACB_NCR, netctl);
584 #endif /* (CONFIG_COMMANDS & CFG_CMD_MII) */
586 #endif /* CONFIG_MACB */