2 * hfcmulti.c low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
4 * Author Andreas Eversberg (jolly@eversberg.eu)
5 * ported to mqueue mechanism:
6 * Peter Sprenger (sprengermoving-bytes.de)
8 * inspired by existing hfc-pci driver:
9 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
10 * Copyright 2008 by Karsten Keil (kkeil@suse.de)
11 * Copyright 2008 by Andreas Eversberg (jolly@eversberg.eu)
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 * Thanks to Cologne Chip AG for this great controller!
34 * By default (0), the card is automatically detected.
35 * Or use the following combinations:
36 * Bit 0-7 = 0x00001 = HFC-E1 (1 port)
37 * or Bit 0-7 = 0x00004 = HFC-4S (4 ports)
38 * or Bit 0-7 = 0x00008 = HFC-8S (8 ports)
39 * Bit 8 = 0x00100 = uLaw (instead of aLaw)
40 * Bit 9 = 0x00200 = Disable DTMF detect on all B-channels via hardware
42 * Bit 11 = 0x00800 = Force PCM bus into slave mode. (otherwhise auto)
43 * or Bit 12 = 0x01000 = Force PCM bus into master mode. (otherwhise auto)
45 * Bit 14 = 0x04000 = Use external ram (128K)
46 * Bit 15 = 0x08000 = Use external ram (512K)
47 * Bit 16 = 0x10000 = Use 64 timeslots instead of 32
48 * or Bit 17 = 0x20000 = Use 128 timeslots instead of anything else
50 * Bit 19 = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog)
51 * (all other bits are reserved and shall be 0)
52 * example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM
55 * port: (optional or required for all ports on all installed cards)
56 * HFC-4S/HFC-8S only bits:
57 * Bit 0 = 0x001 = Use master clock for this S/T interface
58 * (ony once per chip).
59 * Bit 1 = 0x002 = transmitter line setup (non capacitive mode)
60 * Don't use this unless you know what you are doing!
61 * Bit 2 = 0x004 = Disable E-channel. (No E-channel processing)
62 * example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock
63 * received from port 1
66 * Bit 0 = 0x0001 = interface: 0=copper, 1=optical
67 * Bit 1 = 0x0002 = reserved (later for 32 B-channels transparent mode)
68 * Bit 2 = 0x0004 = Report LOS
69 * Bit 3 = 0x0008 = Report AIS
70 * Bit 4 = 0x0010 = Report SLIP
71 * Bit 5 = 0x0020 = Report RDI
72 * Bit 8 = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame
74 * Bit 9 = 0x0200 = Force get clock from interface, even in NT mode.
75 * or Bit 10 = 0x0400 = Force put clock to interface, even in TE mode.
76 * Bit 11 = 0x0800 = Use direct RX clock for PCM sync rather than PLL.
78 * Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0
80 * (all other bits are reserved and shall be 0)
83 * NOTE: only one debug value must be given for all cards
84 * enable debugging (see hfc_multi.h for debug options)
87 * NOTE: only one poll value must be given for all cards
88 * Give the number of samples for each fifo process.
89 * By default 128 is used. Decrease to reduce delay, increase to
90 * reduce cpu load. If unsure, don't mess with it!
91 * Valid is 8, 16, 32, 64, 128, 256.
94 * NOTE: only one pcm value must be given for every card.
95 * The PCM bus id tells the mISDNdsp module about the connected PCM bus.
96 * By default (0), the PCM bus id is 100 for the card that is PCM master.
97 * If multiple cards are PCM master (because they are not interconnected),
98 * each card with PCM master will have increasing PCM id.
99 * All PCM busses with the same ID are expected to be connected and have
100 * common time slots slots.
101 * Only one chip of the PCM bus must be master, the others slave.
102 * -1 means no support of PCM bus not even.
103 * Omit this value, if all cards are interconnected or none is connected.
104 * If unsure, don't give this parameter.
107 * NOTE: only one poll value must be given for every card.
108 * Also this value must be given for non-E1 cards. If omitted, the E1
109 * card has D-channel on time slot 16, which is default.
110 * If 1..15 or 17..31, an alternate time slot is used for D-channel.
111 * In this case, the application must be able to handle this.
112 * If -1 is given, the D-channel is disabled and all 31 slots can be used
113 * for B-channel. (only for specific applications)
114 * If you don't know how to use it, you don't need it!
117 * NOTE: only one mode value must be given for every card.
118 * -> See hfc_multi.h for HFC_IO_MODE_* values
119 * By default, the IO mode is pci memory IO (MEMIO).
120 * Some cards requre specific IO mode, so it cannot be changed.
121 * It may be usefull to set IO mode to register io (REGIO) to solve
122 * PCI bridge problems.
123 * If unsure, don't give this parameter.
126 * NOTE: only one clockdelay_nt value must be given once for all cards.
127 * Give the value of the clock control register (A_ST_CLK_DLY)
128 * of the S/T interfaces in NT mode.
129 * This register is needed for the TBR3 certification, so don't change it.
132 * NOTE: only one clockdelay_te value must be given once
133 * Give the value of the clock control register (A_ST_CLK_DLY)
134 * of the S/T interfaces in TE mode.
135 * This register is needed for the TBR3 certification, so don't change it.
139 * debug register access (never use this, it will flood your system log)
140 * #define HFC_REGISTER_DEBUG
143 #define HFC_MULTI_VERSION "2.03"
145 #include <linux/module.h>
146 #include <linux/pci.h>
147 #include <linux/delay.h>
148 #include <linux/mISDNhw.h>
149 #include <linux/mISDNdsp.h>
152 #define IRQCOUNT_DEBUG
156 #include "hfc_multi.h"
162 #define MAX_PORTS (8 * MAX_CARDS)
164 static LIST_HEAD(HFClist);
165 static spinlock_t HFClock; /* global hfc list lock */
167 static void ph_state_change(struct dchannel *);
169 static struct hfc_multi *syncmaster;
170 static int plxsd_master; /* if we have a master card (yet) */
171 static spinlock_t plx_lock; /* may not acquire other lock inside */
177 static int poll_timer = 6; /* default = 128 samples = 16ms */
178 /* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */
179 static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30 };
180 #define CLKDEL_TE 0x0f /* CLKDEL in TE mode */
181 #define CLKDEL_NT 0x6c /* CLKDEL in NT mode
182 (0x60 MUST be included!) */
184 #define DIP_4S 0x1 /* DIP Switches for Beronet 1S/2S/4S cards */
185 #define DIP_8S 0x2 /* DIP Switches for Beronet 8S+ cards */
186 #define DIP_E1 0x3 /* DIP Switches for Beronet E1 cards */
192 static uint type[MAX_CARDS];
193 static uint pcm[MAX_CARDS];
194 static uint dslot[MAX_CARDS];
195 static uint iomode[MAX_CARDS];
196 static uint port[MAX_PORTS];
200 static uint clockdelay_te = CLKDEL_TE;
201 static uint clockdelay_nt = CLKDEL_NT;
203 static int HFC_cnt, Port_cnt, PCM_cnt = 99;
205 MODULE_AUTHOR("Andreas Eversberg");
206 MODULE_LICENSE("GPL");
207 MODULE_VERSION(HFC_MULTI_VERSION);
208 module_param(debug, uint, S_IRUGO | S_IWUSR);
209 module_param(poll, uint, S_IRUGO | S_IWUSR);
210 module_param(timer, uint, S_IRUGO | S_IWUSR);
211 module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR);
212 module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR);
213 module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR);
214 module_param_array(pcm, uint, NULL, S_IRUGO | S_IWUSR);
215 module_param_array(dslot, uint, NULL, S_IRUGO | S_IWUSR);
216 module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR);
217 module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR);
219 #ifdef HFC_REGISTER_DEBUG
220 #define HFC_outb(hc, reg, val) \
221 (hc->HFC_outb(hc, reg, val, __func__, __LINE__))
222 #define HFC_outb_nodebug(hc, reg, val) \
223 (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__))
224 #define HFC_inb(hc, reg) \
225 (hc->HFC_inb(hc, reg, __func__, __LINE__))
226 #define HFC_inb_nodebug(hc, reg) \
227 (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__))
228 #define HFC_inw(hc, reg) \
229 (hc->HFC_inw(hc, reg, __func__, __LINE__))
230 #define HFC_inw_nodebug(hc, reg) \
231 (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__))
232 #define HFC_wait(hc) \
233 (hc->HFC_wait(hc, __func__, __LINE__))
234 #define HFC_wait_nodebug(hc) \
235 (hc->HFC_wait_nodebug(hc, __func__, __LINE__))
237 #define HFC_outb(hc, reg, val) (hc->HFC_outb(hc, reg, val))
238 #define HFC_outb_nodebug(hc, reg, val) (hc->HFC_outb_nodebug(hc, reg, val))
239 #define HFC_inb(hc, reg) (hc->HFC_inb(hc, reg))
240 #define HFC_inb_nodebug(hc, reg) (hc->HFC_inb_nodebug(hc, reg))
241 #define HFC_inw(hc, reg) (hc->HFC_inw(hc, reg))
242 #define HFC_inw_nodebug(hc, reg) (hc->HFC_inw_nodebug(hc, reg))
243 #define HFC_wait(hc) (hc->HFC_wait(hc))
244 #define HFC_wait_nodebug(hc) (hc->HFC_wait_nodebug(hc))
247 /* HFC_IO_MODE_PCIMEM */
249 #ifdef HFC_REGISTER_DEBUG
250 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val,
251 const char *function, int line)
253 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val)
256 writeb(val, (hc->pci_membase)+reg);
259 #ifdef HFC_REGISTER_DEBUG
260 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
262 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg)
265 return readb((hc->pci_membase)+reg);
268 #ifdef HFC_REGISTER_DEBUG
269 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
271 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg)
274 return readw((hc->pci_membase)+reg);
277 #ifdef HFC_REGISTER_DEBUG
278 HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line)
280 HFC_wait_pcimem(struct hfc_multi *hc)
283 while (readb((hc->pci_membase)+R_STATUS) & V_BUSY);
286 /* HFC_IO_MODE_REGIO */
288 #ifdef HFC_REGISTER_DEBUG
289 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val,
290 const char *function, int line)
292 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val)
295 outb(reg, (hc->pci_iobase)+4);
296 outb(val, hc->pci_iobase);
299 #ifdef HFC_REGISTER_DEBUG
300 HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
302 HFC_inb_regio(struct hfc_multi *hc, u_char reg)
305 outb(reg, (hc->pci_iobase)+4);
306 return inb(hc->pci_iobase);
309 #ifdef HFC_REGISTER_DEBUG
310 HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
312 HFC_inw_regio(struct hfc_multi *hc, u_char reg)
315 outb(reg, (hc->pci_iobase)+4);
316 return inw(hc->pci_iobase);
319 #ifdef HFC_REGISTER_DEBUG
320 HFC_wait_regio(struct hfc_multi *hc, const char *function, int line)
322 HFC_wait_regio(struct hfc_multi *hc)
325 outb(R_STATUS, (hc->pci_iobase)+4);
326 while (inb(hc->pci_iobase) & V_BUSY);
329 #ifdef HFC_REGISTER_DEBUG
331 HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val,
332 const char *function, int line)
334 char regname[256] = "", bits[9] = "xxxxxxxx";
338 while (hfc_register_names[++i].name) {
339 if (hfc_register_names[i].reg == reg)
340 strcat(regname, hfc_register_names[i].name);
342 if (regname[0] == '\0')
343 strcpy(regname, "register");
345 bits[7] = '0'+(!!(val&1));
346 bits[6] = '0'+(!!(val&2));
347 bits[5] = '0'+(!!(val&4));
348 bits[4] = '0'+(!!(val&8));
349 bits[3] = '0'+(!!(val&16));
350 bits[2] = '0'+(!!(val&32));
351 bits[1] = '0'+(!!(val&64));
352 bits[0] = '0'+(!!(val&128));
354 "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n",
355 hc->id, reg, regname, val, bits, function, line);
356 HFC_outb_nodebug(hc, reg, val);
359 HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
361 char regname[256] = "", bits[9] = "xxxxxxxx";
362 u_char val = HFC_inb_nodebug(hc, reg);
366 while (hfc_register_names[i++].name)
368 while (hfc_register_names[++i].name) {
369 if (hfc_register_names[i].reg == reg)
370 strcat(regname, hfc_register_names[i].name);
372 if (regname[0] == '\0')
373 strcpy(regname, "register");
375 bits[7] = '0'+(!!(val&1));
376 bits[6] = '0'+(!!(val&2));
377 bits[5] = '0'+(!!(val&4));
378 bits[4] = '0'+(!!(val&8));
379 bits[3] = '0'+(!!(val&16));
380 bits[2] = '0'+(!!(val&32));
381 bits[1] = '0'+(!!(val&64));
382 bits[0] = '0'+(!!(val&128));
384 "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n",
385 hc->id, reg, regname, val, bits, function, line);
389 HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
391 char regname[256] = "";
392 u_short val = HFC_inw_nodebug(hc, reg);
396 while (hfc_register_names[i++].name)
398 while (hfc_register_names[++i].name) {
399 if (hfc_register_names[i].reg == reg)
400 strcat(regname, hfc_register_names[i].name);
402 if (regname[0] == '\0')
403 strcpy(regname, "register");
406 "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n",
407 hc->id, reg, regname, val, function, line);
411 HFC_wait_debug(struct hfc_multi *hc, const char *function, int line)
413 printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n",
414 hc->id, function, line);
415 HFC_wait_nodebug(hc);
419 /* write fifo data (REGIO) */
421 write_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
423 outb(A_FIFO_DATA0, (hc->pci_iobase)+4);
425 outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase);
430 outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase);
435 outb(*data, hc->pci_iobase);
440 /* write fifo data (PCIMEM) */
442 write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
445 writel(cpu_to_le32(*(u32 *)data),
446 hc->pci_membase + A_FIFO_DATA0);
451 writew(cpu_to_le16(*(u16 *)data),
452 hc->pci_membase + A_FIFO_DATA0);
457 writeb(*data, hc->pci_membase + A_FIFO_DATA0);
462 /* read fifo data (REGIO) */
464 read_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
466 outb(A_FIFO_DATA0, (hc->pci_iobase)+4);
468 *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase));
473 *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase));
478 *data = inb(hc->pci_iobase);
484 /* read fifo data (PCIMEM) */
486 read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
490 le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0));
496 le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0));
501 *data = readb(hc->pci_membase + A_FIFO_DATA0);
509 enable_hwirq(struct hfc_multi *hc)
511 hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN;
512 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
516 disable_hwirq(struct hfc_multi *hc)
518 hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN);
519 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
523 #define MAX_TDM_CHAN 32
527 enablepcibridge(struct hfc_multi *c)
529 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */
533 disablepcibridge(struct hfc_multi *c)
535 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */
539 readpcibridge(struct hfc_multi *hc, unsigned char address)
547 /* slow down a PCI read access by 1 PCI clock cycle */
548 HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/
555 /* select local bridge port address by writing to CIP port */
556 /* data = HFC_inb(c, cipv); * was _io before */
557 outw(cipv, hc->pci_iobase + 4);
558 data = inb(hc->pci_iobase);
560 /* restore R_CTRL for normal PCI read cycle speed */
561 HFC_outb(hc, R_CTRL, 0x0); /* was _io before */
567 writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data)
580 /* select local bridge port address by writing to CIP port */
581 outw(cipv, hc->pci_iobase + 4);
582 /* define a 32 bit dword with 4 identical bytes for write sequence */
583 datav = data | ((__u32) data << 8) | ((__u32) data << 16) |
584 ((__u32) data << 24);
587 * write this 32 bit dword to the bridge data port
588 * this will initiate a write sequence of up to 4 writes to the same
589 * address on the local bus interface the number of write accesses
590 * is undefined but >=1 and depends on the next PCI transaction
591 * during write sequence on the local bus
593 outl(datav, hc->pci_iobase);
597 cpld_set_reg(struct hfc_multi *hc, unsigned char reg)
599 /* Do data pin read low byte */
600 HFC_outb(hc, R_GPIO_OUT1, reg);
604 cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val)
606 cpld_set_reg(hc, reg);
609 writepcibridge(hc, 1, val);
610 disablepcibridge(hc);
616 cpld_read_reg(struct hfc_multi *hc, unsigned char reg)
618 unsigned char bytein;
620 cpld_set_reg(hc, reg);
622 /* Do data pin read low byte */
623 HFC_outb(hc, R_GPIO_OUT1, reg);
626 bytein = readpcibridge(hc, 1);
627 disablepcibridge(hc);
633 vpm_write_address(struct hfc_multi *hc, unsigned short addr)
635 cpld_write_reg(hc, 0, 0xff & addr);
636 cpld_write_reg(hc, 1, 0x01 & (addr >> 8));
639 inline unsigned short
640 vpm_read_address(struct hfc_multi *c)
643 unsigned short highbit;
645 addr = cpld_read_reg(c, 0);
646 highbit = cpld_read_reg(c, 1);
648 addr = addr | (highbit << 8);
654 vpm_in(struct hfc_multi *c, int which, unsigned short addr)
658 vpm_write_address(c, addr);
666 res = readpcibridge(c, 1);
675 vpm_out(struct hfc_multi *c, int which, unsigned short addr,
678 vpm_write_address(c, addr);
687 writepcibridge(c, 1, data);
695 regin = vpm_in(c, which, addr);
697 printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back "
698 "0x%x\n", data, addr, regin);
705 vpm_init(struct hfc_multi *wc)
709 unsigned int i, x, y;
712 for (x = 0; x < NUM_EC; x++) {
715 ver = vpm_in(wc, x, 0x1a0);
716 printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver);
719 for (y = 0; y < 4; y++) {
720 vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */
721 vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */
722 vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */
725 /* Setup TDM path - sets fsync and tdm_clk as inputs */
726 reg = vpm_in(wc, x, 0x1a3); /* misc_con */
727 vpm_out(wc, x, 0x1a3, reg & ~2);
729 /* Setup Echo length (256 taps) */
730 vpm_out(wc, x, 0x022, 1);
731 vpm_out(wc, x, 0x023, 0xff);
733 /* Setup timeslots */
734 vpm_out(wc, x, 0x02f, 0x00);
735 mask = 0x02020202 << (x * 4);
737 /* Setup the tdm channel masks for all chips */
738 for (i = 0; i < 4; i++)
739 vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff);
741 /* Setup convergence rate */
742 printk(KERN_DEBUG "VPM: A-law mode\n");
743 reg = 0x00 | 0x10 | 0x01;
744 vpm_out(wc, x, 0x20, reg);
745 printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg);
746 /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */
748 vpm_out(wc, x, 0x24, 0x02);
749 reg = vpm_in(wc, x, 0x24);
750 printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg);
752 /* Initialize echo cans */
753 for (i = 0; i < MAX_TDM_CHAN; i++) {
754 if (mask & (0x00000001 << i))
755 vpm_out(wc, x, i, 0x00);
759 * ARM arch at least disallows a udelay of
760 * more than 2ms... it gives a fake "__bad_udelay"
761 * reference at link-time.
762 * long delays in kernel code are pretty sucky anyway
763 * for now work around it using 5 x 2ms instead of 1 x 10ms
772 /* Put in bypass mode */
773 for (i = 0; i < MAX_TDM_CHAN; i++) {
774 if (mask & (0x00000001 << i))
775 vpm_out(wc, x, i, 0x01);
779 for (i = 0; i < MAX_TDM_CHAN; i++) {
780 if (mask & (0x00000001 << i))
781 vpm_out(wc, x, 0x78 + i, 0x01);
789 vpm_check(struct hfc_multi *hctmp)
793 gpi2 = HFC_inb(hctmp, R_GPI_IN2);
795 if ((gpi2 & 0x3) != 0x3)
796 printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2);
802 * Interface to enable/disable the HW Echocan
804 * these functions are called within a spin_lock_irqsave on
805 * the channel instance lock, so we are not disturbed by irqs
807 * we can later easily change the interface to make other
808 * things configurable, for now we configure the taps
813 vpm_echocan_on(struct hfc_multi *hc, int ch, int taps)
815 unsigned int timeslot;
817 struct bchannel *bch = hc->chan[ch].bch;
822 if (hc->chan[ch].protocol != ISDN_P_B_RAW)
829 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
830 sizeof(int), &txadj, GFP_ATOMIC);
832 recv_Bchannel_skb(bch, skb);
835 timeslot = ((ch/4)*8) + ((ch%4)*4) + 1;
838 printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n",
841 vpm_out(hc, unit, timeslot, 0x7e);
845 vpm_echocan_off(struct hfc_multi *hc, int ch)
847 unsigned int timeslot;
849 struct bchannel *bch = hc->chan[ch].bch;
855 if (hc->chan[ch].protocol != ISDN_P_B_RAW)
862 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
863 sizeof(int), &txadj, GFP_ATOMIC);
865 recv_Bchannel_skb(bch, skb);
868 timeslot = ((ch/4)*8) + ((ch%4)*4) + 1;
871 printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n",
874 vpm_out(hc, unit, timeslot, 0x01);
879 * Speech Design resync feature
880 * NOTE: This is called sometimes outside interrupt handler.
881 * We must lock irqsave, so no other interrupt (other card) will occurr!
882 * Also multiple interrupts may nest, so must lock each access (lists, card)!
885 hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
887 struct hfc_multi *hc, *next, *pcmmaster = NULL;
888 void __iomem *plx_acc_32;
892 spin_lock_irqsave(&HFClock, flags);
893 spin_lock(&plx_lock); /* must be locked inside other locks */
895 if (debug & DEBUG_HFCMULTI_PLXSD)
896 printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n",
897 __func__, syncmaster);
899 /* select new master */
901 if (debug & DEBUG_HFCMULTI_PLXSD)
902 printk(KERN_DEBUG "using provided controller\n");
904 list_for_each_entry_safe(hc, next, &HFClist, list) {
905 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
906 if (hc->syncronized) {
914 /* Disable sync of all cards */
915 list_for_each_entry_safe(hc, next, &HFClist, list) {
916 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
917 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
918 pv = readl(plx_acc_32);
919 pv &= ~PLX_SYNC_O_EN;
920 writel(pv, plx_acc_32);
921 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
924 if (debug & DEBUG_HFCMULTI_PLXSD)
926 "Schedule SYNC_I\n");
927 hc->e1_resync |= 1; /* get SYNC_I */
935 if (debug & DEBUG_HFCMULTI_PLXSD)
936 printk(KERN_DEBUG "id=%d (0x%p) = syncronized with "
937 "interface.\n", hc->id, hc);
938 /* Enable new sync master */
939 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
940 pv = readl(plx_acc_32);
942 writel(pv, plx_acc_32);
943 /* switch to jatt PLL, if not disabled by RX_SYNC */
944 if (hc->type == 1 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
945 if (debug & DEBUG_HFCMULTI_PLXSD)
946 printk(KERN_DEBUG "Schedule jatt PLL\n");
947 hc->e1_resync |= 2; /* switch to jatt */
952 if (debug & DEBUG_HFCMULTI_PLXSD)
954 "id=%d (0x%p) = PCM master syncronized "
955 "with QUARTZ\n", hc->id, hc);
957 /* Use the crystal clock for the PCM
959 if (debug & DEBUG_HFCMULTI_PLXSD)
961 "Schedule QUARTZ for HFC-E1\n");
962 hc->e1_resync |= 4; /* switch quartz */
964 if (debug & DEBUG_HFCMULTI_PLXSD)
966 "QUARTZ is automatically "
967 "enabled by HFC-%dS\n", hc->type);
969 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
970 pv = readl(plx_acc_32);
972 writel(pv, plx_acc_32);
975 printk(KERN_ERR "%s no pcm master, this MUST "
976 "not happen!\n", __func__);
978 syncmaster = newmaster;
980 spin_unlock(&plx_lock);
981 spin_unlock_irqrestore(&HFClock, flags);
984 /* This must be called AND hc must be locked irqsave!!! */
986 plxsd_checksync(struct hfc_multi *hc, int rm)
988 if (hc->syncronized) {
989 if (syncmaster == NULL) {
990 if (debug & DEBUG_HFCMULTI_PLXSD)
991 printk(KERN_WARNING "%s: GOT sync on card %d"
992 " (id=%d)\n", __func__, hc->id + 1,
994 hfcmulti_resync(hc, hc, rm);
997 if (syncmaster == hc) {
998 if (debug & DEBUG_HFCMULTI_PLXSD)
999 printk(KERN_WARNING "%s: LOST sync on card %d"
1000 " (id=%d)\n", __func__, hc->id + 1,
1002 hfcmulti_resync(hc, NULL, rm);
1009 * free hardware resources used by driver
1012 release_io_hfcmulti(struct hfc_multi *hc)
1014 void __iomem *plx_acc_32;
1018 if (debug & DEBUG_HFCMULTI_INIT)
1019 printk(KERN_DEBUG "%s: entered\n", __func__);
1021 /* soft reset also masks all interrupts */
1022 hc->hw.r_cirm |= V_SRES;
1023 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1025 hc->hw.r_cirm &= ~V_SRES;
1026 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1027 udelay(1000); /* instead of 'wait' that may cause locking */
1029 /* release Speech Design card, if PLX was initialized */
1030 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) {
1031 if (debug & DEBUG_HFCMULTI_PLXSD)
1032 printk(KERN_DEBUG "%s: release PLXSD card %d\n",
1033 __func__, hc->id + 1);
1034 spin_lock_irqsave(&plx_lock, plx_flags);
1035 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1036 writel(PLX_GPIOC_INIT, plx_acc_32);
1037 pv = readl(plx_acc_32);
1038 /* Termination off */
1040 /* Disconnect the PCM */
1041 pv |= PLX_SLAVE_EN_N;
1042 pv &= ~PLX_MASTER_EN;
1043 pv &= ~PLX_SYNC_O_EN;
1044 /* Put the DSP in Reset */
1045 pv &= ~PLX_DSP_RES_N;
1046 writel(pv, plx_acc_32);
1047 if (debug & DEBUG_HFCMULTI_INIT)
1048 printk(KERN_WARNING "%s: PCM off: PLX_GPIO=%x\n",
1050 spin_unlock_irqrestore(&plx_lock, plx_flags);
1053 /* disable memory mapped ports / io ports */
1054 test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */
1055 pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
1056 if (hc->pci_membase)
1057 iounmap(hc->pci_membase);
1058 if (hc->plx_membase)
1059 iounmap(hc->plx_membase);
1061 release_region(hc->pci_iobase, 8);
1064 pci_disable_device(hc->pci_dev);
1065 pci_set_drvdata(hc->pci_dev, NULL);
1067 if (debug & DEBUG_HFCMULTI_INIT)
1068 printk(KERN_DEBUG "%s: done\n", __func__);
1072 * function called to reset the HFC chip. A complete software reset of chip
1073 * and fifos is done. All configuration of the chip is done.
1077 init_chip(struct hfc_multi *hc)
1079 u_long flags, val, val2 = 0, rev;
1081 u_char r_conf_en, rval;
1082 void __iomem *plx_acc_32;
1084 u_long plx_flags, hfc_flags;
1086 struct hfc_multi *pos, *next, *plx_last_hc;
1088 spin_lock_irqsave(&hc->lock, flags);
1089 /* reset all registers */
1090 memset(&hc->hw, 0, sizeof(struct hfcm_hw));
1092 /* revision check */
1093 if (debug & DEBUG_HFCMULTI_INIT)
1094 printk(KERN_DEBUG "%s: entered\n", __func__);
1095 val = HFC_inb(hc, R_CHIP_ID)>>4;
1096 if (val != 0x8 && val != 0xc && val != 0xe) {
1097 printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val);
1101 rev = HFC_inb(hc, R_CHIP_RV);
1103 "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n",
1104 val, rev, (rev == 0) ? " (old FIFO handling)" : "");
1106 test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip);
1108 "HFC_multi: NOTE: Your chip is revision 0, "
1109 "ask Cologne Chip for update. Newer chips "
1110 "have a better FIFO handling. Old chips "
1111 "still work but may have slightly lower "
1112 "HDLC transmit performance.\n");
1115 printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't "
1116 "consider chip revision = %ld. The chip / "
1117 "bridge may not work.\n", rev);
1120 /* set s-ram size */
1124 hc->DTMFbase = 0x1000;
1125 if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) {
1126 if (debug & DEBUG_HFCMULTI_INIT)
1127 printk(KERN_DEBUG "%s: changing to 128K extenal RAM\n",
1129 hc->hw.r_ctrl |= V_EXT_RAM;
1130 hc->hw.r_ram_sz = 1;
1134 hc->DTMFbase = 0x2000;
1136 if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) {
1137 if (debug & DEBUG_HFCMULTI_INIT)
1138 printk(KERN_DEBUG "%s: changing to 512K extenal RAM\n",
1140 hc->hw.r_ctrl |= V_EXT_RAM;
1141 hc->hw.r_ram_sz = 2;
1145 hc->DTMFbase = 0x2000;
1147 hc->max_trans = poll << 1;
1148 if (hc->max_trans > hc->Zlen)
1149 hc->max_trans = hc->Zlen;
1151 /* Speech Design PLX bridge */
1152 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1153 if (debug & DEBUG_HFCMULTI_PLXSD)
1154 printk(KERN_DEBUG "%s: initializing PLXSD card %d\n",
1155 __func__, hc->id + 1);
1156 spin_lock_irqsave(&plx_lock, plx_flags);
1157 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1158 writel(PLX_GPIOC_INIT, plx_acc_32);
1159 pv = readl(plx_acc_32);
1160 /* The first and the last cards are terminating the PCM bus */
1161 pv |= PLX_TERM_ON; /* hc is currently the last */
1162 /* Disconnect the PCM */
1163 pv |= PLX_SLAVE_EN_N;
1164 pv &= ~PLX_MASTER_EN;
1165 pv &= ~PLX_SYNC_O_EN;
1166 /* Put the DSP in Reset */
1167 pv &= ~PLX_DSP_RES_N;
1168 writel(pv, plx_acc_32);
1169 spin_unlock_irqrestore(&plx_lock, plx_flags);
1170 if (debug & DEBUG_HFCMULTI_INIT)
1171 printk(KERN_WARNING "%s: slave/term: PLX_GPIO=%x\n",
1174 * If we are the 3rd PLXSD card or higher, we must turn
1175 * termination of last PLXSD card off.
1177 spin_lock_irqsave(&HFClock, hfc_flags);
1180 list_for_each_entry_safe(pos, next, &HFClist, list) {
1181 if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) {
1187 if (plx_count >= 3) {
1188 if (debug & DEBUG_HFCMULTI_PLXSD)
1189 printk(KERN_DEBUG "%s: card %d is between, so "
1190 "we disable termination\n",
1191 __func__, plx_last_hc->id + 1);
1192 spin_lock_irqsave(&plx_lock, plx_flags);
1193 plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC;
1194 pv = readl(plx_acc_32);
1196 writel(pv, plx_acc_32);
1197 spin_unlock_irqrestore(&plx_lock, plx_flags);
1198 if (debug & DEBUG_HFCMULTI_INIT)
1199 printk(KERN_WARNING "%s: term off: PLX_GPIO=%x\n",
1202 spin_unlock_irqrestore(&HFClock, hfc_flags);
1203 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1206 /* we only want the real Z2 read-pointer for revision > 0 */
1207 if (!test_bit(HFC_CHIP_REVISION0, &hc->chip))
1208 hc->hw.r_ram_sz |= V_FZ_MD;
1210 /* select pcm mode */
1211 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1212 if (debug & DEBUG_HFCMULTI_INIT)
1213 printk(KERN_DEBUG "%s: setting PCM into slave mode\n",
1216 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) {
1217 if (debug & DEBUG_HFCMULTI_INIT)
1218 printk(KERN_DEBUG "%s: setting PCM into master mode\n",
1220 hc->hw.r_pcm_md0 |= V_PCM_MD;
1222 if (debug & DEBUG_HFCMULTI_INIT)
1223 printk(KERN_DEBUG "%s: performing PCM auto detect\n",
1228 HFC_outb(hc, R_CTRL, hc->hw.r_ctrl);
1229 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1230 HFC_outb(hc, R_FIFO_MD, 0);
1231 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES | V_RLD_EPR;
1232 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1235 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1237 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1239 /* Speech Design PLX bridge pcm and sync mode */
1240 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1241 spin_lock_irqsave(&plx_lock, plx_flags);
1242 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1243 pv = readl(plx_acc_32);
1245 if (hc->hw.r_pcm_md0 & V_PCM_MD) {
1246 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1247 pv |= PLX_SYNC_O_EN;
1248 if (debug & DEBUG_HFCMULTI_INIT)
1249 printk(KERN_WARNING "%s: master: PLX_GPIO=%x\n",
1252 pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N);
1253 pv &= ~PLX_SYNC_O_EN;
1254 if (debug & DEBUG_HFCMULTI_INIT)
1255 printk(KERN_WARNING "%s: slave: PLX_GPIO=%x\n",
1258 writel(pv, plx_acc_32);
1259 spin_unlock_irqrestore(&plx_lock, plx_flags);
1263 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90);
1264 if (hc->slots == 32)
1265 HFC_outb(hc, R_PCM_MD1, 0x00);
1266 if (hc->slots == 64)
1267 HFC_outb(hc, R_PCM_MD1, 0x10);
1268 if (hc->slots == 128)
1269 HFC_outb(hc, R_PCM_MD1, 0x20);
1270 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
1271 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
1272 HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */
1274 HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */
1275 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1276 for (i = 0; i < 256; i++) {
1277 HFC_outb_nodebug(hc, R_SLOT, i);
1278 HFC_outb_nodebug(hc, A_SL_CFG, 0);
1279 HFC_outb_nodebug(hc, A_CONF, 0);
1280 hc->slot_owner[i] = -1;
1283 /* set clock speed */
1284 if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) {
1285 if (debug & DEBUG_HFCMULTI_INIT)
1287 "%s: setting double clock\n", __func__);
1288 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1292 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1293 printk(KERN_NOTICE "Setting GPIOs\n");
1294 HFC_outb(hc, R_GPIO_SEL, 0x30);
1295 HFC_outb(hc, R_GPIO_EN1, 0x3);
1297 printk(KERN_NOTICE "calling vpm_init\n");
1301 /* check if R_F0_CNT counts (8 kHz frame count) */
1302 val = HFC_inb(hc, R_F0_CNTL);
1303 val += HFC_inb(hc, R_F0_CNTH) << 8;
1304 if (debug & DEBUG_HFCMULTI_INIT)
1306 "HFC_multi F0_CNT %ld after reset\n", val);
1307 spin_unlock_irqrestore(&hc->lock, flags);
1308 set_current_state(TASK_UNINTERRUPTIBLE);
1309 schedule_timeout((HZ/100)?:1); /* Timeout minimum 10ms */
1310 spin_lock_irqsave(&hc->lock, flags);
1311 val2 = HFC_inb(hc, R_F0_CNTL);
1312 val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1313 if (debug & DEBUG_HFCMULTI_INIT)
1315 "HFC_multi F0_CNT %ld after 10 ms (1st try)\n",
1317 if (val2 >= val+8) { /* 1 ms */
1318 /* it counts, so we keep the pcm mode */
1319 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1320 printk(KERN_INFO "controller is PCM bus MASTER\n");
1322 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip))
1323 printk(KERN_INFO "controller is PCM bus SLAVE\n");
1325 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
1326 printk(KERN_INFO "controller is PCM bus SLAVE "
1327 "(auto detected)\n");
1330 /* does not count */
1331 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
1333 printk(KERN_ERR "HFC_multi ERROR, getting no 125us "
1334 "pulse. Seems that controller fails.\n");
1338 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1339 printk(KERN_INFO "controller is PCM bus SLAVE "
1340 "(ignoring missing PCM clock)\n");
1342 /* only one pcm master */
1343 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
1345 printk(KERN_ERR "HFC_multi ERROR, no clock "
1346 "on another Speech Design card found. "
1347 "Please be sure to connect PCM cable.\n");
1351 /* retry with master clock */
1352 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1353 spin_lock_irqsave(&plx_lock, plx_flags);
1354 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1355 pv = readl(plx_acc_32);
1356 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1357 pv |= PLX_SYNC_O_EN;
1358 writel(pv, plx_acc_32);
1359 spin_unlock_irqrestore(&plx_lock, plx_flags);
1360 if (debug & DEBUG_HFCMULTI_INIT)
1361 printk(KERN_WARNING "%s: master: PLX_GPIO"
1362 "=%x\n", __func__, pv);
1364 hc->hw.r_pcm_md0 |= V_PCM_MD;
1365 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1366 spin_unlock_irqrestore(&hc->lock, flags);
1367 set_current_state(TASK_UNINTERRUPTIBLE);
1368 schedule_timeout((HZ/100)?:1); /* Timeout min. 10ms */
1369 spin_lock_irqsave(&hc->lock, flags);
1370 val2 = HFC_inb(hc, R_F0_CNTL);
1371 val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1372 if (debug & DEBUG_HFCMULTI_INIT)
1373 printk(KERN_DEBUG "HFC_multi F0_CNT %ld after "
1374 "10 ms (2nd try)\n", val2);
1375 if (val2 >= val+8) { /* 1 ms */
1376 test_and_set_bit(HFC_CHIP_PCM_MASTER,
1378 printk(KERN_INFO "controller is PCM bus MASTER "
1379 "(auto detected)\n");
1381 goto controller_fail;
1385 /* Release the DSP Reset */
1386 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1387 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1389 spin_lock_irqsave(&plx_lock, plx_flags);
1390 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1391 pv = readl(plx_acc_32);
1392 pv |= PLX_DSP_RES_N;
1393 writel(pv, plx_acc_32);
1394 spin_unlock_irqrestore(&plx_lock, plx_flags);
1395 if (debug & DEBUG_HFCMULTI_INIT)
1396 printk(KERN_WARNING "%s: reset off: PLX_GPIO=%x\n",
1402 printk(KERN_INFO "controller has given PCM BUS ID %d\n",
1405 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)
1406 || test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1407 PCM_cnt++; /* SD has proprietary bridging */
1410 printk(KERN_INFO "controller has PCM BUS ID %d "
1411 "(auto selected)\n", hc->pcm);
1415 HFC_outb(hc, R_TI_WD, poll_timer);
1416 hc->hw.r_irqmsk_misc |= V_TI_IRQMSK;
1418 /* set E1 state machine IRQ */
1420 hc->hw.r_irqmsk_misc |= V_STA_IRQMSK;
1422 /* set DTMF detection */
1423 if (test_bit(HFC_CHIP_DTMF, &hc->chip)) {
1424 if (debug & DEBUG_HFCMULTI_INIT)
1425 printk(KERN_DEBUG "%s: enabling DTMF detection "
1426 "for all B-channel\n", __func__);
1427 hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP;
1428 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1429 hc->hw.r_dtmf |= V_ULAW_SEL;
1430 HFC_outb(hc, R_DTMF_N, 102 - 1);
1431 hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK;
1434 /* conference engine */
1435 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1436 r_conf_en = V_CONF_EN | V_ULAW;
1438 r_conf_en = V_CONF_EN;
1439 HFC_outb(hc, R_CONF_EN, r_conf_en);
1443 case 1: /* HFC-E1 OEM */
1444 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
1445 HFC_outb(hc, R_GPIO_SEL, 0x32);
1447 HFC_outb(hc, R_GPIO_SEL, 0x30);
1449 HFC_outb(hc, R_GPIO_EN1, 0x0f);
1450 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1452 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1455 case 2: /* HFC-4S OEM */
1457 HFC_outb(hc, R_GPIO_SEL, 0xf0);
1458 HFC_outb(hc, R_GPIO_EN1, 0xff);
1459 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1463 /* set master clock */
1464 if (hc->masterclk >= 0) {
1465 if (debug & DEBUG_HFCMULTI_INIT)
1466 printk(KERN_DEBUG "%s: setting ST master clock "
1467 "to port %d (0..%d)\n",
1468 __func__, hc->masterclk, hc->ports-1);
1469 hc->hw.r_st_sync = hc->masterclk | V_AUTO_SYNC;
1470 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1473 /* setting misc irq */
1474 HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc);
1475 if (debug & DEBUG_HFCMULTI_INIT)
1476 printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n",
1477 hc->hw.r_irqmsk_misc);
1479 /* RAM access test */
1480 HFC_outb(hc, R_RAM_ADDR0, 0);
1481 HFC_outb(hc, R_RAM_ADDR1, 0);
1482 HFC_outb(hc, R_RAM_ADDR2, 0);
1483 for (i = 0; i < 256; i++) {
1484 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1485 HFC_outb_nodebug(hc, R_RAM_DATA, ((i*3)&0xff));
1487 for (i = 0; i < 256; i++) {
1488 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1489 HFC_inb_nodebug(hc, R_RAM_DATA);
1490 rval = HFC_inb_nodebug(hc, R_INT_DATA);
1491 if (rval != ((i * 3) & 0xff)) {
1493 "addr:%x val:%x should:%x\n", i, rval,
1499 printk(KERN_DEBUG "aborting - %d RAM access errors\n", err);
1504 if (debug & DEBUG_HFCMULTI_INIT)
1505 printk(KERN_DEBUG "%s: done\n", __func__);
1507 spin_unlock_irqrestore(&hc->lock, flags);
1513 * control the watchdog
1516 hfcmulti_watchdog(struct hfc_multi *hc)
1520 if (hc->wdcount > 10) {
1522 hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ?
1523 V_GPIO_OUT3 : V_GPIO_OUT2;
1525 /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */
1526 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1527 HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte);
1537 hfcmulti_leds(struct hfc_multi *hc)
1540 unsigned long leddw;
1541 int i, state, active, leds;
1542 struct dchannel *dch;
1545 hc->ledcount += poll;
1546 if (hc->ledcount > 4096) {
1547 hc->ledcount -= 4096;
1548 hc->ledstate = 0xAFFEAFFE;
1552 case 1: /* HFC-E1 OEM */
1553 /* 2 red blinking: NT mode deactivate
1554 * 2 red steady: TE mode deactivate
1555 * left green: L1 active
1556 * left red: frame sync, but no L1
1557 * right green: L2 active
1559 if (hc->chan[hc->dslot].sync != 2) { /* no frame sync */
1560 if (hc->chan[hc->dslot].dch->dev.D.protocol
1564 } else if (hc->ledcount>>11) {
1573 } else { /* with frame sync */
1574 /* TODO make it work */
1580 leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF;
1581 /* leds are inverted */
1582 if (leds != (int)hc->ledstate) {
1583 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds);
1584 hc->ledstate = leds;
1588 case 2: /* HFC-4S OEM */
1589 /* red blinking = PH_DEACTIVATE NT Mode
1590 * red steady = PH_DEACTIVATE TE Mode
1591 * green steady = PH_ACTIVATE
1593 for (i = 0; i < 4; i++) {
1596 dch = hc->chan[(i << 2) | 2].dch;
1599 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1605 if (state == active) {
1606 led[i] = 1; /* led green */
1608 if (dch->dev.D.protocol == ISDN_P_TE_S0)
1609 /* TE mode: led red */
1612 if (hc->ledcount>>11)
1619 led[i] = 0; /* led off */
1621 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1623 for (i = 0; i < 4; i++) {
1626 leds |= (0x2 << (i * 2));
1627 } else if (led[i] == 2) {
1629 leds |= (0x1 << (i * 2));
1632 if (leds != (int)hc->ledstate) {
1633 vpm_out(hc, 0, 0x1a8 + 3, leds);
1634 hc->ledstate = leds;
1637 leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) |
1638 ((led[0] > 0) << 2) | ((led[2] > 0) << 3) |
1639 ((led[3] & 1) << 4) | ((led[1] & 1) << 5) |
1640 ((led[0] & 1) << 6) | ((led[2] & 1) << 7);
1641 if (leds != (int)hc->ledstate) {
1642 HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F);
1643 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4);
1644 hc->ledstate = leds;
1649 case 3: /* HFC 1S/2S Beronet */
1650 /* red blinking = PH_DEACTIVATE NT Mode
1651 * red steady = PH_DEACTIVATE TE Mode
1652 * green steady = PH_ACTIVATE
1654 for (i = 0; i < 2; i++) {
1657 dch = hc->chan[(i << 2) | 2].dch;
1660 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1666 if (state == active) {
1667 led[i] = 1; /* led green */
1669 if (dch->dev.D.protocol == ISDN_P_TE_S0)
1670 /* TE mode: led red */
1673 if (hc->ledcount >> 11)
1680 led[i] = 0; /* led off */
1684 leds = (led[0] > 0) | ((led[1] > 0)<<1) | ((led[0]&1)<<2)
1686 if (leds != (int)hc->ledstate) {
1687 HFC_outb_nodebug(hc, R_GPIO_EN1,
1688 ((led[0] > 0) << 2) | ((led[1] > 0) << 3));
1689 HFC_outb_nodebug(hc, R_GPIO_OUT1,
1690 ((led[0] & 1) << 2) | ((led[1] & 1) << 3));
1691 hc->ledstate = leds;
1694 case 8: /* HFC 8S+ Beronet */
1697 for (i = 0; i < 8; i++) {
1700 dch = hc->chan[(i << 2) | 2].dch;
1703 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1709 if (state == active) {
1712 if (hc->ledcount >> 11)
1719 leddw = lled << 24 | lled << 16 | lled << 8 | lled;
1720 if (leddw != hc->ledstate) {
1721 /* HFC_outb(hc, R_BRG_PCM_CFG, 1);
1722 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */
1723 /* was _io before */
1724 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
1725 outw(0x4000, hc->pci_iobase + 4);
1726 outl(leddw, hc->pci_iobase);
1727 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1728 hc->ledstate = leddw;
1734 * read dtmf coefficients
1738 hfcmulti_dtmf(struct hfc_multi *hc)
1743 struct bchannel *bch = NULL;
1748 struct sk_buff *skb;
1749 struct mISDNhead *hh;
1751 if (debug & DEBUG_HFCMULTI_DTMF)
1752 printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__);
1753 for (ch = 0; ch <= 31; ch++) {
1754 /* only process enabled B-channels */
1755 bch = hc->chan[ch].bch;
1758 if (!hc->created[hc->chan[ch].port])
1760 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1762 if (debug & DEBUG_HFCMULTI_DTMF)
1763 printk(KERN_DEBUG "%s: dtmf channel %d:",
1765 coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]);
1767 for (co = 0; co < 8; co++) {
1768 /* read W(n-1) coefficient */
1769 addr = hc->DTMFbase + ((co<<7) | (ch<<2));
1770 HFC_outb_nodebug(hc, R_RAM_ADDR0, addr);
1771 HFC_outb_nodebug(hc, R_RAM_ADDR1, addr>>8);
1772 HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr>>16)
1774 w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1775 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1776 if (debug & DEBUG_HFCMULTI_DTMF)
1777 printk(" %04x", w_float);
1779 /* decode float (see chip doc) */
1780 mantissa = w_float & 0x0fff;
1781 if (w_float & 0x8000)
1782 mantissa |= 0xfffff000;
1783 exponent = (w_float>>12) & 0x7;
1786 mantissa <<= (exponent-1);
1789 /* store coefficient */
1790 coeff[co<<1] = mantissa;
1792 /* read W(n) coefficient */
1793 w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1794 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1795 if (debug & DEBUG_HFCMULTI_DTMF)
1796 printk(" %04x", w_float);
1798 /* decode float (see chip doc) */
1799 mantissa = w_float & 0x0fff;
1800 if (w_float & 0x8000)
1801 mantissa |= 0xfffff000;
1802 exponent = (w_float>>12) & 0x7;
1805 mantissa <<= (exponent-1);
1808 /* store coefficient */
1809 coeff[(co<<1)|1] = mantissa;
1811 if (debug & DEBUG_HFCMULTI_DTMF)
1812 printk("%s: DTMF ready %08x %08x %08x %08x "
1813 "%08x %08x %08x %08x\n", __func__,
1814 coeff[0], coeff[1], coeff[2], coeff[3],
1815 coeff[4], coeff[5], coeff[6], coeff[7]);
1816 hc->chan[ch].coeff_count++;
1817 if (hc->chan[ch].coeff_count == 8) {
1818 hc->chan[ch].coeff_count = 0;
1819 skb = mI_alloc_skb(512, GFP_ATOMIC);
1821 printk(KERN_WARNING "%s: No memory for skb\n",
1825 hh = mISDN_HEAD_P(skb);
1826 hh->prim = PH_CONTROL_IND;
1827 hh->id = DTMF_HFC_COEF;
1828 memcpy(skb_put(skb, 512), hc->chan[ch].coeff, 512);
1829 recv_Bchannel_skb(bch, skb);
1833 /* restart DTMF processing */
1836 HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF);
1841 * fill fifo as much as possible
1845 hfcmulti_tx(struct hfc_multi *hc, int ch)
1847 int i, ii, temp, len = 0;
1848 int Zspace, z1, z2; /* must be int for calculation */
1851 int *txpending, slot_tx;
1852 struct bchannel *bch;
1853 struct dchannel *dch;
1854 struct sk_buff **sp = NULL;
1857 bch = hc->chan[ch].bch;
1858 dch = hc->chan[ch].dch;
1859 if ((!dch) && (!bch))
1862 txpending = &hc->chan[ch].txpending;
1863 slot_tx = hc->chan[ch].slot_tx;
1865 if (!test_bit(FLG_ACTIVE, &dch->Flags))
1868 idxp = &dch->tx_idx;
1870 if (!test_bit(FLG_ACTIVE, &bch->Flags))
1873 idxp = &bch->tx_idx;
1878 if ((!len) && *txpending != 1)
1879 return; /* no data */
1881 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
1882 (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
1883 (hc->chan[ch].slot_rx < 0) &&
1884 (hc->chan[ch].slot_tx < 0))
1885 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1));
1887 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
1888 HFC_wait_nodebug(hc);
1890 if (*txpending == 2) {
1892 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
1893 HFC_wait_nodebug(hc);
1894 HFC_outb(hc, A_SUBCH_CFG, 0);
1898 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
1899 f1 = HFC_inb_nodebug(hc, A_F1);
1900 f2 = HFC_inb_nodebug(hc, A_F2);
1901 while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) {
1902 if (debug & DEBUG_HFCMULTI_FIFO)
1904 "%s(card %d): reread f2 because %d!=%d\n",
1905 __func__, hc->id + 1, temp, f2);
1906 f2 = temp; /* repeat until F2 is equal */
1908 Fspace = f2 - f1 - 1;
1912 * Old FIFO handling doesn't give us the current Z2 read
1913 * pointer, so we cannot send the next frame before the fifo
1914 * is empty. It makes no difference except for a slightly
1915 * lower performance.
1917 if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) {
1923 /* one frame only for ST D-channels, to allow resending */
1924 if (hc->type != 1 && dch) {
1928 /* F-counter full condition */
1932 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
1933 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
1934 while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) {
1935 if (debug & DEBUG_HFCMULTI_FIFO)
1936 printk(KERN_DEBUG "%s(card %d): reread z2 because "
1937 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
1938 z2 = temp; /* repeat unti Z2 is equal */
1943 Zspace -= 4; /* keep not too full, so pointers will not overrun */
1944 /* fill transparent data only to maxinum transparent load (minus 4) */
1945 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
1946 Zspace = Zspace - hc->Zlen + hc->max_trans;
1947 if (Zspace <= 0) /* no space of 4 bytes */
1952 if (z1 == z2) { /* empty */
1953 /* if done with FIFO audio data during PCM connection */
1954 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) &&
1955 *txpending && slot_tx >= 0) {
1956 if (debug & DEBUG_HFCMULTI_MODE)
1958 "%s: reconnecting PCM due to no "
1959 "more FIFO data: channel %d "
1961 __func__, ch, slot_tx);
1963 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
1964 V_HDLC_TRP | V_IFF);
1965 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
1966 HFC_wait_nodebug(hc);
1967 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
1968 V_HDLC_TRP | V_IFF);
1969 HFC_outb_nodebug(hc, R_FIFO, ch<<1);
1970 HFC_wait_nodebug(hc);
1974 return; /* no data */
1977 /* "fill fifo if empty" feature */
1978 if (bch && test_bit(FLG_FILLEMPTY, &bch->Flags)
1979 && !test_bit(FLG_HDLC, &bch->Flags) && z2 == z1) {
1980 if (debug & DEBUG_HFCMULTI_FILL)
1981 printk(KERN_DEBUG "%s: buffer empty, so we have "
1982 "underrun\n", __func__);
1983 /* fill buffer, to prevent future underrun */
1984 hc->write_fifo(hc, hc->silence_data, poll >> 1);
1985 Zspace -= (poll >> 1);
1988 /* if audio data and connected slot */
1989 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending)
1991 if (debug & DEBUG_HFCMULTI_MODE)
1992 printk(KERN_DEBUG "%s: disconnecting PCM due to "
1993 "FIFO data: channel %d slot_tx %d\n",
1994 __func__, ch, slot_tx);
1995 /* disconnect slot */
1996 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF);
1997 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
1998 HFC_wait_nodebug(hc);
1999 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF);
2000 HFC_outb_nodebug(hc, R_FIFO, ch<<1);
2001 HFC_wait_nodebug(hc);
2006 hc->activity[hc->chan[ch].port] = 1;
2008 /* fill fifo to what we have left */
2010 if (dch || test_bit(FLG_HDLC, &bch->Flags))
2015 d = (*sp)->data + i;
2016 if (ii - i > Zspace)
2018 if (debug & DEBUG_HFCMULTI_FIFO)
2019 printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space "
2020 "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n",
2021 __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i,
2022 temp ? "HDLC":"TRANS");
2024 /* Have to prep the audio data */
2025 hc->write_fifo(hc, d, ii - i);
2028 /* if not all data has been written */
2030 /* NOTE: fifo is started by the calling function */
2034 /* if all data has been written, terminate frame */
2035 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2036 /* increment f-counter */
2037 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2038 HFC_wait_nodebug(hc);
2041 /* send confirm, since get_net_bframe will not do it with trans */
2042 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2045 /* check for next frame */
2047 if (bch && get_next_bframe(bch)) { /* hdlc is confirmed here */
2051 if (dch && get_next_dframe(dch)) {
2057 * now we have no more data, so in case of transparent,
2058 * we set the last byte in fifo to 'silence' in case we will get
2059 * no more data at all. this prevents sending an undefined value.
2061 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2062 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
2066 /* NOTE: only called if E1 card is in active state */
2068 hfcmulti_rx(struct hfc_multi *hc, int ch)
2071 int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */
2072 int f1 = 0, f2 = 0; /* = 0, to make GCC happy */
2074 struct bchannel *bch;
2075 struct dchannel *dch;
2076 struct sk_buff *skb, **sp = NULL;
2079 bch = hc->chan[ch].bch;
2080 dch = hc->chan[ch].dch;
2081 if ((!dch) && (!bch))
2084 if (!test_bit(FLG_ACTIVE, &dch->Flags))
2087 maxlen = dch->maxlen;
2089 if (!test_bit(FLG_ACTIVE, &bch->Flags))
2092 maxlen = bch->maxlen;
2095 /* on first AND before getting next valid frame, R_FIFO must be written
2097 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2098 (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
2099 (hc->chan[ch].slot_rx < 0) &&
2100 (hc->chan[ch].slot_tx < 0))
2101 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch<<1) | 1);
2103 HFC_outb_nodebug(hc, R_FIFO, (ch<<1)|1);
2104 HFC_wait_nodebug(hc);
2106 /* ignore if rx is off BUT change fifo (above) to start pending TX */
2107 if (hc->chan[ch].rx_off)
2110 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2111 f1 = HFC_inb_nodebug(hc, A_F1);
2112 while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) {
2113 if (debug & DEBUG_HFCMULTI_FIFO)
2115 "%s(card %d): reread f1 because %d!=%d\n",
2116 __func__, hc->id + 1, temp, f1);
2117 f1 = temp; /* repeat until F1 is equal */
2119 f2 = HFC_inb_nodebug(hc, A_F2);
2121 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2122 while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) {
2123 if (debug & DEBUG_HFCMULTI_FIFO)
2124 printk(KERN_DEBUG "%s(card %d): reread z2 because "
2125 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2126 z1 = temp; /* repeat until Z1 is equal */
2128 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2130 if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2)
2131 /* complete hdlc frame */
2135 /* if buffer is empty */
2140 *sp = mI_alloc_skb(maxlen + 3, GFP_ATOMIC);
2142 printk(KERN_DEBUG "%s: No mem for rx_skb\n",
2148 hc->activity[hc->chan[ch].port] = 1;
2150 /* empty fifo with what we have */
2151 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2152 if (debug & DEBUG_HFCMULTI_FIFO)
2153 printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d "
2154 "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) "
2155 "got=%d (again %d)\n", __func__, hc->id + 1, ch,
2156 Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE",
2157 f1, f2, Zsize + (*sp)->len, again);
2159 if ((Zsize + (*sp)->len) > (maxlen + 3)) {
2160 if (debug & DEBUG_HFCMULTI_FIFO)
2162 "%s(card %d): hdlc-frame too large.\n",
2163 __func__, hc->id + 1);
2165 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
2166 HFC_wait_nodebug(hc);
2170 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2173 /* increment Z2,F2-counter */
2174 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2175 HFC_wait_nodebug(hc);
2177 if ((*sp)->len < 4) {
2178 if (debug & DEBUG_HFCMULTI_FIFO)
2180 "%s(card %d): Frame below minimum "
2181 "size\n", __func__, hc->id + 1);
2185 /* there is at least one complete frame, check crc */
2186 if ((*sp)->data[(*sp)->len - 1]) {
2187 if (debug & DEBUG_HFCMULTI_CRC)
2189 "%s: CRC-error\n", __func__);
2193 skb_trim(*sp, (*sp)->len - 3);
2194 if ((*sp)->len < MISDN_COPY_SIZE) {
2196 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2198 memcpy(skb_put(*sp, skb->len),
2199 skb->data, skb->len);
2202 printk(KERN_DEBUG "%s: No mem\n",
2210 if (debug & DEBUG_HFCMULTI_FIFO) {
2211 printk(KERN_DEBUG "%s(card %d):",
2212 __func__, hc->id + 1);
2214 while (temp < (*sp)->len)
2215 printk(" %02x", (*sp)->data[temp++]);
2226 /* there is an incomplete frame */
2229 if (Zsize > skb_tailroom(*sp))
2230 Zsize = skb_tailroom(*sp);
2231 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2232 if (((*sp)->len) < MISDN_COPY_SIZE) {
2234 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2236 memcpy(skb_put(*sp, skb->len),
2237 skb->data, skb->len);
2240 printk(KERN_DEBUG "%s: No mem\n", __func__);
2247 if (debug & DEBUG_HFCMULTI_FIFO)
2249 "%s(card %d): fifo(%d) reading %d bytes "
2250 "(z1=%04x, z2=%04x) TRANS\n",
2251 __func__, hc->id + 1, ch, Zsize, z1, z2);
2252 /* only bch is transparent */
2263 signal_state_up(struct dchannel *dch, int info, char *msg)
2265 struct sk_buff *skb;
2266 int id, data = info;
2268 if (debug & DEBUG_HFCMULTI_STATE)
2269 printk(KERN_DEBUG "%s: %s\n", __func__, msg);
2271 id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */
2273 skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data,
2277 recv_Dchannel_skb(dch, skb);
2281 handle_timer_irq(struct hfc_multi *hc)
2284 struct dchannel *dch;
2287 /* process queued resync jobs */
2288 if (hc->e1_resync) {
2289 /* lock, so e1_resync gets not changed */
2290 spin_lock_irqsave(&HFClock, flags);
2291 if (hc->e1_resync & 1) {
2292 if (debug & DEBUG_HFCMULTI_PLXSD)
2293 printk(KERN_DEBUG "Enable SYNC_I\n");
2294 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC);
2295 /* disable JATT, if RX_SYNC is set */
2296 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
2297 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
2299 if (hc->e1_resync & 2) {
2300 if (debug & DEBUG_HFCMULTI_PLXSD)
2301 printk(KERN_DEBUG "Enable jatt PLL\n");
2302 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
2304 if (hc->e1_resync & 4) {
2305 if (debug & DEBUG_HFCMULTI_PLXSD)
2307 "Enable QUARTZ for HFC-E1\n");
2308 /* set jatt to quartz */
2309 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC
2311 /* switch to JATT, in case it is not already */
2312 HFC_outb(hc, R_SYNC_OUT, 0);
2315 spin_unlock_irqrestore(&HFClock, flags);
2318 if (hc->type != 1 || hc->e1_state == 1)
2319 for (ch = 0; ch <= 31; ch++) {
2320 if (hc->created[hc->chan[ch].port]) {
2321 hfcmulti_tx(hc, ch);
2322 /* fifo is started when switching to rx-fifo */
2323 hfcmulti_rx(hc, ch);
2324 if (hc->chan[ch].dch &&
2325 hc->chan[ch].nt_timer > -1) {
2326 dch = hc->chan[ch].dch;
2327 if (!(--hc->chan[ch].nt_timer)) {
2331 DEBUG_HFCMULTI_STATE)
2341 if (hc->type == 1 && hc->created[0]) {
2342 dch = hc->chan[hc->dslot].dch;
2343 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
2345 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS;
2346 if (!temp && hc->chan[hc->dslot].los)
2347 signal_state_up(dch, L1_SIGNAL_LOS_ON,
2349 if (temp && !hc->chan[hc->dslot].los)
2350 signal_state_up(dch, L1_SIGNAL_LOS_OFF,
2352 hc->chan[hc->dslot].los = temp;
2354 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dslot].cfg)) {
2356 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS;
2357 if (!temp && hc->chan[hc->dslot].ais)
2358 signal_state_up(dch, L1_SIGNAL_AIS_ON,
2360 if (temp && !hc->chan[hc->dslot].ais)
2361 signal_state_up(dch, L1_SIGNAL_AIS_OFF,
2363 hc->chan[hc->dslot].ais = temp;
2365 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dslot].cfg)) {
2367 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX;
2368 if (!temp && hc->chan[hc->dslot].slip_rx)
2369 signal_state_up(dch, L1_SIGNAL_SLIP_RX,
2370 " bit SLIP detected RX");
2371 hc->chan[hc->dslot].slip_rx = temp;
2372 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX;
2373 if (!temp && hc->chan[hc->dslot].slip_tx)
2374 signal_state_up(dch, L1_SIGNAL_SLIP_TX,
2375 " bit SLIP detected TX");
2376 hc->chan[hc->dslot].slip_tx = temp;
2378 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dslot].cfg)) {
2380 temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A;
2381 if (!temp && hc->chan[hc->dslot].rdi)
2382 signal_state_up(dch, L1_SIGNAL_RDI_ON,
2384 if (temp && !hc->chan[hc->dslot].rdi)
2385 signal_state_up(dch, L1_SIGNAL_RDI_OFF,
2387 hc->chan[hc->dslot].rdi = temp;
2389 temp = HFC_inb_nodebug(hc, R_JATT_DIR);
2390 switch (hc->chan[hc->dslot].sync) {
2392 if ((temp & 0x60) == 0x60) {
2393 if (debug & DEBUG_HFCMULTI_SYNC)
2395 "%s: (id=%d) E1 now "
2398 HFC_outb(hc, R_RX_OFF,
2399 hc->chan[hc->dslot].jitter | V_RX_INIT);
2400 HFC_outb(hc, R_TX_OFF,
2401 hc->chan[hc->dslot].jitter | V_RX_INIT);
2402 hc->chan[hc->dslot].sync = 1;
2403 goto check_framesync;
2407 if ((temp & 0x60) != 0x60) {
2408 if (debug & DEBUG_HFCMULTI_SYNC)
2411 "lost clock sync\n",
2413 hc->chan[hc->dslot].sync = 0;
2417 temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2419 if (debug & DEBUG_HFCMULTI_SYNC)
2422 "now in frame sync\n",
2424 hc->chan[hc->dslot].sync = 2;
2428 if ((temp & 0x60) != 0x60) {
2429 if (debug & DEBUG_HFCMULTI_SYNC)
2431 "%s: (id=%d) E1 lost "
2432 "clock & frame sync\n",
2434 hc->chan[hc->dslot].sync = 0;
2437 temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2439 if (debug & DEBUG_HFCMULTI_SYNC)
2442 "lost frame sync\n",
2444 hc->chan[hc->dslot].sync = 1;
2450 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
2451 hfcmulti_watchdog(hc);
2458 ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech)
2460 struct dchannel *dch;
2463 u_char st_status, temp;
2466 for (ch = 0; ch <= 31; ch++) {
2467 if (hc->chan[ch].dch) {
2468 dch = hc->chan[ch].dch;
2469 if (r_irq_statech & 1) {
2470 HFC_outb_nodebug(hc, R_ST_SEL,
2472 /* undocumented: delay after R_ST_SEL */
2474 /* undocumented: status changes during read */
2475 st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE);
2476 while (st_status != (temp =
2477 HFC_inb_nodebug(hc, A_ST_RD_STATE))) {
2478 if (debug & DEBUG_HFCMULTI_STATE)
2479 printk(KERN_DEBUG "%s: reread "
2480 "STATE because %d!=%d\n",
2483 st_status = temp; /* repeat */
2486 /* Speech Design TE-sync indication */
2487 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) &&
2488 dch->dev.D.protocol == ISDN_P_TE_S0) {
2489 if (st_status & V_FR_SYNC_ST)
2491 (1 << hc->chan[ch].port);
2494 ~(1 << hc->chan[ch].port);
2496 dch->state = st_status & 0x0f;
2497 if (dch->dev.D.protocol == ISDN_P_NT_S0)
2501 if (dch->state == active) {
2502 HFC_outb_nodebug(hc, R_FIFO,
2504 HFC_wait_nodebug(hc);
2505 HFC_outb_nodebug(hc,
2506 R_INC_RES_FIFO, V_RES_F);
2507 HFC_wait_nodebug(hc);
2510 schedule_event(dch, FLG_PHCHANGE);
2511 if (debug & DEBUG_HFCMULTI_STATE)
2513 "%s: S/T newstate %x port %d\n",
2514 __func__, dch->state,
2517 r_irq_statech >>= 1;
2520 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2521 plxsd_checksync(hc, 0);
2525 fifo_irq(struct hfc_multi *hc, int block)
2528 struct dchannel *dch;
2529 struct bchannel *bch;
2530 u_char r_irq_fifo_bl;
2532 r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block);
2535 ch = (block << 2) + (j >> 1);
2536 dch = hc->chan[ch].dch;
2537 bch = hc->chan[ch].bch;
2538 if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) {
2542 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2543 test_bit(FLG_ACTIVE, &dch->Flags)) {
2544 hfcmulti_tx(hc, ch);
2546 HFC_outb_nodebug(hc, R_FIFO, 0);
2547 HFC_wait_nodebug(hc);
2549 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2550 test_bit(FLG_ACTIVE, &bch->Flags)) {
2551 hfcmulti_tx(hc, ch);
2553 HFC_outb_nodebug(hc, R_FIFO, 0);
2554 HFC_wait_nodebug(hc);
2557 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2558 test_bit(FLG_ACTIVE, &dch->Flags)) {
2559 hfcmulti_rx(hc, ch);
2561 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2562 test_bit(FLG_ACTIVE, &bch->Flags)) {
2563 hfcmulti_rx(hc, ch);
2573 hfcmulti_interrupt(int intno, void *dev_id)
2575 #ifdef IRQCOUNT_DEBUG
2576 static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0,
2577 iq5 = 0, iq6 = 0, iqcnt = 0;
2579 struct hfc_multi *hc = dev_id;
2580 struct dchannel *dch;
2581 u_char r_irq_statech, status, r_irq_misc, r_irq_oview;
2583 void __iomem *plx_acc;
2585 u_char e1_syncsta, temp;
2589 printk(KERN_ERR "HFC-multi: Spurious interrupt!\n");
2593 spin_lock(&hc->lock);
2597 printk(KERN_ERR "irq for card %d during irq from "
2598 "card %d, this is no bug.\n", hc->id + 1, irqsem);
2599 irqsem = hc->id + 1;
2602 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
2603 spin_lock_irqsave(&plx_lock, flags);
2604 plx_acc = hc->plx_membase + PLX_INTCSR;
2605 wval = readw(plx_acc);
2606 spin_unlock_irqrestore(&plx_lock, flags);
2607 if (!(wval & PLX_INTCSR_LINTI1_STATUS))
2611 status = HFC_inb_nodebug(hc, R_STATUS);
2612 r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH);
2613 #ifdef IRQCOUNT_DEBUG
2616 if (status & V_DTMF_STA)
2618 if (status & V_LOST_STA)
2620 if (status & V_EXT_IRQSTA)
2622 if (status & V_MISC_IRQSTA)
2624 if (status & V_FR_IRQSTA)
2626 if (iqcnt++ > 5000) {
2627 printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n",
2628 iq1, iq2, iq3, iq4, iq5, iq6);
2632 if (!r_irq_statech &&
2633 !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA |
2634 V_MISC_IRQSTA | V_FR_IRQSTA))) {
2635 /* irq is not for us */
2639 if (r_irq_statech) {
2641 ph_state_irq(hc, r_irq_statech);
2643 if (status & V_EXT_IRQSTA)
2644 ; /* external IRQ */
2645 if (status & V_LOST_STA) {
2647 HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */
2649 if (status & V_MISC_IRQSTA) {
2651 r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC);
2652 if (r_irq_misc & V_STA_IRQ) {
2653 if (hc->type == 1) {
2655 dch = hc->chan[hc->dslot].dch;
2656 e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA);
2657 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
2658 && hc->e1_getclock) {
2659 if (e1_syncsta & V_FR_SYNC_E1)
2660 hc->syncronized = 1;
2662 hc->syncronized = 0;
2664 /* undocumented: status changes during read */
2665 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA);
2666 while (dch->state != (temp =
2667 HFC_inb_nodebug(hc, R_E1_RD_STA))) {
2668 if (debug & DEBUG_HFCMULTI_STATE)
2669 printk(KERN_DEBUG "%s: reread "
2670 "STATE because %d!=%d\n",
2673 dch->state = temp; /* repeat */
2675 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA)
2677 schedule_event(dch, FLG_PHCHANGE);
2678 if (debug & DEBUG_HFCMULTI_STATE)
2680 "%s: E1 (id=%d) newstate %x\n",
2681 __func__, hc->id, dch->state);
2682 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2683 plxsd_checksync(hc, 0);
2686 if (r_irq_misc & V_TI_IRQ)
2687 handle_timer_irq(hc);
2689 if (r_irq_misc & V_DTMF_IRQ) {
2693 if (r_irq_misc & V_IRQ_PROC) {
2694 static int irq_proc_cnt;
2695 if (!irq_proc_cnt++)
2696 printk(KERN_WARNING "%s: got V_IRQ_PROC -"
2697 " this should not happen\n", __func__);
2701 if (status & V_FR_IRQSTA) {
2703 r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW);
2704 for (i = 0; i < 8; i++) {
2705 if (r_irq_oview & (1 << i))
2713 spin_unlock(&hc->lock);
2720 spin_unlock(&hc->lock);
2726 * timer callback for D-chan busy resolution. Currently no function
2730 hfcmulti_dbusy_timer(struct hfc_multi *hc)
2736 * activate/deactivate hardware for selected channels and mode
2738 * configure B-channel with the given protocol
2739 * ch eqals to the HFC-channel (0-31)
2740 * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31
2741 * for S/T, 1-31 for E1)
2742 * the hdlc interrupts will be set/unset
2745 mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
2746 int bank_tx, int slot_rx, int bank_rx)
2748 int flow_tx = 0, flow_rx = 0, routing = 0;
2749 int oslot_tx, oslot_rx;
2752 if (ch < 0 || ch > 31)
2754 oslot_tx = hc->chan[ch].slot_tx;
2755 oslot_rx = hc->chan[ch].slot_rx;
2756 conf = hc->chan[ch].conf;
2758 if (debug & DEBUG_HFCMULTI_MODE)
2760 "%s: card %d channel %d protocol %x slot old=%d new=%d "
2761 "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n",
2762 __func__, hc->id, ch, protocol, oslot_tx, slot_tx,
2763 bank_tx, oslot_rx, slot_rx, bank_rx);
2765 if (oslot_tx >= 0 && slot_tx != oslot_tx) {
2766 /* remove from slot */
2767 if (debug & DEBUG_HFCMULTI_MODE)
2768 printk(KERN_DEBUG "%s: remove from slot %d (TX)\n",
2769 __func__, oslot_tx);
2770 if (hc->slot_owner[oslot_tx<<1] == ch) {
2771 HFC_outb(hc, R_SLOT, oslot_tx << 1);
2772 HFC_outb(hc, A_SL_CFG, 0);
2773 HFC_outb(hc, A_CONF, 0);
2774 hc->slot_owner[oslot_tx<<1] = -1;
2776 if (debug & DEBUG_HFCMULTI_MODE)
2778 "%s: we are not owner of this tx slot "
2779 "anymore, channel %d is.\n",
2780 __func__, hc->slot_owner[oslot_tx<<1]);
2784 if (oslot_rx >= 0 && slot_rx != oslot_rx) {
2785 /* remove from slot */
2786 if (debug & DEBUG_HFCMULTI_MODE)
2788 "%s: remove from slot %d (RX)\n",
2789 __func__, oslot_rx);
2790 if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) {
2791 HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR);
2792 HFC_outb(hc, A_SL_CFG, 0);
2793 hc->slot_owner[(oslot_rx << 1) | 1] = -1;
2795 if (debug & DEBUG_HFCMULTI_MODE)
2797 "%s: we are not owner of this rx slot "
2798 "anymore, channel %d is.\n",
2800 hc->slot_owner[(oslot_rx << 1) | 1]);
2805 flow_tx = 0x80; /* FIFO->ST */
2806 /* disable pcm slot */
2807 hc->chan[ch].slot_tx = -1;
2808 hc->chan[ch].bank_tx = 0;
2811 if (hc->chan[ch].txpending)
2812 flow_tx = 0x80; /* FIFO->ST */
2814 flow_tx = 0xc0; /* PCM->ST */
2816 routing = bank_tx ? 0xc0 : 0x80;
2817 if (conf >= 0 || bank_tx > 1)
2818 routing = 0x40; /* loop */
2819 if (debug & DEBUG_HFCMULTI_MODE)
2820 printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2821 " %d flow %02x routing %02x conf %d (TX)\n",
2822 __func__, ch, slot_tx, bank_tx,
2823 flow_tx, routing, conf);
2824 HFC_outb(hc, R_SLOT, slot_tx << 1);
2825 HFC_outb(hc, A_SL_CFG, (ch<<1) | routing);
2826 HFC_outb(hc, A_CONF, (conf < 0) ? 0 : (conf | V_CONF_SL));
2827 hc->slot_owner[slot_tx << 1] = ch;
2828 hc->chan[ch].slot_tx = slot_tx;
2829 hc->chan[ch].bank_tx = bank_tx;
2832 /* disable pcm slot */
2833 flow_rx = 0x80; /* ST->FIFO */
2834 hc->chan[ch].slot_rx = -1;
2835 hc->chan[ch].bank_rx = 0;
2838 if (hc->chan[ch].txpending)
2839 flow_rx = 0x80; /* ST->FIFO */
2841 flow_rx = 0xc0; /* ST->(FIFO,PCM) */
2843 routing = bank_rx?0x80:0xc0; /* reversed */
2844 if (conf >= 0 || bank_rx > 1)
2845 routing = 0x40; /* loop */
2846 if (debug & DEBUG_HFCMULTI_MODE)
2847 printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2848 " %d flow %02x routing %02x conf %d (RX)\n",
2849 __func__, ch, slot_rx, bank_rx,
2850 flow_rx, routing, conf);
2851 HFC_outb(hc, R_SLOT, (slot_rx<<1) | V_SL_DIR);
2852 HFC_outb(hc, A_SL_CFG, (ch<<1) | V_CH_DIR | routing);
2853 hc->slot_owner[(slot_rx<<1)|1] = ch;
2854 hc->chan[ch].slot_rx = slot_rx;
2855 hc->chan[ch].bank_rx = bank_rx;
2860 /* disable TX fifo */
2861 HFC_outb(hc, R_FIFO, ch << 1);
2863 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF);
2864 HFC_outb(hc, A_SUBCH_CFG, 0);
2865 HFC_outb(hc, A_IRQ_MSK, 0);
2866 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2868 /* disable RX fifo */
2869 HFC_outb(hc, R_FIFO, (ch<<1)|1);
2871 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00);
2872 HFC_outb(hc, A_SUBCH_CFG, 0);
2873 HFC_outb(hc, A_IRQ_MSK, 0);
2874 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2876 if (hc->chan[ch].bch && hc->type != 1) {
2877 hc->hw.a_st_ctrl0[hc->chan[ch].port] &=
2878 ((ch & 0x3) == 0)? ~V_B1_EN: ~V_B2_EN;
2879 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2880 /* undocumented: delay after R_ST_SEL */
2882 HFC_outb(hc, A_ST_CTRL0,
2883 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2885 if (hc->chan[ch].bch) {
2886 test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
2887 test_and_clear_bit(FLG_TRANSPARENT,
2888 &hc->chan[ch].bch->Flags);
2891 case (ISDN_P_B_RAW): /* B-channel */
2893 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2894 (hc->chan[ch].slot_rx < 0) &&
2895 (hc->chan[ch].slot_tx < 0)) {
2898 "Setting B-channel %d to echo cancelable "
2899 "state on PCM slot %d\n", ch,
2900 ((ch / 4) * 8) + ((ch % 4) * 4) + 1);
2902 "Enabling pass through for channel\n");
2903 vpm_out(hc, ch, ((ch / 4) * 8) +
2904 ((ch % 4) * 4) + 1, 0x01);
2907 HFC_outb(hc, R_FIFO, (ch << 1));
2909 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
2910 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
2911 ((ch % 4) * 4) + 1) << 1);
2912 HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1));
2915 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1);
2917 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
2918 HFC_outb(hc, A_SUBCH_CFG, 0);
2919 HFC_outb(hc, A_IRQ_MSK, 0);
2920 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2922 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
2923 ((ch % 4) * 4) + 1) << 1) | 1);
2924 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1);
2928 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
2930 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
2931 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
2932 ((ch % 4) * 4)) << 1) | 1);
2933 HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1);
2936 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1));
2938 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
2939 HFC_outb(hc, A_SUBCH_CFG, 0);
2940 HFC_outb(hc, A_IRQ_MSK, 0);
2941 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2944 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
2945 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
2946 ((ch % 4) * 4)) << 1);
2947 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1));
2949 /* enable TX fifo */
2950 HFC_outb(hc, R_FIFO, ch << 1);
2952 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 |
2953 V_HDLC_TRP | V_IFF);
2954 HFC_outb(hc, A_SUBCH_CFG, 0);
2955 HFC_outb(hc, A_IRQ_MSK, 0);
2956 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2959 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
2960 /* enable RX fifo */
2961 HFC_outb(hc, R_FIFO, (ch<<1)|1);
2963 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 | V_HDLC_TRP);
2964 HFC_outb(hc, A_SUBCH_CFG, 0);
2965 HFC_outb(hc, A_IRQ_MSK, 0);
2966 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2969 if (hc->type != 1) {
2970 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
2971 ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
2972 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2973 /* undocumented: delay after R_ST_SEL */
2975 HFC_outb(hc, A_ST_CTRL0,
2976 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2978 if (hc->chan[ch].bch)
2979 test_and_set_bit(FLG_TRANSPARENT,
2980 &hc->chan[ch].bch->Flags);
2982 case (ISDN_P_B_HDLC): /* B-channel */
2983 case (ISDN_P_TE_S0): /* D-channel */
2984 case (ISDN_P_NT_S0):
2985 case (ISDN_P_TE_E1):
2986 case (ISDN_P_NT_E1):
2987 /* enable TX fifo */
2988 HFC_outb(hc, R_FIFO, ch<<1);
2990 if (hc->type == 1 || hc->chan[ch].bch) {
2991 /* E1 or B-channel */
2992 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04);
2993 HFC_outb(hc, A_SUBCH_CFG, 0);
2995 /* D-Channel without HDLC fill flags */
2996 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF);
2997 HFC_outb(hc, A_SUBCH_CFG, 2);
2999 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3000 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3002 /* enable RX fifo */
3003 HFC_outb(hc, R_FIFO, (ch<<1)|1);
3005 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04);
3006 if (hc->type == 1 || hc->chan[ch].bch)
3007 HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */
3009 HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */
3010 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3011 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3013 if (hc->chan[ch].bch) {
3014 test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3015 if (hc->type != 1) {
3016 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3017 ((ch&0x3) == 0) ? V_B1_EN : V_B2_EN;
3018 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3019 /* undocumented: delay after R_ST_SEL */
3021 HFC_outb(hc, A_ST_CTRL0,
3022 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3027 printk(KERN_DEBUG "%s: protocol not known %x\n",
3028 __func__, protocol);
3029 hc->chan[ch].protocol = ISDN_P_NONE;
3030 return -ENOPROTOOPT;
3032 hc->chan[ch].protocol = protocol;
3038 * connect/disconnect PCM
3042 hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx,
3043 int slot_rx, int bank_rx)
3045 if (slot_rx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) {
3047 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0);
3052 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx,
3057 * set/disable conference
3061 hfcmulti_conf(struct hfc_multi *hc, int ch, int num)
3063 if (num >= 0 && num <= 7)
3064 hc->chan[ch].conf = num;
3066 hc->chan[ch].conf = -1;
3067 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx,
3068 hc->chan[ch].bank_tx, hc->chan[ch].slot_rx,
3069 hc->chan[ch].bank_rx);
3074 * set/disable sample loop
3077 /* NOTE: this function is experimental and therefore disabled */
3080 * Layer 1 callback function
3083 hfcm_l1callback(struct dchannel *dch, u_int cmd)
3085 struct hfc_multi *hc = dch->hw;
3093 /* start activation */
3094 spin_lock_irqsave(&hc->lock, flags);
3095 if (hc->type == 1) {
3096 if (debug & DEBUG_HFCMULTI_MSG)
3098 "%s: HW_RESET_REQ no BRI\n",
3101 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3102 /* undocumented: delay after R_ST_SEL */
3104 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */
3105 udelay(6); /* wait at least 5,21us */
3106 HFC_outb(hc, A_ST_WR_STATE, 3);
3107 HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT*3));
3110 spin_unlock_irqrestore(&hc->lock, flags);
3111 l1_event(dch->l1, HW_POWERUP_IND);
3114 /* start deactivation */
3115 spin_lock_irqsave(&hc->lock, flags);
3116 if (hc->type == 1) {
3117 if (debug & DEBUG_HFCMULTI_MSG)
3119 "%s: HW_DEACT_REQ no BRI\n",
3122 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3123 /* undocumented: delay after R_ST_SEL */
3125 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT*2);
3127 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3129 ~(1 << hc->chan[dch->slot].port);
3130 plxsd_checksync(hc, 0);
3133 skb_queue_purge(&dch->squeue);
3135 dev_kfree_skb(dch->tx_skb);
3140 dev_kfree_skb(dch->rx_skb);
3143 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3144 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3145 del_timer(&dch->timer);
3146 spin_unlock_irqrestore(&hc->lock, flags);
3148 case HW_POWERUP_REQ:
3149 spin_lock_irqsave(&hc->lock, flags);
3150 if (hc->type == 1) {
3151 if (debug & DEBUG_HFCMULTI_MSG)
3153 "%s: HW_POWERUP_REQ no BRI\n",
3156 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3157 /* undocumented: delay after R_ST_SEL */
3159 HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */
3160 udelay(6); /* wait at least 5,21us */
3161 HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */
3163 spin_unlock_irqrestore(&hc->lock, flags);
3165 case PH_ACTIVATE_IND:
3166 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3167 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3170 case PH_DEACTIVATE_IND:
3171 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3172 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3176 if (dch->debug & DEBUG_HW)
3177 printk(KERN_DEBUG "%s: unknown command %x\n",
3185 * Layer2 -> Layer 1 Transfer
3189 handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3191 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
3192 struct dchannel *dch = container_of(dev, struct dchannel, dev);
3193 struct hfc_multi *hc = dch->hw;
3194 struct mISDNhead *hh = mISDN_HEAD_P(skb);
3203 spin_lock_irqsave(&hc->lock, flags);
3204 ret = dchannel_senddata(dch, skb);
3205 if (ret > 0) { /* direct TX */
3206 id = hh->id; /* skb can be freed */
3207 hfcmulti_tx(hc, dch->slot);
3210 HFC_outb(hc, R_FIFO, 0);
3212 spin_unlock_irqrestore(&hc->lock, flags);
3213 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3215 spin_unlock_irqrestore(&hc->lock, flags);
3217 case PH_ACTIVATE_REQ:
3218 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3219 spin_lock_irqsave(&hc->lock, flags);
3221 if (debug & DEBUG_HFCMULTI_MSG)
3223 "%s: PH_ACTIVATE port %d (0..%d)\n",
3224 __func__, hc->chan[dch->slot].port,
3226 /* start activation */
3227 if (hc->type == 1) {
3228 ph_state_change(dch);
3229 if (debug & DEBUG_HFCMULTI_STATE)
3231 "%s: E1 report state %x \n",
3232 __func__, dch->state);
3234 HFC_outb(hc, R_ST_SEL,
3235 hc->chan[dch->slot].port);
3236 /* undocumented: delay after R_ST_SEL */
3238 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1);
3240 udelay(6); /* wait at least 5,21us */
3241 HFC_outb(hc, A_ST_WR_STATE, 1);
3242 HFC_outb(hc, A_ST_WR_STATE, 1 |
3243 (V_ST_ACT*3)); /* activate */
3246 spin_unlock_irqrestore(&hc->lock, flags);
3248 ret = l1_event(dch->l1, hh->prim);
3250 case PH_DEACTIVATE_REQ:
3251 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
3252 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3253 spin_lock_irqsave(&hc->lock, flags);
3254 if (debug & DEBUG_HFCMULTI_MSG)
3256 "%s: PH_DEACTIVATE port %d (0..%d)\n",
3257 __func__, hc->chan[dch->slot].port,
3259 /* start deactivation */
3260 if (hc->type == 1) {
3261 if (debug & DEBUG_HFCMULTI_MSG)
3263 "%s: PH_DEACTIVATE no BRI\n",
3266 HFC_outb(hc, R_ST_SEL,
3267 hc->chan[dch->slot].port);
3268 /* undocumented: delay after R_ST_SEL */
3270 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3274 skb_queue_purge(&dch->squeue);
3276 dev_kfree_skb(dch->tx_skb);
3281 dev_kfree_skb(dch->rx_skb);
3284 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3285 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3286 del_timer(&dch->timer);
3288 if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
3289 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
3292 spin_unlock_irqrestore(&hc->lock, flags);
3294 ret = l1_event(dch->l1, hh->prim);
3303 deactivate_bchannel(struct bchannel *bch)
3305 struct hfc_multi *hc = bch->hw;
3308 spin_lock_irqsave(&hc->lock, flags);
3309 if (test_and_clear_bit(FLG_TX_NEXT, &bch->Flags)) {
3310 dev_kfree_skb(bch->next_skb);
3311 bch->next_skb = NULL;
3314 dev_kfree_skb(bch->tx_skb);
3319 dev_kfree_skb(bch->rx_skb);
3322 hc->chan[bch->slot].coeff_count = 0;
3323 test_and_clear_bit(FLG_ACTIVE, &bch->Flags);
3324 test_and_clear_bit(FLG_TX_BUSY, &bch->Flags);
3325 hc->chan[bch->slot].rx_off = 0;
3326 hc->chan[bch->slot].conf = -1;
3327 mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0);
3328 spin_unlock_irqrestore(&hc->lock, flags);
3332 handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3334 struct bchannel *bch = container_of(ch, struct bchannel, ch);
3335 struct hfc_multi *hc = bch->hw;
3337 struct mISDNhead *hh = mISDN_HEAD_P(skb);
3345 spin_lock_irqsave(&hc->lock, flags);
3346 ret = bchannel_senddata(bch, skb);
3347 if (ret > 0) { /* direct TX */
3348 id = hh->id; /* skb can be freed */
3349 hfcmulti_tx(hc, bch->slot);
3352 HFC_outb_nodebug(hc, R_FIFO, 0);
3353 HFC_wait_nodebug(hc);
3354 if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) {
3355 spin_unlock_irqrestore(&hc->lock, flags);
3356 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3358 spin_unlock_irqrestore(&hc->lock, flags);
3360 spin_unlock_irqrestore(&hc->lock, flags);
3362 case PH_ACTIVATE_REQ:
3363 if (debug & DEBUG_HFCMULTI_MSG)
3364 printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n",
3365 __func__, bch->slot);
3366 spin_lock_irqsave(&hc->lock, flags);
3367 /* activate B-channel if not already activated */
3368 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) {
3369 hc->chan[bch->slot].txpending = 0;
3370 ret = mode_hfcmulti(hc, bch->slot,
3372 hc->chan[bch->slot].slot_tx,
3373 hc->chan[bch->slot].bank_tx,
3374 hc->chan[bch->slot].slot_rx,
3375 hc->chan[bch->slot].bank_rx);
3377 if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf
3378 && test_bit(HFC_CHIP_DTMF, &hc->chip)) {
3381 if (debug & DEBUG_HFCMULTI_DTMF)
3383 "%s: start dtmf decoder\n",
3385 HFC_outb(hc, R_DTMF, hc->hw.r_dtmf |
3391 spin_unlock_irqrestore(&hc->lock, flags);
3393 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3396 case PH_CONTROL_REQ:
3397 spin_lock_irqsave(&hc->lock, flags);
3399 case HFC_SPL_LOOP_ON: /* set sample loop */
3400 if (debug & DEBUG_HFCMULTI_MSG)
3402 "%s: HFC_SPL_LOOP_ON (len = %d)\n",
3403 __func__, skb->len);
3406 case HFC_SPL_LOOP_OFF: /* set silence */
3407 if (debug & DEBUG_HFCMULTI_MSG)
3408 printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n",
3414 "%s: unknown PH_CONTROL_REQ info %x\n",
3418 spin_unlock_irqrestore(&hc->lock, flags);
3420 case PH_DEACTIVATE_REQ:
3421 deactivate_bchannel(bch); /* locked there */
3422 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3433 * bchannel control function
3436 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
3439 struct dsp_features *features =
3440 (struct dsp_features *)(*((u_long *)&cq->p1));
3441 struct hfc_multi *hc = bch->hw;
3449 case MISDN_CTRL_GETOP:
3450 cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP
3451 | MISDN_CTRL_RX_OFF | MISDN_CTRL_FILL_EMPTY;
3453 case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */
3454 hc->chan[bch->slot].rx_off = !!cq->p1;
3455 if (!hc->chan[bch->slot].rx_off) {
3456 /* reset fifo on rx on */
3457 HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1);
3458 HFC_wait_nodebug(hc);
3459 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
3460 HFC_wait_nodebug(hc);
3462 if (debug & DEBUG_HFCMULTI_MSG)
3463 printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n",
3464 __func__, bch->nr, hc->chan[bch->slot].rx_off);
3466 case MISDN_CTRL_FILL_EMPTY: /* fill fifo, if empty */
3467 test_and_set_bit(FLG_FILLEMPTY, &bch->Flags);
3468 if (debug & DEBUG_HFCMULTI_MSG)
3469 printk(KERN_DEBUG "%s: FILL_EMPTY request (nr=%d "
3470 "off=%d)\n", __func__, bch->nr, !!cq->p1);
3472 case MISDN_CTRL_HW_FEATURES: /* fill features structure */
3473 if (debug & DEBUG_HFCMULTI_MSG)
3474 printk(KERN_DEBUG "%s: HW_FEATURE request\n",
3476 /* create confirm */
3477 features->hfc_id = hc->id;
3478 if (test_bit(HFC_CHIP_DTMF, &hc->chip))
3479 features->hfc_dtmf = 1;
3480 features->hfc_loops = 0;
3481 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
3482 features->hfc_echocanhw = 1;
3484 features->pcm_id = hc->pcm;
3485 features->pcm_slots = hc->slots;
3486 features->pcm_banks = 2;
3489 case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */
3490 slot_tx = cq->p1 & 0xff;
3491 bank_tx = cq->p1 >> 8;
3492 slot_rx = cq->p2 & 0xff;
3493 bank_rx = cq->p2 >> 8;
3494 if (debug & DEBUG_HFCMULTI_MSG)
3496 "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3497 "slot %d bank %d (RX)\n",
3498 __func__, slot_tx, bank_tx,
3500 if (slot_tx < hc->slots && bank_tx <= 2 &&
3501 slot_rx < hc->slots && bank_rx <= 2)
3502 hfcmulti_pcm(hc, bch->slot,
3503 slot_tx, bank_tx, slot_rx, bank_rx);
3506 "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3507 "slot %d bank %d (RX) out of range\n",
3508 __func__, slot_tx, bank_tx,
3513 case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */
3514 if (debug & DEBUG_HFCMULTI_MSG)
3515 printk(KERN_DEBUG "%s: HFC_PCM_DISC\n",
3517 hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0);
3519 case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */
3520 num = cq->p1 & 0xff;
3521 if (debug & DEBUG_HFCMULTI_MSG)
3522 printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n",
3525 hfcmulti_conf(hc, bch->slot, num);
3528 "%s: HW_CONF_JOIN conf %d out of range\n",
3533 case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */
3534 if (debug & DEBUG_HFCMULTI_MSG)
3535 printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__);
3536 hfcmulti_conf(hc, bch->slot, -1);
3538 case MISDN_CTRL_HFC_ECHOCAN_ON:
3539 if (debug & DEBUG_HFCMULTI_MSG)
3540 printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__);
3541 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3542 vpm_echocan_on(hc, bch->slot, cq->p1);
3547 case MISDN_CTRL_HFC_ECHOCAN_OFF:
3548 if (debug & DEBUG_HFCMULTI_MSG)
3549 printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n",
3551 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3552 vpm_echocan_off(hc, bch->slot);
3557 printk(KERN_WARNING "%s: unknown Op %x\n",
3566 hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
3568 struct bchannel *bch = container_of(ch, struct bchannel, ch);
3569 struct hfc_multi *hc = bch->hw;
3573 if (bch->debug & DEBUG_HW)
3574 printk(KERN_DEBUG "%s: cmd:%x %p\n",
3575 __func__, cmd, arg);
3578 test_and_clear_bit(FLG_OPEN, &bch->Flags);
3579 if (test_bit(FLG_ACTIVE, &bch->Flags))
3580 deactivate_bchannel(bch); /* locked there */
3581 ch->protocol = ISDN_P_NONE;
3583 module_put(THIS_MODULE);
3586 case CONTROL_CHANNEL:
3587 spin_lock_irqsave(&hc->lock, flags);
3588 err = channel_bctrl(bch, arg);
3589 spin_unlock_irqrestore(&hc->lock, flags);
3592 printk(KERN_WARNING "%s: unknown prim(%x)\n",
3599 * handle D-channel events
3601 * handle state change event
3604 ph_state_change(struct dchannel *dch)
3606 struct hfc_multi *hc = dch->hw;
3610 printk(KERN_WARNING "%s: ERROR given dch is NULL\n",
3616 if (hc->type == 1) {
3617 if (dch->dev.D.protocol == ISDN_P_TE_E1) {
3618 if (debug & DEBUG_HFCMULTI_STATE)
3620 "%s: E1 TE (id=%d) newstate %x\n",
3621 __func__, hc->id, dch->state);
3623 if (debug & DEBUG_HFCMULTI_STATE)
3625 "%s: E1 NT (id=%d) newstate %x\n",
3626 __func__, hc->id, dch->state);
3628 switch (dch->state) {
3630 if (hc->e1_state != 1) {
3631 for (i = 1; i <= 31; i++) {
3632 /* reset fifos on e1 activation */
3633 HFC_outb_nodebug(hc, R_FIFO, (i << 1) | 1);
3634 HFC_wait_nodebug(hc);
3635 HFC_outb_nodebug(hc,
3636 R_INC_RES_FIFO, V_RES_F);
3637 HFC_wait_nodebug(hc);
3640 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3641 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3642 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3646 if (hc->e1_state != 1)
3648 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3649 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3650 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3652 hc->e1_state = dch->state;
3654 if (dch->dev.D.protocol == ISDN_P_TE_S0) {
3655 if (debug & DEBUG_HFCMULTI_STATE)
3657 "%s: S/T TE newstate %x\n",
3658 __func__, dch->state);
3659 switch (dch->state) {
3661 l1_event(dch->l1, HW_RESET_IND);
3664 l1_event(dch->l1, HW_DEACT_IND);
3668 l1_event(dch->l1, ANYSIGNAL);
3671 l1_event(dch->l1, INFO2);
3674 l1_event(dch->l1, INFO4_P8);
3678 if (debug & DEBUG_HFCMULTI_STATE)
3679 printk(KERN_DEBUG "%s: S/T NT newstate %x\n",
3680 __func__, dch->state);
3681 switch (dch->state) {
3683 if (hc->chan[ch].nt_timer == 0) {
3684 hc->chan[ch].nt_timer = -1;
3685 HFC_outb(hc, R_ST_SEL,
3687 /* undocumented: delay after R_ST_SEL */
3689 HFC_outb(hc, A_ST_WR_STATE, 4 |
3690 V_ST_LD_STA); /* G4 */
3691 udelay(6); /* wait at least 5,21us */
3692 HFC_outb(hc, A_ST_WR_STATE, 4);
3695 /* one extra count for the next event */
3696 hc->chan[ch].nt_timer =
3697 nt_t1_count[poll_timer] + 1;
3698 HFC_outb(hc, R_ST_SEL,
3700 /* undocumented: delay after R_ST_SEL */
3702 /* allow G2 -> G3 transition */
3703 HFC_outb(hc, A_ST_WR_STATE, 2 |
3708 hc->chan[ch].nt_timer = -1;
3709 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3710 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3711 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3714 hc->chan[ch].nt_timer = -1;
3717 hc->chan[ch].nt_timer = -1;
3718 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3719 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3720 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3728 * called for card mode init message
3732 hfcmulti_initmode(struct dchannel *dch)
3734 struct hfc_multi *hc = dch->hw;
3735 u_char a_st_wr_state, r_e1_wr_sta;
3738 if (debug & DEBUG_HFCMULTI_INIT)
3739 printk(KERN_DEBUG "%s: entered\n", __func__);
3741 if (hc->type == 1) {
3742 hc->chan[hc->dslot].slot_tx = -1;
3743 hc->chan[hc->dslot].slot_rx = -1;
3744 hc->chan[hc->dslot].conf = -1;
3746 mode_hfcmulti(hc, hc->dslot, dch->dev.D.protocol,
3748 dch->timer.function = (void *) hfcmulti_dbusy_timer;
3749 dch->timer.data = (long) dch;
3750 init_timer(&dch->timer);
3752 for (i = 1; i <= 31; i++) {
3755 hc->chan[i].slot_tx = -1;
3756 hc->chan[i].slot_rx = -1;
3757 hc->chan[i].conf = -1;
3758 mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0);
3761 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
3762 HFC_outb(hc, R_LOS0, 255); /* 2 ms */
3763 HFC_outb(hc, R_LOS1, 255); /* 512 ms */
3765 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dslot].cfg)) {
3766 HFC_outb(hc, R_RX0, 0);
3767 hc->hw.r_tx0 = 0 | V_OUT_EN;
3769 HFC_outb(hc, R_RX0, 1);
3770 hc->hw.r_tx0 = 1 | V_OUT_EN;
3772 hc->hw.r_tx1 = V_ATX | V_NTRI;
3773 HFC_outb(hc, R_TX0, hc->hw.r_tx0);
3774 HFC_outb(hc, R_TX1, hc->hw.r_tx1);
3775 HFC_outb(hc, R_TX_FR0, 0x00);
3776 HFC_outb(hc, R_TX_FR1, 0xf8);
3778 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3779 HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E);
3781 HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0);
3783 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3784 HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC);
3786 if (dch->dev.D.protocol == ISDN_P_NT_E1) {
3787 if (debug & DEBUG_HFCMULTI_INIT)
3788 printk(KERN_DEBUG "%s: E1 port is NT-mode\n",
3790 r_e1_wr_sta = 0; /* G0 */
3791 hc->e1_getclock = 0;
3793 if (debug & DEBUG_HFCMULTI_INIT)
3794 printk(KERN_DEBUG "%s: E1 port is TE-mode\n",
3796 r_e1_wr_sta = 0; /* F0 */
3797 hc->e1_getclock = 1;
3799 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
3800 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
3802 HFC_outb(hc, R_SYNC_OUT, 0);
3803 if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip))
3804 hc->e1_getclock = 1;
3805 if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip))
3806 hc->e1_getclock = 0;
3807 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
3808 /* SLAVE (clock master) */
3809 if (debug & DEBUG_HFCMULTI_INIT)
3811 "%s: E1 port is clock master "
3812 "(clock from PCM)\n", __func__);
3813 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC);
3815 if (hc->e1_getclock) {
3816 /* MASTER (clock slave) */
3817 if (debug & DEBUG_HFCMULTI_INIT)
3819 "%s: E1 port is clock slave "
3820 "(clock to PCM)\n", __func__);
3821 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
3823 /* MASTER (clock master) */
3824 if (debug & DEBUG_HFCMULTI_INIT)
3825 printk(KERN_DEBUG "%s: E1 port is "
3827 "(clock from QUARTZ)\n",
3829 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC |
3830 V_PCM_SYNC | V_JATT_OFF);
3831 HFC_outb(hc, R_SYNC_OUT, 0);
3834 HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */
3835 HFC_outb(hc, R_PWM_MD, V_PWM0_MD);
3836 HFC_outb(hc, R_PWM0, 0x50);
3837 HFC_outb(hc, R_PWM1, 0xff);
3838 /* state machine setup */
3839 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA);
3840 udelay(6); /* wait at least 5,21us */
3841 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta);
3842 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3843 hc->syncronized = 0;
3844 plxsd_checksync(hc, 0);
3848 hc->chan[i].slot_tx = -1;
3849 hc->chan[i].slot_rx = -1;
3850 hc->chan[i].conf = -1;
3851 mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0);
3852 dch->timer.function = (void *)hfcmulti_dbusy_timer;
3853 dch->timer.data = (long) dch;
3854 init_timer(&dch->timer);
3855 hc->chan[i - 2].slot_tx = -1;
3856 hc->chan[i - 2].slot_rx = -1;
3857 hc->chan[i - 2].conf = -1;
3858 mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0);
3859 hc->chan[i - 1].slot_tx = -1;
3860 hc->chan[i - 1].slot_rx = -1;
3861 hc->chan[i - 1].conf = -1;
3862 mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0);
3864 pt = hc->chan[i].port;
3865 /* select interface */
3866 HFC_outb(hc, R_ST_SEL, pt);
3867 /* undocumented: delay after R_ST_SEL */
3869 if (dch->dev.D.protocol == ISDN_P_NT_S0) {
3870 if (debug & DEBUG_HFCMULTI_INIT)
3872 "%s: ST port %d is NT-mode\n",
3875 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt);
3876 a_st_wr_state = 1; /* G1 */
3877 hc->hw.a_st_ctrl0[pt] = V_ST_MD;
3879 if (debug & DEBUG_HFCMULTI_INIT)
3881 "%s: ST port %d is TE-mode\n",
3884 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te);
3885 a_st_wr_state = 2; /* F2 */
3886 hc->hw.a_st_ctrl0[pt] = 0;
3888 if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg))
3889 hc->hw.a_st_ctrl0[pt] |= V_TX_LI;
3891 HFC_outb(hc, A_ST_CTRL0, hc->hw.a_st_ctrl0[pt]);
3892 /* disable E-channel */
3893 if ((dch->dev.D.protocol == ISDN_P_NT_S0) ||
3894 test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg))
3895 HFC_outb(hc, A_ST_CTRL1, V_E_IGNO);
3897 HFC_outb(hc, A_ST_CTRL1, 0);
3898 /* enable B-channel receive */
3899 HFC_outb(hc, A_ST_CTRL2, V_B1_RX_EN | V_B2_RX_EN);
3900 /* state machine setup */
3901 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA);
3902 udelay(6); /* wait at least 5,21us */
3903 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state);
3904 hc->hw.r_sci_msk |= 1 << pt;
3905 /* state machine interrupts */
3906 HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk);
3907 /* unset sync on port */
3908 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3910 ~(1 << hc->chan[dch->slot].port);
3911 plxsd_checksync(hc, 0);
3914 if (debug & DEBUG_HFCMULTI_INIT)
3915 printk("%s: done\n", __func__);
3920 open_dchannel(struct hfc_multi *hc, struct dchannel *dch,
3921 struct channel_req *rq)
3926 if (debug & DEBUG_HW_OPEN)
3927 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
3928 dch->dev.id, __builtin_return_address(0));
3929 if (rq->protocol == ISDN_P_NONE)
3931 if ((dch->dev.D.protocol != ISDN_P_NONE) &&
3932 (dch->dev.D.protocol != rq->protocol)) {
3933 if (debug & DEBUG_HFCMULTI_MODE)
3934 printk(KERN_WARNING "%s: change protocol %x to %x\n",
3935 __func__, dch->dev.D.protocol, rq->protocol);
3937 if ((dch->dev.D.protocol == ISDN_P_TE_S0)
3938 && (rq->protocol != ISDN_P_TE_S0))
3939 l1_event(dch->l1, CLOSE_CHANNEL);
3940 if (dch->dev.D.protocol != rq->protocol) {
3941 if (rq->protocol == ISDN_P_TE_S0) {
3942 err = create_l1(dch, hfcm_l1callback);
3946 dch->dev.D.protocol = rq->protocol;
3947 spin_lock_irqsave(&hc->lock, flags);
3948 hfcmulti_initmode(dch);
3949 spin_unlock_irqrestore(&hc->lock, flags);
3952 if (((rq->protocol == ISDN_P_NT_S0) && (dch->state == 3)) ||
3953 ((rq->protocol == ISDN_P_TE_S0) && (dch->state == 7)) ||
3954 ((rq->protocol == ISDN_P_NT_E1) && (dch->state == 1)) ||
3955 ((rq->protocol == ISDN_P_TE_E1) && (dch->state == 1))) {
3956 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY,
3957 0, NULL, GFP_KERNEL);
3959 rq->ch = &dch->dev.D;
3960 if (!try_module_get(THIS_MODULE))
3961 printk(KERN_WARNING "%s:cannot get module\n", __func__);
3966 open_bchannel(struct hfc_multi *hc, struct dchannel *dch,
3967 struct channel_req *rq)
3969 struct bchannel *bch;
3972 if (!test_channelmap(rq->adr.channel, dch->dev.channelmap))
3974 if (rq->protocol == ISDN_P_NONE)
3977 ch = rq->adr.channel;
3979 ch = (rq->adr.channel - 1) + (dch->slot - 2);
3980 bch = hc->chan[ch].bch;
3982 printk(KERN_ERR "%s:internal error ch %d has no bch\n",
3986 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
3987 return -EBUSY; /* b-channel can be only open once */
3988 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
3989 bch->ch.protocol = rq->protocol;
3990 hc->chan[ch].rx_off = 0;
3992 if (!try_module_get(THIS_MODULE))
3993 printk(KERN_WARNING "%s:cannot get module\n", __func__);
3998 * device control function
4001 channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq)
4006 case MISDN_CTRL_GETOP:
4010 printk(KERN_WARNING "%s: unknown Op %x\n",
4019 hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
4021 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
4022 struct dchannel *dch = container_of(dev, struct dchannel, dev);
4023 struct hfc_multi *hc = dch->hw;
4024 struct channel_req *rq;
4028 if (dch->debug & DEBUG_HW)
4029 printk(KERN_DEBUG "%s: cmd:%x %p\n",
4030 __func__, cmd, arg);
4034 switch (rq->protocol) {
4037 if (hc->type == 1) {
4041 err = open_dchannel(hc, dch, rq); /* locked there */
4045 if (hc->type != 1) {
4049 err = open_dchannel(hc, dch, rq); /* locked there */
4052 spin_lock_irqsave(&hc->lock, flags);
4053 err = open_bchannel(hc, dch, rq);
4054 spin_unlock_irqrestore(&hc->lock, flags);
4058 if (debug & DEBUG_HW_OPEN)
4059 printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
4060 __func__, dch->dev.id,
4061 __builtin_return_address(0));
4062 module_put(THIS_MODULE);
4064 case CONTROL_CHANNEL:
4065 spin_lock_irqsave(&hc->lock, flags);
4066 err = channel_dctrl(dch, arg);
4067 spin_unlock_irqrestore(&hc->lock, flags);
4070 if (dch->debug & DEBUG_HW)
4071 printk(KERN_DEBUG "%s: unknown command %x\n",
4079 * initialize the card
4083 * start timer irq, wait some time and check if we have interrupts.
4084 * if not, reset chip and try again.
4087 init_card(struct hfc_multi *hc)
4091 void __iomem *plx_acc;
4094 if (debug & DEBUG_HFCMULTI_INIT)
4095 printk(KERN_DEBUG "%s: entered\n", __func__);
4097 spin_lock_irqsave(&hc->lock, flags);
4098 /* set interrupts but leave global interrupt disabled */
4099 hc->hw.r_irq_ctrl = V_FIFO_IRQ;
4101 spin_unlock_irqrestore(&hc->lock, flags);
4103 if (request_irq(hc->pci_dev->irq, hfcmulti_interrupt, IRQF_SHARED,
4105 printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n",
4109 hc->irq = hc->pci_dev->irq;
4111 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4112 spin_lock_irqsave(&plx_lock, plx_flags);
4113 plx_acc = hc->plx_membase + PLX_INTCSR;
4114 writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE),
4115 plx_acc); /* enable PCI & LINT1 irq */
4116 spin_unlock_irqrestore(&plx_lock, plx_flags);
4119 if (debug & DEBUG_HFCMULTI_INIT)
4120 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4121 __func__, hc->irq, hc->irqcnt);
4122 err = init_chip(hc);
4126 * Finally enable IRQ output
4127 * this is only allowed, if an IRQ routine is allready
4128 * established for this HFC, so don't do that earlier
4130 spin_lock_irqsave(&hc->lock, flags);
4132 spin_unlock_irqrestore(&hc->lock, flags);
4133 /* printk(KERN_DEBUG "no master irq set!!!\n"); */
4134 set_current_state(TASK_UNINTERRUPTIBLE);
4135 schedule_timeout((100*HZ)/1000); /* Timeout 100ms */
4136 /* turn IRQ off until chip is completely initialized */
4137 spin_lock_irqsave(&hc->lock, flags);
4139 spin_unlock_irqrestore(&hc->lock, flags);
4140 if (debug & DEBUG_HFCMULTI_INIT)
4141 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4142 __func__, hc->irq, hc->irqcnt);
4144 if (debug & DEBUG_HFCMULTI_INIT)
4145 printk(KERN_DEBUG "%s: done\n", __func__);
4149 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
4150 printk(KERN_INFO "ignoring missing interrupts\n");
4154 printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n",
4160 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4161 spin_lock_irqsave(&plx_lock, plx_flags);
4162 plx_acc = hc->plx_membase + PLX_INTCSR;
4163 writew(0x00, plx_acc); /*disable IRQs*/
4164 spin_unlock_irqrestore(&plx_lock, plx_flags);
4167 if (debug & DEBUG_HFCMULTI_INIT)
4168 printk(KERN_WARNING "%s: free irq %d\n", __func__, hc->irq);
4170 free_irq(hc->irq, hc);
4174 if (debug & DEBUG_HFCMULTI_INIT)
4175 printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err);
4180 * find pci device and set it up
4184 setup_pci(struct hfc_multi *hc, struct pci_dev *pdev,
4185 const struct pci_device_id *ent)
4187 struct hm_map *m = (struct hm_map *)ent->driver_data;
4190 "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n",
4191 m->vendor_name, m->card_name, m->clock2 ? "double" : "normal");
4195 test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip);
4197 if (ent->device == 0xB410) {
4198 test_and_set_bit(HFC_CHIP_B410P, &hc->chip);
4199 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4200 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4204 if (hc->pci_dev->irq <= 0) {
4205 printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n");
4208 if (pci_enable_device(hc->pci_dev)) {
4209 printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n");
4213 hc->ledstate = 0xAFFEAFFE;
4214 hc->opticalsupport = m->opticalsupport;
4216 /* set memory access methods */
4217 if (m->io_mode) /* use mode from card config */
4218 hc->io_mode = m->io_mode;
4219 switch (hc->io_mode) {
4220 case HFC_IO_MODE_PLXSD:
4221 test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip);
4222 hc->slots = 128; /* required */
4224 case HFC_IO_MODE_PCIMEM:
4225 hc->HFC_outb = HFC_outb_pcimem;
4226 hc->HFC_inb = HFC_inb_pcimem;
4227 hc->HFC_inw = HFC_inw_pcimem;
4228 hc->HFC_wait = HFC_wait_pcimem;
4229 hc->read_fifo = read_fifo_pcimem;
4230 hc->write_fifo = write_fifo_pcimem;
4232 case HFC_IO_MODE_REGIO:
4233 hc->HFC_outb = HFC_outb_regio;
4234 hc->HFC_inb = HFC_inb_regio;
4235 hc->HFC_inw = HFC_inw_regio;
4236 hc->HFC_wait = HFC_wait_regio;
4237 hc->read_fifo = read_fifo_regio;
4238 hc->write_fifo = write_fifo_regio;
4241 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4242 pci_disable_device(hc->pci_dev);
4245 hc->HFC_outb_nodebug = hc->HFC_outb;
4246 hc->HFC_inb_nodebug = hc->HFC_inb;
4247 hc->HFC_inw_nodebug = hc->HFC_inw;
4248 hc->HFC_wait_nodebug = hc->HFC_wait;
4249 #ifdef HFC_REGISTER_DEBUG
4250 hc->HFC_outb = HFC_outb_debug;
4251 hc->HFC_inb = HFC_inb_debug;
4252 hc->HFC_inw = HFC_inw_debug;
4253 hc->HFC_wait = HFC_wait_debug;
4256 hc->pci_membase = NULL;
4257 hc->plx_membase = NULL;
4259 switch (hc->io_mode) {
4260 case HFC_IO_MODE_PLXSD:
4261 hc->plx_origmembase = hc->pci_dev->resource[0].start;
4262 /* MEMBASE 1 is PLX PCI Bridge */
4264 if (!hc->plx_origmembase) {
4266 "HFC-multi: No IO-Memory for PCI PLX bridge found\n");
4267 pci_disable_device(hc->pci_dev);
4271 hc->plx_membase = ioremap(hc->plx_origmembase, 0x80);
4272 if (!hc->plx_membase) {
4274 "HFC-multi: failed to remap plx address space. "
4275 "(internal error)\n");
4276 pci_disable_device(hc->pci_dev);
4280 "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n",
4281 (u_long)hc->plx_membase, hc->plx_origmembase);
4283 hc->pci_origmembase = hc->pci_dev->resource[2].start;
4284 /* MEMBASE 1 is PLX PCI Bridge */
4285 if (!hc->pci_origmembase) {
4287 "HFC-multi: No IO-Memory for PCI card found\n");
4288 pci_disable_device(hc->pci_dev);
4292 hc->pci_membase = ioremap(hc->pci_origmembase, 0x400);
4293 if (!hc->pci_membase) {
4294 printk(KERN_WARNING "HFC-multi: failed to remap io "
4295 "address space. (internal error)\n");
4296 pci_disable_device(hc->pci_dev);
4301 "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d "
4303 hc->id, (u_long)hc->pci_membase, hc->pci_origmembase,
4304 hc->pci_dev->irq, HZ, hc->leds);
4305 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4307 case HFC_IO_MODE_PCIMEM:
4308 hc->pci_origmembase = hc->pci_dev->resource[1].start;
4309 if (!hc->pci_origmembase) {
4311 "HFC-multi: No IO-Memory for PCI card found\n");
4312 pci_disable_device(hc->pci_dev);
4316 hc->pci_membase = ioremap(hc->pci_origmembase, 256);
4317 if (!hc->pci_membase) {
4319 "HFC-multi: failed to remap io address space. "
4320 "(internal error)\n");
4321 pci_disable_device(hc->pci_dev);
4324 printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d "
4325 "HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
4326 hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds);
4327 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4329 case HFC_IO_MODE_REGIO:
4330 hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start;
4331 if (!hc->pci_iobase) {
4333 "HFC-multi: No IO for PCI card found\n");
4334 pci_disable_device(hc->pci_dev);
4338 if (!request_region(hc->pci_iobase, 8, "hfcmulti")) {
4339 printk(KERN_WARNING "HFC-multi: failed to request "
4340 "address space at 0x%08lx (internal error)\n",
4342 pci_disable_device(hc->pci_dev);
4347 "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n",
4348 m->vendor_name, m->card_name, (u_int) hc->pci_iobase,
4349 hc->pci_dev->irq, HZ, hc->leds);
4350 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO);
4353 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4354 pci_disable_device(hc->pci_dev);
4358 pci_set_drvdata(hc->pci_dev, hc);
4360 /* At this point the needed PCI config is done */
4361 /* fifos are still not enabled */
4371 release_port(struct hfc_multi *hc, struct dchannel *dch)
4375 struct bchannel *pb;
4378 pt = hc->chan[ci].port;
4380 if (debug & DEBUG_HFCMULTI_INIT)
4381 printk(KERN_DEBUG "%s: entered for port %d\n",
4384 if (pt >= hc->ports) {
4385 printk(KERN_WARNING "%s: ERROR port out of range (%d).\n",
4390 if (debug & DEBUG_HFCMULTI_INIT)
4391 printk(KERN_DEBUG "%s: releasing port=%d\n",
4394 if (dch->dev.D.protocol == ISDN_P_TE_S0)
4395 l1_event(dch->l1, CLOSE_CHANNEL);
4397 hc->chan[ci].dch = NULL;
4399 if (hc->created[pt]) {
4400 hc->created[pt] = 0;
4401 mISDN_unregister_device(&dch->dev);
4404 spin_lock_irqsave(&hc->lock, flags);
4406 if (dch->timer.function) {
4407 del_timer(&dch->timer);
4408 dch->timer.function = NULL;
4411 if (hc->type == 1) { /* E1 */
4413 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4414 hc->syncronized = 0;
4415 plxsd_checksync(hc, 1);
4418 for (i = 0; i <= 31; i++) {
4419 if (hc->chan[i].bch) {
4420 if (debug & DEBUG_HFCMULTI_INIT)
4422 "%s: free port %d channel %d\n",
4423 __func__, hc->chan[i].port+1, i);
4424 pb = hc->chan[i].bch;
4425 hc->chan[i].bch = NULL;
4426 spin_unlock_irqrestore(&hc->lock, flags);
4427 mISDN_freebchannel(pb);
4429 kfree(hc->chan[i].coeff);
4430 spin_lock_irqsave(&hc->lock, flags);
4435 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4437 ~(1 << hc->chan[ci].port);
4438 plxsd_checksync(hc, 1);
4441 if (hc->chan[ci - 2].bch) {
4442 if (debug & DEBUG_HFCMULTI_INIT)
4444 "%s: free port %d channel %d\n",
4445 __func__, hc->chan[ci - 2].port+1,
4447 pb = hc->chan[ci - 2].bch;
4448 hc->chan[ci - 2].bch = NULL;
4449 spin_unlock_irqrestore(&hc->lock, flags);
4450 mISDN_freebchannel(pb);
4452 kfree(hc->chan[ci - 2].coeff);
4453 spin_lock_irqsave(&hc->lock, flags);
4455 if (hc->chan[ci - 1].bch) {
4456 if (debug & DEBUG_HFCMULTI_INIT)
4458 "%s: free port %d channel %d\n",
4459 __func__, hc->chan[ci - 1].port+1,
4461 pb = hc->chan[ci - 1].bch;
4462 hc->chan[ci - 1].bch = NULL;
4463 spin_unlock_irqrestore(&hc->lock, flags);
4464 mISDN_freebchannel(pb);
4466 kfree(hc->chan[ci - 1].coeff);
4467 spin_lock_irqsave(&hc->lock, flags);
4471 spin_unlock_irqrestore(&hc->lock, flags);
4473 if (debug & DEBUG_HFCMULTI_INIT)
4474 printk(KERN_DEBUG "%s: free port %d channel D\n", __func__, pt);
4475 mISDN_freedchannel(dch);
4478 if (debug & DEBUG_HFCMULTI_INIT)
4479 printk(KERN_DEBUG "%s: done!\n", __func__);
4483 release_card(struct hfc_multi *hc)
4488 if (debug & DEBUG_HFCMULTI_INIT)
4489 printk(KERN_WARNING "%s: release card (%d) entered\n",
4492 spin_lock_irqsave(&hc->lock, flags);
4494 spin_unlock_irqrestore(&hc->lock, flags);
4502 /* disable D-channels & B-channels */
4503 if (debug & DEBUG_HFCMULTI_INIT)
4504 printk(KERN_DEBUG "%s: disable all channels (d and b)\n",
4506 for (ch = 0; ch <= 31; ch++) {
4507 if (hc->chan[ch].dch)
4508 release_port(hc, hc->chan[ch].dch);
4511 /* release hardware & irq */
4513 if (debug & DEBUG_HFCMULTI_INIT)
4514 printk(KERN_WARNING "%s: free irq %d\n",
4516 free_irq(hc->irq, hc);
4520 release_io_hfcmulti(hc);
4522 if (debug & DEBUG_HFCMULTI_INIT)
4523 printk(KERN_WARNING "%s: remove instance from list\n",
4525 list_del(&hc->list);
4527 if (debug & DEBUG_HFCMULTI_INIT)
4528 printk(KERN_WARNING "%s: delete instance\n", __func__);
4529 if (hc == syncmaster)
4532 if (debug & DEBUG_HFCMULTI_INIT)
4533 printk(KERN_WARNING "%s: card successfully removed\n",
4538 init_e1_port(struct hfc_multi *hc, struct hm_map *m)
4540 struct dchannel *dch;
4541 struct bchannel *bch;
4543 char name[MISDN_MAX_IDLEN];
4545 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4549 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4551 dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1);
4552 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4553 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4554 dch->dev.D.send = handle_dmsg;
4555 dch->dev.D.ctrl = hfcm_dctrl;
4556 dch->dev.nrbchan = (hc->dslot)?30:31;
4557 dch->slot = hc->dslot;
4558 hc->chan[hc->dslot].dch = dch;
4559 hc->chan[hc->dslot].port = 0;
4560 hc->chan[hc->dslot].nt_timer = -1;
4561 for (ch = 1; ch <= 31; ch++) {
4562 if (ch == hc->dslot) /* skip dchannel */
4564 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4566 printk(KERN_ERR "%s: no memory for bchannel\n",
4571 hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL);
4572 if (!hc->chan[ch].coeff) {
4573 printk(KERN_ERR "%s: no memory for coeffs\n",
4581 mISDN_initbchannel(bch, MAX_DATA_MEM);
4583 bch->ch.send = handle_bmsg;
4584 bch->ch.ctrl = hfcm_bctrl;
4586 list_add(&bch->ch.list, &dch->dev.bchannels);
4587 hc->chan[ch].bch = bch;
4588 hc->chan[ch].port = 0;
4589 set_channelmap(bch->nr, dch->dev.channelmap);
4591 /* set optical line type */
4592 if (port[Port_cnt] & 0x001) {
4593 if (!m->opticalsupport) {
4595 "This board has no optical "
4598 if (debug & DEBUG_HFCMULTI_INIT)
4600 "%s: PORT set optical "
4601 "interfacs: card(%d) "
4605 test_and_set_bit(HFC_CFG_OPTICAL,
4606 &hc->chan[hc->dslot].cfg);
4609 /* set LOS report */
4610 if (port[Port_cnt] & 0x004) {
4611 if (debug & DEBUG_HFCMULTI_INIT)
4612 printk(KERN_DEBUG "%s: PORT set "
4613 "LOS report: card(%d) port(%d)\n",
4614 __func__, HFC_cnt + 1, 1);
4615 test_and_set_bit(HFC_CFG_REPORT_LOS,
4616 &hc->chan[hc->dslot].cfg);
4618 /* set AIS report */
4619 if (port[Port_cnt] & 0x008) {
4620 if (debug & DEBUG_HFCMULTI_INIT)
4621 printk(KERN_DEBUG "%s: PORT set "
4622 "AIS report: card(%d) port(%d)\n",
4623 __func__, HFC_cnt + 1, 1);
4624 test_and_set_bit(HFC_CFG_REPORT_AIS,
4625 &hc->chan[hc->dslot].cfg);
4627 /* set SLIP report */
4628 if (port[Port_cnt] & 0x010) {
4629 if (debug & DEBUG_HFCMULTI_INIT)
4631 "%s: PORT set SLIP report: "
4632 "card(%d) port(%d)\n",
4633 __func__, HFC_cnt + 1, 1);
4634 test_and_set_bit(HFC_CFG_REPORT_SLIP,
4635 &hc->chan[hc->dslot].cfg);
4637 /* set RDI report */
4638 if (port[Port_cnt] & 0x020) {
4639 if (debug & DEBUG_HFCMULTI_INIT)
4641 "%s: PORT set RDI report: "
4642 "card(%d) port(%d)\n",
4643 __func__, HFC_cnt + 1, 1);
4644 test_and_set_bit(HFC_CFG_REPORT_RDI,
4645 &hc->chan[hc->dslot].cfg);
4647 /* set CRC-4 Mode */
4648 if (!(port[Port_cnt] & 0x100)) {
4649 if (debug & DEBUG_HFCMULTI_INIT)
4650 printk(KERN_DEBUG "%s: PORT turn on CRC4 report:"
4651 " card(%d) port(%d)\n",
4652 __func__, HFC_cnt + 1, 1);
4653 test_and_set_bit(HFC_CFG_CRC4,
4654 &hc->chan[hc->dslot].cfg);
4656 if (debug & DEBUG_HFCMULTI_INIT)
4657 printk(KERN_DEBUG "%s: PORT turn off CRC4"
4658 " report: card(%d) port(%d)\n",
4659 __func__, HFC_cnt + 1, 1);
4661 /* set forced clock */
4662 if (port[Port_cnt] & 0x0200) {
4663 if (debug & DEBUG_HFCMULTI_INIT)
4664 printk(KERN_DEBUG "%s: PORT force getting clock from "
4665 "E1: card(%d) port(%d)\n",
4666 __func__, HFC_cnt + 1, 1);
4667 test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip);
4669 if (port[Port_cnt] & 0x0400) {
4670 if (debug & DEBUG_HFCMULTI_INIT)
4671 printk(KERN_DEBUG "%s: PORT force putting clock to "
4672 "E1: card(%d) port(%d)\n",
4673 __func__, HFC_cnt + 1, 1);
4674 test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip);
4677 if (port[Port_cnt] & 0x0800) {
4678 if (debug & DEBUG_HFCMULTI_INIT)
4679 printk(KERN_DEBUG "%s: PORT disable JATT PLL on "
4680 "E1: card(%d) port(%d)\n",
4681 __func__, HFC_cnt + 1, 1);
4682 test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip);
4684 /* set elastic jitter buffer */
4685 if (port[Port_cnt] & 0x3000) {
4686 hc->chan[hc->dslot].jitter = (port[Port_cnt]>>12) & 0x3;
4687 if (debug & DEBUG_HFCMULTI_INIT)
4689 "%s: PORT set elastic "
4690 "buffer to %d: card(%d) port(%d)\n",
4691 __func__, hc->chan[hc->dslot].jitter,
4694 hc->chan[hc->dslot].jitter = 2; /* default */
4695 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1);
4696 ret = mISDN_register_device(&dch->dev, name);
4702 release_port(hc, dch);
4707 init_multi_port(struct hfc_multi *hc, int pt)
4709 struct dchannel *dch;
4710 struct bchannel *bch;
4712 char name[MISDN_MAX_IDLEN];
4714 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4718 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4720 dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
4721 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4722 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4723 dch->dev.D.send = handle_dmsg;
4724 dch->dev.D.ctrl = hfcm_dctrl;
4725 dch->dev.nrbchan = 2;
4728 hc->chan[i + 2].dch = dch;
4729 hc->chan[i + 2].port = pt;
4730 hc->chan[i + 2].nt_timer = -1;
4731 for (ch = 0; ch < dch->dev.nrbchan; ch++) {
4732 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4734 printk(KERN_ERR "%s: no memory for bchannel\n",
4739 hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL);
4740 if (!hc->chan[i + ch].coeff) {
4741 printk(KERN_ERR "%s: no memory for coeffs\n",
4749 mISDN_initbchannel(bch, MAX_DATA_MEM);
4751 bch->ch.send = handle_bmsg;
4752 bch->ch.ctrl = hfcm_bctrl;
4753 bch->ch.nr = ch + 1;
4754 list_add(&bch->ch.list, &dch->dev.bchannels);
4755 hc->chan[i + ch].bch = bch;
4756 hc->chan[i + ch].port = pt;
4757 set_channelmap(bch->nr, dch->dev.channelmap);
4759 /* set master clock */
4760 if (port[Port_cnt] & 0x001) {
4761 if (debug & DEBUG_HFCMULTI_INIT)
4763 "%s: PROTOCOL set master clock: "
4764 "card(%d) port(%d)\n",
4765 __func__, HFC_cnt + 1, pt + 1);
4766 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
4767 printk(KERN_ERR "Error: Master clock "
4768 "for port(%d) of card(%d) is only"
4769 " possible with TE-mode\n",
4770 pt + 1, HFC_cnt + 1);
4774 if (hc->masterclk >= 0) {
4775 printk(KERN_ERR "Error: Master clock "
4776 "for port(%d) of card(%d) already "
4777 "defined for port(%d)\n",
4778 pt + 1, HFC_cnt + 1, hc->masterclk+1);
4784 /* set transmitter line to non capacitive */
4785 if (port[Port_cnt] & 0x002) {
4786 if (debug & DEBUG_HFCMULTI_INIT)
4788 "%s: PROTOCOL set non capacitive "
4789 "transmitter: card(%d) port(%d)\n",
4790 __func__, HFC_cnt + 1, pt + 1);
4791 test_and_set_bit(HFC_CFG_NONCAP_TX,
4792 &hc->chan[i + 2].cfg);
4794 /* disable E-channel */
4795 if (port[Port_cnt] & 0x004) {
4796 if (debug & DEBUG_HFCMULTI_INIT)
4798 "%s: PROTOCOL disable E-channel: "
4799 "card(%d) port(%d)\n",
4800 __func__, HFC_cnt + 1, pt + 1);
4801 test_and_set_bit(HFC_CFG_DIS_ECHANNEL,
4802 &hc->chan[i + 2].cfg);
4804 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d/%d",
4805 hc->type, HFC_cnt + 1, pt + 1);
4806 ret = mISDN_register_device(&dch->dev, name);
4809 hc->created[pt] = 1;
4812 release_port(hc, dch);
4817 hfcmulti_init(struct pci_dev *pdev, const struct pci_device_id *ent)
4819 struct hm_map *m = (struct hm_map *)ent->driver_data;
4822 struct hfc_multi *hc;
4824 u_char dips = 0, pmj = 0; /* dip settings, port mode Jumpers */
4827 if (HFC_cnt >= MAX_CARDS) {
4828 printk(KERN_ERR "too many cards (max=%d).\n",
4832 if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) {
4833 printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but "
4834 "type[%d] %d was supplied as module parameter\n",
4835 m->vendor_name, m->card_name, m->type, HFC_cnt,
4836 type[HFC_cnt] & 0xff);
4837 printk(KERN_WARNING "HFC-MULTI: Load module without parameters "
4838 "first, to see cards and their types.");
4841 if (debug & DEBUG_HFCMULTI_INIT)
4842 printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n",
4843 __func__, m->vendor_name, m->card_name, m->type,
4846 /* allocate card+fifo structure */
4847 hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL);
4849 printk(KERN_ERR "No kmem for HFC-Multi card\n");
4852 spin_lock_init(&hc->lock);
4855 hc->ports = m->ports;
4857 hc->pcm = pcm[HFC_cnt];
4858 hc->io_mode = iomode[HFC_cnt];
4859 if (dslot[HFC_cnt] < 0 && hc->type == 1) {
4861 printk(KERN_INFO "HFC-E1 card has disabled D-channel, but "
4863 } if (dslot[HFC_cnt] > 0 && dslot[HFC_cnt] < 32 && hc->type == 1) {
4864 hc->dslot = dslot[HFC_cnt];
4865 printk(KERN_INFO "HFC-E1 card has alternating D-channel on "
4866 "time slot %d\n", dslot[HFC_cnt]);
4870 /* set chip specific features */
4872 if (type[HFC_cnt] & 0x100) {
4873 test_and_set_bit(HFC_CHIP_ULAW, &hc->chip);
4874 hc->silence = 0xff; /* ulaw silence */
4876 hc->silence = 0x2a; /* alaw silence */
4877 if ((poll >> 1) > sizeof(hc->silence_data)) {
4878 printk(KERN_ERR "HFCMULTI error: silence_data too small, "
4882 for (i = 0; i < (poll >> 1); i++)
4883 hc->silence_data[i] = hc->silence;
4885 if (!(type[HFC_cnt] & 0x200))
4886 test_and_set_bit(HFC_CHIP_DTMF, &hc->chip);
4888 if (type[HFC_cnt] & 0x800)
4889 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4890 if (type[HFC_cnt] & 0x1000) {
4891 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4892 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4894 if (type[HFC_cnt] & 0x4000)
4895 test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip);
4896 if (type[HFC_cnt] & 0x8000)
4897 test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip);
4899 if (type[HFC_cnt] & 0x10000)
4901 if (type[HFC_cnt] & 0x20000)
4903 if (type[HFC_cnt] & 0x80000) {
4904 test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip);
4906 hc->wdbyte = V_GPIO_OUT2;
4907 printk(KERN_NOTICE "Watchdog enabled\n");
4910 /* setup pci, hc->slots may change due to PLXSD */
4911 ret_err = setup_pci(hc, pdev, ent);
4913 if (hc == syncmaster)
4919 /* crate channels */
4920 for (pt = 0; pt < hc->ports; pt++) {
4921 if (Port_cnt >= MAX_PORTS) {
4922 printk(KERN_ERR "too many ports (max=%d).\n",
4928 ret_err = init_e1_port(hc, m);
4930 ret_err = init_multi_port(hc, pt);
4931 if (debug & DEBUG_HFCMULTI_INIT)
4933 "%s: Registering D-channel, card(%d) port(%d)"
4935 __func__, HFC_cnt + 1, pt, ret_err);
4938 while (pt) { /* release already registered ports */
4940 release_port(hc, hc->chan[(pt << 2) + 2].dch);
4948 switch (m->dip_type) {
4951 * Get DIP setting for beroNet 1S/2S/4S cards
4952 * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) +
4953 * GPI 19/23 (R_GPI_IN2))
4955 dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) |
4956 ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) |
4957 (~HFC_inb(hc, R_GPI_IN2) & 0x08);
4959 /* Port mode (TE/NT) jumpers */
4960 pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4) & 0xf);
4962 if (test_bit(HFC_CHIP_B410P, &hc->chip))
4965 printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n",
4966 m->vendor_name, m->card_name, dips, pmj);
4970 * Get DIP Setting for beroNet 8S0+ cards
4971 * Enable PCI auxbridge function
4973 HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
4974 /* prepare access to auxport */
4975 outw(0x4000, hc->pci_iobase + 4);
4977 * some dummy reads are required to
4978 * read valid DIP switch data
4980 dips = inb(hc->pci_iobase);
4981 dips = inb(hc->pci_iobase);
4982 dips = inb(hc->pci_iobase);
4983 dips = ~inb(hc->pci_iobase) & 0x3F;
4984 outw(0x0, hc->pci_iobase + 4);
4985 /* disable PCI auxbridge function */
4986 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
4987 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
4988 m->vendor_name, m->card_name, dips);
4992 * get DIP Setting for beroNet E1 cards
4993 * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0)
4995 dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0)>>4;
4996 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
4997 m->vendor_name, m->card_name, dips);
5002 spin_lock_irqsave(&HFClock, flags);
5003 list_add_tail(&hc->list, &HFClist);
5004 spin_unlock_irqrestore(&HFClock, flags);
5006 /* initialize hardware */
5007 ret_err = init_card(hc);
5009 printk(KERN_ERR "init card returns %d\n", ret_err);
5014 /* start IRQ and return */
5015 spin_lock_irqsave(&hc->lock, flags);
5017 spin_unlock_irqrestore(&hc->lock, flags);
5021 release_io_hfcmulti(hc);
5022 if (hc == syncmaster)
5028 static void __devexit hfc_remove_pci(struct pci_dev *pdev)
5030 struct hfc_multi *card = pci_get_drvdata(pdev);
5034 printk(KERN_INFO "removing hfc_multi card vendor:%x "
5035 "device:%x subvendor:%x subdevice:%x\n",
5036 pdev->vendor, pdev->device,
5037 pdev->subsystem_vendor, pdev->subsystem_device);
5040 spin_lock_irqsave(&HFClock, flags);
5042 spin_unlock_irqrestore(&HFClock, flags);
5045 printk(KERN_WARNING "%s: drvdata allready removed\n",
5050 #define VENDOR_CCD "Cologne Chip AG"
5051 #define VENDOR_BN "beroNet GmbH"
5052 #define VENDOR_DIG "Digium Inc."
5053 #define VENDOR_JH "Junghanns.NET GmbH"
5054 #define VENDOR_PRIM "PrimuX"
5056 static const struct hm_map hfcm_map[] = {
5057 /*0*/ {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0},
5058 /*1*/ {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0},
5059 /*2*/ {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0},
5060 /*3*/ {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0},
5061 /*4*/ {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0},
5062 /*5*/ {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0},
5063 /*6*/ {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0},
5064 /*7*/ {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0},
5065 /*8*/ {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO},
5066 /*9*/ {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0},
5067 /*10*/ {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0},
5068 /*11*/ {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0},
5070 /*12*/ {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0},
5071 /*13*/ {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S,
5073 /*14*/ {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0},
5074 /*15*/ {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0},
5076 /*16*/ {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0},
5077 /*17*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0},
5078 /*18*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0},
5080 /*19*/ {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0},
5081 /*20*/ {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0},
5082 /*21*/ {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0},
5083 /*22*/ {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0},
5085 /*23*/ {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0},
5086 /*24*/ {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0},
5087 /*25*/ {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0},
5089 /*26*/ {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0,
5091 /*27*/ {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0,
5093 /*28*/ {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0},
5094 /*29*/ {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0},
5095 /*30*/ {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0},
5099 #define H(x) ((unsigned long)&hfcm_map[x])
5100 static struct pci_device_id hfmultipci_ids[] __devinitdata = {
5102 /* Cards with HFC-4S Chip */
5103 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5104 PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */
5105 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5106 PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */
5107 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5108 PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */
5109 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5110 PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */
5111 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5112 PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */
5113 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5114 PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */
5115 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5116 PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */
5117 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5118 PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */
5119 { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S,
5120 PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)},
5121 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5122 PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */
5123 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5124 PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)},
5125 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5126 PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */
5127 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5128 PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */
5129 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5130 PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */
5132 /* Cards with HFC-8S Chip */
5133 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5134 PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */
5135 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5136 PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */
5137 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5138 PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */
5139 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5140 PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)}, /* IOB8ST Recording */
5141 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5142 PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST */
5143 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5144 PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST */
5145 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5146 PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */
5147 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5148 PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */
5151 /* Cards with HFC-E1 Chip */
5152 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5153 PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */
5154 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5155 PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */
5156 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5157 PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */
5158 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5159 PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */
5161 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5162 PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */
5163 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5164 PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */
5165 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5166 PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */
5168 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5169 PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */
5170 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5171 PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */
5172 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_ANY_ID, PCI_ANY_ID,
5174 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_ANY_ID, PCI_ANY_ID,
5176 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_ANY_ID, PCI_ANY_ID,
5182 MODULE_DEVICE_TABLE(pci, hfmultipci_ids);
5185 hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
5187 struct hm_map *m = (struct hm_map *)ent->driver_data;
5190 if (m == NULL && ent->vendor == PCI_VENDOR_ID_CCD && (
5191 ent->device == PCI_DEVICE_ID_CCD_HFC4S ||
5192 ent->device == PCI_DEVICE_ID_CCD_HFC8S ||
5193 ent->device == PCI_DEVICE_ID_CCD_HFCE1)) {
5195 "Unknown HFC multiport controller (vendor:%x device:%x "
5196 "subvendor:%x subdevice:%x)\n", ent->vendor, ent->device,
5197 ent->subvendor, ent->subdevice);
5199 "Please contact the driver maintainer for support.\n");
5202 ret = hfcmulti_init(pdev, ent);
5206 printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5210 static struct pci_driver hfcmultipci_driver = {
5211 .name = "hfc_multi",
5212 .probe = hfcmulti_probe,
5213 .remove = __devexit_p(hfc_remove_pci),
5214 .id_table = hfmultipci_ids,
5218 HFCmulti_cleanup(void)
5220 struct hfc_multi *card, *next;
5222 /* get rid of all devices of this driver */
5223 list_for_each_entry_safe(card, next, &HFClist, list)
5225 pci_unregister_driver(&hfcmultipci_driver);
5233 printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION);
5236 printk(KERN_DEBUG "%s: IRQ_DEBUG IS ENABLED!\n", __func__);
5239 spin_lock_init(&HFClock);
5240 spin_lock_init(&plx_lock);
5242 if (debug & DEBUG_HFCMULTI_INIT)
5243 printk(KERN_DEBUG "%s: init entered\n", __func__);
5270 "%s: Wrong poll value (%d).\n", __func__, poll);
5276 err = pci_register_driver(&hfcmultipci_driver);
5278 printk(KERN_ERR "error registering pci driver: %x\n", err);
5285 module_init(HFCmulti_init);
5286 module_exit(HFCmulti_cleanup);