drivers/irqchip/qcom-pdc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/err.h>
   7 #include <linux/init.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/irq.h>
  10 #include <linux/irqchip.h>
  11 #include <linux/irqdomain.h>
  12 #include <linux/io.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_irq.h>
  18 #include <linux/soc/qcom/irq.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/slab.h>
  21 #include <linux/types.h>
  22
  23 #define PDC_MAX_GPIO_IRQS       256
  24
  25 #define IRQ_ENABLE_BANK         0x10
  26 #define IRQ_i_CFG               0x110
  27
  28 struct pdc_pin_region {
  29         u32 pin_base;
  30         u32 parent_base;
  31         u32 cnt;
  32 };
  33
  34 #define pin_to_hwirq(r, p)      ((r)->parent_base + (p) - (r)->pin_base)
  35
  36 static DEFINE_RAW_SPINLOCK(pdc_lock);
  37 static void __iomem *pdc_base;
  38 static struct pdc_pin_region *pdc_region;
  39 static int pdc_region_cnt;
  40
  41 static void pdc_reg_write(int reg, u32 i, u32 val)
  42 {
  43         writel_relaxed(val, pdc_base + reg + i * sizeof(u32));
  44 }
  45
  46 static u32 pdc_reg_read(int reg, u32 i)
  47 {
  48         return readl_relaxed(pdc_base + reg + i * sizeof(u32));
  49 }
  50
  51 static void pdc_enable_intr(struct irq_data *d, bool on)
  52 {
  53         int pin_out = d->hwirq;
  54         unsigned long enable;
  55         unsigned long flags;
  56         u32 index, mask;
  57
  58         index = pin_out / 32;
  59         mask = pin_out % 32;
  60
  61         raw_spin_lock_irqsave(&pdc_lock, flags);
  62         enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
  63         __assign_bit(mask, &enable, on);
  64         pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
  65         raw_spin_unlock_irqrestore(&pdc_lock, flags);
  66 }
  67
  68 static void qcom_pdc_gic_disable(struct irq_data *d)
  69 {
  70         pdc_enable_intr(d, false);
  71         irq_chip_disable_parent(d);
  72 }
  73
  74 static void qcom_pdc_gic_enable(struct irq_data *d)
  75 {
  76         pdc_enable_intr(d, true);
  77         irq_chip_enable_parent(d);
  78 }
  79
  80 /*
  81  * GIC does not handle falling edge or active low. To allow falling edge and
  82  * active low interrupts to be handled at GIC, PDC has an inverter that inverts
  83  * falling edge into a rising edge and active low into an active high.
  84  * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to
  85  * set as per the table below.
  86  * Level sensitive active low    LOW
  87  * Rising edge sensitive         NOT USED
  88  * Falling edge sensitive        LOW
  89  * Dual Edge sensitive           NOT USED
  90  * Level sensitive active High   HIGH
  91  * Falling Edge sensitive        NOT USED
  92  * Rising edge sensitive         HIGH
  93  * Dual Edge sensitive           HIGH
  94  */
  95 enum pdc_irq_config_bits {
  96         PDC_LEVEL_LOW           = 0b000,
  97         PDC_EDGE_FALLING        = 0b010,
  98         PDC_LEVEL_HIGH          = 0b100,
  99         PDC_EDGE_RISING         = 0b110,
 100         PDC_EDGE_DUAL           = 0b111,
 101 };
 102
 103 /**
 104  * qcom_pdc_gic_set_type: Configure PDC for the interrupt
 105  *
 106  * @d: the interrupt data
 107  * @type: the interrupt type
 108  *
 109  * If @type is edge triggered, forward that as Rising edge as PDC
 110  * takes care of converting falling edge to rising edge signal
 111  * If @type is level, then forward that as level high as PDC
 112  * takes care of converting falling edge to rising edge signal
 113  */
 114 static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
 115 {
 116         enum pdc_irq_config_bits pdc_type;
 117         enum pdc_irq_config_bits old_pdc_type;
 118         int ret;
 119
 120         switch (type) {
 121         case IRQ_TYPE_EDGE_RISING:
 122                 pdc_type = PDC_EDGE_RISING;
 123                 break;
 124         case IRQ_TYPE_EDGE_FALLING:
 125                 pdc_type = PDC_EDGE_FALLING;
 126                 type = IRQ_TYPE_EDGE_RISING;
 127                 break;
 128         case IRQ_TYPE_EDGE_BOTH:
 129                 pdc_type = PDC_EDGE_DUAL;
 130                 type = IRQ_TYPE_EDGE_RISING;
 131                 break;
 132         case IRQ_TYPE_LEVEL_HIGH:
 133                 pdc_type = PDC_LEVEL_HIGH;
 134                 break;
 135         case IRQ_TYPE_LEVEL_LOW:
 136                 pdc_type = PDC_LEVEL_LOW;
 137                 type = IRQ_TYPE_LEVEL_HIGH;
 138                 break;
 139         default:
 140                 WARN_ON(1);
 141                 return -EINVAL;
 142         }
 143
 144         old_pdc_type = pdc_reg_read(IRQ_i_CFG, d->hwirq);
 145         pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type);
 146
 147         ret = irq_chip_set_type_parent(d, type);
 148         if (ret)
 149                 return ret;
 150
 151         /*
 152          * When we change types the PDC can give a phantom interrupt.
 153          * Clear it.  Specifically the phantom shows up when reconfiguring
 154          * polarity of interrupt without changing the state of the signal
 155          * but let's be consistent and clear it always.
 156          *
 157          * Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the
 158          * interrupt will be cleared before the rest of the system sees it.
 159          */
 160         if (old_pdc_type != pdc_type)
 161                 irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false);
 162
 163         return 0;
 164 }
 165
 166 static struct irq_chip qcom_pdc_gic_chip = {
 167         .name                   = "PDC",
 168         .irq_eoi                = irq_chip_eoi_parent,
 169         .irq_mask               = irq_chip_mask_parent,
 170         .irq_unmask             = irq_chip_unmask_parent,
 171         .irq_disable            = qcom_pdc_gic_disable,
 172         .irq_enable             = qcom_pdc_gic_enable,
 173         .irq_get_irqchip_state  = irq_chip_get_parent_state,
 174         .irq_set_irqchip_state  = irq_chip_set_parent_state,
 175         .irq_retrigger          = irq_chip_retrigger_hierarchy,
 176         .irq_set_type           = qcom_pdc_gic_set_type,
 177         .flags                  = IRQCHIP_MASK_ON_SUSPEND |
 178                                   IRQCHIP_SET_TYPE_MASKED |
 179                                   IRQCHIP_SKIP_SET_WAKE |
 180                                   IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
 181         .irq_set_vcpu_affinity  = irq_chip_set_vcpu_affinity_parent,
 182         .irq_set_affinity       = irq_chip_set_affinity_parent,
 183 };
 184
 185 static struct pdc_pin_region *get_pin_region(int pin)
 186 {
 187         int i;
 188
 189         for (i = 0; i < pdc_region_cnt; i++) {
 190                 if (pin >= pdc_region[i].pin_base &&
 191                     pin < pdc_region[i].pin_base + pdc_region[i].cnt)
 192                         return &pdc_region[i];
 193         }
 194
 195         return NULL;
 196 }
 197
 198 static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
 199                           unsigned int nr_irqs, void *data)
 200 {
 201         struct irq_fwspec *fwspec = data;
 202         struct irq_fwspec parent_fwspec;
 203         struct pdc_pin_region *region;
 204         irq_hw_number_t hwirq;
 205         unsigned int type;
 206         int ret;
 207
 208         ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
 209         if (ret)
 210                 return ret;
 211
 212         if (hwirq == GPIO_NO_WAKE_IRQ)
 213                 return irq_domain_disconnect_hierarchy(domain, virq);
 214
 215         ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
 216                                             &qcom_pdc_gic_chip, NULL);
 217         if (ret)
 218                 return ret;
 219
 220         region = get_pin_region(hwirq);
 221         if (!region)
 222                 return irq_domain_disconnect_hierarchy(domain->parent, virq);
 223
 224         if (type & IRQ_TYPE_EDGE_BOTH)
 225                 type = IRQ_TYPE_EDGE_RISING;
 226
 227         if (type & IRQ_TYPE_LEVEL_MASK)
 228                 type = IRQ_TYPE_LEVEL_HIGH;
 229
 230         parent_fwspec.fwnode      = domain->parent->fwnode;
 231         parent_fwspec.param_count = 3;
 232         parent_fwspec.param[0]    = 0;
 233         parent_fwspec.param[1]    = pin_to_hwirq(region, hwirq);
 234         parent_fwspec.param[2]    = type;
 235
 236         return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
 237                                             &parent_fwspec);
 238 }
 239
 240 static const struct irq_domain_ops qcom_pdc_ops = {
 241         .translate      = irq_domain_translate_twocell,
 242         .alloc          = qcom_pdc_alloc,
 243         .free           = irq_domain_free_irqs_common,
 244 };
 245
 246 static int pdc_setup_pin_mapping(struct device_node *np)
 247 {
 248         int ret, n, i;
 249         u32 irq_index, reg_index, val;
 250
 251         n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));
 252         if (n <= 0 || n % 3)
 253                 return -EINVAL;
 254
 255         pdc_region_cnt = n / 3;
 256         pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL);
 257         if (!pdc_region) {
 258                 pdc_region_cnt = 0;
 259                 return -ENOMEM;
 260         }
 261
 262         for (n = 0; n < pdc_region_cnt; n++) {
 263                 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
 264                                                  n * 3 + 0,
 265                                                  &pdc_region[n].pin_base);
 266                 if (ret)
 267                         return ret;
 268                 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
 269                                                  n * 3 + 1,
 270                                                  &pdc_region[n].parent_base);
 271                 if (ret)
 272                         return ret;
 273                 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
 274                                                  n * 3 + 2,
 275                                                  &pdc_region[n].cnt);
 276                 if (ret)
 277                         return ret;
 278
 279                 for (i = 0; i < pdc_region[n].cnt; i++) {
 280                         reg_index = (i + pdc_region[n].pin_base) >> 5;
 281                         irq_index = (i + pdc_region[n].pin_base) & 0x1f;
 282                         val = pdc_reg_read(IRQ_ENABLE_BANK, reg_index);
 283                         val &= ~BIT(irq_index);
 284                         pdc_reg_write(IRQ_ENABLE_BANK, reg_index, val);
 285                 }
 286         }
 287
 288         return 0;
 289 }
 290
 291 static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
 292 {
 293         struct irq_domain *parent_domain, *pdc_domain;
 294         int ret;
 295
 296         pdc_base = of_iomap(node, 0);
 297         if (!pdc_base) {
 298                 pr_err("%pOF: unable to map PDC registers\n", node);
 299                 return -ENXIO;
 300         }
 301
 302         parent_domain = irq_find_host(parent);
 303         if (!parent_domain) {
 304                 pr_err("%pOF: unable to find PDC's parent domain\n", node);
 305                 ret = -ENXIO;
 306                 goto fail;
 307         }
 308
 309         ret = pdc_setup_pin_mapping(node);
 310         if (ret) {
 311                 pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);
 312                 goto fail;
 313         }
 314
 315         pdc_domain = irq_domain_create_hierarchy(parent_domain,
 316                                         IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP,
 317                                         PDC_MAX_GPIO_IRQS,
 318                                         of_fwnode_handle(node),
 319                                         &qcom_pdc_ops, NULL);
 320         if (!pdc_domain) {
 321                 pr_err("%pOF: PDC domain add failed\n", node);
 322                 ret = -ENOMEM;
 323                 goto fail;
 324         }
 325
 326         irq_domain_update_bus_token(pdc_domain, DOMAIN_BUS_WAKEUP);
 327
 328         return 0;
 329
 330 fail:
 331         kfree(pdc_region);
 332         iounmap(pdc_base);
 333         return ret;
 334 }
 335
 336 IRQCHIP_PLATFORM_DRIVER_BEGIN(qcom_pdc)
 337 IRQCHIP_MATCH("qcom,pdc", qcom_pdc_init)
 338 IRQCHIP_PLATFORM_DRIVER_END(qcom_pdc)
 339 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Power Domain Controller");
 340 MODULE_LICENSE("GPL v2");