drivers/irqchip/qcom-pdc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/err.h>
   7 #include <linux/init.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/irq.h>
  10 #include <linux/irqchip.h>
  11 #include <linux/irqdomain.h>
  12 #include <linux/io.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_device.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/soc/qcom/irq.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/slab.h>
  22 #include <linux/types.h>
  23
  24 #define PDC_MAX_IRQS            168
  25 #define PDC_MAX_GPIO_IRQS       256
  26
  27 #define CLEAR_INTR(reg, intr)   (reg & ~(1 << intr))
  28 #define ENABLE_INTR(reg, intr)  (reg | (1 << intr))
  29
  30 #define IRQ_ENABLE_BANK         0x10
  31 #define IRQ_i_CFG               0x110
  32
  33 #define PDC_NO_PARENT_IRQ       ~0UL
  34
  35 struct pdc_pin_region {
  36         u32 pin_base;
  37         u32 parent_base;
  38         u32 cnt;
  39 };
  40
  41 static DEFINE_RAW_SPINLOCK(pdc_lock);
  42 static void __iomem *pdc_base;
  43 static struct pdc_pin_region *pdc_region;
  44 static int pdc_region_cnt;
  45
  46 static void pdc_reg_write(int reg, u32 i, u32 val)
  47 {
  48         writel_relaxed(val, pdc_base + reg + i * sizeof(u32));
  49 }
  50
  51 static u32 pdc_reg_read(int reg, u32 i)
  52 {
  53         return readl_relaxed(pdc_base + reg + i * sizeof(u32));
  54 }
  55
  56 static void pdc_enable_intr(struct irq_data *d, bool on)
  57 {
  58         int pin_out = d->hwirq;
  59         unsigned long flags;
  60         u32 index, mask;
  61         u32 enable;
  62
  63         index = pin_out / 32;
  64         mask = pin_out % 32;
  65
  66         raw_spin_lock_irqsave(&pdc_lock, flags);
  67         enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
  68         enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask);
  69         pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
  70         raw_spin_unlock_irqrestore(&pdc_lock, flags);
  71 }
  72
  73 static void qcom_pdc_gic_disable(struct irq_data *d)
  74 {
  75         pdc_enable_intr(d, false);
  76         irq_chip_disable_parent(d);
  77 }
  78
  79 static void qcom_pdc_gic_enable(struct irq_data *d)
  80 {
  81         pdc_enable_intr(d, true);
  82         irq_chip_enable_parent(d);
  83 }
  84
  85 /*
  86  * GIC does not handle falling edge or active low. To allow falling edge and
  87  * active low interrupts to be handled at GIC, PDC has an inverter that inverts
  88  * falling edge into a rising edge and active low into an active high.
  89  * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to
  90  * set as per the table below.
  91  * Level sensitive active low    LOW
  92  * Rising edge sensitive         NOT USED
  93  * Falling edge sensitive        LOW
  94  * Dual Edge sensitive           NOT USED
  95  * Level sensitive active High   HIGH
  96  * Falling Edge sensitive        NOT USED
  97  * Rising edge sensitive         HIGH
  98  * Dual Edge sensitive           HIGH
  99  */
 100 enum pdc_irq_config_bits {
 101         PDC_LEVEL_LOW           = 0b000,
 102         PDC_EDGE_FALLING        = 0b010,
 103         PDC_LEVEL_HIGH          = 0b100,
 104         PDC_EDGE_RISING         = 0b110,
 105         PDC_EDGE_DUAL           = 0b111,
 106 };
 107
 108 /**
 109  * qcom_pdc_gic_set_type: Configure PDC for the interrupt
 110  *
 111  * @d: the interrupt data
 112  * @type: the interrupt type
 113  *
 114  * If @type is edge triggered, forward that as Rising edge as PDC
 115  * takes care of converting falling edge to rising edge signal
 116  * If @type is level, then forward that as level high as PDC
 117  * takes care of converting falling edge to rising edge signal
 118  */
 119 static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
 120 {
 121         enum pdc_irq_config_bits pdc_type;
 122         enum pdc_irq_config_bits old_pdc_type;
 123         int ret;
 124
 125         switch (type) {
 126         case IRQ_TYPE_EDGE_RISING:
 127                 pdc_type = PDC_EDGE_RISING;
 128                 break;
 129         case IRQ_TYPE_EDGE_FALLING:
 130                 pdc_type = PDC_EDGE_FALLING;
 131                 type = IRQ_TYPE_EDGE_RISING;
 132                 break;
 133         case IRQ_TYPE_EDGE_BOTH:
 134                 pdc_type = PDC_EDGE_DUAL;
 135                 type = IRQ_TYPE_EDGE_RISING;
 136                 break;
 137         case IRQ_TYPE_LEVEL_HIGH:
 138                 pdc_type = PDC_LEVEL_HIGH;
 139                 break;
 140         case IRQ_TYPE_LEVEL_LOW:
 141                 pdc_type = PDC_LEVEL_LOW;
 142                 type = IRQ_TYPE_LEVEL_HIGH;
 143                 break;
 144         default:
 145                 WARN_ON(1);
 146                 return -EINVAL;
 147         }
 148
 149         old_pdc_type = pdc_reg_read(IRQ_i_CFG, d->hwirq);
 150         pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type);
 151
 152         ret = irq_chip_set_type_parent(d, type);
 153         if (ret)
 154                 return ret;
 155
 156         /*
 157          * When we change types the PDC can give a phantom interrupt.
 158          * Clear it.  Specifically the phantom shows up when reconfiguring
 159          * polarity of interrupt without changing the state of the signal
 160          * but let's be consistent and clear it always.
 161          *
 162          * Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the
 163          * interrupt will be cleared before the rest of the system sees it.
 164          */
 165         if (old_pdc_type != pdc_type)
 166                 irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false);
 167
 168         return 0;
 169 }
 170
 171 static struct irq_chip qcom_pdc_gic_chip = {
 172         .name                   = "PDC",
 173         .irq_eoi                = irq_chip_eoi_parent,
 174         .irq_mask               = irq_chip_mask_parent,
 175         .irq_unmask             = irq_chip_unmask_parent,
 176         .irq_disable            = qcom_pdc_gic_disable,
 177         .irq_enable             = qcom_pdc_gic_enable,
 178         .irq_get_irqchip_state  = irq_chip_get_parent_state,
 179         .irq_set_irqchip_state  = irq_chip_set_parent_state,
 180         .irq_retrigger          = irq_chip_retrigger_hierarchy,
 181         .irq_set_type           = qcom_pdc_gic_set_type,
 182         .flags                  = IRQCHIP_MASK_ON_SUSPEND |
 183                                   IRQCHIP_SET_TYPE_MASKED |
 184                                   IRQCHIP_SKIP_SET_WAKE |
 185                                   IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
 186         .irq_set_vcpu_affinity  = irq_chip_set_vcpu_affinity_parent,
 187         .irq_set_affinity       = irq_chip_set_affinity_parent,
 188 };
 189
 190 static irq_hw_number_t get_parent_hwirq(int pin)
 191 {
 192         int i;
 193         struct pdc_pin_region *region;
 194
 195         for (i = 0; i < pdc_region_cnt; i++) {
 196                 region = &pdc_region[i];
 197                 if (pin >= region->pin_base &&
 198                     pin < region->pin_base + region->cnt)
 199                         return (region->parent_base + pin - region->pin_base);
 200         }
 201
 202         return PDC_NO_PARENT_IRQ;
 203 }
 204
 205 static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
 206                               unsigned long *hwirq, unsigned int *type)
 207 {
 208         if (is_of_node(fwspec->fwnode)) {
 209                 if (fwspec->param_count != 2)
 210                         return -EINVAL;
 211
 212                 *hwirq = fwspec->param[0];
 213                 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
 214                 return 0;
 215         }
 216
 217         return -EINVAL;
 218 }
 219
 220 static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
 221                           unsigned int nr_irqs, void *data)
 222 {
 223         struct irq_fwspec *fwspec = data;
 224         struct irq_fwspec parent_fwspec;
 225         irq_hw_number_t hwirq, parent_hwirq;
 226         unsigned int type;
 227         int ret;
 228
 229         ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
 230         if (ret)
 231                 return ret;
 232
 233         ret  = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
 234                                              &qcom_pdc_gic_chip, NULL);
 235         if (ret)
 236                 return ret;
 237
 238         parent_hwirq = get_parent_hwirq(hwirq);
 239         if (parent_hwirq == PDC_NO_PARENT_IRQ)
 240                 return irq_domain_disconnect_hierarchy(domain->parent, virq);
 241
 242         if (type & IRQ_TYPE_EDGE_BOTH)
 243                 type = IRQ_TYPE_EDGE_RISING;
 244
 245         if (type & IRQ_TYPE_LEVEL_MASK)
 246                 type = IRQ_TYPE_LEVEL_HIGH;
 247
 248         parent_fwspec.fwnode      = domain->parent->fwnode;
 249         parent_fwspec.param_count = 3;
 250         parent_fwspec.param[0]    = 0;
 251         parent_fwspec.param[1]    = parent_hwirq;
 252         parent_fwspec.param[2]    = type;
 253
 254         return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
 255                                             &parent_fwspec);
 256 }
 257
 258 static const struct irq_domain_ops qcom_pdc_ops = {
 259         .translate      = qcom_pdc_translate,
 260         .alloc          = qcom_pdc_alloc,
 261         .free           = irq_domain_free_irqs_common,
 262 };
 263
 264 static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq,
 265                                unsigned int nr_irqs, void *data)
 266 {
 267         struct irq_fwspec *fwspec = data;
 268         struct irq_fwspec parent_fwspec;
 269         irq_hw_number_t hwirq, parent_hwirq;
 270         unsigned int type;
 271         int ret;
 272
 273         ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
 274         if (ret)
 275                 return ret;
 276
 277         if (hwirq == GPIO_NO_WAKE_IRQ)
 278                 return irq_domain_disconnect_hierarchy(domain, virq);
 279
 280         ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
 281                                             &qcom_pdc_gic_chip, NULL);
 282         if (ret)
 283                 return ret;
 284
 285         parent_hwirq = get_parent_hwirq(hwirq);
 286         if (parent_hwirq == PDC_NO_PARENT_IRQ)
 287                 return irq_domain_disconnect_hierarchy(domain->parent, virq);
 288
 289         if (type & IRQ_TYPE_EDGE_BOTH)
 290                 type = IRQ_TYPE_EDGE_RISING;
 291
 292         if (type & IRQ_TYPE_LEVEL_MASK)
 293                 type = IRQ_TYPE_LEVEL_HIGH;
 294
 295         parent_fwspec.fwnode      = domain->parent->fwnode;
 296         parent_fwspec.param_count = 3;
 297         parent_fwspec.param[0]    = 0;
 298         parent_fwspec.param[1]    = parent_hwirq;
 299         parent_fwspec.param[2]    = type;
 300
 301         return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
 302                                             &parent_fwspec);
 303 }
 304
 305 static int qcom_pdc_gpio_domain_select(struct irq_domain *d,
 306                                        struct irq_fwspec *fwspec,
 307                                        enum irq_domain_bus_token bus_token)
 308 {
 309         return bus_token == DOMAIN_BUS_WAKEUP;
 310 }
 311
 312 static const struct irq_domain_ops qcom_pdc_gpio_ops = {
 313         .select         = qcom_pdc_gpio_domain_select,
 314         .alloc          = qcom_pdc_gpio_alloc,
 315         .free           = irq_domain_free_irqs_common,
 316 };
 317
 318 static int pdc_setup_pin_mapping(struct device_node *np)
 319 {
 320         int ret, n, i;
 321         u32 irq_index, reg_index, val;
 322
 323         n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));
 324         if (n <= 0 || n % 3)
 325                 return -EINVAL;
 326
 327         pdc_region_cnt = n / 3;
 328         pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL);
 329         if (!pdc_region) {
 330                 pdc_region_cnt = 0;
 331                 return -ENOMEM;
 332         }
 333
 334         for (n = 0; n < pdc_region_cnt; n++) {
 335                 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
 336                                                  n * 3 + 0,
 337                                                  &pdc_region[n].pin_base);
 338                 if (ret)
 339                         return ret;
 340                 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
 341                                                  n * 3 + 1,
 342                                                  &pdc_region[n].parent_base);
 343                 if (ret)
 344                         return ret;
 345                 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
 346                                                  n * 3 + 2,
 347                                                  &pdc_region[n].cnt);
 348                 if (ret)
 349                         return ret;
 350
 351                 for (i = 0; i < pdc_region[n].cnt; i++) {
 352                         reg_index = (i + pdc_region[n].pin_base) >> 5;
 353                         irq_index = (i + pdc_region[n].pin_base) & 0x1f;
 354                         val = pdc_reg_read(IRQ_ENABLE_BANK, reg_index);
 355                         val &= ~BIT(irq_index);
 356                         pdc_reg_write(IRQ_ENABLE_BANK, reg_index, val);
 357                 }
 358         }
 359
 360         return 0;
 361 }
 362
 363 static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
 364 {
 365         struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain;
 366         int ret;
 367
 368         pdc_base = of_iomap(node, 0);
 369         if (!pdc_base) {
 370                 pr_err("%pOF: unable to map PDC registers\n", node);
 371                 return -ENXIO;
 372         }
 373
 374         parent_domain = irq_find_host(parent);
 375         if (!parent_domain) {
 376                 pr_err("%pOF: unable to find PDC's parent domain\n", node);
 377                 ret = -ENXIO;
 378                 goto fail;
 379         }
 380
 381         ret = pdc_setup_pin_mapping(node);
 382         if (ret) {
 383                 pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);
 384                 goto fail;
 385         }
 386
 387         pdc_domain = irq_domain_create_hierarchy(parent_domain, 0, PDC_MAX_IRQS,
 388                                                  of_fwnode_handle(node),
 389                                                  &qcom_pdc_ops, NULL);
 390         if (!pdc_domain) {
 391                 pr_err("%pOF: GIC domain add failed\n", node);
 392                 ret = -ENOMEM;
 393                 goto fail;
 394         }
 395
 396         pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain,
 397                                         IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP,
 398                                         PDC_MAX_GPIO_IRQS,
 399                                         of_fwnode_handle(node),
 400                                         &qcom_pdc_gpio_ops, NULL);
 401         if (!pdc_gpio_domain) {
 402                 pr_err("%pOF: PDC domain add failed for GPIO domain\n", node);
 403                 ret = -ENOMEM;
 404                 goto remove;
 405         }
 406
 407         irq_domain_update_bus_token(pdc_gpio_domain, DOMAIN_BUS_WAKEUP);
 408
 409         return 0;
 410
 411 remove:
 412         irq_domain_remove(pdc_domain);
 413 fail:
 414         kfree(pdc_region);
 415         iounmap(pdc_base);
 416         return ret;
 417 }
 418
 419 IRQCHIP_PLATFORM_DRIVER_BEGIN(qcom_pdc)
 420 IRQCHIP_MATCH("qcom,pdc", qcom_pdc_init)
 421 IRQCHIP_PLATFORM_DRIVER_END(qcom_pdc)
 422 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Power Domain Controller");
 423 MODULE_LICENSE("GPL v2");