drivers/irqchip/irq-sni-exiu.c

   1 /*
   2  * Driver for Socionext External Interrupt Unit (EXIU)
   3  *
   4  * Copyright (c) 2017-2019 Linaro, Ltd. <ard.biesheuvel@linaro.org>
   5  *
   6  * Based on irq-tegra.c:
   7  *   Copyright (C) 2011 Google, Inc.
   8  *   Copyright (C) 2010,2013, NVIDIA Corporation
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/irq.h>
  18 #include <linux/irqchip.h>
  19 #include <linux/irqdomain.h>
  20 #include <linux/of.h>
  21 #include <linux/of_address.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/platform_device.h>
  24
  25 #include <dt-bindings/interrupt-controller/arm-gic.h>
  26
  27 #define NUM_IRQS        32
  28
  29 #define EIMASK          0x00
  30 #define EISRCSEL        0x04
  31 #define EIREQSTA        0x08
  32 #define EIRAWREQSTA     0x0C
  33 #define EIREQCLR        0x10
  34 #define EILVL           0x14
  35 #define EIEDG           0x18
  36 #define EISIR           0x1C
  37
  38 struct exiu_irq_data {
  39         void __iomem    *base;
  40         u32             spi_base;
  41 };
  42
  43 static void exiu_irq_eoi(struct irq_data *d)
  44 {
  45         struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
  46
  47         writel(BIT(d->hwirq), data->base + EIREQCLR);
  48         irq_chip_eoi_parent(d);
  49 }
  50
  51 static void exiu_irq_mask(struct irq_data *d)
  52 {
  53         struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
  54         u32 val;
  55
  56         val = readl_relaxed(data->base + EIMASK) | BIT(d->hwirq);
  57         writel_relaxed(val, data->base + EIMASK);
  58         irq_chip_mask_parent(d);
  59 }
  60
  61 static void exiu_irq_unmask(struct irq_data *d)
  62 {
  63         struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
  64         u32 val;
  65
  66         val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq);
  67         writel_relaxed(val, data->base + EIMASK);
  68         irq_chip_unmask_parent(d);
  69 }
  70
  71 static void exiu_irq_enable(struct irq_data *d)
  72 {
  73         struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
  74         u32 val;
  75
  76         /* clear interrupts that were latched while disabled */
  77         writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR);
  78
  79         val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq);
  80         writel_relaxed(val, data->base + EIMASK);
  81         irq_chip_enable_parent(d);
  82 }
  83
  84 static int exiu_irq_set_type(struct irq_data *d, unsigned int type)
  85 {
  86         struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
  87         u32 val;
  88
  89         val = readl_relaxed(data->base + EILVL);
  90         if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
  91                 val |= BIT(d->hwirq);
  92         else
  93                 val &= ~BIT(d->hwirq);
  94         writel_relaxed(val, data->base + EILVL);
  95
  96         val = readl_relaxed(data->base + EIEDG);
  97         if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
  98                 val &= ~BIT(d->hwirq);
  99         else
 100                 val |= BIT(d->hwirq);
 101         writel_relaxed(val, data->base + EIEDG);
 102
 103         writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR);
 104
 105         return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
 106 }
 107
 108 static struct irq_chip exiu_irq_chip = {
 109         .name                   = "EXIU",
 110         .irq_eoi                = exiu_irq_eoi,
 111         .irq_enable             = exiu_irq_enable,
 112         .irq_mask               = exiu_irq_mask,
 113         .irq_unmask             = exiu_irq_unmask,
 114         .irq_set_type           = exiu_irq_set_type,
 115         .irq_set_affinity       = irq_chip_set_affinity_parent,
 116         .flags                  = IRQCHIP_SET_TYPE_MASKED |
 117                                   IRQCHIP_SKIP_SET_WAKE |
 118                                   IRQCHIP_EOI_THREADED |
 119                                   IRQCHIP_MASK_ON_SUSPEND,
 120 };
 121
 122 static int exiu_domain_translate(struct irq_domain *domain,
 123                                  struct irq_fwspec *fwspec,
 124                                  unsigned long *hwirq,
 125                                  unsigned int *type)
 126 {
 127         struct exiu_irq_data *info = domain->host_data;
 128
 129         if (is_of_node(fwspec->fwnode)) {
 130                 if (fwspec->param_count != 3)
 131                         return -EINVAL;
 132
 133                 if (fwspec->param[0] != GIC_SPI)
 134                         return -EINVAL; /* No PPI should point to this domain */
 135
 136                 *hwirq = fwspec->param[1] - info->spi_base;
 137                 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
 138         } else {
 139                 if (fwspec->param_count != 2)
 140                         return -EINVAL;
 141                 *hwirq = fwspec->param[0];
 142                 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
 143         }
 144         return 0;
 145 }
 146
 147 static int exiu_domain_alloc(struct irq_domain *dom, unsigned int virq,
 148                              unsigned int nr_irqs, void *data)
 149 {
 150         struct irq_fwspec *fwspec = data;
 151         struct irq_fwspec parent_fwspec;
 152         struct exiu_irq_data *info = dom->host_data;
 153         irq_hw_number_t hwirq;
 154
 155         parent_fwspec = *fwspec;
 156         if (is_of_node(dom->parent->fwnode)) {
 157                 if (fwspec->param_count != 3)
 158                         return -EINVAL; /* Not GIC compliant */
 159                 if (fwspec->param[0] != GIC_SPI)
 160                         return -EINVAL; /* No PPI should point to this domain */
 161
 162                 hwirq = fwspec->param[1] - info->spi_base;
 163         } else {
 164                 hwirq = fwspec->param[0];
 165                 parent_fwspec.param[0] = hwirq + info->spi_base + 32;
 166         }
 167         WARN_ON(nr_irqs != 1);
 168         irq_domain_set_hwirq_and_chip(dom, virq, hwirq, &exiu_irq_chip, info);
 169
 170         parent_fwspec.fwnode = dom->parent->fwnode;
 171         return irq_domain_alloc_irqs_parent(dom, virq, nr_irqs, &parent_fwspec);
 172 }
 173
 174 static const struct irq_domain_ops exiu_domain_ops = {
 175         .translate      = exiu_domain_translate,
 176         .alloc          = exiu_domain_alloc,
 177         .free           = irq_domain_free_irqs_common,
 178 };
 179
 180 static struct exiu_irq_data *exiu_init(const struct fwnode_handle *fwnode,
 181                                        struct resource *res)
 182 {
 183         struct exiu_irq_data *data;
 184         int err;
 185
 186         data = kzalloc(sizeof(*data), GFP_KERNEL);
 187         if (!data)
 188                 return ERR_PTR(-ENOMEM);
 189
 190         if (fwnode_property_read_u32_array(fwnode, "socionext,spi-base",
 191                                            &data->spi_base, 1)) {
 192                 err = -ENODEV;
 193                 goto out_free;
 194         }
 195
 196         data->base = ioremap(res->start, resource_size(res));
 197         if (!data->base) {
 198                 err = -ENODEV;
 199                 goto out_free;
 200         }
 201
 202         /* clear and mask all interrupts */
 203         writel_relaxed(0xFFFFFFFF, data->base + EIREQCLR);
 204         writel_relaxed(0xFFFFFFFF, data->base + EIMASK);
 205
 206         return data;
 207
 208 out_free:
 209         kfree(data);
 210         return ERR_PTR(err);
 211 }
 212
 213 static int __init exiu_dt_init(struct device_node *node,
 214                                struct device_node *parent)
 215 {
 216         struct irq_domain *parent_domain, *domain;
 217         struct exiu_irq_data *data;
 218         struct resource res;
 219
 220         if (!parent) {
 221                 pr_err("%pOF: no parent, giving up\n", node);
 222                 return -ENODEV;
 223         }
 224
 225         parent_domain = irq_find_host(parent);
 226         if (!parent_domain) {
 227                 pr_err("%pOF: unable to obtain parent domain\n", node);
 228                 return -ENXIO;
 229         }
 230
 231         if (of_address_to_resource(node, 0, &res)) {
 232                 pr_err("%pOF: failed to parse memory resource\n", node);
 233                 return -ENXIO;
 234         }
 235
 236         data = exiu_init(of_node_to_fwnode(node), &res);
 237         if (IS_ERR(data))
 238                 return PTR_ERR(data);
 239
 240         domain = irq_domain_add_hierarchy(parent_domain, 0, NUM_IRQS, node,
 241                                           &exiu_domain_ops, data);
 242         if (!domain) {
 243                 pr_err("%pOF: failed to allocate domain\n", node);
 244                 goto out_unmap;
 245         }
 246
 247         pr_info("%pOF: %d interrupts forwarded to %pOF\n", node, NUM_IRQS,
 248                 parent);
 249
 250         return 0;
 251
 252 out_unmap:
 253         iounmap(data->base);
 254         kfree(data);
 255         return -ENOMEM;
 256 }
 257 IRQCHIP_DECLARE(exiu, "socionext,synquacer-exiu", exiu_dt_init);
 258
 259 #ifdef CONFIG_ACPI
 260 static int exiu_acpi_probe(struct platform_device *pdev)
 261 {
 262         struct irq_domain *domain;
 263         struct exiu_irq_data *data;
 264         struct resource *res;
 265
 266         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 267         if (!res) {
 268                 dev_err(&pdev->dev, "failed to parse memory resource\n");
 269                 return -ENXIO;
 270         }
 271
 272         data = exiu_init(dev_fwnode(&pdev->dev), res);
 273         if (IS_ERR(data))
 274                 return PTR_ERR(data);
 275
 276         domain = acpi_irq_create_hierarchy(0, NUM_IRQS, dev_fwnode(&pdev->dev),
 277                                            &exiu_domain_ops, data);
 278         if (!domain) {
 279                 dev_err(&pdev->dev, "failed to create IRQ domain\n");
 280                 goto out_unmap;
 281         }
 282
 283         dev_info(&pdev->dev, "%d interrupts forwarded\n", NUM_IRQS);
 284
 285         return 0;
 286
 287 out_unmap:
 288         iounmap(data->base);
 289         kfree(data);
 290         return -ENOMEM;
 291 }
 292
 293 static const struct acpi_device_id exiu_acpi_ids[] = {
 294         { "SCX0008" },
 295         { /* sentinel */ }
 296 };
 297 MODULE_DEVICE_TABLE(acpi, exiu_acpi_ids);
 298
 299 static struct platform_driver exiu_driver = {
 300         .driver = {
 301                 .name = "exiu",
 302                 .acpi_match_table = exiu_acpi_ids,
 303         },
 304         .probe = exiu_acpi_probe,
 305 };
 306 builtin_platform_driver(exiu_driver);
 307 #endif