drivers/irqchip/irq-mvebu-pic.c

   1 /*
   2  * Copyright (C) 2016 Marvell
   3  *
   4  * Yehuda Yitschak <yehuday@marvell.com>
   5  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2.  This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/irq.h>
  15 #include <linux/irqchip.h>
  16 #include <linux/irqchip/chained_irq.h>
  17 #include <linux/irqdomain.h>
  18 #include <linux/module.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/platform_device.h>
  21
  22 #define PIC_CAUSE              0x0
  23 #define PIC_MASK               0x4
  24
  25 #define PIC_MAX_IRQS            32
  26 #define PIC_MAX_IRQ_MASK        ((1UL << PIC_MAX_IRQS) - 1)
  27
  28 struct mvebu_pic {
  29         void __iomem *base;
  30         u32 parent_irq;
  31         struct irq_domain *domain;
  32         struct irq_chip irq_chip;
  33 };
  34
  35 static void mvebu_pic_reset(struct mvebu_pic *pic)
  36 {
  37         /* ACK and mask all interrupts */
  38         writel(0, pic->base + PIC_MASK);
  39         writel(PIC_MAX_IRQ_MASK, pic->base + PIC_CAUSE);
  40 }
  41
  42 static void mvebu_pic_eoi_irq(struct irq_data *d)
  43 {
  44         struct mvebu_pic *pic = irq_data_get_irq_chip_data(d);
  45
  46         writel(1 << d->hwirq, pic->base + PIC_CAUSE);
  47 }
  48
  49 static void mvebu_pic_mask_irq(struct irq_data *d)
  50 {
  51         struct mvebu_pic *pic = irq_data_get_irq_chip_data(d);
  52         u32 reg;
  53
  54         reg =  readl(pic->base + PIC_MASK);
  55         reg |= (1 << d->hwirq);
  56         writel(reg, pic->base + PIC_MASK);
  57 }
  58
  59 static void mvebu_pic_unmask_irq(struct irq_data *d)
  60 {
  61         struct mvebu_pic *pic = irq_data_get_irq_chip_data(d);
  62         u32 reg;
  63
  64         reg = readl(pic->base + PIC_MASK);
  65         reg &= ~(1 << d->hwirq);
  66         writel(reg, pic->base + PIC_MASK);
  67 }
  68
  69 static int mvebu_pic_irq_map(struct irq_domain *domain, unsigned int virq,
  70                              irq_hw_number_t hwirq)
  71 {
  72         struct mvebu_pic *pic = domain->host_data;
  73
  74         irq_set_percpu_devid(virq);
  75         irq_set_chip_data(virq, pic);
  76         irq_set_chip_and_handler(virq, &pic->irq_chip,
  77                                  handle_percpu_devid_irq);
  78         irq_set_status_flags(virq, IRQ_LEVEL);
  79         irq_set_probe(virq);
  80
  81         return 0;
  82 }
  83
  84 static const struct irq_domain_ops mvebu_pic_domain_ops = {
  85         .map = mvebu_pic_irq_map,
  86         .xlate = irq_domain_xlate_onecell,
  87 };
  88
  89 static void mvebu_pic_handle_cascade_irq(struct irq_desc *desc)
  90 {
  91         struct mvebu_pic *pic = irq_desc_get_handler_data(desc);
  92         struct irq_chip *chip = irq_desc_get_chip(desc);
  93         unsigned long irqmap, irqn;
  94
  95         irqmap = readl_relaxed(pic->base + PIC_CAUSE);
  96         chained_irq_enter(chip, desc);
  97
  98         for_each_set_bit(irqn, &irqmap, BITS_PER_LONG)
  99                 generic_handle_domain_irq(pic->domain, irqn);
 100
 101         chained_irq_exit(chip, desc);
 102 }
 103
 104 static void mvebu_pic_enable_percpu_irq(void *data)
 105 {
 106         struct mvebu_pic *pic = data;
 107
 108         mvebu_pic_reset(pic);
 109         enable_percpu_irq(pic->parent_irq, IRQ_TYPE_NONE);
 110 }
 111
 112 static void mvebu_pic_disable_percpu_irq(void *data)
 113 {
 114         struct mvebu_pic *pic = data;
 115
 116         disable_percpu_irq(pic->parent_irq);
 117 }
 118
 119 static int mvebu_pic_probe(struct platform_device *pdev)
 120 {
 121         struct device_node *node = pdev->dev.of_node;
 122         struct mvebu_pic *pic;
 123         struct irq_chip *irq_chip;
 124         struct resource *res;
 125
 126         pic = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pic), GFP_KERNEL);
 127         if (!pic)
 128                 return -ENOMEM;
 129
 130         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 131         pic->base = devm_ioremap_resource(&pdev->dev, res);
 132         if (IS_ERR(pic->base))
 133                 return PTR_ERR(pic->base);
 134
 135         irq_chip = &pic->irq_chip;
 136         irq_chip->name = dev_name(&pdev->dev);
 137         irq_chip->irq_mask = mvebu_pic_mask_irq;
 138         irq_chip->irq_unmask = mvebu_pic_unmask_irq;
 139         irq_chip->irq_eoi = mvebu_pic_eoi_irq;
 140
 141         pic->parent_irq = irq_of_parse_and_map(node, 0);
 142         if (pic->parent_irq <= 0) {
 143                 dev_err(&pdev->dev, "Failed to parse parent interrupt\n");
 144                 return -EINVAL;
 145         }
 146
 147         pic->domain = irq_domain_add_linear(node, PIC_MAX_IRQS,
 148                                             &mvebu_pic_domain_ops, pic);
 149         if (!pic->domain) {
 150                 dev_err(&pdev->dev, "Failed to allocate irq domain\n");
 151                 return -ENOMEM;
 152         }
 153
 154         irq_set_chained_handler(pic->parent_irq, mvebu_pic_handle_cascade_irq);
 155         irq_set_handler_data(pic->parent_irq, pic);
 156
 157         on_each_cpu(mvebu_pic_enable_percpu_irq, pic, 1);
 158
 159         platform_set_drvdata(pdev, pic);
 160
 161         return 0;
 162 }
 163
 164 static int mvebu_pic_remove(struct platform_device *pdev)
 165 {
 166         struct mvebu_pic *pic = platform_get_drvdata(pdev);
 167
 168         on_each_cpu(mvebu_pic_disable_percpu_irq, pic, 1);
 169         irq_domain_remove(pic->domain);
 170
 171         return 0;
 172 }
 173
 174 static const struct of_device_id mvebu_pic_of_match[] = {
 175         { .compatible = "marvell,armada-8k-pic", },
 176         {},
 177 };
 178 MODULE_DEVICE_TABLE(of, mvebu_pic_of_match);
 179
 180 static struct platform_driver mvebu_pic_driver = {
 181         .probe  = mvebu_pic_probe,
 182         .remove = mvebu_pic_remove,
 183         .driver = {
 184                 .name = "mvebu-pic",
 185                 .of_match_table = mvebu_pic_of_match,
 186         },
 187 };
 188 module_platform_driver(mvebu_pic_driver);
 189
 190 MODULE_AUTHOR("Yehuda Yitschak <yehuday@marvell.com>");
 191 MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
 192 MODULE_LICENSE("GPL v2");
 193 MODULE_ALIAS("platform:mvebu_pic");
 194