2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
10 #define pr_fmt(fmt) "irq-mips-gic: " fmt
12 #include <linux/bitmap.h>
13 #include <linux/clocksource.h>
14 #include <linux/cpuhotplug.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/irqchip.h>
19 #include <linux/irqdomain.h>
20 #include <linux/of_address.h>
21 #include <linux/percpu.h>
22 #include <linux/sched.h>
23 #include <linux/smp.h>
25 #include <asm/mips-cps.h>
26 #include <asm/setup.h>
27 #include <asm/traps.h>
29 #include <dt-bindings/interrupt-controller/mips-gic.h>
31 #define GIC_MAX_INTRS 256
32 #define GIC_MAX_LONGS BITS_TO_LONGS(GIC_MAX_INTRS)
34 /* Add 2 to convert GIC CPU pin to core interrupt */
35 #define GIC_CPU_PIN_OFFSET 2
37 /* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
38 #define GIC_PIN_TO_VEC_OFFSET 1
40 /* Convert between local/shared IRQ number and GIC HW IRQ number. */
41 #define GIC_LOCAL_HWIRQ_BASE 0
42 #define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x))
43 #define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
44 #define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS
45 #define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x))
46 #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
48 void __iomem *mips_gic_base;
50 static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks);
52 static DEFINE_SPINLOCK(gic_lock);
53 static struct irq_domain *gic_irq_domain;
54 static int gic_shared_intrs;
55 static unsigned int gic_cpu_pin;
56 static unsigned int timer_cpu_pin;
57 static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
59 #ifdef CONFIG_GENERIC_IRQ_IPI
60 static DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS);
61 static DECLARE_BITMAP(ipi_available, GIC_MAX_INTRS);
62 #endif /* CONFIG_GENERIC_IRQ_IPI */
64 static struct gic_all_vpes_chip_data {
67 } gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS];
69 static void gic_clear_pcpu_masks(unsigned int intr)
73 /* Clear the interrupt's bit in all pcpu_masks */
74 for_each_possible_cpu(i)
75 clear_bit(intr, per_cpu_ptr(pcpu_masks, i));
78 static bool gic_local_irq_is_routable(int intr)
82 /* All local interrupts are routable in EIC mode. */
86 vpe_ctl = read_gic_vl_ctl();
88 case GIC_LOCAL_INT_TIMER:
89 return vpe_ctl & GIC_VX_CTL_TIMER_ROUTABLE;
90 case GIC_LOCAL_INT_PERFCTR:
91 return vpe_ctl & GIC_VX_CTL_PERFCNT_ROUTABLE;
92 case GIC_LOCAL_INT_FDC:
93 return vpe_ctl & GIC_VX_CTL_FDC_ROUTABLE;
94 case GIC_LOCAL_INT_SWINT0:
95 case GIC_LOCAL_INT_SWINT1:
96 return vpe_ctl & GIC_VX_CTL_SWINT_ROUTABLE;
102 static void gic_bind_eic_interrupt(int irq, int set)
104 /* Convert irq vector # to hw int # */
105 irq -= GIC_PIN_TO_VEC_OFFSET;
107 /* Set irq to use shadow set */
108 write_gic_vl_eic_shadow_set(irq, set);
111 static void gic_send_ipi(struct irq_data *d, unsigned int cpu)
113 irq_hw_number_t hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(d));
115 write_gic_wedge(GIC_WEDGE_RW | hwirq);
118 int gic_get_c0_compare_int(void)
120 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER))
121 return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
122 return irq_create_mapping(gic_irq_domain,
123 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER));
126 int gic_get_c0_perfcount_int(void)
128 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) {
129 /* Is the performance counter shared with the timer? */
130 if (cp0_perfcount_irq < 0)
132 return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
134 return irq_create_mapping(gic_irq_domain,
135 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR));
138 int gic_get_c0_fdc_int(void)
140 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) {
141 /* Is the FDC IRQ even present? */
144 return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
147 return irq_create_mapping(gic_irq_domain,
148 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));
151 static void gic_handle_shared_int(bool chained)
154 unsigned long *pcpu_mask;
155 DECLARE_BITMAP(pending, GIC_MAX_INTRS);
157 /* Get per-cpu bitmaps */
158 pcpu_mask = this_cpu_ptr(pcpu_masks);
161 __ioread64_copy(pending, addr_gic_pend(),
162 DIV_ROUND_UP(gic_shared_intrs, 64));
164 __ioread32_copy(pending, addr_gic_pend(),
165 DIV_ROUND_UP(gic_shared_intrs, 32));
167 bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs);
169 for_each_set_bit(intr, pending, gic_shared_intrs) {
171 generic_handle_domain_irq(gic_irq_domain,
172 GIC_SHARED_TO_HWIRQ(intr));
174 do_domain_IRQ(gic_irq_domain,
175 GIC_SHARED_TO_HWIRQ(intr));
179 static void gic_mask_irq(struct irq_data *d)
181 unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
183 write_gic_rmask(intr);
184 gic_clear_pcpu_masks(intr);
187 static void gic_unmask_irq(struct irq_data *d)
189 unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
192 write_gic_smask(intr);
194 gic_clear_pcpu_masks(intr);
195 cpu = cpumask_first(irq_data_get_effective_affinity_mask(d));
196 set_bit(intr, per_cpu_ptr(pcpu_masks, cpu));
199 static void gic_ack_irq(struct irq_data *d)
201 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
203 write_gic_wedge(irq);
206 static int gic_set_type(struct irq_data *d, unsigned int type)
208 unsigned int irq, pol, trig, dual;
211 irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
213 spin_lock_irqsave(&gic_lock, flags);
214 switch (type & IRQ_TYPE_SENSE_MASK) {
215 case IRQ_TYPE_EDGE_FALLING:
216 pol = GIC_POL_FALLING_EDGE;
217 trig = GIC_TRIG_EDGE;
218 dual = GIC_DUAL_SINGLE;
220 case IRQ_TYPE_EDGE_RISING:
221 pol = GIC_POL_RISING_EDGE;
222 trig = GIC_TRIG_EDGE;
223 dual = GIC_DUAL_SINGLE;
225 case IRQ_TYPE_EDGE_BOTH:
226 pol = 0; /* Doesn't matter */
227 trig = GIC_TRIG_EDGE;
228 dual = GIC_DUAL_DUAL;
230 case IRQ_TYPE_LEVEL_LOW:
231 pol = GIC_POL_ACTIVE_LOW;
232 trig = GIC_TRIG_LEVEL;
233 dual = GIC_DUAL_SINGLE;
235 case IRQ_TYPE_LEVEL_HIGH:
237 pol = GIC_POL_ACTIVE_HIGH;
238 trig = GIC_TRIG_LEVEL;
239 dual = GIC_DUAL_SINGLE;
243 change_gic_pol(irq, pol);
244 change_gic_trig(irq, trig);
245 change_gic_dual(irq, dual);
247 if (trig == GIC_TRIG_EDGE)
248 irq_set_chip_handler_name_locked(d, &gic_edge_irq_controller,
249 handle_edge_irq, NULL);
251 irq_set_chip_handler_name_locked(d, &gic_level_irq_controller,
252 handle_level_irq, NULL);
253 spin_unlock_irqrestore(&gic_lock, flags);
259 static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
262 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
266 cpu = cpumask_first_and(cpumask, cpu_online_mask);
270 /* Assumption : cpumask refers to a single CPU */
271 spin_lock_irqsave(&gic_lock, flags);
273 /* Re-route this IRQ */
274 write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu)));
276 /* Update the pcpu_masks */
277 gic_clear_pcpu_masks(irq);
278 if (read_gic_mask(irq))
279 set_bit(irq, per_cpu_ptr(pcpu_masks, cpu));
281 irq_data_update_effective_affinity(d, cpumask_of(cpu));
282 spin_unlock_irqrestore(&gic_lock, flags);
284 return IRQ_SET_MASK_OK;
288 static struct irq_chip gic_level_irq_controller = {
290 .irq_mask = gic_mask_irq,
291 .irq_unmask = gic_unmask_irq,
292 .irq_set_type = gic_set_type,
294 .irq_set_affinity = gic_set_affinity,
298 static struct irq_chip gic_edge_irq_controller = {
300 .irq_ack = gic_ack_irq,
301 .irq_mask = gic_mask_irq,
302 .irq_unmask = gic_unmask_irq,
303 .irq_set_type = gic_set_type,
305 .irq_set_affinity = gic_set_affinity,
307 .ipi_send_single = gic_send_ipi,
310 static void gic_handle_local_int(bool chained)
312 unsigned long pending, masked;
315 pending = read_gic_vl_pend();
316 masked = read_gic_vl_mask();
318 bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS);
320 for_each_set_bit(intr, &pending, GIC_NUM_LOCAL_INTRS) {
322 generic_handle_domain_irq(gic_irq_domain,
323 GIC_LOCAL_TO_HWIRQ(intr));
325 do_domain_IRQ(gic_irq_domain,
326 GIC_LOCAL_TO_HWIRQ(intr));
330 static void gic_mask_local_irq(struct irq_data *d)
332 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
334 write_gic_vl_rmask(BIT(intr));
337 static void gic_unmask_local_irq(struct irq_data *d)
339 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
341 write_gic_vl_smask(BIT(intr));
344 static struct irq_chip gic_local_irq_controller = {
345 .name = "MIPS GIC Local",
346 .irq_mask = gic_mask_local_irq,
347 .irq_unmask = gic_unmask_local_irq,
350 static void gic_mask_local_irq_all_vpes(struct irq_data *d)
352 struct gic_all_vpes_chip_data *cd;
356 intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
357 cd = irq_data_get_irq_chip_data(d);
360 spin_lock_irqsave(&gic_lock, flags);
361 for_each_online_cpu(cpu) {
362 write_gic_vl_other(mips_cm_vp_id(cpu));
363 write_gic_vo_rmask(BIT(intr));
365 spin_unlock_irqrestore(&gic_lock, flags);
368 static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
370 struct gic_all_vpes_chip_data *cd;
374 intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
375 cd = irq_data_get_irq_chip_data(d);
378 spin_lock_irqsave(&gic_lock, flags);
379 for_each_online_cpu(cpu) {
380 write_gic_vl_other(mips_cm_vp_id(cpu));
381 write_gic_vo_smask(BIT(intr));
383 spin_unlock_irqrestore(&gic_lock, flags);
386 static void gic_all_vpes_irq_cpu_online(struct irq_data *d)
388 struct gic_all_vpes_chip_data *cd;
391 intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
392 cd = irq_data_get_irq_chip_data(d);
394 write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map);
396 write_gic_vl_smask(BIT(intr));
399 static struct irq_chip gic_all_vpes_local_irq_controller = {
400 .name = "MIPS GIC Local",
401 .irq_mask = gic_mask_local_irq_all_vpes,
402 .irq_unmask = gic_unmask_local_irq_all_vpes,
403 .irq_cpu_online = gic_all_vpes_irq_cpu_online,
406 static void __gic_irq_dispatch(void)
408 gic_handle_local_int(false);
409 gic_handle_shared_int(false);
412 static void gic_irq_dispatch(struct irq_desc *desc)
414 gic_handle_local_int(true);
415 gic_handle_shared_int(true);
418 static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
419 irq_hw_number_t hw, unsigned int cpu)
421 int intr = GIC_HWIRQ_TO_SHARED(hw);
422 struct irq_data *data;
425 data = irq_get_irq_data(virq);
427 spin_lock_irqsave(&gic_lock, flags);
428 write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin);
429 write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu)));
430 irq_data_update_effective_affinity(data, cpumask_of(cpu));
431 spin_unlock_irqrestore(&gic_lock, flags);
436 static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
437 const u32 *intspec, unsigned int intsize,
438 irq_hw_number_t *out_hwirq,
439 unsigned int *out_type)
444 if (intspec[0] == GIC_SHARED)
445 *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]);
446 else if (intspec[0] == GIC_LOCAL)
447 *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]);
450 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
455 static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
456 irq_hw_number_t hwirq)
458 struct gic_all_vpes_chip_data *cd;
464 if (hwirq >= GIC_SHARED_HWIRQ_BASE) {
465 #ifdef CONFIG_GENERIC_IRQ_IPI
466 /* verify that shared irqs don't conflict with an IPI irq */
467 if (test_bit(GIC_HWIRQ_TO_SHARED(hwirq), ipi_resrv))
469 #endif /* CONFIG_GENERIC_IRQ_IPI */
471 err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
472 &gic_level_irq_controller,
477 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
478 return gic_shared_irq_domain_map(d, virq, hwirq, 0);
481 intr = GIC_HWIRQ_TO_LOCAL(hwirq);
482 map = GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin;
485 case GIC_LOCAL_INT_TIMER:
486 /* CONFIG_MIPS_CMP workaround (see __gic_init) */
487 map = GIC_MAP_PIN_MAP_TO_PIN | timer_cpu_pin;
489 case GIC_LOCAL_INT_PERFCTR:
490 case GIC_LOCAL_INT_FDC:
492 * HACK: These are all really percpu interrupts, but
493 * the rest of the MIPS kernel code does not use the
494 * percpu IRQ API for them.
496 cd = &gic_all_vpes_chip_data[intr];
498 err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
499 &gic_all_vpes_local_irq_controller,
504 irq_set_handler(virq, handle_percpu_irq);
508 err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
509 &gic_local_irq_controller,
514 irq_set_handler(virq, handle_percpu_devid_irq);
515 irq_set_percpu_devid(virq);
519 if (!gic_local_irq_is_routable(intr))
522 spin_lock_irqsave(&gic_lock, flags);
523 for_each_online_cpu(cpu) {
524 write_gic_vl_other(mips_cm_vp_id(cpu));
525 write_gic_vo_map(mips_gic_vx_map_reg(intr), map);
527 spin_unlock_irqrestore(&gic_lock, flags);
532 static int gic_irq_domain_alloc(struct irq_domain *d, unsigned int virq,
533 unsigned int nr_irqs, void *arg)
535 struct irq_fwspec *fwspec = arg;
536 irq_hw_number_t hwirq;
538 if (fwspec->param[0] == GIC_SHARED)
539 hwirq = GIC_SHARED_TO_HWIRQ(fwspec->param[1]);
541 hwirq = GIC_LOCAL_TO_HWIRQ(fwspec->param[1]);
543 return gic_irq_domain_map(d, virq, hwirq);
546 void gic_irq_domain_free(struct irq_domain *d, unsigned int virq,
547 unsigned int nr_irqs)
551 static const struct irq_domain_ops gic_irq_domain_ops = {
552 .xlate = gic_irq_domain_xlate,
553 .alloc = gic_irq_domain_alloc,
554 .free = gic_irq_domain_free,
555 .map = gic_irq_domain_map,
558 #ifdef CONFIG_GENERIC_IRQ_IPI
560 static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
561 const u32 *intspec, unsigned int intsize,
562 irq_hw_number_t *out_hwirq,
563 unsigned int *out_type)
566 * There's nothing to translate here. hwirq is dynamically allocated and
567 * the irq type is always edge triggered.
570 *out_type = IRQ_TYPE_EDGE_RISING;
575 static int gic_ipi_domain_alloc(struct irq_domain *d, unsigned int virq,
576 unsigned int nr_irqs, void *arg)
578 struct cpumask *ipimask = arg;
579 irq_hw_number_t hwirq, base_hwirq;
582 base_hwirq = find_first_bit(ipi_available, gic_shared_intrs);
583 if (base_hwirq == gic_shared_intrs)
586 /* check that we have enough space */
587 for (i = base_hwirq; i < nr_irqs; i++) {
588 if (!test_bit(i, ipi_available))
591 bitmap_clear(ipi_available, base_hwirq, nr_irqs);
593 /* map the hwirq for each cpu consecutively */
595 for_each_cpu(cpu, ipimask) {
596 hwirq = GIC_SHARED_TO_HWIRQ(base_hwirq + i);
598 ret = irq_domain_set_hwirq_and_chip(d, virq + i, hwirq,
599 &gic_edge_irq_controller,
604 ret = irq_domain_set_hwirq_and_chip(d->parent, virq + i, hwirq,
605 &gic_edge_irq_controller,
610 ret = irq_set_irq_type(virq + i, IRQ_TYPE_EDGE_RISING);
614 ret = gic_shared_irq_domain_map(d, virq + i, hwirq, cpu);
623 bitmap_set(ipi_available, base_hwirq, nr_irqs);
627 static void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq,
628 unsigned int nr_irqs)
630 irq_hw_number_t base_hwirq;
631 struct irq_data *data;
633 data = irq_get_irq_data(virq);
637 base_hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(data));
638 bitmap_set(ipi_available, base_hwirq, nr_irqs);
641 static int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node,
642 enum irq_domain_bus_token bus_token)
648 is_ipi = d->bus_token == bus_token;
649 return (!node || to_of_node(d->fwnode) == node) && is_ipi;
656 static const struct irq_domain_ops gic_ipi_domain_ops = {
657 .xlate = gic_ipi_domain_xlate,
658 .alloc = gic_ipi_domain_alloc,
659 .free = gic_ipi_domain_free,
660 .match = gic_ipi_domain_match,
663 static int gic_register_ipi_domain(struct device_node *node)
665 struct irq_domain *gic_ipi_domain;
666 unsigned int v[2], num_ipis;
668 gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain,
669 IRQ_DOMAIN_FLAG_IPI_PER_CPU,
670 GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
671 node, &gic_ipi_domain_ops, NULL);
672 if (!gic_ipi_domain) {
673 pr_err("Failed to add IPI domain");
677 irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI);
680 !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
681 bitmap_set(ipi_resrv, v[0], v[1]);
684 * Reserve 2 interrupts per possible CPU/VP for use as IPIs,
685 * meeting the requirements of arch/mips SMP.
687 num_ipis = 2 * num_possible_cpus();
688 bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis);
691 bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS);
696 #else /* !CONFIG_GENERIC_IRQ_IPI */
698 static inline int gic_register_ipi_domain(struct device_node *node)
703 #endif /* !CONFIG_GENERIC_IRQ_IPI */
705 static int gic_cpu_startup(unsigned int cpu)
707 /* Enable or disable EIC */
708 change_gic_vl_ctl(GIC_VX_CTL_EIC,
709 cpu_has_veic ? GIC_VX_CTL_EIC : 0);
711 /* Clear all local IRQ masks (ie. disable all local interrupts) */
712 write_gic_vl_rmask(~0);
714 /* Invoke irq_cpu_online callbacks to enable desired interrupts */
720 static int __init gic_of_init(struct device_node *node,
721 struct device_node *parent)
723 unsigned int cpu_vec, i, gicconfig;
724 unsigned long reserved;
725 phys_addr_t gic_base;
730 /* Find the first available CPU vector. */
732 reserved = (C_SW0 | C_SW1) >> __ffs(C_SW0);
733 while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",
735 reserved |= BIT(cpu_vec);
737 cpu_vec = find_first_zero_bit(&reserved, hweight_long(ST0_IM));
738 if (cpu_vec == hweight_long(ST0_IM)) {
739 pr_err("No CPU vectors available\n");
743 if (of_address_to_resource(node, 0, &res)) {
745 * Probe the CM for the GIC base address if not specified
746 * in the device-tree.
748 if (mips_cm_present()) {
749 gic_base = read_gcr_gic_base() &
750 ~CM_GCR_GIC_BASE_GICEN;
752 pr_warn("Using inherited base address %pa\n",
755 pr_err("Failed to get memory range\n");
759 gic_base = res.start;
760 gic_len = resource_size(&res);
763 if (mips_cm_present()) {
764 write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN);
765 /* Ensure GIC region is enabled before trying to access it */
769 mips_gic_base = ioremap(gic_base, gic_len);
770 if (!mips_gic_base) {
771 pr_err("Failed to ioremap gic_base\n");
775 gicconfig = read_gic_config();
776 gic_shared_intrs = gicconfig & GIC_CONFIG_NUMINTERRUPTS;
777 gic_shared_intrs >>= __ffs(GIC_CONFIG_NUMINTERRUPTS);
778 gic_shared_intrs = (gic_shared_intrs + 1) * 8;
781 /* Always use vector 1 in EIC mode */
783 timer_cpu_pin = gic_cpu_pin;
784 set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET,
787 gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;
788 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec,
791 * With the CMP implementation of SMP (deprecated), other CPUs
792 * are started by the bootloader and put into a timer based
793 * waiting poll loop. We must not re-route those CPU's local
794 * timer interrupts as the wait instruction will never finish,
795 * so just handle whatever CPU interrupt it is routed to by
798 * This workaround should be removed when CMP support is
801 if (IS_ENABLED(CONFIG_MIPS_CMP) &&
802 gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) {
803 timer_cpu_pin = read_gic_vl_timer_map() & GIC_MAP_PIN_MAP;
804 irq_set_chained_handler(MIPS_CPU_IRQ_BASE +
809 timer_cpu_pin = gic_cpu_pin;
813 gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS +
815 &gic_irq_domain_ops, NULL);
816 if (!gic_irq_domain) {
817 pr_err("Failed to add IRQ domain");
821 ret = gic_register_ipi_domain(node);
825 board_bind_eic_interrupt = &gic_bind_eic_interrupt;
828 for (i = 0; i < gic_shared_intrs; i++) {
829 change_gic_pol(i, GIC_POL_ACTIVE_HIGH);
830 change_gic_trig(i, GIC_TRIG_LEVEL);
834 return cpuhp_setup_state(CPUHP_AP_IRQ_MIPS_GIC_STARTING,
835 "irqchip/mips/gic:starting",
836 gic_cpu_startup, NULL);
838 IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init);