drivers/irqchip/irq-gic-v3.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
   4  * Author: Marc Zyngier <marc.zyngier@arm.com>
   5  */
   6
   7 #define pr_fmt(fmt)     "GICv3: " fmt
   8
   9 #include <linux/acpi.h>
  10 #include <linux/cpu.h>
  11 #include <linux/cpu_pm.h>
  12 #include <linux/delay.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irqdomain.h>
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_irq.h>
  18 #include <linux/percpu.h>
  19 #include <linux/refcount.h>
  20 #include <linux/slab.h>
  21
  22 #include <linux/irqchip.h>
  23 #include <linux/irqchip/arm-gic-common.h>
  24 #include <linux/irqchip/arm-gic-v3.h>
  25 #include <linux/irqchip/irq-partition-percpu.h>
  26
  27 #include <asm/cputype.h>
  28 #include <asm/exception.h>
  29 #include <asm/smp_plat.h>
  30 #include <asm/virt.h>
  31
  32 #include "irq-gic-common.h"
  33
  34 #define GICD_INT_NMI_PRI        (GICD_INT_DEF_PRI & ~0x80)
  35
  36 #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996     (1ULL << 0)
  37 #define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539   (1ULL << 1)
  38
  39 #define GIC_IRQ_TYPE_PARTITION  (GIC_IRQ_TYPE_LPI + 1)
  40
  41 struct redist_region {
  42         void __iomem            *redist_base;
  43         phys_addr_t             phys_base;
  44         bool                    single_redist;
  45 };
  46
  47 struct gic_chip_data {
  48         struct fwnode_handle    *fwnode;
  49         void __iomem            *dist_base;
  50         struct redist_region    *redist_regions;
  51         struct rdists           rdists;
  52         struct irq_domain       *domain;
  53         u64                     redist_stride;
  54         u32                     nr_redist_regions;
  55         u64                     flags;
  56         bool                    has_rss;
  57         unsigned int            ppi_nr;
  58         struct partition_desc   **ppi_descs;
  59 };
  60
  61 static struct gic_chip_data gic_data __read_mostly;
  62 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
  63
  64 #define GIC_ID_NR       (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer))
  65 #define GIC_LINE_NR     min(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U)
  66 #define GIC_ESPI_NR     GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer)
  67
  68 /*
  69  * The behaviours of RPR and PMR registers differ depending on the value of
  70  * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
  71  * distributor and redistributors depends on whether security is enabled in the
  72  * GIC.
  73  *
  74  * When security is enabled, non-secure priority values from the (re)distributor
  75  * are presented to the GIC CPUIF as follow:
  76  *     (GIC_(R)DIST_PRI[irq] >> 1) | 0x80;
  77  *
  78  * If SCR_EL3.FIQ == 1, the values written to/read from PMR and RPR at non-secure
  79  * EL1 are subject to a similar operation thus matching the priorities presented
  80  * from the (re)distributor when security is enabled. When SCR_EL3.FIQ == 0,
  81  * these values are unchanged by the GIC.
  82  *
  83  * see GICv3/GICv4 Architecture Specification (IHI0069D):
  84  * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
  85  *   priorities.
  86  * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1
  87  *   interrupt.
  88  */
  89 static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis);
  90
  91 /*
  92  * Global static key controlling whether an update to PMR allowing more
  93  * interrupts requires to be propagated to the redistributor (DSB SY).
  94  * And this needs to be exported for modules to be able to enable
  95  * interrupts...
  96  */
  97 DEFINE_STATIC_KEY_FALSE(gic_pmr_sync);
  98 EXPORT_SYMBOL(gic_pmr_sync);
  99
 100 DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities);
 101 EXPORT_SYMBOL(gic_nonsecure_priorities);
 102
 103 /*
 104  * When the Non-secure world has access to group 0 interrupts (as a
 105  * consequence of SCR_EL3.FIQ == 0), reading the ICC_RPR_EL1 register will
 106  * return the Distributor's view of the interrupt priority.
 107  *
 108  * When GIC security is enabled (GICD_CTLR.DS == 0), the interrupt priority
 109  * written by software is moved to the Non-secure range by the Distributor.
 110  *
 111  * If both are true (which is when gic_nonsecure_priorities gets enabled),
 112  * we need to shift down the priority programmed by software to match it
 113  * against the value returned by ICC_RPR_EL1.
 114  */
 115 #define GICD_INT_RPR_PRI(priority)                                      \
 116         ({                                                              \
 117                 u32 __priority = (priority);                            \
 118                 if (static_branch_unlikely(&gic_nonsecure_priorities))  \
 119                         __priority = 0x80 | (__priority >> 1);          \
 120                                                                         \
 121                 __priority;                                             \
 122         })
 123
 124 /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */
 125 static refcount_t *ppi_nmi_refs;
 126
 127 static struct gic_kvm_info gic_v3_kvm_info __initdata;
 128 static DEFINE_PER_CPU(bool, has_rss);
 129
 130 #define MPIDR_RS(mpidr)                 (((mpidr) & 0xF0UL) >> 4)
 131 #define gic_data_rdist()                (this_cpu_ptr(gic_data.rdists.rdist))
 132 #define gic_data_rdist_rd_base()        (gic_data_rdist()->rd_base)
 133 #define gic_data_rdist_sgi_base()       (gic_data_rdist_rd_base() + SZ_64K)
 134
 135 /* Our default, arbitrary priority value. Linux only uses one anyway. */
 136 #define DEFAULT_PMR_VALUE       0xf0
 137
 138 enum gic_intid_range {
 139         SGI_RANGE,
 140         PPI_RANGE,
 141         SPI_RANGE,
 142         EPPI_RANGE,
 143         ESPI_RANGE,
 144         LPI_RANGE,
 145         __INVALID_RANGE__
 146 };
 147
 148 static enum gic_intid_range __get_intid_range(irq_hw_number_t hwirq)
 149 {
 150         switch (hwirq) {
 151         case 0 ... 15:
 152                 return SGI_RANGE;
 153         case 16 ... 31:
 154                 return PPI_RANGE;
 155         case 32 ... 1019:
 156                 return SPI_RANGE;
 157         case EPPI_BASE_INTID ... (EPPI_BASE_INTID + 63):
 158                 return EPPI_RANGE;
 159         case ESPI_BASE_INTID ... (ESPI_BASE_INTID + 1023):
 160                 return ESPI_RANGE;
 161         case 8192 ... GENMASK(23, 0):
 162                 return LPI_RANGE;
 163         default:
 164                 return __INVALID_RANGE__;
 165         }
 166 }
 167
 168 static enum gic_intid_range get_intid_range(struct irq_data *d)
 169 {
 170         return __get_intid_range(d->hwirq);
 171 }
 172
 173 static inline unsigned int gic_irq(struct irq_data *d)
 174 {
 175         return d->hwirq;
 176 }
 177
 178 static inline bool gic_irq_in_rdist(struct irq_data *d)
 179 {
 180         switch (get_intid_range(d)) {
 181         case SGI_RANGE:
 182         case PPI_RANGE:
 183         case EPPI_RANGE:
 184                 return true;
 185         default:
 186                 return false;
 187         }
 188 }
 189
 190 static inline void __iomem *gic_dist_base(struct irq_data *d)
 191 {
 192         switch (get_intid_range(d)) {
 193         case SGI_RANGE:
 194         case PPI_RANGE:
 195         case EPPI_RANGE:
 196                 /* SGI+PPI -> SGI_base for this CPU */
 197                 return gic_data_rdist_sgi_base();
 198
 199         case SPI_RANGE:
 200         case ESPI_RANGE:
 201                 /* SPI -> dist_base */
 202                 return gic_data.dist_base;
 203
 204         default:
 205                 return NULL;
 206         }
 207 }
 208
 209 static void gic_do_wait_for_rwp(void __iomem *base, u32 bit)
 210 {
 211         u32 count = 1000000;    /* 1s! */
 212
 213         while (readl_relaxed(base + GICD_CTLR) & bit) {
 214                 count--;
 215                 if (!count) {
 216                         pr_err_ratelimited("RWP timeout, gone fishing\n");
 217                         return;
 218                 }
 219                 cpu_relax();
 220                 udelay(1);
 221         }
 222 }
 223
 224 /* Wait for completion of a distributor change */
 225 static void gic_dist_wait_for_rwp(void)
 226 {
 227         gic_do_wait_for_rwp(gic_data.dist_base, GICD_CTLR_RWP);
 228 }
 229
 230 /* Wait for completion of a redistributor change */
 231 static void gic_redist_wait_for_rwp(void)
 232 {
 233         gic_do_wait_for_rwp(gic_data_rdist_rd_base(), GICR_CTLR_RWP);
 234 }
 235
 236 #ifdef CONFIG_ARM64
 237
 238 static u64 __maybe_unused gic_read_iar(void)
 239 {
 240         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154))
 241                 return gic_read_iar_cavium_thunderx();
 242         else
 243                 return gic_read_iar_common();
 244 }
 245 #endif
 246
 247 static void gic_enable_redist(bool enable)
 248 {
 249         void __iomem *rbase;
 250         u32 count = 1000000;    /* 1s! */
 251         u32 val;
 252
 253         if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996)
 254                 return;
 255
 256         rbase = gic_data_rdist_rd_base();
 257
 258         val = readl_relaxed(rbase + GICR_WAKER);
 259         if (enable)
 260                 /* Wake up this CPU redistributor */
 261                 val &= ~GICR_WAKER_ProcessorSleep;
 262         else
 263                 val |= GICR_WAKER_ProcessorSleep;
 264         writel_relaxed(val, rbase + GICR_WAKER);
 265
 266         if (!enable) {          /* Check that GICR_WAKER is writeable */
 267                 val = readl_relaxed(rbase + GICR_WAKER);
 268                 if (!(val & GICR_WAKER_ProcessorSleep))
 269                         return; /* No PM support in this redistributor */
 270         }
 271
 272         while (--count) {
 273                 val = readl_relaxed(rbase + GICR_WAKER);
 274                 if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep))
 275                         break;
 276                 cpu_relax();
 277                 udelay(1);
 278         }
 279         if (!count)
 280                 pr_err_ratelimited("redistributor failed to %s...\n",
 281                                    enable ? "wakeup" : "sleep");
 282 }
 283
 284 /*
 285  * Routines to disable, enable, EOI and route interrupts
 286  */
 287 static u32 convert_offset_index(struct irq_data *d, u32 offset, u32 *index)
 288 {
 289         switch (get_intid_range(d)) {
 290         case SGI_RANGE:
 291         case PPI_RANGE:
 292         case SPI_RANGE:
 293                 *index = d->hwirq;
 294                 return offset;
 295         case EPPI_RANGE:
 296                 /*
 297                  * Contrary to the ESPI range, the EPPI range is contiguous
 298                  * to the PPI range in the registers, so let's adjust the
 299                  * displacement accordingly. Consistency is overrated.
 300                  */
 301                 *index = d->hwirq - EPPI_BASE_INTID + 32;
 302                 return offset;
 303         case ESPI_RANGE:
 304                 *index = d->hwirq - ESPI_BASE_INTID;
 305                 switch (offset) {
 306                 case GICD_ISENABLER:
 307                         return GICD_ISENABLERnE;
 308                 case GICD_ICENABLER:
 309                         return GICD_ICENABLERnE;
 310                 case GICD_ISPENDR:
 311                         return GICD_ISPENDRnE;
 312                 case GICD_ICPENDR:
 313                         return GICD_ICPENDRnE;
 314                 case GICD_ISACTIVER:
 315                         return GICD_ISACTIVERnE;
 316                 case GICD_ICACTIVER:
 317                         return GICD_ICACTIVERnE;
 318                 case GICD_IPRIORITYR:
 319                         return GICD_IPRIORITYRnE;
 320                 case GICD_ICFGR:
 321                         return GICD_ICFGRnE;
 322                 case GICD_IROUTER:
 323                         return GICD_IROUTERnE;
 324                 default:
 325                         break;
 326                 }
 327                 break;
 328         default:
 329                 break;
 330         }
 331
 332         WARN_ON(1);
 333         *index = d->hwirq;
 334         return offset;
 335 }
 336
 337 static int gic_peek_irq(struct irq_data *d, u32 offset)
 338 {
 339         void __iomem *base;
 340         u32 index, mask;
 341
 342         offset = convert_offset_index(d, offset, &index);
 343         mask = 1 << (index % 32);
 344
 345         if (gic_irq_in_rdist(d))
 346                 base = gic_data_rdist_sgi_base();
 347         else
 348                 base = gic_data.dist_base;
 349
 350         return !!(readl_relaxed(base + offset + (index / 32) * 4) & mask);
 351 }
 352
 353 static void gic_poke_irq(struct irq_data *d, u32 offset)
 354 {
 355         void (*rwp_wait)(void);
 356         void __iomem *base;
 357         u32 index, mask;
 358
 359         offset = convert_offset_index(d, offset, &index);
 360         mask = 1 << (index % 32);
 361
 362         if (gic_irq_in_rdist(d)) {
 363                 base = gic_data_rdist_sgi_base();
 364                 rwp_wait = gic_redist_wait_for_rwp;
 365         } else {
 366                 base = gic_data.dist_base;
 367                 rwp_wait = gic_dist_wait_for_rwp;
 368         }
 369
 370         writel_relaxed(mask, base + offset + (index / 32) * 4);
 371         rwp_wait();
 372 }
 373
 374 static void gic_mask_irq(struct irq_data *d)
 375 {
 376         gic_poke_irq(d, GICD_ICENABLER);
 377 }
 378
 379 static void gic_eoimode1_mask_irq(struct irq_data *d)
 380 {
 381         gic_mask_irq(d);
 382         /*
 383          * When masking a forwarded interrupt, make sure it is
 384          * deactivated as well.
 385          *
 386          * This ensures that an interrupt that is getting
 387          * disabled/masked will not get "stuck", because there is
 388          * noone to deactivate it (guest is being terminated).
 389          */
 390         if (irqd_is_forwarded_to_vcpu(d))
 391                 gic_poke_irq(d, GICD_ICACTIVER);
 392 }
 393
 394 static void gic_unmask_irq(struct irq_data *d)
 395 {
 396         gic_poke_irq(d, GICD_ISENABLER);
 397 }
 398
 399 static inline bool gic_supports_nmi(void)
 400 {
 401         return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) &&
 402                static_branch_likely(&supports_pseudo_nmis);
 403 }
 404
 405 static int gic_irq_set_irqchip_state(struct irq_data *d,
 406                                      enum irqchip_irq_state which, bool val)
 407 {
 408         u32 reg;
 409
 410         if (d->hwirq >= 8192) /* SGI/PPI/SPI only */
 411                 return -EINVAL;
 412
 413         switch (which) {
 414         case IRQCHIP_STATE_PENDING:
 415                 reg = val ? GICD_ISPENDR : GICD_ICPENDR;
 416                 break;
 417
 418         case IRQCHIP_STATE_ACTIVE:
 419                 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;
 420                 break;
 421
 422         case IRQCHIP_STATE_MASKED:
 423                 reg = val ? GICD_ICENABLER : GICD_ISENABLER;
 424                 break;
 425
 426         default:
 427                 return -EINVAL;
 428         }
 429
 430         gic_poke_irq(d, reg);
 431         return 0;
 432 }
 433
 434 static int gic_irq_get_irqchip_state(struct irq_data *d,
 435                                      enum irqchip_irq_state which, bool *val)
 436 {
 437         if (d->hwirq >= 8192) /* PPI/SPI only */
 438                 return -EINVAL;
 439
 440         switch (which) {
 441         case IRQCHIP_STATE_PENDING:
 442                 *val = gic_peek_irq(d, GICD_ISPENDR);
 443                 break;
 444
 445         case IRQCHIP_STATE_ACTIVE:
 446                 *val = gic_peek_irq(d, GICD_ISACTIVER);
 447                 break;
 448
 449         case IRQCHIP_STATE_MASKED:
 450                 *val = !gic_peek_irq(d, GICD_ISENABLER);
 451                 break;
 452
 453         default:
 454                 return -EINVAL;
 455         }
 456
 457         return 0;
 458 }
 459
 460 static void gic_irq_set_prio(struct irq_data *d, u8 prio)
 461 {
 462         void __iomem *base = gic_dist_base(d);
 463         u32 offset, index;
 464
 465         offset = convert_offset_index(d, GICD_IPRIORITYR, &index);
 466
 467         writeb_relaxed(prio, base + offset + index);
 468 }
 469
 470 static u32 __gic_get_ppi_index(irq_hw_number_t hwirq)
 471 {
 472         switch (__get_intid_range(hwirq)) {
 473         case PPI_RANGE:
 474                 return hwirq - 16;
 475         case EPPI_RANGE:
 476                 return hwirq - EPPI_BASE_INTID + 16;
 477         default:
 478                 unreachable();
 479         }
 480 }
 481
 482 static u32 gic_get_ppi_index(struct irq_data *d)
 483 {
 484         return __gic_get_ppi_index(d->hwirq);
 485 }
 486
 487 static int gic_irq_nmi_setup(struct irq_data *d)
 488 {
 489         struct irq_desc *desc = irq_to_desc(d->irq);
 490
 491         if (!gic_supports_nmi())
 492                 return -EINVAL;
 493
 494         if (gic_peek_irq(d, GICD_ISENABLER)) {
 495                 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);
 496                 return -EINVAL;
 497         }
 498
 499         /*
 500          * A secondary irq_chip should be in charge of LPI request,
 501          * it should not be possible to get there
 502          */
 503         if (WARN_ON(gic_irq(d) >= 8192))
 504                 return -EINVAL;
 505
 506         /* desc lock should already be held */
 507         if (gic_irq_in_rdist(d)) {
 508                 u32 idx = gic_get_ppi_index(d);
 509
 510                 /* Setting up PPI as NMI, only switch handler for first NMI */
 511                 if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) {
 512                         refcount_set(&ppi_nmi_refs[idx], 1);
 513                         desc->handle_irq = handle_percpu_devid_fasteoi_nmi;
 514                 }
 515         } else {
 516                 desc->handle_irq = handle_fasteoi_nmi;
 517         }
 518
 519         gic_irq_set_prio(d, GICD_INT_NMI_PRI);
 520
 521         return 0;
 522 }
 523
 524 static void gic_irq_nmi_teardown(struct irq_data *d)
 525 {
 526         struct irq_desc *desc = irq_to_desc(d->irq);
 527
 528         if (WARN_ON(!gic_supports_nmi()))
 529                 return;
 530
 531         if (gic_peek_irq(d, GICD_ISENABLER)) {
 532                 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);
 533                 return;
 534         }
 535
 536         /*
 537          * A secondary irq_chip should be in charge of LPI request,
 538          * it should not be possible to get there
 539          */
 540         if (WARN_ON(gic_irq(d) >= 8192))
 541                 return;
 542
 543         /* desc lock should already be held */
 544         if (gic_irq_in_rdist(d)) {
 545                 u32 idx = gic_get_ppi_index(d);
 546
 547                 /* Tearing down NMI, only switch handler for last NMI */
 548                 if (refcount_dec_and_test(&ppi_nmi_refs[idx]))
 549                         desc->handle_irq = handle_percpu_devid_irq;
 550         } else {
 551                 desc->handle_irq = handle_fasteoi_irq;
 552         }
 553
 554         gic_irq_set_prio(d, GICD_INT_DEF_PRI);
 555 }
 556
 557 static void gic_eoi_irq(struct irq_data *d)
 558 {
 559         write_gicreg(gic_irq(d), ICC_EOIR1_EL1);
 560         isb();
 561 }
 562
 563 static void gic_eoimode1_eoi_irq(struct irq_data *d)
 564 {
 565         /*
 566          * No need to deactivate an LPI, or an interrupt that
 567          * is is getting forwarded to a vcpu.
 568          */
 569         if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
 570                 return;
 571         gic_write_dir(gic_irq(d));
 572 }
 573
 574 static int gic_set_type(struct irq_data *d, unsigned int type)
 575 {
 576         enum gic_intid_range range;
 577         unsigned int irq = gic_irq(d);
 578         void (*rwp_wait)(void);
 579         void __iomem *base;
 580         u32 offset, index;
 581         int ret;
 582
 583         range = get_intid_range(d);
 584
 585         /* Interrupt configuration for SGIs can't be changed */
 586         if (range == SGI_RANGE)
 587                 return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0;
 588
 589         /* SPIs have restrictions on the supported types */
 590         if ((range == SPI_RANGE || range == ESPI_RANGE) &&
 591             type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
 592                 return -EINVAL;
 593
 594         if (gic_irq_in_rdist(d)) {
 595                 base = gic_data_rdist_sgi_base();
 596                 rwp_wait = gic_redist_wait_for_rwp;
 597         } else {
 598                 base = gic_data.dist_base;
 599                 rwp_wait = gic_dist_wait_for_rwp;
 600         }
 601
 602         offset = convert_offset_index(d, GICD_ICFGR, &index);
 603
 604         ret = gic_configure_irq(index, type, base + offset, rwp_wait);
 605         if (ret && (range == PPI_RANGE || range == EPPI_RANGE)) {
 606                 /* Misconfigured PPIs are usually not fatal */
 607                 pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq);
 608                 ret = 0;
 609         }
 610
 611         return ret;
 612 }
 613
 614 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
 615 {
 616         if (get_intid_range(d) == SGI_RANGE)
 617                 return -EINVAL;
 618
 619         if (vcpu)
 620                 irqd_set_forwarded_to_vcpu(d);
 621         else
 622                 irqd_clr_forwarded_to_vcpu(d);
 623         return 0;
 624 }
 625
 626 static u64 gic_mpidr_to_affinity(unsigned long mpidr)
 627 {
 628         u64 aff;
 629
 630         aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
 631                MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
 632                MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8  |
 633                MPIDR_AFFINITY_LEVEL(mpidr, 0));
 634
 635         return aff;
 636 }
 637
 638 static void gic_deactivate_unhandled(u32 irqnr)
 639 {
 640         if (static_branch_likely(&supports_deactivate_key)) {
 641                 if (irqnr < 8192)
 642                         gic_write_dir(irqnr);
 643         } else {
 644                 write_gicreg(irqnr, ICC_EOIR1_EL1);
 645                 isb();
 646         }
 647 }
 648
 649 /*
 650  * Follow a read of the IAR with any HW maintenance that needs to happen prior
 651  * to invoking the relevant IRQ handler. We must do two things:
 652  *
 653  * (1) Ensure instruction ordering between a read of IAR and subsequent
 654  *     instructions in the IRQ handler using an ISB.
 655  *
 656  *     It is possible for the IAR to report an IRQ which was signalled *after*
 657  *     the CPU took an IRQ exception as multiple interrupts can race to be
 658  *     recognized by the GIC, earlier interrupts could be withdrawn, and/or
 659  *     later interrupts could be prioritized by the GIC.
 660  *
 661  *     For devices which are tightly coupled to the CPU, such as PMUs, a
 662  *     context synchronization event is necessary to ensure that system
 663  *     register state is not stale, as these may have been indirectly written
 664  *     *after* exception entry.
 665  *
 666  * (2) Deactivate the interrupt when EOI mode 1 is in use.
 667  */
 668 static inline void gic_complete_ack(u32 irqnr)
 669 {
 670         if (static_branch_likely(&supports_deactivate_key))
 671                 write_gicreg(irqnr, ICC_EOIR1_EL1);
 672
 673         isb();
 674 }
 675
 676 static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs)
 677 {
 678         bool irqs_enabled = interrupts_enabled(regs);
 679         int err;
 680
 681         if (irqs_enabled)
 682                 nmi_enter();
 683
 684         gic_complete_ack(irqnr);
 685
 686         /*
 687          * Leave the PSR.I bit set to prevent other NMIs to be
 688          * received while handling this one.
 689          * PSR.I will be restored when we ERET to the
 690          * interrupted context.
 691          */
 692         err = handle_domain_nmi(gic_data.domain, irqnr, regs);
 693         if (err)
 694                 gic_deactivate_unhandled(irqnr);
 695
 696         if (irqs_enabled)
 697                 nmi_exit();
 698 }
 699
 700 static u32 do_read_iar(struct pt_regs *regs)
 701 {
 702         u32 iar;
 703
 704         if (gic_supports_nmi() && unlikely(!interrupts_enabled(regs))) {
 705                 u64 pmr;
 706
 707                 /*
 708                  * We were in a context with IRQs disabled. However, the
 709                  * entry code has set PMR to a value that allows any
 710                  * interrupt to be acknowledged, and not just NMIs. This can
 711                  * lead to surprising effects if the NMI has been retired in
 712                  * the meantime, and that there is an IRQ pending. The IRQ
 713                  * would then be taken in NMI context, something that nobody
 714                  * wants to debug twice.
 715                  *
 716                  * Until we sort this, drop PMR again to a level that will
 717                  * actually only allow NMIs before reading IAR, and then
 718                  * restore it to what it was.
 719                  */
 720                 pmr = gic_read_pmr();
 721                 gic_pmr_mask_irqs();
 722                 isb();
 723
 724                 iar = gic_read_iar();
 725
 726                 gic_write_pmr(pmr);
 727         } else {
 728                 iar = gic_read_iar();
 729         }
 730
 731         return iar;
 732 }
 733
 734 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
 735 {
 736         u32 irqnr;
 737
 738         irqnr = do_read_iar(regs);
 739
 740         /* Check for special IDs first */
 741         if ((irqnr >= 1020 && irqnr <= 1023))
 742                 return;
 743
 744         if (gic_supports_nmi() &&
 745             unlikely(gic_read_rpr() == GICD_INT_RPR_PRI(GICD_INT_NMI_PRI))) {
 746                 gic_handle_nmi(irqnr, regs);
 747                 return;
 748         }
 749
 750         if (gic_prio_masking_enabled()) {
 751                 gic_pmr_mask_irqs();
 752                 gic_arch_enable_irqs();
 753         }
 754
 755         gic_complete_ack(irqnr);
 756
 757         if (handle_domain_irq(gic_data.domain, irqnr, regs)) {
 758                 WARN_ONCE(true, "Unexpected interrupt received!\n");
 759                 gic_deactivate_unhandled(irqnr);
 760         }
 761 }
 762
 763 static u32 gic_get_pribits(void)
 764 {
 765         u32 pribits;
 766
 767         pribits = gic_read_ctlr();
 768         pribits &= ICC_CTLR_EL1_PRI_BITS_MASK;
 769         pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT;
 770         pribits++;
 771
 772         return pribits;
 773 }
 774
 775 static bool gic_has_group0(void)
 776 {
 777         u32 val;
 778         u32 old_pmr;
 779
 780         old_pmr = gic_read_pmr();
 781
 782         /*
 783          * Let's find out if Group0 is under control of EL3 or not by
 784          * setting the highest possible, non-zero priority in PMR.
 785          *
 786          * If SCR_EL3.FIQ is set, the priority gets shifted down in
 787          * order for the CPU interface to set bit 7, and keep the
 788          * actual priority in the non-secure range. In the process, it
 789          * looses the least significant bit and the actual priority
 790          * becomes 0x80. Reading it back returns 0, indicating that
 791          * we're don't have access to Group0.
 792          */
 793         gic_write_pmr(BIT(8 - gic_get_pribits()));
 794         val = gic_read_pmr();
 795
 796         gic_write_pmr(old_pmr);
 797
 798         return val != 0;
 799 }
 800
 801 static void __init gic_dist_init(void)
 802 {
 803         unsigned int i;
 804         u64 affinity;
 805         void __iomem *base = gic_data.dist_base;
 806         u32 val;
 807
 808         /* Disable the distributor */
 809         writel_relaxed(0, base + GICD_CTLR);
 810         gic_dist_wait_for_rwp();
 811
 812         /*
 813          * Configure SPIs as non-secure Group-1. This will only matter
 814          * if the GIC only has a single security state. This will not
 815          * do the right thing if the kernel is running in secure mode,
 816          * but that's not the intended use case anyway.
 817          */
 818         for (i = 32; i < GIC_LINE_NR; i += 32)
 819                 writel_relaxed(~0, base + GICD_IGROUPR + i / 8);
 820
 821         /* Extended SPI range, not handled by the GICv2/GICv3 common code */
 822         for (i = 0; i < GIC_ESPI_NR; i += 32) {
 823                 writel_relaxed(~0U, base + GICD_ICENABLERnE + i / 8);
 824                 writel_relaxed(~0U, base + GICD_ICACTIVERnE + i / 8);
 825         }
 826
 827         for (i = 0; i < GIC_ESPI_NR; i += 32)
 828                 writel_relaxed(~0U, base + GICD_IGROUPRnE + i / 8);
 829
 830         for (i = 0; i < GIC_ESPI_NR; i += 16)
 831                 writel_relaxed(0, base + GICD_ICFGRnE + i / 4);
 832
 833         for (i = 0; i < GIC_ESPI_NR; i += 4)
 834                 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i);
 835
 836         /* Now do the common stuff, and wait for the distributor to drain */
 837         gic_dist_config(base, GIC_LINE_NR, gic_dist_wait_for_rwp);
 838
 839         val = GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1;
 840         if (gic_data.rdists.gicd_typer2 & GICD_TYPER2_nASSGIcap) {
 841                 pr_info("Enabling SGIs without active state\n");
 842                 val |= GICD_CTLR_nASSGIreq;
 843         }
 844
 845         /* Enable distributor with ARE, Group1 */
 846         writel_relaxed(val, base + GICD_CTLR);
 847
 848         /*
 849          * Set all global interrupts to the boot CPU only. ARE must be
 850          * enabled.
 851          */
 852         affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
 853         for (i = 32; i < GIC_LINE_NR; i++)
 854                 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8);
 855
 856         for (i = 0; i < GIC_ESPI_NR; i++)
 857                 gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 8);
 858 }
 859
 860 static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *))
 861 {
 862         int ret = -ENODEV;
 863         int i;
 864
 865         for (i = 0; i < gic_data.nr_redist_regions; i++) {
 866                 void __iomem *ptr = gic_data.redist_regions[i].redist_base;
 867                 u64 typer;
 868                 u32 reg;
 869
 870                 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
 871                 if (reg != GIC_PIDR2_ARCH_GICv3 &&
 872                     reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
 873                         pr_warn("No redistributor present @%p\n", ptr);
 874                         break;
 875                 }
 876
 877                 do {
 878                         typer = gic_read_typer(ptr + GICR_TYPER);
 879                         ret = fn(gic_data.redist_regions + i, ptr);
 880                         if (!ret)
 881                                 return 0;
 882
 883                         if (gic_data.redist_regions[i].single_redist)
 884                                 break;
 885
 886                         if (gic_data.redist_stride) {
 887                                 ptr += gic_data.redist_stride;
 888                         } else {
 889                                 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
 890                                 if (typer & GICR_TYPER_VLPIS)
 891                                         ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
 892                         }
 893                 } while (!(typer & GICR_TYPER_LAST));
 894         }
 895
 896         return ret ? -ENODEV : 0;
 897 }
 898
 899 static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr)
 900 {
 901         unsigned long mpidr = cpu_logical_map(smp_processor_id());
 902         u64 typer;
 903         u32 aff;
 904
 905         /*
 906          * Convert affinity to a 32bit value that can be matched to
 907          * GICR_TYPER bits [63:32].
 908          */
 909         aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
 910                MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
 911                MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
 912                MPIDR_AFFINITY_LEVEL(mpidr, 0));
 913
 914         typer = gic_read_typer(ptr + GICR_TYPER);
 915         if ((typer >> 32) == aff) {
 916                 u64 offset = ptr - region->redist_base;
 917                 raw_spin_lock_init(&gic_data_rdist()->rd_lock);
 918                 gic_data_rdist_rd_base() = ptr;
 919                 gic_data_rdist()->phys_base = region->phys_base + offset;
 920
 921                 pr_info("CPU%d: found redistributor %lx region %d:%pa\n",
 922                         smp_processor_id(), mpidr,
 923                         (int)(region - gic_data.redist_regions),
 924                         &gic_data_rdist()->phys_base);
 925                 return 0;
 926         }
 927
 928         /* Try next one */
 929         return 1;
 930 }
 931
 932 static int gic_populate_rdist(void)
 933 {
 934         if (gic_iterate_rdists(__gic_populate_rdist) == 0)
 935                 return 0;
 936
 937         /* We couldn't even deal with ourselves... */
 938         WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n",
 939              smp_processor_id(),
 940              (unsigned long)cpu_logical_map(smp_processor_id()));
 941         return -ENODEV;
 942 }
 943
 944 static int __gic_update_rdist_properties(struct redist_region *region,
 945                                          void __iomem *ptr)
 946 {
 947         u64 typer = gic_read_typer(ptr + GICR_TYPER);
 948
 949         /* Boot-time cleanip */
 950         if ((typer & GICR_TYPER_VLPIS) && (typer & GICR_TYPER_RVPEID)) {
 951                 u64 val;
 952
 953                 /* Deactivate any present vPE */
 954                 val = gicr_read_vpendbaser(ptr + SZ_128K + GICR_VPENDBASER);
 955                 if (val & GICR_VPENDBASER_Valid)
 956                         gicr_write_vpendbaser(GICR_VPENDBASER_PendingLast,
 957                                               ptr + SZ_128K + GICR_VPENDBASER);
 958
 959                 /* Mark the VPE table as invalid */
 960                 val = gicr_read_vpropbaser(ptr + SZ_128K + GICR_VPROPBASER);
 961                 val &= ~GICR_VPROPBASER_4_1_VALID;
 962                 gicr_write_vpropbaser(val, ptr + SZ_128K + GICR_VPROPBASER);
 963         }
 964
 965         gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS);
 966
 967         /* RVPEID implies some form of DirectLPI, no matter what the doc says... :-/ */
 968         gic_data.rdists.has_rvpeid &= !!(typer & GICR_TYPER_RVPEID);
 969         gic_data.rdists.has_direct_lpi &= (!!(typer & GICR_TYPER_DirectLPIS) |
 970                                            gic_data.rdists.has_rvpeid);
 971         gic_data.rdists.has_vpend_valid_dirty &= !!(typer & GICR_TYPER_DIRTY);
 972
 973         /* Detect non-sensical configurations */
 974         if (WARN_ON_ONCE(gic_data.rdists.has_rvpeid && !gic_data.rdists.has_vlpis)) {
 975                 gic_data.rdists.has_direct_lpi = false;
 976                 gic_data.rdists.has_vlpis = false;
 977                 gic_data.rdists.has_rvpeid = false;
 978         }
 979
 980         gic_data.ppi_nr = min(GICR_TYPER_NR_PPIS(typer), gic_data.ppi_nr);
 981
 982         return 1;
 983 }
 984
 985 static void gic_update_rdist_properties(void)
 986 {
 987         gic_data.ppi_nr = UINT_MAX;
 988         gic_iterate_rdists(__gic_update_rdist_properties);
 989         if (WARN_ON(gic_data.ppi_nr == UINT_MAX))
 990                 gic_data.ppi_nr = 0;
 991         pr_info("%d PPIs implemented\n", gic_data.ppi_nr);
 992         if (gic_data.rdists.has_vlpis)
 993                 pr_info("GICv4 features: %s%s%s\n",
 994                         gic_data.rdists.has_direct_lpi ? "DirectLPI " : "",
 995                         gic_data.rdists.has_rvpeid ? "RVPEID " : "",
 996                         gic_data.rdists.has_vpend_valid_dirty ? "Valid+Dirty " : "");
 997 }
 998
 999 /* Check whether it's single security state view */
1000 static inline bool gic_dist_security_disabled(void)
1001 {
1002         return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS;
1003 }
1004
1005 static void gic_cpu_sys_reg_init(void)
1006 {
1007         int i, cpu = smp_processor_id();
1008         u64 mpidr = cpu_logical_map(cpu);
1009         u64 need_rss = MPIDR_RS(mpidr);
1010         bool group0;
1011         u32 pribits;
1012
1013         /*
1014          * Need to check that the SRE bit has actually been set. If
1015          * not, it means that SRE is disabled at EL2. We're going to
1016          * die painfully, and there is nothing we can do about it.
1017          *
1018          * Kindly inform the luser.
1019          */
1020         if (!gic_enable_sre())
1021                 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
1022
1023         pribits = gic_get_pribits();
1024
1025         group0 = gic_has_group0();
1026
1027         /* Set priority mask register */
1028         if (!gic_prio_masking_enabled()) {
1029                 write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1);
1030         } else if (gic_supports_nmi()) {
1031                 /*
1032                  * Mismatch configuration with boot CPU, the system is likely
1033                  * to die as interrupt masking will not work properly on all
1034                  * CPUs
1035                  *
1036                  * The boot CPU calls this function before enabling NMI support,
1037                  * and as a result we'll never see this warning in the boot path
1038                  * for that CPU.
1039                  */
1040                 if (static_branch_unlikely(&gic_nonsecure_priorities))
1041                         WARN_ON(!group0 || gic_dist_security_disabled());
1042                 else
1043                         WARN_ON(group0 && !gic_dist_security_disabled());
1044         }
1045
1046         /*
1047          * Some firmwares hand over to the kernel with the BPR changed from
1048          * its reset value (and with a value large enough to prevent
1049          * any pre-emptive interrupts from working at all). Writing a zero
1050          * to BPR restores is reset value.
1051          */
1052         gic_write_bpr1(0);
1053
1054         if (static_branch_likely(&supports_deactivate_key)) {
1055                 /* EOI drops priority only (mode 1) */
1056                 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);
1057         } else {
1058                 /* EOI deactivates interrupt too (mode 0) */
1059                 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
1060         }
1061
1062         /* Always whack Group0 before Group1 */
1063         if (group0) {
1064                 switch(pribits) {
1065                 case 8:
1066                 case 7:
1067                         write_gicreg(0, ICC_AP0R3_EL1);
1068                         write_gicreg(0, ICC_AP0R2_EL1);
1069                         fallthrough;
1070                 case 6:
1071                         write_gicreg(0, ICC_AP0R1_EL1);
1072                         fallthrough;
1073                 case 5:
1074                 case 4:
1075                         write_gicreg(0, ICC_AP0R0_EL1);
1076                 }
1077
1078                 isb();
1079         }
1080
1081         switch(pribits) {
1082         case 8:
1083         case 7:
1084                 write_gicreg(0, ICC_AP1R3_EL1);
1085                 write_gicreg(0, ICC_AP1R2_EL1);
1086                 fallthrough;
1087         case 6:
1088                 write_gicreg(0, ICC_AP1R1_EL1);
1089                 fallthrough;
1090         case 5:
1091         case 4:
1092                 write_gicreg(0, ICC_AP1R0_EL1);
1093         }
1094
1095         isb();
1096
1097         /* ... and let's hit the road... */
1098         gic_write_grpen1(1);
1099
1100         /* Keep the RSS capability status in per_cpu variable */
1101         per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS);
1102
1103         /* Check all the CPUs have capable of sending SGIs to other CPUs */
1104         for_each_online_cpu(i) {
1105                 bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu);
1106
1107                 need_rss |= MPIDR_RS(cpu_logical_map(i));
1108                 if (need_rss && (!have_rss))
1109                         pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n",
1110                                 cpu, (unsigned long)mpidr,
1111                                 i, (unsigned long)cpu_logical_map(i));
1112         }
1113
1114         /**
1115          * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0,
1116          * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED
1117          * UNPREDICTABLE choice of :
1118          *   - The write is ignored.
1119          *   - The RS field is treated as 0.
1120          */
1121         if (need_rss && (!gic_data.has_rss))
1122                 pr_crit_once("RSS is required but GICD doesn't support it\n");
1123 }
1124
1125 static bool gicv3_nolpi;
1126
1127 static int __init gicv3_nolpi_cfg(char *buf)
1128 {
1129         return strtobool(buf, &gicv3_nolpi);
1130 }
1131 early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg);
1132
1133 static int gic_dist_supports_lpis(void)
1134 {
1135         return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) &&
1136                 !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) &&
1137                 !gicv3_nolpi);
1138 }
1139
1140 static void gic_cpu_init(void)
1141 {
1142         void __iomem *rbase;
1143         int i;
1144
1145         /* Register ourselves with the rest of the world */
1146         if (gic_populate_rdist())
1147                 return;
1148
1149         gic_enable_redist(true);
1150
1151         WARN((gic_data.ppi_nr > 16 || GIC_ESPI_NR != 0) &&
1152              !(gic_read_ctlr() & ICC_CTLR_EL1_ExtRange),
1153              "Distributor has extended ranges, but CPU%d doesn't\n",
1154              smp_processor_id());
1155
1156         rbase = gic_data_rdist_sgi_base();
1157
1158         /* Configure SGIs/PPIs as non-secure Group-1 */
1159         for (i = 0; i < gic_data.ppi_nr + 16; i += 32)
1160                 writel_relaxed(~0, rbase + GICR_IGROUPR0 + i / 8);
1161
1162         gic_cpu_config(rbase, gic_data.ppi_nr + 16, gic_redist_wait_for_rwp);
1163
1164         /* initialise system registers */
1165         gic_cpu_sys_reg_init();
1166 }
1167
1168 #ifdef CONFIG_SMP
1169
1170 #define MPIDR_TO_SGI_RS(mpidr)  (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT)
1171 #define MPIDR_TO_SGI_CLUSTER_ID(mpidr)  ((mpidr) & ~0xFUL)
1172
1173 static int gic_starting_cpu(unsigned int cpu)
1174 {
1175         gic_cpu_init();
1176
1177         if (gic_dist_supports_lpis())
1178                 its_cpu_init();
1179
1180         return 0;
1181 }
1182
1183 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
1184                                    unsigned long cluster_id)
1185 {
1186         int next_cpu, cpu = *base_cpu;
1187         unsigned long mpidr = cpu_logical_map(cpu);
1188         u16 tlist = 0;
1189
1190         while (cpu < nr_cpu_ids) {
1191                 tlist |= 1 << (mpidr & 0xf);
1192
1193                 next_cpu = cpumask_next(cpu, mask);
1194                 if (next_cpu >= nr_cpu_ids)
1195                         goto out;
1196                 cpu = next_cpu;
1197
1198                 mpidr = cpu_logical_map(cpu);
1199
1200                 if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) {
1201                         cpu--;
1202                         goto out;
1203                 }
1204         }
1205 out:
1206         *base_cpu = cpu;
1207         return tlist;
1208 }
1209
1210 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \
1211         (MPIDR_AFFINITY_LEVEL(cluster_id, level) \
1212                 << ICC_SGI1R_AFFINITY_## level ##_SHIFT)
1213
1214 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
1215 {
1216         u64 val;
1217
1218         val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3)     |
1219                MPIDR_TO_SGI_AFFINITY(cluster_id, 2)     |
1220                irq << ICC_SGI1R_SGI_ID_SHIFT            |
1221                MPIDR_TO_SGI_AFFINITY(cluster_id, 1)     |
1222                MPIDR_TO_SGI_RS(cluster_id)              |
1223                tlist << ICC_SGI1R_TARGET_LIST_SHIFT);
1224
1225         pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
1226         gic_write_sgi1r(val);
1227 }
1228
1229 static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
1230 {
1231         int cpu;
1232
1233         if (WARN_ON(d->hwirq >= 16))
1234                 return;
1235
1236         /*
1237          * Ensure that stores to Normal memory are visible to the
1238          * other CPUs before issuing the IPI.
1239          */
1240         wmb();
1241
1242         for_each_cpu(cpu, mask) {
1243                 u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu));
1244                 u16 tlist;
1245
1246                 tlist = gic_compute_target_list(&cpu, mask, cluster_id);
1247                 gic_send_sgi(cluster_id, tlist, d->hwirq);
1248         }
1249
1250         /* Force the above writes to ICC_SGI1R_EL1 to be executed */
1251         isb();
1252 }
1253
1254 static void __init gic_smp_init(void)
1255 {
1256         struct irq_fwspec sgi_fwspec = {
1257                 .fwnode         = gic_data.fwnode,
1258                 .param_count    = 1,
1259         };
1260         int base_sgi;
1261
1262         cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
1263                                   "irqchip/arm/gicv3:starting",
1264                                   gic_starting_cpu, NULL);
1265
1266         /* Register all 8 non-secure SGIs */
1267         base_sgi = __irq_domain_alloc_irqs(gic_data.domain, -1, 8,
1268                                            NUMA_NO_NODE, &sgi_fwspec,
1269                                            false, NULL);
1270         if (WARN_ON(base_sgi <= 0))
1271                 return;
1272
1273         set_smp_ipi_range(base_sgi, 8);
1274 }
1275
1276 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1277                             bool force)
1278 {
1279         unsigned int cpu;
1280         u32 offset, index;
1281         void __iomem *reg;
1282         int enabled;
1283         u64 val;
1284
1285         if (force)
1286                 cpu = cpumask_first(mask_val);
1287         else
1288                 cpu = cpumask_any_and(mask_val, cpu_online_mask);
1289
1290         if (cpu >= nr_cpu_ids)
1291                 return -EINVAL;
1292
1293         if (gic_irq_in_rdist(d))
1294                 return -EINVAL;
1295
1296         /* If interrupt was enabled, disable it first */
1297         enabled = gic_peek_irq(d, GICD_ISENABLER);
1298         if (enabled)
1299                 gic_mask_irq(d);
1300
1301         offset = convert_offset_index(d, GICD_IROUTER, &index);
1302         reg = gic_dist_base(d) + offset + (index * 8);
1303         val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
1304
1305         gic_write_irouter(val, reg);
1306
1307         /*
1308          * If the interrupt was enabled, enabled it again. Otherwise,
1309          * just wait for the distributor to have digested our changes.
1310          */
1311         if (enabled)
1312                 gic_unmask_irq(d);
1313         else
1314                 gic_dist_wait_for_rwp();
1315
1316         irq_data_update_effective_affinity(d, cpumask_of(cpu));
1317
1318         return IRQ_SET_MASK_OK_DONE;
1319 }
1320 #else
1321 #define gic_set_affinity        NULL
1322 #define gic_ipi_send_mask       NULL
1323 #define gic_smp_init()          do { } while(0)
1324 #endif
1325
1326 static int gic_retrigger(struct irq_data *data)
1327 {
1328         return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true);
1329 }
1330
1331 #ifdef CONFIG_CPU_PM
1332 static int gic_cpu_pm_notifier(struct notifier_block *self,
1333                                unsigned long cmd, void *v)
1334 {
1335         if (cmd == CPU_PM_EXIT) {
1336                 if (gic_dist_security_disabled())
1337                         gic_enable_redist(true);
1338                 gic_cpu_sys_reg_init();
1339         } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) {
1340                 gic_write_grpen1(0);
1341                 gic_enable_redist(false);
1342         }
1343         return NOTIFY_OK;
1344 }
1345
1346 static struct notifier_block gic_cpu_pm_notifier_block = {
1347         .notifier_call = gic_cpu_pm_notifier,
1348 };
1349
1350 static void gic_cpu_pm_init(void)
1351 {
1352         cpu_pm_register_notifier(&gic_cpu_pm_notifier_block);
1353 }
1354
1355 #else
1356 static inline void gic_cpu_pm_init(void) { }
1357 #endif /* CONFIG_CPU_PM */
1358
1359 static struct irq_chip gic_chip = {
1360         .name                   = "GICv3",
1361         .irq_mask               = gic_mask_irq,
1362         .irq_unmask             = gic_unmask_irq,
1363         .irq_eoi                = gic_eoi_irq,
1364         .irq_set_type           = gic_set_type,
1365         .irq_set_affinity       = gic_set_affinity,
1366         .irq_retrigger          = gic_retrigger,
1367         .irq_get_irqchip_state  = gic_irq_get_irqchip_state,
1368         .irq_set_irqchip_state  = gic_irq_set_irqchip_state,
1369         .irq_nmi_setup          = gic_irq_nmi_setup,
1370         .irq_nmi_teardown       = gic_irq_nmi_teardown,
1371         .ipi_send_mask          = gic_ipi_send_mask,
1372         .flags                  = IRQCHIP_SET_TYPE_MASKED |
1373                                   IRQCHIP_SKIP_SET_WAKE |
1374                                   IRQCHIP_MASK_ON_SUSPEND,
1375 };
1376
1377 static struct irq_chip gic_eoimode1_chip = {
1378         .name                   = "GICv3",
1379         .irq_mask               = gic_eoimode1_mask_irq,
1380         .irq_unmask             = gic_unmask_irq,
1381         .irq_eoi                = gic_eoimode1_eoi_irq,
1382         .irq_set_type           = gic_set_type,
1383         .irq_set_affinity       = gic_set_affinity,
1384         .irq_retrigger          = gic_retrigger,
1385         .irq_get_irqchip_state  = gic_irq_get_irqchip_state,
1386         .irq_set_irqchip_state  = gic_irq_set_irqchip_state,
1387         .irq_set_vcpu_affinity  = gic_irq_set_vcpu_affinity,
1388         .irq_nmi_setup          = gic_irq_nmi_setup,
1389         .irq_nmi_teardown       = gic_irq_nmi_teardown,
1390         .ipi_send_mask          = gic_ipi_send_mask,
1391         .flags                  = IRQCHIP_SET_TYPE_MASKED |
1392                                   IRQCHIP_SKIP_SET_WAKE |
1393                                   IRQCHIP_MASK_ON_SUSPEND,
1394 };
1395
1396 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
1397                               irq_hw_number_t hw)
1398 {
1399         struct irq_chip *chip = &gic_chip;
1400         struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq));
1401
1402         if (static_branch_likely(&supports_deactivate_key))
1403                 chip = &gic_eoimode1_chip;
1404
1405         switch (__get_intid_range(hw)) {
1406         case SGI_RANGE:
1407         case PPI_RANGE:
1408         case EPPI_RANGE:
1409                 irq_set_percpu_devid(irq);
1410                 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1411                                     handle_percpu_devid_irq, NULL, NULL);
1412                 break;
1413
1414         case SPI_RANGE:
1415         case ESPI_RANGE:
1416                 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1417                                     handle_fasteoi_irq, NULL, NULL);
1418                 irq_set_probe(irq);
1419                 irqd_set_single_target(irqd);
1420                 break;
1421
1422         case LPI_RANGE:
1423                 if (!gic_dist_supports_lpis())
1424                         return -EPERM;
1425                 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1426                                     handle_fasteoi_irq, NULL, NULL);
1427                 break;
1428
1429         default:
1430                 return -EPERM;
1431         }
1432
1433         /* Prevents SW retriggers which mess up the ACK/EOI ordering */
1434         irqd_set_handle_enforce_irqctx(irqd);
1435         return 0;
1436 }
1437
1438 static int gic_irq_domain_translate(struct irq_domain *d,
1439                                     struct irq_fwspec *fwspec,
1440                                     unsigned long *hwirq,
1441                                     unsigned int *type)
1442 {
1443         if (fwspec->param_count == 1 && fwspec->param[0] < 16) {
1444                 *hwirq = fwspec->param[0];
1445                 *type = IRQ_TYPE_EDGE_RISING;
1446                 return 0;
1447         }
1448
1449         if (is_of_node(fwspec->fwnode)) {
1450                 if (fwspec->param_count < 3)
1451                         return -EINVAL;
1452
1453                 switch (fwspec->param[0]) {
1454                 case 0:                 /* SPI */
1455                         *hwirq = fwspec->param[1] + 32;
1456                         break;
1457                 case 1:                 /* PPI */
1458                         *hwirq = fwspec->param[1] + 16;
1459                         break;
1460                 case 2:                 /* ESPI */
1461                         *hwirq = fwspec->param[1] + ESPI_BASE_INTID;
1462                         break;
1463                 case 3:                 /* EPPI */
1464                         *hwirq = fwspec->param[1] + EPPI_BASE_INTID;
1465                         break;
1466                 case GIC_IRQ_TYPE_LPI:  /* LPI */
1467                         *hwirq = fwspec->param[1];
1468                         break;
1469                 case GIC_IRQ_TYPE_PARTITION:
1470                         *hwirq = fwspec->param[1];
1471                         if (fwspec->param[1] >= 16)
1472                                 *hwirq += EPPI_BASE_INTID - 16;
1473                         else
1474                                 *hwirq += 16;
1475                         break;
1476                 default:
1477                         return -EINVAL;
1478                 }
1479
1480                 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1481
1482                 /*
1483                  * Make it clear that broken DTs are... broken.
1484                  * Partitioned PPIs are an unfortunate exception.
1485                  */
1486                 WARN_ON(*type == IRQ_TYPE_NONE &&
1487                         fwspec->param[0] != GIC_IRQ_TYPE_PARTITION);
1488                 return 0;
1489         }
1490
1491         if (is_fwnode_irqchip(fwspec->fwnode)) {
1492                 if(fwspec->param_count != 2)
1493                         return -EINVAL;
1494
1495                 if (fwspec->param[0] < 16) {
1496                         pr_err(FW_BUG "Illegal GSI%d translation request\n",
1497                                fwspec->param[0]);
1498                         return -EINVAL;
1499                 }
1500
1501                 *hwirq = fwspec->param[0];
1502                 *type = fwspec->param[1];
1503
1504                 WARN_ON(*type == IRQ_TYPE_NONE);
1505                 return 0;
1506         }
1507
1508         return -EINVAL;
1509 }
1510
1511 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1512                                 unsigned int nr_irqs, void *arg)
1513 {
1514         int i, ret;
1515         irq_hw_number_t hwirq;
1516         unsigned int type = IRQ_TYPE_NONE;
1517         struct irq_fwspec *fwspec = arg;
1518
1519         ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
1520         if (ret)
1521                 return ret;
1522
1523         for (i = 0; i < nr_irqs; i++) {
1524                 ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
1525                 if (ret)
1526                         return ret;
1527         }
1528
1529         return 0;
1530 }
1531
1532 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1533                                 unsigned int nr_irqs)
1534 {
1535         int i;
1536
1537         for (i = 0; i < nr_irqs; i++) {
1538                 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
1539                 irq_set_handler(virq + i, NULL);
1540                 irq_domain_reset_irq_data(d);
1541         }
1542 }
1543
1544 static bool fwspec_is_partitioned_ppi(struct irq_fwspec *fwspec,
1545                                       irq_hw_number_t hwirq)
1546 {
1547         enum gic_intid_range range;
1548
1549         if (!gic_data.ppi_descs)
1550                 return false;
1551
1552         if (!is_of_node(fwspec->fwnode))
1553                 return false;
1554
1555         if (fwspec->param_count < 4 || !fwspec->param[3])
1556                 return false;
1557
1558         range = __get_intid_range(hwirq);
1559         if (range != PPI_RANGE && range != EPPI_RANGE)
1560                 return false;
1561
1562         return true;
1563 }
1564
1565 static int gic_irq_domain_select(struct irq_domain *d,
1566                                  struct irq_fwspec *fwspec,
1567                                  enum irq_domain_bus_token bus_token)
1568 {
1569         unsigned int type, ret, ppi_idx;
1570         irq_hw_number_t hwirq;
1571
1572         /* Not for us */
1573         if (fwspec->fwnode != d->fwnode)
1574                 return 0;
1575
1576         /* If this is not DT, then we have a single domain */
1577         if (!is_of_node(fwspec->fwnode))
1578                 return 1;
1579
1580         ret = gic_irq_domain_translate(d, fwspec, &hwirq, &type);
1581         if (WARN_ON_ONCE(ret))
1582                 return 0;
1583
1584         if (!fwspec_is_partitioned_ppi(fwspec, hwirq))
1585                 return d == gic_data.domain;
1586
1587         /*
1588          * If this is a PPI and we have a 4th (non-null) parameter,
1589          * then we need to match the partition domain.
1590          */
1591         ppi_idx = __gic_get_ppi_index(hwirq);
1592         return d == partition_get_domain(gic_data.ppi_descs[ppi_idx]);
1593 }
1594
1595 static const struct irq_domain_ops gic_irq_domain_ops = {
1596         .translate = gic_irq_domain_translate,
1597         .alloc = gic_irq_domain_alloc,
1598         .free = gic_irq_domain_free,
1599         .select = gic_irq_domain_select,
1600 };
1601
1602 static int partition_domain_translate(struct irq_domain *d,
1603                                       struct irq_fwspec *fwspec,
1604                                       unsigned long *hwirq,
1605                                       unsigned int *type)
1606 {
1607         unsigned long ppi_intid;
1608         struct device_node *np;
1609         unsigned int ppi_idx;
1610         int ret;
1611
1612         if (!gic_data.ppi_descs)
1613                 return -ENOMEM;
1614
1615         np = of_find_node_by_phandle(fwspec->param[3]);
1616         if (WARN_ON(!np))
1617                 return -EINVAL;
1618
1619         ret = gic_irq_domain_translate(d, fwspec, &ppi_intid, type);
1620         if (WARN_ON_ONCE(ret))
1621                 return 0;
1622
1623         ppi_idx = __gic_get_ppi_index(ppi_intid);
1624         ret = partition_translate_id(gic_data.ppi_descs[ppi_idx],
1625                                      of_node_to_fwnode(np));
1626         if (ret < 0)
1627                 return ret;
1628
1629         *hwirq = ret;
1630         *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1631
1632         return 0;
1633 }
1634
1635 static const struct irq_domain_ops partition_domain_ops = {
1636         .translate = partition_domain_translate,
1637         .select = gic_irq_domain_select,
1638 };
1639
1640 static bool gic_enable_quirk_msm8996(void *data)
1641 {
1642         struct gic_chip_data *d = data;
1643
1644         d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996;
1645
1646         return true;
1647 }
1648
1649 static bool gic_enable_quirk_cavium_38539(void *data)
1650 {
1651         struct gic_chip_data *d = data;
1652
1653         d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539;
1654
1655         return true;
1656 }
1657
1658 static bool gic_enable_quirk_hip06_07(void *data)
1659 {
1660         struct gic_chip_data *d = data;
1661
1662         /*
1663          * HIP06 GICD_IIDR clashes with GIC-600 product number (despite
1664          * not being an actual ARM implementation). The saving grace is
1665          * that GIC-600 doesn't have ESPI, so nothing to do in that case.
1666          * HIP07 doesn't even have a proper IIDR, and still pretends to
1667          * have ESPI. In both cases, put them right.
1668          */
1669         if (d->rdists.gicd_typer & GICD_TYPER_ESPI) {
1670                 /* Zero both ESPI and the RES0 field next to it... */
1671                 d->rdists.gicd_typer &= ~GENMASK(9, 8);
1672                 return true;
1673         }
1674
1675         return false;
1676 }
1677
1678 static const struct gic_quirk gic_quirks[] = {
1679         {
1680                 .desc   = "GICv3: Qualcomm MSM8996 broken firmware",
1681                 .compatible = "qcom,msm8996-gic-v3",
1682                 .init   = gic_enable_quirk_msm8996,
1683         },
1684         {
1685                 .desc   = "GICv3: HIP06 erratum 161010803",
1686                 .iidr   = 0x0204043b,
1687                 .mask   = 0xffffffff,
1688                 .init   = gic_enable_quirk_hip06_07,
1689         },
1690         {
1691                 .desc   = "GICv3: HIP07 erratum 161010803",
1692                 .iidr   = 0x00000000,
1693                 .mask   = 0xffffffff,
1694                 .init   = gic_enable_quirk_hip06_07,
1695         },
1696         {
1697                 /*
1698                  * Reserved register accesses generate a Synchronous
1699                  * External Abort. This erratum applies to:
1700                  * - ThunderX: CN88xx
1701                  * - OCTEON TX: CN83xx, CN81xx
1702                  * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx*
1703                  */
1704                 .desc   = "GICv3: Cavium erratum 38539",
1705                 .iidr   = 0xa000034c,
1706                 .mask   = 0xe8f00fff,
1707                 .init   = gic_enable_quirk_cavium_38539,
1708         },
1709         {
1710         }
1711 };
1712
1713 static void gic_enable_nmi_support(void)
1714 {
1715         int i;
1716
1717         if (!gic_prio_masking_enabled())
1718                 return;
1719
1720         ppi_nmi_refs = kcalloc(gic_data.ppi_nr, sizeof(*ppi_nmi_refs), GFP_KERNEL);
1721         if (!ppi_nmi_refs)
1722                 return;
1723
1724         for (i = 0; i < gic_data.ppi_nr; i++)
1725                 refcount_set(&ppi_nmi_refs[i], 0);
1726
1727         /*
1728          * Linux itself doesn't use 1:N distribution, so has no need to
1729          * set PMHE. The only reason to have it set is if EL3 requires it
1730          * (and we can't change it).
1731          */
1732         if (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK)
1733                 static_branch_enable(&gic_pmr_sync);
1734
1735         pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n",
1736                 static_branch_unlikely(&gic_pmr_sync) ? "forced" : "relaxed");
1737
1738         /*
1739          * How priority values are used by the GIC depends on two things:
1740          * the security state of the GIC (controlled by the GICD_CTRL.DS bit)
1741          * and if Group 0 interrupts can be delivered to Linux in the non-secure
1742          * world as FIQs (controlled by the SCR_EL3.FIQ bit). These affect the
1743          * the ICC_PMR_EL1 register and the priority that software assigns to
1744          * interrupts:
1745          *
1746          * GICD_CTRL.DS | SCR_EL3.FIQ | ICC_PMR_EL1 | Group 1 priority
1747          * -----------------------------------------------------------
1748          *      1       |      -      |  unchanged  |    unchanged
1749          * -----------------------------------------------------------
1750          *      0       |      1      |  non-secure |    non-secure
1751          * -----------------------------------------------------------
1752          *      0       |      0      |  unchanged  |    non-secure
1753          *
1754          * where non-secure means that the value is right-shifted by one and the
1755          * MSB bit set, to make it fit in the non-secure priority range.
1756          *
1757          * In the first two cases, where ICC_PMR_EL1 and the interrupt priority
1758          * are both either modified or unchanged, we can use the same set of
1759          * priorities.
1760          *
1761          * In the last case, where only the interrupt priorities are modified to
1762          * be in the non-secure range, we use a different PMR value to mask IRQs
1763          * and the rest of the values that we use remain unchanged.
1764          */
1765         if (gic_has_group0() && !gic_dist_security_disabled())
1766                 static_branch_enable(&gic_nonsecure_priorities);
1767
1768         static_branch_enable(&supports_pseudo_nmis);
1769
1770         if (static_branch_likely(&supports_deactivate_key))
1771                 gic_eoimode1_chip.flags |= IRQCHIP_SUPPORTS_NMI;
1772         else
1773                 gic_chip.flags |= IRQCHIP_SUPPORTS_NMI;
1774 }
1775
1776 static int __init gic_init_bases(void __iomem *dist_base,
1777                                  struct redist_region *rdist_regs,
1778                                  u32 nr_redist_regions,
1779                                  u64 redist_stride,
1780                                  struct fwnode_handle *handle)
1781 {
1782         u32 typer;
1783         int err;
1784
1785         if (!is_hyp_mode_available())
1786                 static_branch_disable(&supports_deactivate_key);
1787
1788         if (static_branch_likely(&supports_deactivate_key))
1789                 pr_info("GIC: Using split EOI/Deactivate mode\n");
1790
1791         gic_data.fwnode = handle;
1792         gic_data.dist_base = dist_base;
1793         gic_data.redist_regions = rdist_regs;
1794         gic_data.nr_redist_regions = nr_redist_regions;
1795         gic_data.redist_stride = redist_stride;
1796
1797         /*
1798          * Find out how many interrupts are supported.
1799          */
1800         typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
1801         gic_data.rdists.gicd_typer = typer;
1802
1803         gic_enable_quirks(readl_relaxed(gic_data.dist_base + GICD_IIDR),
1804                           gic_quirks, &gic_data);
1805
1806         pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32);
1807         pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR);
1808
1809         /*
1810          * ThunderX1 explodes on reading GICD_TYPER2, in violation of the
1811          * architecture spec (which says that reserved registers are RES0).
1812          */
1813         if (!(gic_data.flags & FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539))
1814                 gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2);
1815
1816         gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
1817                                                  &gic_data);
1818         gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
1819         gic_data.rdists.has_rvpeid = true;
1820         gic_data.rdists.has_vlpis = true;
1821         gic_data.rdists.has_direct_lpi = true;
1822         gic_data.rdists.has_vpend_valid_dirty = true;
1823
1824         if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
1825                 err = -ENOMEM;
1826                 goto out_free;
1827         }
1828
1829         irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED);
1830
1831         gic_data.has_rss = !!(typer & GICD_TYPER_RSS);
1832         pr_info("Distributor has %sRange Selector support\n",
1833                 gic_data.has_rss ? "" : "no ");
1834
1835         if (typer & GICD_TYPER_MBIS) {
1836                 err = mbi_init(handle, gic_data.domain);
1837                 if (err)
1838                         pr_err("Failed to initialize MBIs\n");
1839         }
1840
1841         set_handle_irq(gic_handle_irq);
1842
1843         gic_update_rdist_properties();
1844
1845         gic_dist_init();
1846         gic_cpu_init();
1847         gic_smp_init();
1848         gic_cpu_pm_init();
1849
1850         if (gic_dist_supports_lpis()) {
1851                 its_init(handle, &gic_data.rdists, gic_data.domain);
1852                 its_cpu_init();
1853         } else {
1854                 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1855                         gicv2m_init(handle, gic_data.domain);
1856         }
1857
1858         gic_enable_nmi_support();
1859
1860         return 0;
1861
1862 out_free:
1863         if (gic_data.domain)
1864                 irq_domain_remove(gic_data.domain);
1865         free_percpu(gic_data.rdists.rdist);
1866         return err;
1867 }
1868
1869 static int __init gic_validate_dist_version(void __iomem *dist_base)
1870 {
1871         u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
1872
1873         if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4)
1874                 return -ENODEV;
1875
1876         return 0;
1877 }
1878
1879 /* Create all possible partitions at boot time */
1880 static void __init gic_populate_ppi_partitions(struct device_node *gic_node)
1881 {
1882         struct device_node *parts_node, *child_part;
1883         int part_idx = 0, i;
1884         int nr_parts;
1885         struct partition_affinity *parts;
1886
1887         parts_node = of_get_child_by_name(gic_node, "ppi-partitions");
1888         if (!parts_node)
1889                 return;
1890
1891         gic_data.ppi_descs = kcalloc(gic_data.ppi_nr, sizeof(*gic_data.ppi_descs), GFP_KERNEL);
1892         if (!gic_data.ppi_descs)
1893                 goto out_put_node;
1894
1895         nr_parts = of_get_child_count(parts_node);
1896
1897         if (!nr_parts)
1898                 goto out_put_node;
1899
1900         parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL);
1901         if (WARN_ON(!parts))
1902                 goto out_put_node;
1903
1904         for_each_child_of_node(parts_node, child_part) {
1905                 struct partition_affinity *part;
1906                 int n;
1907
1908                 part = &parts[part_idx];
1909
1910                 part->partition_id = of_node_to_fwnode(child_part);
1911
1912                 pr_info("GIC: PPI partition %pOFn[%d] { ",
1913                         child_part, part_idx);
1914
1915                 n = of_property_count_elems_of_size(child_part, "affinity",
1916                                                     sizeof(u32));
1917                 WARN_ON(n <= 0);
1918
1919                 for (i = 0; i < n; i++) {
1920                         int err, cpu;
1921                         u32 cpu_phandle;
1922                         struct device_node *cpu_node;
1923
1924                         err = of_property_read_u32_index(child_part, "affinity",
1925                                                          i, &cpu_phandle);
1926                         if (WARN_ON(err))
1927                                 continue;
1928
1929                         cpu_node = of_find_node_by_phandle(cpu_phandle);
1930                         if (WARN_ON(!cpu_node))
1931                                 continue;
1932
1933                         cpu = of_cpu_node_to_id(cpu_node);
1934                         if (WARN_ON(cpu < 0)) {
1935                                 of_node_put(cpu_node);
1936                                 continue;
1937                         }
1938
1939                         pr_cont("%pOF[%d] ", cpu_node, cpu);
1940
1941                         cpumask_set_cpu(cpu, &part->mask);
1942                         of_node_put(cpu_node);
1943                 }
1944
1945                 pr_cont("}\n");
1946                 part_idx++;
1947         }
1948
1949         for (i = 0; i < gic_data.ppi_nr; i++) {
1950                 unsigned int irq;
1951                 struct partition_desc *desc;
1952                 struct irq_fwspec ppi_fwspec = {
1953                         .fwnode         = gic_data.fwnode,
1954                         .param_count    = 3,
1955                         .param          = {
1956                                 [0]     = GIC_IRQ_TYPE_PARTITION,
1957                                 [1]     = i,
1958                                 [2]     = IRQ_TYPE_NONE,
1959                         },
1960                 };
1961
1962                 irq = irq_create_fwspec_mapping(&ppi_fwspec);
1963                 if (WARN_ON(!irq))
1964                         continue;
1965                 desc = partition_create_desc(gic_data.fwnode, parts, nr_parts,
1966                                              irq, &partition_domain_ops);
1967                 if (WARN_ON(!desc))
1968                         continue;
1969
1970                 gic_data.ppi_descs[i] = desc;
1971         }
1972
1973 out_put_node:
1974         of_node_put(parts_node);
1975 }
1976
1977 static void __init gic_of_setup_kvm_info(struct device_node *node)
1978 {
1979         int ret;
1980         struct resource r;
1981         u32 gicv_idx;
1982
1983         gic_v3_kvm_info.type = GIC_V3;
1984
1985         gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1986         if (!gic_v3_kvm_info.maint_irq)
1987                 return;
1988
1989         if (of_property_read_u32(node, "#redistributor-regions",
1990                                  &gicv_idx))
1991                 gicv_idx = 1;
1992
1993         gicv_idx += 3;  /* Also skip GICD, GICC, GICH */
1994         ret = of_address_to_resource(node, gicv_idx, &r);
1995         if (!ret)
1996                 gic_v3_kvm_info.vcpu = r;
1997
1998         gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
1999         gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid;
2000         vgic_set_kvm_info(&gic_v3_kvm_info);
2001 }
2002
2003 static int __init gic_of_init(struct device_node *node, struct device_node *parent)
2004 {
2005         void __iomem *dist_base;
2006         struct redist_region *rdist_regs;
2007         u64 redist_stride;
2008         u32 nr_redist_regions;
2009         int err, i;
2010
2011         dist_base = of_iomap(node, 0);
2012         if (!dist_base) {
2013                 pr_err("%pOF: unable to map gic dist registers\n", node);
2014                 return -ENXIO;
2015         }
2016
2017         err = gic_validate_dist_version(dist_base);
2018         if (err) {
2019                 pr_err("%pOF: no distributor detected, giving up\n", node);
2020                 goto out_unmap_dist;
2021         }
2022
2023         if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions))
2024                 nr_redist_regions = 1;
2025
2026         rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs),
2027                              GFP_KERNEL);
2028         if (!rdist_regs) {
2029                 err = -ENOMEM;
2030                 goto out_unmap_dist;
2031         }
2032
2033         for (i = 0; i < nr_redist_regions; i++) {
2034                 struct resource res;
2035                 int ret;
2036
2037                 ret = of_address_to_resource(node, 1 + i, &res);
2038                 rdist_regs[i].redist_base = of_iomap(node, 1 + i);
2039                 if (ret || !rdist_regs[i].redist_base) {
2040                         pr_err("%pOF: couldn't map region %d\n", node, i);
2041                         err = -ENODEV;
2042                         goto out_unmap_rdist;
2043                 }
2044                 rdist_regs[i].phys_base = res.start;
2045         }
2046
2047         if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
2048                 redist_stride = 0;
2049
2050         gic_enable_of_quirks(node, gic_quirks, &gic_data);
2051
2052         err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions,
2053                              redist_stride, &node->fwnode);
2054         if (err)
2055                 goto out_unmap_rdist;
2056
2057         gic_populate_ppi_partitions(node);
2058
2059         if (static_branch_likely(&supports_deactivate_key))
2060                 gic_of_setup_kvm_info(node);
2061         return 0;
2062
2063 out_unmap_rdist:
2064         for (i = 0; i < nr_redist_regions; i++)
2065                 if (rdist_regs[i].redist_base)
2066                         iounmap(rdist_regs[i].redist_base);
2067         kfree(rdist_regs);
2068 out_unmap_dist:
2069         iounmap(dist_base);
2070         return err;
2071 }
2072
2073 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
2074
2075 #ifdef CONFIG_ACPI
2076 static struct
2077 {
2078         void __iomem *dist_base;
2079         struct redist_region *redist_regs;
2080         u32 nr_redist_regions;
2081         bool single_redist;
2082         int enabled_rdists;
2083         u32 maint_irq;
2084         int maint_irq_mode;
2085         phys_addr_t vcpu_base;
2086 } acpi_data __initdata;
2087
2088 static void __init
2089 gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base)
2090 {
2091         static int count = 0;
2092
2093         acpi_data.redist_regs[count].phys_base = phys_base;
2094         acpi_data.redist_regs[count].redist_base = redist_base;
2095         acpi_data.redist_regs[count].single_redist = acpi_data.single_redist;
2096         count++;
2097 }
2098
2099 static int __init
2100 gic_acpi_parse_madt_redist(union acpi_subtable_headers *header,
2101                            const unsigned long end)
2102 {
2103         struct acpi_madt_generic_redistributor *redist =
2104                         (struct acpi_madt_generic_redistributor *)header;
2105         void __iomem *redist_base;
2106
2107         redist_base = ioremap(redist->base_address, redist->length);
2108         if (!redist_base) {
2109                 pr_err("Couldn't map GICR region @%llx\n", redist->base_address);
2110                 return -ENOMEM;
2111         }
2112
2113         gic_acpi_register_redist(redist->base_address, redist_base);
2114         return 0;
2115 }
2116
2117 static int __init
2118 gic_acpi_parse_madt_gicc(union acpi_subtable_headers *header,
2119                          const unsigned long end)
2120 {
2121         struct acpi_madt_generic_interrupt *gicc =
2122                                 (struct acpi_madt_generic_interrupt *)header;
2123         u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
2124         u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;
2125         void __iomem *redist_base;
2126
2127         /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */
2128         if (!(gicc->flags & ACPI_MADT_ENABLED))
2129                 return 0;
2130
2131         redist_base = ioremap(gicc->gicr_base_address, size);
2132         if (!redist_base)
2133                 return -ENOMEM;
2134
2135         gic_acpi_register_redist(gicc->gicr_base_address, redist_base);
2136         return 0;
2137 }
2138
2139 static int __init gic_acpi_collect_gicr_base(void)
2140 {
2141         acpi_tbl_entry_handler redist_parser;
2142         enum acpi_madt_type type;
2143
2144         if (acpi_data.single_redist) {
2145                 type = ACPI_MADT_TYPE_GENERIC_INTERRUPT;
2146                 redist_parser = gic_acpi_parse_madt_gicc;
2147         } else {
2148                 type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR;
2149                 redist_parser = gic_acpi_parse_madt_redist;
2150         }
2151
2152         /* Collect redistributor base addresses in GICR entries */
2153         if (acpi_table_parse_madt(type, redist_parser, 0) > 0)
2154                 return 0;
2155
2156         pr_info("No valid GICR entries exist\n");
2157         return -ENODEV;
2158 }
2159
2160 static int __init gic_acpi_match_gicr(union acpi_subtable_headers *header,
2161                                   const unsigned long end)
2162 {
2163         /* Subtable presence means that redist exists, that's it */
2164         return 0;
2165 }
2166
2167 static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header,
2168                                       const unsigned long end)
2169 {
2170         struct acpi_madt_generic_interrupt *gicc =
2171                                 (struct acpi_madt_generic_interrupt *)header;
2172
2173         /*
2174          * If GICC is enabled and has valid gicr base address, then it means
2175          * GICR base is presented via GICC
2176          */
2177         if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) {
2178                 acpi_data.enabled_rdists++;
2179                 return 0;
2180         }
2181
2182         /*
2183          * It's perfectly valid firmware can pass disabled GICC entry, driver
2184          * should not treat as errors, skip the entry instead of probe fail.
2185          */
2186         if (!(gicc->flags & ACPI_MADT_ENABLED))
2187                 return 0;
2188
2189         return -ENODEV;
2190 }
2191
2192 static int __init gic_acpi_count_gicr_regions(void)
2193 {
2194         int count;
2195
2196         /*
2197          * Count how many redistributor regions we have. It is not allowed
2198          * to mix redistributor description, GICR and GICC subtables have to be
2199          * mutually exclusive.
2200          */
2201         count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
2202                                       gic_acpi_match_gicr, 0);
2203         if (count > 0) {
2204                 acpi_data.single_redist = false;
2205                 return count;
2206         }
2207
2208         count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
2209                                       gic_acpi_match_gicc, 0);
2210         if (count > 0) {
2211                 acpi_data.single_redist = true;
2212                 count = acpi_data.enabled_rdists;
2213         }
2214
2215         return count;
2216 }
2217
2218 static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header,
2219                                            struct acpi_probe_entry *ape)
2220 {
2221         struct acpi_madt_generic_distributor *dist;
2222         int count;
2223
2224         dist = (struct acpi_madt_generic_distributor *)header;
2225         if (dist->version != ape->driver_data)
2226                 return false;
2227
2228         /* We need to do that exercise anyway, the sooner the better */
2229         count = gic_acpi_count_gicr_regions();
2230         if (count <= 0)
2231                 return false;
2232
2233         acpi_data.nr_redist_regions = count;
2234         return true;
2235 }
2236
2237 static int __init gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers *header,
2238                                                 const unsigned long end)
2239 {
2240         struct acpi_madt_generic_interrupt *gicc =
2241                 (struct acpi_madt_generic_interrupt *)header;
2242         int maint_irq_mode;
2243         static int first_madt = true;
2244
2245         /* Skip unusable CPUs */
2246         if (!(gicc->flags & ACPI_MADT_ENABLED))
2247                 return 0;
2248
2249         maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
2250                 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
2251
2252         if (first_madt) {
2253                 first_madt = false;
2254
2255                 acpi_data.maint_irq = gicc->vgic_interrupt;
2256                 acpi_data.maint_irq_mode = maint_irq_mode;
2257                 acpi_data.vcpu_base = gicc->gicv_base_address;
2258
2259                 return 0;
2260         }
2261
2262         /*
2263          * The maintenance interrupt and GICV should be the same for every CPU
2264          */
2265         if ((acpi_data.maint_irq != gicc->vgic_interrupt) ||
2266             (acpi_data.maint_irq_mode != maint_irq_mode) ||
2267             (acpi_data.vcpu_base != gicc->gicv_base_address))
2268                 return -EINVAL;
2269
2270         return 0;
2271 }
2272
2273 static bool __init gic_acpi_collect_virt_info(void)
2274 {
2275         int count;
2276
2277         count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
2278                                       gic_acpi_parse_virt_madt_gicc, 0);
2279
2280         return (count > 0);
2281 }
2282
2283 #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
2284 #define ACPI_GICV2_VCTRL_MEM_SIZE       (SZ_4K)
2285 #define ACPI_GICV2_VCPU_MEM_SIZE        (SZ_8K)
2286
2287 static void __init gic_acpi_setup_kvm_info(void)
2288 {
2289         int irq;
2290
2291         if (!gic_acpi_collect_virt_info()) {
2292                 pr_warn("Unable to get hardware information used for virtualization\n");
2293                 return;
2294         }
2295
2296         gic_v3_kvm_info.type = GIC_V3;
2297
2298         irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
2299                                 acpi_data.maint_irq_mode,
2300                                 ACPI_ACTIVE_HIGH);
2301         if (irq <= 0)
2302                 return;
2303
2304         gic_v3_kvm_info.maint_irq = irq;
2305
2306         if (acpi_data.vcpu_base) {
2307                 struct resource *vcpu = &gic_v3_kvm_info.vcpu;
2308
2309                 vcpu->flags = IORESOURCE_MEM;
2310                 vcpu->start = acpi_data.vcpu_base;
2311                 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
2312         }
2313
2314         gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
2315         gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid;
2316         vgic_set_kvm_info(&gic_v3_kvm_info);
2317 }
2318
2319 static int __init
2320 gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end)
2321 {
2322         struct acpi_madt_generic_distributor *dist;
2323         struct fwnode_handle *domain_handle;
2324         size_t size;
2325         int i, err;
2326
2327         /* Get distributor base address */
2328         dist = (struct acpi_madt_generic_distributor *)header;
2329         acpi_data.dist_base = ioremap(dist->base_address,
2330                                       ACPI_GICV3_DIST_MEM_SIZE);
2331         if (!acpi_data.dist_base) {
2332                 pr_err("Unable to map GICD registers\n");
2333                 return -ENOMEM;
2334         }
2335
2336         err = gic_validate_dist_version(acpi_data.dist_base);
2337         if (err) {
2338                 pr_err("No distributor detected at @%p, giving up\n",
2339                        acpi_data.dist_base);
2340                 goto out_dist_unmap;
2341         }
2342
2343         size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions;
2344         acpi_data.redist_regs = kzalloc(size, GFP_KERNEL);
2345         if (!acpi_data.redist_regs) {
2346                 err = -ENOMEM;
2347                 goto out_dist_unmap;
2348         }
2349
2350         err = gic_acpi_collect_gicr_base();
2351         if (err)
2352                 goto out_redist_unmap;
2353
2354         domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
2355         if (!domain_handle) {
2356                 err = -ENOMEM;
2357                 goto out_redist_unmap;
2358         }
2359
2360         err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs,
2361                              acpi_data.nr_redist_regions, 0, domain_handle);
2362         if (err)
2363                 goto out_fwhandle_free;
2364
2365         acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
2366
2367         if (static_branch_likely(&supports_deactivate_key))
2368                 gic_acpi_setup_kvm_info();
2369
2370         return 0;
2371
2372 out_fwhandle_free:
2373         irq_domain_free_fwnode(domain_handle);
2374 out_redist_unmap:
2375         for (i = 0; i < acpi_data.nr_redist_regions; i++)
2376                 if (acpi_data.redist_regs[i].redist_base)
2377                         iounmap(acpi_data.redist_regs[i].redist_base);
2378         kfree(acpi_data.redist_regs);
2379 out_dist_unmap:
2380         iounmap(acpi_data.dist_base);
2381         return err;
2382 }
2383 IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2384                      acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3,
2385                      gic_acpi_init);
2386 IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2387                      acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4,
2388                      gic_acpi_init);
2389 IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2390                      acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE,
2391                      gic_acpi_init);
2392 #endif