drivers/irqchip/irq-gic-v3.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
   4  * Author: Marc Zyngier <marc.zyngier@arm.com>
   5  */
   6
   7 #define pr_fmt(fmt)     "GICv3: " fmt
   8
   9 #include <linux/acpi.h>
  10 #include <linux/cpu.h>
  11 #include <linux/cpu_pm.h>
  12 #include <linux/delay.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irqdomain.h>
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_irq.h>
  18 #include <linux/percpu.h>
  19 #include <linux/refcount.h>
  20 #include <linux/slab.h>
  21
  22 #include <linux/irqchip.h>
  23 #include <linux/irqchip/arm-gic-common.h>
  24 #include <linux/irqchip/arm-gic-v3.h>
  25 #include <linux/irqchip/irq-partition-percpu.h>
  26
  27 #include <asm/cputype.h>
  28 #include <asm/exception.h>
  29 #include <asm/smp_plat.h>
  30 #include <asm/virt.h>
  31
  32 #include "irq-gic-common.h"
  33
  34 #define GICD_INT_NMI_PRI        (GICD_INT_DEF_PRI & ~0x80)
  35
  36 #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996     (1ULL << 0)
  37 #define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539   (1ULL << 1)
  38
  39 struct redist_region {
  40         void __iomem            *redist_base;
  41         phys_addr_t             phys_base;
  42         bool                    single_redist;
  43 };
  44
  45 struct gic_chip_data {
  46         struct fwnode_handle    *fwnode;
  47         void __iomem            *dist_base;
  48         struct redist_region    *redist_regions;
  49         struct rdists           rdists;
  50         struct irq_domain       *domain;
  51         u64                     redist_stride;
  52         u32                     nr_redist_regions;
  53         u64                     flags;
  54         bool                    has_rss;
  55         unsigned int            ppi_nr;
  56         struct partition_desc   **ppi_descs;
  57 };
  58
  59 static struct gic_chip_data gic_data __read_mostly;
  60 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
  61
  62 #define GIC_ID_NR       (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer))
  63 #define GIC_LINE_NR     min(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U)
  64 #define GIC_ESPI_NR     GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer)
  65
  66 /*
  67  * The behaviours of RPR and PMR registers differ depending on the value of
  68  * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
  69  * distributor and redistributors depends on whether security is enabled in the
  70  * GIC.
  71  *
  72  * When security is enabled, non-secure priority values from the (re)distributor
  73  * are presented to the GIC CPUIF as follow:
  74  *     (GIC_(R)DIST_PRI[irq] >> 1) | 0x80;
  75  *
  76  * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure
  77  * EL1 are subject to a similar operation thus matching the priorities presented
  78  * from the (re)distributor when security is enabled.
  79  *
  80  * see GICv3/GICv4 Architecture Specification (IHI0069D):
  81  * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
  82  *   priorities.
  83  * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1
  84  *   interrupt.
  85  *
  86  * For now, we only support pseudo-NMIs if we have non-secure view of
  87  * priorities.
  88  */
  89 static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis);
  90
  91 /*
  92  * Global static key controlling whether an update to PMR allowing more
  93  * interrupts requires to be propagated to the redistributor (DSB SY).
  94  * And this needs to be exported for modules to be able to enable
  95  * interrupts...
  96  */
  97 DEFINE_STATIC_KEY_FALSE(gic_pmr_sync);
  98 EXPORT_SYMBOL(gic_pmr_sync);
  99
 100 /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */
 101 static refcount_t *ppi_nmi_refs;
 102
 103 static struct gic_kvm_info gic_v3_kvm_info;
 104 static DEFINE_PER_CPU(bool, has_rss);
 105
 106 #define MPIDR_RS(mpidr)                 (((mpidr) & 0xF0UL) >> 4)
 107 #define gic_data_rdist()                (this_cpu_ptr(gic_data.rdists.rdist))
 108 #define gic_data_rdist_rd_base()        (gic_data_rdist()->rd_base)
 109 #define gic_data_rdist_sgi_base()       (gic_data_rdist_rd_base() + SZ_64K)
 110
 111 /* Our default, arbitrary priority value. Linux only uses one anyway. */
 112 #define DEFAULT_PMR_VALUE       0xf0
 113
 114 enum gic_intid_range {
 115         PPI_RANGE,
 116         SPI_RANGE,
 117         EPPI_RANGE,
 118         ESPI_RANGE,
 119         LPI_RANGE,
 120         __INVALID_RANGE__
 121 };
 122
 123 static enum gic_intid_range __get_intid_range(irq_hw_number_t hwirq)
 124 {
 125         switch (hwirq) {
 126         case 16 ... 31:
 127                 return PPI_RANGE;
 128         case 32 ... 1019:
 129                 return SPI_RANGE;
 130         case EPPI_BASE_INTID ... (EPPI_BASE_INTID + 63):
 131                 return EPPI_RANGE;
 132         case ESPI_BASE_INTID ... (ESPI_BASE_INTID + 1023):
 133                 return ESPI_RANGE;
 134         case 8192 ... GENMASK(23, 0):
 135                 return LPI_RANGE;
 136         default:
 137                 return __INVALID_RANGE__;
 138         }
 139 }
 140
 141 static enum gic_intid_range get_intid_range(struct irq_data *d)
 142 {
 143         return __get_intid_range(d->hwirq);
 144 }
 145
 146 static inline unsigned int gic_irq(struct irq_data *d)
 147 {
 148         return d->hwirq;
 149 }
 150
 151 static inline int gic_irq_in_rdist(struct irq_data *d)
 152 {
 153         enum gic_intid_range range = get_intid_range(d);
 154         return range == PPI_RANGE || range == EPPI_RANGE;
 155 }
 156
 157 static inline void __iomem *gic_dist_base(struct irq_data *d)
 158 {
 159         switch (get_intid_range(d)) {
 160         case PPI_RANGE:
 161         case EPPI_RANGE:
 162                 /* SGI+PPI -> SGI_base for this CPU */
 163                 return gic_data_rdist_sgi_base();
 164
 165         case SPI_RANGE:
 166         case ESPI_RANGE:
 167                 /* SPI -> dist_base */
 168                 return gic_data.dist_base;
 169
 170         default:
 171                 return NULL;
 172         }
 173 }
 174
 175 static void gic_do_wait_for_rwp(void __iomem *base)
 176 {
 177         u32 count = 1000000;    /* 1s! */
 178
 179         while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
 180                 count--;
 181                 if (!count) {
 182                         pr_err_ratelimited("RWP timeout, gone fishing\n");
 183                         return;
 184                 }
 185                 cpu_relax();
 186                 udelay(1);
 187         }
 188 }
 189
 190 /* Wait for completion of a distributor change */
 191 static void gic_dist_wait_for_rwp(void)
 192 {
 193         gic_do_wait_for_rwp(gic_data.dist_base);
 194 }
 195
 196 /* Wait for completion of a redistributor change */
 197 static void gic_redist_wait_for_rwp(void)
 198 {
 199         gic_do_wait_for_rwp(gic_data_rdist_rd_base());
 200 }
 201
 202 #ifdef CONFIG_ARM64
 203
 204 static u64 __maybe_unused gic_read_iar(void)
 205 {
 206         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154))
 207                 return gic_read_iar_cavium_thunderx();
 208         else
 209                 return gic_read_iar_common();
 210 }
 211 #endif
 212
 213 static void gic_enable_redist(bool enable)
 214 {
 215         void __iomem *rbase;
 216         u32 count = 1000000;    /* 1s! */
 217         u32 val;
 218
 219         if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996)
 220                 return;
 221
 222         rbase = gic_data_rdist_rd_base();
 223
 224         val = readl_relaxed(rbase + GICR_WAKER);
 225         if (enable)
 226                 /* Wake up this CPU redistributor */
 227                 val &= ~GICR_WAKER_ProcessorSleep;
 228         else
 229                 val |= GICR_WAKER_ProcessorSleep;
 230         writel_relaxed(val, rbase + GICR_WAKER);
 231
 232         if (!enable) {          /* Check that GICR_WAKER is writeable */
 233                 val = readl_relaxed(rbase + GICR_WAKER);
 234                 if (!(val & GICR_WAKER_ProcessorSleep))
 235                         return; /* No PM support in this redistributor */
 236         }
 237
 238         while (--count) {
 239                 val = readl_relaxed(rbase + GICR_WAKER);
 240                 if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep))
 241                         break;
 242                 cpu_relax();
 243                 udelay(1);
 244         }
 245         if (!count)
 246                 pr_err_ratelimited("redistributor failed to %s...\n",
 247                                    enable ? "wakeup" : "sleep");
 248 }
 249
 250 /*
 251  * Routines to disable, enable, EOI and route interrupts
 252  */
 253 static u32 convert_offset_index(struct irq_data *d, u32 offset, u32 *index)
 254 {
 255         switch (get_intid_range(d)) {
 256         case PPI_RANGE:
 257         case SPI_RANGE:
 258                 *index = d->hwirq;
 259                 return offset;
 260         case EPPI_RANGE:
 261                 /*
 262                  * Contrary to the ESPI range, the EPPI range is contiguous
 263                  * to the PPI range in the registers, so let's adjust the
 264                  * displacement accordingly. Consistency is overrated.
 265                  */
 266                 *index = d->hwirq - EPPI_BASE_INTID + 32;
 267                 return offset;
 268         case ESPI_RANGE:
 269                 *index = d->hwirq - ESPI_BASE_INTID;
 270                 switch (offset) {
 271                 case GICD_ISENABLER:
 272                         return GICD_ISENABLERnE;
 273                 case GICD_ICENABLER:
 274                         return GICD_ICENABLERnE;
 275                 case GICD_ISPENDR:
 276                         return GICD_ISPENDRnE;
 277                 case GICD_ICPENDR:
 278                         return GICD_ICPENDRnE;
 279                 case GICD_ISACTIVER:
 280                         return GICD_ISACTIVERnE;
 281                 case GICD_ICACTIVER:
 282                         return GICD_ICACTIVERnE;
 283                 case GICD_IPRIORITYR:
 284                         return GICD_IPRIORITYRnE;
 285                 case GICD_ICFGR:
 286                         return GICD_ICFGRnE;
 287                 case GICD_IROUTER:
 288                         return GICD_IROUTERnE;
 289                 default:
 290                         break;
 291                 }
 292                 break;
 293         default:
 294                 break;
 295         }
 296
 297         WARN_ON(1);
 298         *index = d->hwirq;
 299         return offset;
 300 }
 301
 302 static int gic_peek_irq(struct irq_data *d, u32 offset)
 303 {
 304         void __iomem *base;
 305         u32 index, mask;
 306
 307         offset = convert_offset_index(d, offset, &index);
 308         mask = 1 << (index % 32);
 309
 310         if (gic_irq_in_rdist(d))
 311                 base = gic_data_rdist_sgi_base();
 312         else
 313                 base = gic_data.dist_base;
 314
 315         return !!(readl_relaxed(base + offset + (index / 32) * 4) & mask);
 316 }
 317
 318 static void gic_poke_irq(struct irq_data *d, u32 offset)
 319 {
 320         void (*rwp_wait)(void);
 321         void __iomem *base;
 322         u32 index, mask;
 323
 324         offset = convert_offset_index(d, offset, &index);
 325         mask = 1 << (index % 32);
 326
 327         if (gic_irq_in_rdist(d)) {
 328                 base = gic_data_rdist_sgi_base();
 329                 rwp_wait = gic_redist_wait_for_rwp;
 330         } else {
 331                 base = gic_data.dist_base;
 332                 rwp_wait = gic_dist_wait_for_rwp;
 333         }
 334
 335         writel_relaxed(mask, base + offset + (index / 32) * 4);
 336         rwp_wait();
 337 }
 338
 339 static void gic_mask_irq(struct irq_data *d)
 340 {
 341         gic_poke_irq(d, GICD_ICENABLER);
 342 }
 343
 344 static void gic_eoimode1_mask_irq(struct irq_data *d)
 345 {
 346         gic_mask_irq(d);
 347         /*
 348          * When masking a forwarded interrupt, make sure it is
 349          * deactivated as well.
 350          *
 351          * This ensures that an interrupt that is getting
 352          * disabled/masked will not get "stuck", because there is
 353          * noone to deactivate it (guest is being terminated).
 354          */
 355         if (irqd_is_forwarded_to_vcpu(d))
 356                 gic_poke_irq(d, GICD_ICACTIVER);
 357 }
 358
 359 static void gic_unmask_irq(struct irq_data *d)
 360 {
 361         gic_poke_irq(d, GICD_ISENABLER);
 362 }
 363
 364 static inline bool gic_supports_nmi(void)
 365 {
 366         return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) &&
 367                static_branch_likely(&supports_pseudo_nmis);
 368 }
 369
 370 static int gic_irq_set_irqchip_state(struct irq_data *d,
 371                                      enum irqchip_irq_state which, bool val)
 372 {
 373         u32 reg;
 374
 375         if (d->hwirq >= 8192) /* PPI/SPI only */
 376                 return -EINVAL;
 377
 378         switch (which) {
 379         case IRQCHIP_STATE_PENDING:
 380                 reg = val ? GICD_ISPENDR : GICD_ICPENDR;
 381                 break;
 382
 383         case IRQCHIP_STATE_ACTIVE:
 384                 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;
 385                 break;
 386
 387         case IRQCHIP_STATE_MASKED:
 388                 reg = val ? GICD_ICENABLER : GICD_ISENABLER;
 389                 break;
 390
 391         default:
 392                 return -EINVAL;
 393         }
 394
 395         gic_poke_irq(d, reg);
 396         return 0;
 397 }
 398
 399 static int gic_irq_get_irqchip_state(struct irq_data *d,
 400                                      enum irqchip_irq_state which, bool *val)
 401 {
 402         if (d->hwirq >= 8192) /* PPI/SPI only */
 403                 return -EINVAL;
 404
 405         switch (which) {
 406         case IRQCHIP_STATE_PENDING:
 407                 *val = gic_peek_irq(d, GICD_ISPENDR);
 408                 break;
 409
 410         case IRQCHIP_STATE_ACTIVE:
 411                 *val = gic_peek_irq(d, GICD_ISACTIVER);
 412                 break;
 413
 414         case IRQCHIP_STATE_MASKED:
 415                 *val = !gic_peek_irq(d, GICD_ISENABLER);
 416                 break;
 417
 418         default:
 419                 return -EINVAL;
 420         }
 421
 422         return 0;
 423 }
 424
 425 static void gic_irq_set_prio(struct irq_data *d, u8 prio)
 426 {
 427         void __iomem *base = gic_dist_base(d);
 428         u32 offset, index;
 429
 430         offset = convert_offset_index(d, GICD_IPRIORITYR, &index);
 431
 432         writeb_relaxed(prio, base + offset + index);
 433 }
 434
 435 static u32 gic_get_ppi_index(struct irq_data *d)
 436 {
 437         switch (get_intid_range(d)) {
 438         case PPI_RANGE:
 439                 return d->hwirq - 16;
 440         case EPPI_RANGE:
 441                 return d->hwirq - EPPI_BASE_INTID + 16;
 442         default:
 443                 unreachable();
 444         }
 445 }
 446
 447 static int gic_irq_nmi_setup(struct irq_data *d)
 448 {
 449         struct irq_desc *desc = irq_to_desc(d->irq);
 450
 451         if (!gic_supports_nmi())
 452                 return -EINVAL;
 453
 454         if (gic_peek_irq(d, GICD_ISENABLER)) {
 455                 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);
 456                 return -EINVAL;
 457         }
 458
 459         /*
 460          * A secondary irq_chip should be in charge of LPI request,
 461          * it should not be possible to get there
 462          */
 463         if (WARN_ON(gic_irq(d) >= 8192))
 464                 return -EINVAL;
 465
 466         /* desc lock should already be held */
 467         if (gic_irq_in_rdist(d)) {
 468                 u32 idx = gic_get_ppi_index(d);
 469
 470                 /* Setting up PPI as NMI, only switch handler for first NMI */
 471                 if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) {
 472                         refcount_set(&ppi_nmi_refs[idx], 1);
 473                         desc->handle_irq = handle_percpu_devid_fasteoi_nmi;
 474                 }
 475         } else {
 476                 desc->handle_irq = handle_fasteoi_nmi;
 477         }
 478
 479         gic_irq_set_prio(d, GICD_INT_NMI_PRI);
 480
 481         return 0;
 482 }
 483
 484 static void gic_irq_nmi_teardown(struct irq_data *d)
 485 {
 486         struct irq_desc *desc = irq_to_desc(d->irq);
 487
 488         if (WARN_ON(!gic_supports_nmi()))
 489                 return;
 490
 491         if (gic_peek_irq(d, GICD_ISENABLER)) {
 492                 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);
 493                 return;
 494         }
 495
 496         /*
 497          * A secondary irq_chip should be in charge of LPI request,
 498          * it should not be possible to get there
 499          */
 500         if (WARN_ON(gic_irq(d) >= 8192))
 501                 return;
 502
 503         /* desc lock should already be held */
 504         if (gic_irq_in_rdist(d)) {
 505                 u32 idx = gic_get_ppi_index(d);
 506
 507                 /* Tearing down NMI, only switch handler for last NMI */
 508                 if (refcount_dec_and_test(&ppi_nmi_refs[idx]))
 509                         desc->handle_irq = handle_percpu_devid_irq;
 510         } else {
 511                 desc->handle_irq = handle_fasteoi_irq;
 512         }
 513
 514         gic_irq_set_prio(d, GICD_INT_DEF_PRI);
 515 }
 516
 517 static void gic_eoi_irq(struct irq_data *d)
 518 {
 519         gic_write_eoir(gic_irq(d));
 520 }
 521
 522 static void gic_eoimode1_eoi_irq(struct irq_data *d)
 523 {
 524         /*
 525          * No need to deactivate an LPI, or an interrupt that
 526          * is is getting forwarded to a vcpu.
 527          */
 528         if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
 529                 return;
 530         gic_write_dir(gic_irq(d));
 531 }
 532
 533 static int gic_set_type(struct irq_data *d, unsigned int type)
 534 {
 535         enum gic_intid_range range;
 536         unsigned int irq = gic_irq(d);
 537         void (*rwp_wait)(void);
 538         void __iomem *base;
 539         u32 offset, index;
 540         int ret;
 541
 542         /* Interrupt configuration for SGIs can't be changed */
 543         if (irq < 16)
 544                 return -EINVAL;
 545
 546         range = get_intid_range(d);
 547
 548         /* SPIs have restrictions on the supported types */
 549         if ((range == SPI_RANGE || range == ESPI_RANGE) &&
 550             type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
 551                 return -EINVAL;
 552
 553         if (gic_irq_in_rdist(d)) {
 554                 base = gic_data_rdist_sgi_base();
 555                 rwp_wait = gic_redist_wait_for_rwp;
 556         } else {
 557                 base = gic_data.dist_base;
 558                 rwp_wait = gic_dist_wait_for_rwp;
 559         }
 560
 561         offset = convert_offset_index(d, GICD_ICFGR, &index);
 562
 563         ret = gic_configure_irq(index, type, base + offset, rwp_wait);
 564         if (ret && (range == PPI_RANGE || range == EPPI_RANGE)) {
 565                 /* Misconfigured PPIs are usually not fatal */
 566                 pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq);
 567                 ret = 0;
 568         }
 569
 570         return ret;
 571 }
 572
 573 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
 574 {
 575         if (vcpu)
 576                 irqd_set_forwarded_to_vcpu(d);
 577         else
 578                 irqd_clr_forwarded_to_vcpu(d);
 579         return 0;
 580 }
 581
 582 static u64 gic_mpidr_to_affinity(unsigned long mpidr)
 583 {
 584         u64 aff;
 585
 586         aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
 587                MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
 588                MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8  |
 589                MPIDR_AFFINITY_LEVEL(mpidr, 0));
 590
 591         return aff;
 592 }
 593
 594 static void gic_deactivate_unhandled(u32 irqnr)
 595 {
 596         if (static_branch_likely(&supports_deactivate_key)) {
 597                 if (irqnr < 8192)
 598                         gic_write_dir(irqnr);
 599         } else {
 600                 gic_write_eoir(irqnr);
 601         }
 602 }
 603
 604 static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs)
 605 {
 606         bool irqs_enabled = interrupts_enabled(regs);
 607         int err;
 608
 609         if (irqs_enabled)
 610                 nmi_enter();
 611
 612         if (static_branch_likely(&supports_deactivate_key))
 613                 gic_write_eoir(irqnr);
 614         /*
 615          * Leave the PSR.I bit set to prevent other NMIs to be
 616          * received while handling this one.
 617          * PSR.I will be restored when we ERET to the
 618          * interrupted context.
 619          */
 620         err = handle_domain_nmi(gic_data.domain, irqnr, regs);
 621         if (err)
 622                 gic_deactivate_unhandled(irqnr);
 623
 624         if (irqs_enabled)
 625                 nmi_exit();
 626 }
 627
 628 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
 629 {
 630         u32 irqnr;
 631
 632         irqnr = gic_read_iar();
 633
 634         if (gic_supports_nmi() &&
 635             unlikely(gic_read_rpr() == GICD_INT_NMI_PRI)) {
 636                 gic_handle_nmi(irqnr, regs);
 637                 return;
 638         }
 639
 640         if (gic_prio_masking_enabled()) {
 641                 gic_pmr_mask_irqs();
 642                 gic_arch_enable_irqs();
 643         }
 644
 645         /* Check for special IDs first */
 646         if ((irqnr >= 1020 && irqnr <= 1023))
 647                 return;
 648
 649         /* Treat anything but SGIs in a uniform way */
 650         if (likely(irqnr > 15)) {
 651                 int err;
 652
 653                 if (static_branch_likely(&supports_deactivate_key))
 654                         gic_write_eoir(irqnr);
 655                 else
 656                         isb();
 657
 658                 err = handle_domain_irq(gic_data.domain, irqnr, regs);
 659                 if (err) {
 660                         WARN_ONCE(true, "Unexpected interrupt received!\n");
 661                         gic_deactivate_unhandled(irqnr);
 662                 }
 663                 return;
 664         }
 665         if (irqnr < 16) {
 666                 gic_write_eoir(irqnr);
 667                 if (static_branch_likely(&supports_deactivate_key))
 668                         gic_write_dir(irqnr);
 669 #ifdef CONFIG_SMP
 670                 /*
 671                  * Unlike GICv2, we don't need an smp_rmb() here.
 672                  * The control dependency from gic_read_iar to
 673                  * the ISB in gic_write_eoir is enough to ensure
 674                  * that any shared data read by handle_IPI will
 675                  * be read after the ACK.
 676                  */
 677                 handle_IPI(irqnr, regs);
 678 #else
 679                 WARN_ONCE(true, "Unexpected SGI received!\n");
 680 #endif
 681         }
 682 }
 683
 684 static u32 gic_get_pribits(void)
 685 {
 686         u32 pribits;
 687
 688         pribits = gic_read_ctlr();
 689         pribits &= ICC_CTLR_EL1_PRI_BITS_MASK;
 690         pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT;
 691         pribits++;
 692
 693         return pribits;
 694 }
 695
 696 static bool gic_has_group0(void)
 697 {
 698         u32 val;
 699         u32 old_pmr;
 700
 701         old_pmr = gic_read_pmr();
 702
 703         /*
 704          * Let's find out if Group0 is under control of EL3 or not by
 705          * setting the highest possible, non-zero priority in PMR.
 706          *
 707          * If SCR_EL3.FIQ is set, the priority gets shifted down in
 708          * order for the CPU interface to set bit 7, and keep the
 709          * actual priority in the non-secure range. In the process, it
 710          * looses the least significant bit and the actual priority
 711          * becomes 0x80. Reading it back returns 0, indicating that
 712          * we're don't have access to Group0.
 713          */
 714         gic_write_pmr(BIT(8 - gic_get_pribits()));
 715         val = gic_read_pmr();
 716
 717         gic_write_pmr(old_pmr);
 718
 719         return val != 0;
 720 }
 721
 722 static void __init gic_dist_init(void)
 723 {
 724         unsigned int i;
 725         u64 affinity;
 726         void __iomem *base = gic_data.dist_base;
 727
 728         /* Disable the distributor */
 729         writel_relaxed(0, base + GICD_CTLR);
 730         gic_dist_wait_for_rwp();
 731
 732         /*
 733          * Configure SPIs as non-secure Group-1. This will only matter
 734          * if the GIC only has a single security state. This will not
 735          * do the right thing if the kernel is running in secure mode,
 736          * but that's not the intended use case anyway.
 737          */
 738         for (i = 32; i < GIC_LINE_NR; i += 32)
 739                 writel_relaxed(~0, base + GICD_IGROUPR + i / 8);
 740
 741         /* Extended SPI range, not handled by the GICv2/GICv3 common code */
 742         for (i = 0; i < GIC_ESPI_NR; i += 32) {
 743                 writel_relaxed(~0U, base + GICD_ICENABLERnE + i / 8);
 744                 writel_relaxed(~0U, base + GICD_ICACTIVERnE + i / 8);
 745         }
 746
 747         for (i = 0; i < GIC_ESPI_NR; i += 32)
 748                 writel_relaxed(~0U, base + GICD_IGROUPRnE + i / 8);
 749
 750         for (i = 0; i < GIC_ESPI_NR; i += 16)
 751                 writel_relaxed(0, base + GICD_ICFGRnE + i / 4);
 752
 753         for (i = 0; i < GIC_ESPI_NR; i += 4)
 754                 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i);
 755
 756         /* Now do the common stuff, and wait for the distributor to drain */
 757         gic_dist_config(base, GIC_LINE_NR, gic_dist_wait_for_rwp);
 758
 759         /* Enable distributor with ARE, Group1 */
 760         writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1,
 761                        base + GICD_CTLR);
 762
 763         /*
 764          * Set all global interrupts to the boot CPU only. ARE must be
 765          * enabled.
 766          */
 767         affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
 768         for (i = 32; i < GIC_LINE_NR; i++)
 769                 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8);
 770
 771         for (i = 0; i < GIC_ESPI_NR; i++)
 772                 gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 8);
 773 }
 774
 775 static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *))
 776 {
 777         int ret = -ENODEV;
 778         int i;
 779
 780         for (i = 0; i < gic_data.nr_redist_regions; i++) {
 781                 void __iomem *ptr = gic_data.redist_regions[i].redist_base;
 782                 u64 typer;
 783                 u32 reg;
 784
 785                 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
 786                 if (reg != GIC_PIDR2_ARCH_GICv3 &&
 787                     reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
 788                         pr_warn("No redistributor present @%p\n", ptr);
 789                         break;
 790                 }
 791
 792                 do {
 793                         typer = gic_read_typer(ptr + GICR_TYPER);
 794                         ret = fn(gic_data.redist_regions + i, ptr);
 795                         if (!ret)
 796                                 return 0;
 797
 798                         if (gic_data.redist_regions[i].single_redist)
 799                                 break;
 800
 801                         if (gic_data.redist_stride) {
 802                                 ptr += gic_data.redist_stride;
 803                         } else {
 804                                 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
 805                                 if (typer & GICR_TYPER_VLPIS)
 806                                         ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
 807                         }
 808                 } while (!(typer & GICR_TYPER_LAST));
 809         }
 810
 811         return ret ? -ENODEV : 0;
 812 }
 813
 814 static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr)
 815 {
 816         unsigned long mpidr = cpu_logical_map(smp_processor_id());
 817         u64 typer;
 818         u32 aff;
 819
 820         /*
 821          * Convert affinity to a 32bit value that can be matched to
 822          * GICR_TYPER bits [63:32].
 823          */
 824         aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
 825                MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
 826                MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
 827                MPIDR_AFFINITY_LEVEL(mpidr, 0));
 828
 829         typer = gic_read_typer(ptr + GICR_TYPER);
 830         if ((typer >> 32) == aff) {
 831                 u64 offset = ptr - region->redist_base;
 832                 gic_data_rdist_rd_base() = ptr;
 833                 gic_data_rdist()->phys_base = region->phys_base + offset;
 834
 835                 pr_info("CPU%d: found redistributor %lx region %d:%pa\n",
 836                         smp_processor_id(), mpidr,
 837                         (int)(region - gic_data.redist_regions),
 838                         &gic_data_rdist()->phys_base);
 839                 return 0;
 840         }
 841
 842         /* Try next one */
 843         return 1;
 844 }
 845
 846 static int gic_populate_rdist(void)
 847 {
 848         if (gic_iterate_rdists(__gic_populate_rdist) == 0)
 849                 return 0;
 850
 851         /* We couldn't even deal with ourselves... */
 852         WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n",
 853              smp_processor_id(),
 854              (unsigned long)cpu_logical_map(smp_processor_id()));
 855         return -ENODEV;
 856 }
 857
 858 static int __gic_update_rdist_properties(struct redist_region *region,
 859                                          void __iomem *ptr)
 860 {
 861         u64 typer = gic_read_typer(ptr + GICR_TYPER);
 862
 863         gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS);
 864
 865         /* RVPEID implies some form of DirectLPI, no matter what the doc says... :-/ */
 866         gic_data.rdists.has_rvpeid &= !!(typer & GICR_TYPER_RVPEID);
 867         gic_data.rdists.has_direct_lpi &= (!!(typer & GICR_TYPER_DirectLPIS) |
 868                                            gic_data.rdists.has_rvpeid);
 869
 870         /* Detect non-sensical configurations */
 871         if (WARN_ON_ONCE(gic_data.rdists.has_rvpeid && !gic_data.rdists.has_vlpis)) {
 872                 gic_data.rdists.has_direct_lpi = false;
 873                 gic_data.rdists.has_vlpis = false;
 874                 gic_data.rdists.has_rvpeid = false;
 875         }
 876
 877         gic_data.ppi_nr = min(GICR_TYPER_NR_PPIS(typer), gic_data.ppi_nr);
 878
 879         return 1;
 880 }
 881
 882 static void gic_update_rdist_properties(void)
 883 {
 884         gic_data.ppi_nr = UINT_MAX;
 885         gic_iterate_rdists(__gic_update_rdist_properties);
 886         if (WARN_ON(gic_data.ppi_nr == UINT_MAX))
 887                 gic_data.ppi_nr = 0;
 888         pr_info("%d PPIs implemented\n", gic_data.ppi_nr);
 889         pr_info("%sVLPI support, %sdirect LPI support, %sRVPEID support\n",
 890                 !gic_data.rdists.has_vlpis ? "no " : "",
 891                 !gic_data.rdists.has_direct_lpi ? "no " : "",
 892                 !gic_data.rdists.has_rvpeid ? "no " : "");
 893 }
 894
 895 /* Check whether it's single security state view */
 896 static inline bool gic_dist_security_disabled(void)
 897 {
 898         return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS;
 899 }
 900
 901 static void gic_cpu_sys_reg_init(void)
 902 {
 903         int i, cpu = smp_processor_id();
 904         u64 mpidr = cpu_logical_map(cpu);
 905         u64 need_rss = MPIDR_RS(mpidr);
 906         bool group0;
 907         u32 pribits;
 908
 909         /*
 910          * Need to check that the SRE bit has actually been set. If
 911          * not, it means that SRE is disabled at EL2. We're going to
 912          * die painfully, and there is nothing we can do about it.
 913          *
 914          * Kindly inform the luser.
 915          */
 916         if (!gic_enable_sre())
 917                 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
 918
 919         pribits = gic_get_pribits();
 920
 921         group0 = gic_has_group0();
 922
 923         /* Set priority mask register */
 924         if (!gic_prio_masking_enabled()) {
 925                 write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1);
 926         } else {
 927                 /*
 928                  * Mismatch configuration with boot CPU, the system is likely
 929                  * to die as interrupt masking will not work properly on all
 930                  * CPUs
 931                  */
 932                 WARN_ON(gic_supports_nmi() && group0 &&
 933                         !gic_dist_security_disabled());
 934         }
 935
 936         /*
 937          * Some firmwares hand over to the kernel with the BPR changed from
 938          * its reset value (and with a value large enough to prevent
 939          * any pre-emptive interrupts from working at all). Writing a zero
 940          * to BPR restores is reset value.
 941          */
 942         gic_write_bpr1(0);
 943
 944         if (static_branch_likely(&supports_deactivate_key)) {
 945                 /* EOI drops priority only (mode 1) */
 946                 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);
 947         } else {
 948                 /* EOI deactivates interrupt too (mode 0) */
 949                 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
 950         }
 951
 952         /* Always whack Group0 before Group1 */
 953         if (group0) {
 954                 switch(pribits) {
 955                 case 8:
 956                 case 7:
 957                         write_gicreg(0, ICC_AP0R3_EL1);
 958                         write_gicreg(0, ICC_AP0R2_EL1);
 959                 /* Fall through */
 960                 case 6:
 961                         write_gicreg(0, ICC_AP0R1_EL1);
 962                 /* Fall through */
 963                 case 5:
 964                 case 4:
 965                         write_gicreg(0, ICC_AP0R0_EL1);
 966                 }
 967
 968                 isb();
 969         }
 970
 971         switch(pribits) {
 972         case 8:
 973         case 7:
 974                 write_gicreg(0, ICC_AP1R3_EL1);
 975                 write_gicreg(0, ICC_AP1R2_EL1);
 976                 /* Fall through */
 977         case 6:
 978                 write_gicreg(0, ICC_AP1R1_EL1);
 979                 /* Fall through */
 980         case 5:
 981         case 4:
 982                 write_gicreg(0, ICC_AP1R0_EL1);
 983         }
 984
 985         isb();
 986
 987         /* ... and let's hit the road... */
 988         gic_write_grpen1(1);
 989
 990         /* Keep the RSS capability status in per_cpu variable */
 991         per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS);
 992
 993         /* Check all the CPUs have capable of sending SGIs to other CPUs */
 994         for_each_online_cpu(i) {
 995                 bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu);
 996
 997                 need_rss |= MPIDR_RS(cpu_logical_map(i));
 998                 if (need_rss && (!have_rss))
 999                         pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n",
1000                                 cpu, (unsigned long)mpidr,
1001                                 i, (unsigned long)cpu_logical_map(i));
1002         }
1003
1004         /**
1005          * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0,
1006          * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED
1007          * UNPREDICTABLE choice of :
1008          *   - The write is ignored.
1009          *   - The RS field is treated as 0.
1010          */
1011         if (need_rss && (!gic_data.has_rss))
1012                 pr_crit_once("RSS is required but GICD doesn't support it\n");
1013 }
1014
1015 static bool gicv3_nolpi;
1016
1017 static int __init gicv3_nolpi_cfg(char *buf)
1018 {
1019         return strtobool(buf, &gicv3_nolpi);
1020 }
1021 early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg);
1022
1023 static int gic_dist_supports_lpis(void)
1024 {
1025         return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) &&
1026                 !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) &&
1027                 !gicv3_nolpi);
1028 }
1029
1030 static void gic_cpu_init(void)
1031 {
1032         void __iomem *rbase;
1033         int i;
1034
1035         /* Register ourselves with the rest of the world */
1036         if (gic_populate_rdist())
1037                 return;
1038
1039         gic_enable_redist(true);
1040
1041         WARN((gic_data.ppi_nr > 16 || GIC_ESPI_NR != 0) &&
1042              !(gic_read_ctlr() & ICC_CTLR_EL1_ExtRange),
1043              "Distributor has extended ranges, but CPU%d doesn't\n",
1044              smp_processor_id());
1045
1046         rbase = gic_data_rdist_sgi_base();
1047
1048         /* Configure SGIs/PPIs as non-secure Group-1 */
1049         for (i = 0; i < gic_data.ppi_nr + 16; i += 32)
1050                 writel_relaxed(~0, rbase + GICR_IGROUPR0 + i / 8);
1051
1052         gic_cpu_config(rbase, gic_data.ppi_nr + 16, gic_redist_wait_for_rwp);
1053
1054         /* initialise system registers */
1055         gic_cpu_sys_reg_init();
1056 }
1057
1058 #ifdef CONFIG_SMP
1059
1060 #define MPIDR_TO_SGI_RS(mpidr)  (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT)
1061 #define MPIDR_TO_SGI_CLUSTER_ID(mpidr)  ((mpidr) & ~0xFUL)
1062
1063 static int gic_starting_cpu(unsigned int cpu)
1064 {
1065         gic_cpu_init();
1066
1067         if (gic_dist_supports_lpis())
1068                 its_cpu_init();
1069
1070         return 0;
1071 }
1072
1073 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
1074                                    unsigned long cluster_id)
1075 {
1076         int next_cpu, cpu = *base_cpu;
1077         unsigned long mpidr = cpu_logical_map(cpu);
1078         u16 tlist = 0;
1079
1080         while (cpu < nr_cpu_ids) {
1081                 tlist |= 1 << (mpidr & 0xf);
1082
1083                 next_cpu = cpumask_next(cpu, mask);
1084                 if (next_cpu >= nr_cpu_ids)
1085                         goto out;
1086                 cpu = next_cpu;
1087
1088                 mpidr = cpu_logical_map(cpu);
1089
1090                 if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) {
1091                         cpu--;
1092                         goto out;
1093                 }
1094         }
1095 out:
1096         *base_cpu = cpu;
1097         return tlist;
1098 }
1099
1100 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \
1101         (MPIDR_AFFINITY_LEVEL(cluster_id, level) \
1102                 << ICC_SGI1R_AFFINITY_## level ##_SHIFT)
1103
1104 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
1105 {
1106         u64 val;
1107
1108         val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3)     |
1109                MPIDR_TO_SGI_AFFINITY(cluster_id, 2)     |
1110                irq << ICC_SGI1R_SGI_ID_SHIFT            |
1111                MPIDR_TO_SGI_AFFINITY(cluster_id, 1)     |
1112                MPIDR_TO_SGI_RS(cluster_id)              |
1113                tlist << ICC_SGI1R_TARGET_LIST_SHIFT);
1114
1115         pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
1116         gic_write_sgi1r(val);
1117 }
1118
1119 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
1120 {
1121         int cpu;
1122
1123         if (WARN_ON(irq >= 16))
1124                 return;
1125
1126         /*
1127          * Ensure that stores to Normal memory are visible to the
1128          * other CPUs before issuing the IPI.
1129          */
1130         wmb();
1131
1132         for_each_cpu(cpu, mask) {
1133                 u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu));
1134                 u16 tlist;
1135
1136                 tlist = gic_compute_target_list(&cpu, mask, cluster_id);
1137                 gic_send_sgi(cluster_id, tlist, irq);
1138         }
1139
1140         /* Force the above writes to ICC_SGI1R_EL1 to be executed */
1141         isb();
1142 }
1143
1144 static void gic_smp_init(void)
1145 {
1146         set_smp_cross_call(gic_raise_softirq);
1147         cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
1148                                   "irqchip/arm/gicv3:starting",
1149                                   gic_starting_cpu, NULL);
1150 }
1151
1152 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1153                             bool force)
1154 {
1155         unsigned int cpu;
1156         u32 offset, index;
1157         void __iomem *reg;
1158         int enabled;
1159         u64 val;
1160
1161         if (force)
1162                 cpu = cpumask_first(mask_val);
1163         else
1164                 cpu = cpumask_any_and(mask_val, cpu_online_mask);
1165
1166         if (cpu >= nr_cpu_ids)
1167                 return -EINVAL;
1168
1169         if (gic_irq_in_rdist(d))
1170                 return -EINVAL;
1171
1172         /* If interrupt was enabled, disable it first */
1173         enabled = gic_peek_irq(d, GICD_ISENABLER);
1174         if (enabled)
1175                 gic_mask_irq(d);
1176
1177         offset = convert_offset_index(d, GICD_IROUTER, &index);
1178         reg = gic_dist_base(d) + offset + (index * 8);
1179         val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
1180
1181         gic_write_irouter(val, reg);
1182
1183         /*
1184          * If the interrupt was enabled, enabled it again. Otherwise,
1185          * just wait for the distributor to have digested our changes.
1186          */
1187         if (enabled)
1188                 gic_unmask_irq(d);
1189         else
1190                 gic_dist_wait_for_rwp();
1191
1192         irq_data_update_effective_affinity(d, cpumask_of(cpu));
1193
1194         return IRQ_SET_MASK_OK_DONE;
1195 }
1196 #else
1197 #define gic_set_affinity        NULL
1198 #define gic_smp_init()          do { } while(0)
1199 #endif
1200
1201 #ifdef CONFIG_CPU_PM
1202 static int gic_cpu_pm_notifier(struct notifier_block *self,
1203                                unsigned long cmd, void *v)
1204 {
1205         if (cmd == CPU_PM_EXIT) {
1206                 if (gic_dist_security_disabled())
1207                         gic_enable_redist(true);
1208                 gic_cpu_sys_reg_init();
1209         } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) {
1210                 gic_write_grpen1(0);
1211                 gic_enable_redist(false);
1212         }
1213         return NOTIFY_OK;
1214 }
1215
1216 static struct notifier_block gic_cpu_pm_notifier_block = {
1217         .notifier_call = gic_cpu_pm_notifier,
1218 };
1219
1220 static void gic_cpu_pm_init(void)
1221 {
1222         cpu_pm_register_notifier(&gic_cpu_pm_notifier_block);
1223 }
1224
1225 #else
1226 static inline void gic_cpu_pm_init(void) { }
1227 #endif /* CONFIG_CPU_PM */
1228
1229 static struct irq_chip gic_chip = {
1230         .name                   = "GICv3",
1231         .irq_mask               = gic_mask_irq,
1232         .irq_unmask             = gic_unmask_irq,
1233         .irq_eoi                = gic_eoi_irq,
1234         .irq_set_type           = gic_set_type,
1235         .irq_set_affinity       = gic_set_affinity,
1236         .irq_get_irqchip_state  = gic_irq_get_irqchip_state,
1237         .irq_set_irqchip_state  = gic_irq_set_irqchip_state,
1238         .irq_nmi_setup          = gic_irq_nmi_setup,
1239         .irq_nmi_teardown       = gic_irq_nmi_teardown,
1240         .flags                  = IRQCHIP_SET_TYPE_MASKED |
1241                                   IRQCHIP_SKIP_SET_WAKE |
1242                                   IRQCHIP_MASK_ON_SUSPEND,
1243 };
1244
1245 static struct irq_chip gic_eoimode1_chip = {
1246         .name                   = "GICv3",
1247         .irq_mask               = gic_eoimode1_mask_irq,
1248         .irq_unmask             = gic_unmask_irq,
1249         .irq_eoi                = gic_eoimode1_eoi_irq,
1250         .irq_set_type           = gic_set_type,
1251         .irq_set_affinity       = gic_set_affinity,
1252         .irq_get_irqchip_state  = gic_irq_get_irqchip_state,
1253         .irq_set_irqchip_state  = gic_irq_set_irqchip_state,
1254         .irq_set_vcpu_affinity  = gic_irq_set_vcpu_affinity,
1255         .irq_nmi_setup          = gic_irq_nmi_setup,
1256         .irq_nmi_teardown       = gic_irq_nmi_teardown,
1257         .flags                  = IRQCHIP_SET_TYPE_MASKED |
1258                                   IRQCHIP_SKIP_SET_WAKE |
1259                                   IRQCHIP_MASK_ON_SUSPEND,
1260 };
1261
1262 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
1263                               irq_hw_number_t hw)
1264 {
1265         struct irq_chip *chip = &gic_chip;
1266
1267         if (static_branch_likely(&supports_deactivate_key))
1268                 chip = &gic_eoimode1_chip;
1269
1270         switch (__get_intid_range(hw)) {
1271         case PPI_RANGE:
1272         case EPPI_RANGE:
1273                 irq_set_percpu_devid(irq);
1274                 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1275                                     handle_percpu_devid_irq, NULL, NULL);
1276                 irq_set_status_flags(irq, IRQ_NOAUTOEN);
1277                 break;
1278
1279         case SPI_RANGE:
1280         case ESPI_RANGE:
1281                 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1282                                     handle_fasteoi_irq, NULL, NULL);
1283                 irq_set_probe(irq);
1284                 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
1285                 break;
1286
1287         case LPI_RANGE:
1288                 if (!gic_dist_supports_lpis())
1289                         return -EPERM;
1290                 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1291                                     handle_fasteoi_irq, NULL, NULL);
1292                 break;
1293
1294         default:
1295                 return -EPERM;
1296         }
1297
1298         return 0;
1299 }
1300
1301 #define GIC_IRQ_TYPE_PARTITION  (GIC_IRQ_TYPE_LPI + 1)
1302
1303 static int gic_irq_domain_translate(struct irq_domain *d,
1304                                     struct irq_fwspec *fwspec,
1305                                     unsigned long *hwirq,
1306                                     unsigned int *type)
1307 {
1308         if (is_of_node(fwspec->fwnode)) {
1309                 if (fwspec->param_count < 3)
1310                         return -EINVAL;
1311
1312                 switch (fwspec->param[0]) {
1313                 case 0:                 /* SPI */
1314                         *hwirq = fwspec->param[1] + 32;
1315                         break;
1316                 case 1:                 /* PPI */
1317                         *hwirq = fwspec->param[1] + 16;
1318                         break;
1319                 case 2:                 /* ESPI */
1320                         *hwirq = fwspec->param[1] + ESPI_BASE_INTID;
1321                         break;
1322                 case 3:                 /* EPPI */
1323                         *hwirq = fwspec->param[1] + EPPI_BASE_INTID;
1324                         break;
1325                 case GIC_IRQ_TYPE_LPI:  /* LPI */
1326                         *hwirq = fwspec->param[1];
1327                         break;
1328                 case GIC_IRQ_TYPE_PARTITION:
1329                         *hwirq = fwspec->param[1];
1330                         if (fwspec->param[1] >= 16)
1331                                 *hwirq += EPPI_BASE_INTID - 16;
1332                         else
1333                                 *hwirq += 16;
1334                         break;
1335                 default:
1336                         return -EINVAL;
1337                 }
1338
1339                 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1340
1341                 /*
1342                  * Make it clear that broken DTs are... broken.
1343                  * Partitionned PPIs are an unfortunate exception.
1344                  */
1345                 WARN_ON(*type == IRQ_TYPE_NONE &&
1346                         fwspec->param[0] != GIC_IRQ_TYPE_PARTITION);
1347                 return 0;
1348         }
1349
1350         if (is_fwnode_irqchip(fwspec->fwnode)) {
1351                 if(fwspec->param_count != 2)
1352                         return -EINVAL;
1353
1354                 *hwirq = fwspec->param[0];
1355                 *type = fwspec->param[1];
1356
1357                 WARN_ON(*type == IRQ_TYPE_NONE);
1358                 return 0;
1359         }
1360
1361         return -EINVAL;
1362 }
1363
1364 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1365                                 unsigned int nr_irqs, void *arg)
1366 {
1367         int i, ret;
1368         irq_hw_number_t hwirq;
1369         unsigned int type = IRQ_TYPE_NONE;
1370         struct irq_fwspec *fwspec = arg;
1371
1372         ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
1373         if (ret)
1374                 return ret;
1375
1376         for (i = 0; i < nr_irqs; i++) {
1377                 ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
1378                 if (ret)
1379                         return ret;
1380         }
1381
1382         return 0;
1383 }
1384
1385 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1386                                 unsigned int nr_irqs)
1387 {
1388         int i;
1389
1390         for (i = 0; i < nr_irqs; i++) {
1391                 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
1392                 irq_set_handler(virq + i, NULL);
1393                 irq_domain_reset_irq_data(d);
1394         }
1395 }
1396
1397 static int gic_irq_domain_select(struct irq_domain *d,
1398                                  struct irq_fwspec *fwspec,
1399                                  enum irq_domain_bus_token bus_token)
1400 {
1401         /* Not for us */
1402         if (fwspec->fwnode != d->fwnode)
1403                 return 0;
1404
1405         /* If this is not DT, then we have a single domain */
1406         if (!is_of_node(fwspec->fwnode))
1407                 return 1;
1408
1409         /*
1410          * If this is a PPI and we have a 4th (non-null) parameter,
1411          * then we need to match the partition domain.
1412          */
1413         if (fwspec->param_count >= 4 &&
1414             fwspec->param[0] == 1 && fwspec->param[3] != 0 &&
1415             gic_data.ppi_descs)
1416                 return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]);
1417
1418         return d == gic_data.domain;
1419 }
1420
1421 static const struct irq_domain_ops gic_irq_domain_ops = {
1422         .translate = gic_irq_domain_translate,
1423         .alloc = gic_irq_domain_alloc,
1424         .free = gic_irq_domain_free,
1425         .select = gic_irq_domain_select,
1426 };
1427
1428 static int partition_domain_translate(struct irq_domain *d,
1429                                       struct irq_fwspec *fwspec,
1430                                       unsigned long *hwirq,
1431                                       unsigned int *type)
1432 {
1433         struct device_node *np;
1434         int ret;
1435
1436         if (!gic_data.ppi_descs)
1437                 return -ENOMEM;
1438
1439         np = of_find_node_by_phandle(fwspec->param[3]);
1440         if (WARN_ON(!np))
1441                 return -EINVAL;
1442
1443         ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]],
1444                                      of_node_to_fwnode(np));
1445         if (ret < 0)
1446                 return ret;
1447
1448         *hwirq = ret;
1449         *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1450
1451         return 0;
1452 }
1453
1454 static const struct irq_domain_ops partition_domain_ops = {
1455         .translate = partition_domain_translate,
1456         .select = gic_irq_domain_select,
1457 };
1458
1459 static bool gic_enable_quirk_msm8996(void *data)
1460 {
1461         struct gic_chip_data *d = data;
1462
1463         d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996;
1464
1465         return true;
1466 }
1467
1468 static bool gic_enable_quirk_cavium_38539(void *data)
1469 {
1470         struct gic_chip_data *d = data;
1471
1472         d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539;
1473
1474         return true;
1475 }
1476
1477 static bool gic_enable_quirk_hip06_07(void *data)
1478 {
1479         struct gic_chip_data *d = data;
1480
1481         /*
1482          * HIP06 GICD_IIDR clashes with GIC-600 product number (despite
1483          * not being an actual ARM implementation). The saving grace is
1484          * that GIC-600 doesn't have ESPI, so nothing to do in that case.
1485          * HIP07 doesn't even have a proper IIDR, and still pretends to
1486          * have ESPI. In both cases, put them right.
1487          */
1488         if (d->rdists.gicd_typer & GICD_TYPER_ESPI) {
1489                 /* Zero both ESPI and the RES0 field next to it... */
1490                 d->rdists.gicd_typer &= ~GENMASK(9, 8);
1491                 return true;
1492         }
1493
1494         return false;
1495 }
1496
1497 static const struct gic_quirk gic_quirks[] = {
1498         {
1499                 .desc   = "GICv3: Qualcomm MSM8996 broken firmware",
1500                 .compatible = "qcom,msm8996-gic-v3",
1501                 .init   = gic_enable_quirk_msm8996,
1502         },
1503         {
1504                 .desc   = "GICv3: HIP06 erratum 161010803",
1505                 .iidr   = 0x0204043b,
1506                 .mask   = 0xffffffff,
1507                 .init   = gic_enable_quirk_hip06_07,
1508         },
1509         {
1510                 .desc   = "GICv3: HIP07 erratum 161010803",
1511                 .iidr   = 0x00000000,
1512                 .mask   = 0xffffffff,
1513                 .init   = gic_enable_quirk_hip06_07,
1514         },
1515         {
1516                 /*
1517                  * Reserved register accesses generate a Synchronous
1518                  * External Abort. This erratum applies to:
1519                  * - ThunderX: CN88xx
1520                  * - OCTEON TX: CN83xx, CN81xx
1521                  * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx*
1522                  */
1523                 .desc   = "GICv3: Cavium erratum 38539",
1524                 .iidr   = 0xa000034c,
1525                 .mask   = 0xe8f00fff,
1526                 .init   = gic_enable_quirk_cavium_38539,
1527         },
1528         {
1529         }
1530 };
1531
1532 static void gic_enable_nmi_support(void)
1533 {
1534         int i;
1535
1536         if (!gic_prio_masking_enabled())
1537                 return;
1538
1539         if (gic_has_group0() && !gic_dist_security_disabled()) {
1540                 pr_warn("SCR_EL3.FIQ is cleared, cannot enable use of pseudo-NMIs\n");
1541                 return;
1542         }
1543
1544         ppi_nmi_refs = kcalloc(gic_data.ppi_nr, sizeof(*ppi_nmi_refs), GFP_KERNEL);
1545         if (!ppi_nmi_refs)
1546                 return;
1547
1548         for (i = 0; i < gic_data.ppi_nr; i++)
1549                 refcount_set(&ppi_nmi_refs[i], 0);
1550
1551         /*
1552          * Linux itself doesn't use 1:N distribution, so has no need to
1553          * set PMHE. The only reason to have it set is if EL3 requires it
1554          * (and we can't change it).
1555          */
1556         if (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK)
1557                 static_branch_enable(&gic_pmr_sync);
1558
1559         pr_info("%s ICC_PMR_EL1 synchronisation\n",
1560                 static_branch_unlikely(&gic_pmr_sync) ? "Forcing" : "Relaxing");
1561
1562         static_branch_enable(&supports_pseudo_nmis);
1563
1564         if (static_branch_likely(&supports_deactivate_key))
1565                 gic_eoimode1_chip.flags |= IRQCHIP_SUPPORTS_NMI;
1566         else
1567                 gic_chip.flags |= IRQCHIP_SUPPORTS_NMI;
1568 }
1569
1570 static int __init gic_init_bases(void __iomem *dist_base,
1571                                  struct redist_region *rdist_regs,
1572                                  u32 nr_redist_regions,
1573                                  u64 redist_stride,
1574                                  struct fwnode_handle *handle)
1575 {
1576         u32 typer;
1577         int err;
1578
1579         if (!is_hyp_mode_available())
1580                 static_branch_disable(&supports_deactivate_key);
1581
1582         if (static_branch_likely(&supports_deactivate_key))
1583                 pr_info("GIC: Using split EOI/Deactivate mode\n");
1584
1585         gic_data.fwnode = handle;
1586         gic_data.dist_base = dist_base;
1587         gic_data.redist_regions = rdist_regs;
1588         gic_data.nr_redist_regions = nr_redist_regions;
1589         gic_data.redist_stride = redist_stride;
1590
1591         /*
1592          * Find out how many interrupts are supported.
1593          */
1594         typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
1595         gic_data.rdists.gicd_typer = typer;
1596
1597         gic_enable_quirks(readl_relaxed(gic_data.dist_base + GICD_IIDR),
1598                           gic_quirks, &gic_data);
1599
1600         pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32);
1601         pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR);
1602
1603         /*
1604          * ThunderX1 explodes on reading GICD_TYPER2, in violation of the
1605          * architecture spec (which says that reserved registers are RES0).
1606          */
1607         if (!(gic_data.flags & FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539))
1608                 gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2);
1609
1610         gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
1611                                                  &gic_data);
1612         irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED);
1613         gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
1614         gic_data.rdists.has_rvpeid = true;
1615         gic_data.rdists.has_vlpis = true;
1616         gic_data.rdists.has_direct_lpi = true;
1617
1618         if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
1619                 err = -ENOMEM;
1620                 goto out_free;
1621         }
1622
1623         gic_data.has_rss = !!(typer & GICD_TYPER_RSS);
1624         pr_info("Distributor has %sRange Selector support\n",
1625                 gic_data.has_rss ? "" : "no ");
1626
1627         if (typer & GICD_TYPER_MBIS) {
1628                 err = mbi_init(handle, gic_data.domain);
1629                 if (err)
1630                         pr_err("Failed to initialize MBIs\n");
1631         }
1632
1633         set_handle_irq(gic_handle_irq);
1634
1635         gic_update_rdist_properties();
1636
1637         gic_smp_init();
1638         gic_dist_init();
1639         gic_cpu_init();
1640         gic_cpu_pm_init();
1641
1642         if (gic_dist_supports_lpis()) {
1643                 its_init(handle, &gic_data.rdists, gic_data.domain);
1644                 its_cpu_init();
1645         } else {
1646                 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1647                         gicv2m_init(handle, gic_data.domain);
1648         }
1649
1650         gic_enable_nmi_support();
1651
1652         return 0;
1653
1654 out_free:
1655         if (gic_data.domain)
1656                 irq_domain_remove(gic_data.domain);
1657         free_percpu(gic_data.rdists.rdist);
1658         return err;
1659 }
1660
1661 static int __init gic_validate_dist_version(void __iomem *dist_base)
1662 {
1663         u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
1664
1665         if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4)
1666                 return -ENODEV;
1667
1668         return 0;
1669 }
1670
1671 /* Create all possible partitions at boot time */
1672 static void __init gic_populate_ppi_partitions(struct device_node *gic_node)
1673 {
1674         struct device_node *parts_node, *child_part;
1675         int part_idx = 0, i;
1676         int nr_parts;
1677         struct partition_affinity *parts;
1678
1679         parts_node = of_get_child_by_name(gic_node, "ppi-partitions");
1680         if (!parts_node)
1681                 return;
1682
1683         gic_data.ppi_descs = kcalloc(gic_data.ppi_nr, sizeof(*gic_data.ppi_descs), GFP_KERNEL);
1684         if (!gic_data.ppi_descs)
1685                 return;
1686
1687         nr_parts = of_get_child_count(parts_node);
1688
1689         if (!nr_parts)
1690                 goto out_put_node;
1691
1692         parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL);
1693         if (WARN_ON(!parts))
1694                 goto out_put_node;
1695
1696         for_each_child_of_node(parts_node, child_part) {
1697                 struct partition_affinity *part;
1698                 int n;
1699
1700                 part = &parts[part_idx];
1701
1702                 part->partition_id = of_node_to_fwnode(child_part);
1703
1704                 pr_info("GIC: PPI partition %pOFn[%d] { ",
1705                         child_part, part_idx);
1706
1707                 n = of_property_count_elems_of_size(child_part, "affinity",
1708                                                     sizeof(u32));
1709                 WARN_ON(n <= 0);
1710
1711                 for (i = 0; i < n; i++) {
1712                         int err, cpu;
1713                         u32 cpu_phandle;
1714                         struct device_node *cpu_node;
1715
1716                         err = of_property_read_u32_index(child_part, "affinity",
1717                                                          i, &cpu_phandle);
1718                         if (WARN_ON(err))
1719                                 continue;
1720
1721                         cpu_node = of_find_node_by_phandle(cpu_phandle);
1722                         if (WARN_ON(!cpu_node))
1723                                 continue;
1724
1725                         cpu = of_cpu_node_to_id(cpu_node);
1726                         if (WARN_ON(cpu < 0))
1727                                 continue;
1728
1729                         pr_cont("%pOF[%d] ", cpu_node, cpu);
1730
1731                         cpumask_set_cpu(cpu, &part->mask);
1732                 }
1733
1734                 pr_cont("}\n");
1735                 part_idx++;
1736         }
1737
1738         for (i = 0; i < gic_data.ppi_nr; i++) {
1739                 unsigned int irq;
1740                 struct partition_desc *desc;
1741                 struct irq_fwspec ppi_fwspec = {
1742                         .fwnode         = gic_data.fwnode,
1743                         .param_count    = 3,
1744                         .param          = {
1745                                 [0]     = GIC_IRQ_TYPE_PARTITION,
1746                                 [1]     = i,
1747                                 [2]     = IRQ_TYPE_NONE,
1748                         },
1749                 };
1750
1751                 irq = irq_create_fwspec_mapping(&ppi_fwspec);
1752                 if (WARN_ON(!irq))
1753                         continue;
1754                 desc = partition_create_desc(gic_data.fwnode, parts, nr_parts,
1755                                              irq, &partition_domain_ops);
1756                 if (WARN_ON(!desc))
1757                         continue;
1758
1759                 gic_data.ppi_descs[i] = desc;
1760         }
1761
1762 out_put_node:
1763         of_node_put(parts_node);
1764 }
1765
1766 static void __init gic_of_setup_kvm_info(struct device_node *node)
1767 {
1768         int ret;
1769         struct resource r;
1770         u32 gicv_idx;
1771
1772         gic_v3_kvm_info.type = GIC_V3;
1773
1774         gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1775         if (!gic_v3_kvm_info.maint_irq)
1776                 return;
1777
1778         if (of_property_read_u32(node, "#redistributor-regions",
1779                                  &gicv_idx))
1780                 gicv_idx = 1;
1781
1782         gicv_idx += 3;  /* Also skip GICD, GICC, GICH */
1783         ret = of_address_to_resource(node, gicv_idx, &r);
1784         if (!ret)
1785                 gic_v3_kvm_info.vcpu = r;
1786
1787         gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
1788         gic_set_kvm_info(&gic_v3_kvm_info);
1789 }
1790
1791 static int __init gic_of_init(struct device_node *node, struct device_node *parent)
1792 {
1793         void __iomem *dist_base;
1794         struct redist_region *rdist_regs;
1795         u64 redist_stride;
1796         u32 nr_redist_regions;
1797         int err, i;
1798
1799         dist_base = of_iomap(node, 0);
1800         if (!dist_base) {
1801                 pr_err("%pOF: unable to map gic dist registers\n", node);
1802                 return -ENXIO;
1803         }
1804
1805         err = gic_validate_dist_version(dist_base);
1806         if (err) {
1807                 pr_err("%pOF: no distributor detected, giving up\n", node);
1808                 goto out_unmap_dist;
1809         }
1810
1811         if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions))
1812                 nr_redist_regions = 1;
1813
1814         rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs),
1815                              GFP_KERNEL);
1816         if (!rdist_regs) {
1817                 err = -ENOMEM;
1818                 goto out_unmap_dist;
1819         }
1820
1821         for (i = 0; i < nr_redist_regions; i++) {
1822                 struct resource res;
1823                 int ret;
1824
1825                 ret = of_address_to_resource(node, 1 + i, &res);
1826                 rdist_regs[i].redist_base = of_iomap(node, 1 + i);
1827                 if (ret || !rdist_regs[i].redist_base) {
1828                         pr_err("%pOF: couldn't map region %d\n", node, i);
1829                         err = -ENODEV;
1830                         goto out_unmap_rdist;
1831                 }
1832                 rdist_regs[i].phys_base = res.start;
1833         }
1834
1835         if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
1836                 redist_stride = 0;
1837
1838         gic_enable_of_quirks(node, gic_quirks, &gic_data);
1839
1840         err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions,
1841                              redist_stride, &node->fwnode);
1842         if (err)
1843                 goto out_unmap_rdist;
1844
1845         gic_populate_ppi_partitions(node);
1846
1847         if (static_branch_likely(&supports_deactivate_key))
1848                 gic_of_setup_kvm_info(node);
1849         return 0;
1850
1851 out_unmap_rdist:
1852         for (i = 0; i < nr_redist_regions; i++)
1853                 if (rdist_regs[i].redist_base)
1854                         iounmap(rdist_regs[i].redist_base);
1855         kfree(rdist_regs);
1856 out_unmap_dist:
1857         iounmap(dist_base);
1858         return err;
1859 }
1860
1861 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
1862
1863 #ifdef CONFIG_ACPI
1864 static struct
1865 {
1866         void __iomem *dist_base;
1867         struct redist_region *redist_regs;
1868         u32 nr_redist_regions;
1869         bool single_redist;
1870         int enabled_rdists;
1871         u32 maint_irq;
1872         int maint_irq_mode;
1873         phys_addr_t vcpu_base;
1874 } acpi_data __initdata;
1875
1876 static void __init
1877 gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base)
1878 {
1879         static int count = 0;
1880
1881         acpi_data.redist_regs[count].phys_base = phys_base;
1882         acpi_data.redist_regs[count].redist_base = redist_base;
1883         acpi_data.redist_regs[count].single_redist = acpi_data.single_redist;
1884         count++;
1885 }
1886
1887 static int __init
1888 gic_acpi_parse_madt_redist(union acpi_subtable_headers *header,
1889                            const unsigned long end)
1890 {
1891         struct acpi_madt_generic_redistributor *redist =
1892                         (struct acpi_madt_generic_redistributor *)header;
1893         void __iomem *redist_base;
1894
1895         redist_base = ioremap(redist->base_address, redist->length);
1896         if (!redist_base) {
1897                 pr_err("Couldn't map GICR region @%llx\n", redist->base_address);
1898                 return -ENOMEM;
1899         }
1900
1901         gic_acpi_register_redist(redist->base_address, redist_base);
1902         return 0;
1903 }
1904
1905 static int __init
1906 gic_acpi_parse_madt_gicc(union acpi_subtable_headers *header,
1907                          const unsigned long end)
1908 {
1909         struct acpi_madt_generic_interrupt *gicc =
1910                                 (struct acpi_madt_generic_interrupt *)header;
1911         u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
1912         u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;
1913         void __iomem *redist_base;
1914
1915         /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */
1916         if (!(gicc->flags & ACPI_MADT_ENABLED))
1917                 return 0;
1918
1919         redist_base = ioremap(gicc->gicr_base_address, size);
1920         if (!redist_base)
1921                 return -ENOMEM;
1922
1923         gic_acpi_register_redist(gicc->gicr_base_address, redist_base);
1924         return 0;
1925 }
1926
1927 static int __init gic_acpi_collect_gicr_base(void)
1928 {
1929         acpi_tbl_entry_handler redist_parser;
1930         enum acpi_madt_type type;
1931
1932         if (acpi_data.single_redist) {
1933                 type = ACPI_MADT_TYPE_GENERIC_INTERRUPT;
1934                 redist_parser = gic_acpi_parse_madt_gicc;
1935         } else {
1936                 type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR;
1937                 redist_parser = gic_acpi_parse_madt_redist;
1938         }
1939
1940         /* Collect redistributor base addresses in GICR entries */
1941         if (acpi_table_parse_madt(type, redist_parser, 0) > 0)
1942                 return 0;
1943
1944         pr_info("No valid GICR entries exist\n");
1945         return -ENODEV;
1946 }
1947
1948 static int __init gic_acpi_match_gicr(union acpi_subtable_headers *header,
1949                                   const unsigned long end)
1950 {
1951         /* Subtable presence means that redist exists, that's it */
1952         return 0;
1953 }
1954
1955 static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header,
1956                                       const unsigned long end)
1957 {
1958         struct acpi_madt_generic_interrupt *gicc =
1959                                 (struct acpi_madt_generic_interrupt *)header;
1960
1961         /*
1962          * If GICC is enabled and has valid gicr base address, then it means
1963          * GICR base is presented via GICC
1964          */
1965         if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) {
1966                 acpi_data.enabled_rdists++;
1967                 return 0;
1968         }
1969
1970         /*
1971          * It's perfectly valid firmware can pass disabled GICC entry, driver
1972          * should not treat as errors, skip the entry instead of probe fail.
1973          */
1974         if (!(gicc->flags & ACPI_MADT_ENABLED))
1975                 return 0;
1976
1977         return -ENODEV;
1978 }
1979
1980 static int __init gic_acpi_count_gicr_regions(void)
1981 {
1982         int count;
1983
1984         /*
1985          * Count how many redistributor regions we have. It is not allowed
1986          * to mix redistributor description, GICR and GICC subtables have to be
1987          * mutually exclusive.
1988          */
1989         count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1990                                       gic_acpi_match_gicr, 0);
1991         if (count > 0) {
1992                 acpi_data.single_redist = false;
1993                 return count;
1994         }
1995
1996         count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1997                                       gic_acpi_match_gicc, 0);
1998         if (count > 0) {
1999                 acpi_data.single_redist = true;
2000                 count = acpi_data.enabled_rdists;
2001         }
2002
2003         return count;
2004 }
2005
2006 static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header,
2007                                            struct acpi_probe_entry *ape)
2008 {
2009         struct acpi_madt_generic_distributor *dist;
2010         int count;
2011
2012         dist = (struct acpi_madt_generic_distributor *)header;
2013         if (dist->version != ape->driver_data)
2014                 return false;
2015
2016         /* We need to do that exercise anyway, the sooner the better */
2017         count = gic_acpi_count_gicr_regions();
2018         if (count <= 0)
2019                 return false;
2020
2021         acpi_data.nr_redist_regions = count;
2022         return true;
2023 }
2024
2025 static int __init gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers *header,
2026                                                 const unsigned long end)
2027 {
2028         struct acpi_madt_generic_interrupt *gicc =
2029                 (struct acpi_madt_generic_interrupt *)header;
2030         int maint_irq_mode;
2031         static int first_madt = true;
2032
2033         /* Skip unusable CPUs */
2034         if (!(gicc->flags & ACPI_MADT_ENABLED))
2035                 return 0;
2036
2037         maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
2038                 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
2039
2040         if (first_madt) {
2041                 first_madt = false;
2042
2043                 acpi_data.maint_irq = gicc->vgic_interrupt;
2044                 acpi_data.maint_irq_mode = maint_irq_mode;
2045                 acpi_data.vcpu_base = gicc->gicv_base_address;
2046
2047                 return 0;
2048         }
2049
2050         /*
2051          * The maintenance interrupt and GICV should be the same for every CPU
2052          */
2053         if ((acpi_data.maint_irq != gicc->vgic_interrupt) ||
2054             (acpi_data.maint_irq_mode != maint_irq_mode) ||
2055             (acpi_data.vcpu_base != gicc->gicv_base_address))
2056                 return -EINVAL;
2057
2058         return 0;
2059 }
2060
2061 static bool __init gic_acpi_collect_virt_info(void)
2062 {
2063         int count;
2064
2065         count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
2066                                       gic_acpi_parse_virt_madt_gicc, 0);
2067
2068         return (count > 0);
2069 }
2070
2071 #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
2072 #define ACPI_GICV2_VCTRL_MEM_SIZE       (SZ_4K)
2073 #define ACPI_GICV2_VCPU_MEM_SIZE        (SZ_8K)
2074
2075 static void __init gic_acpi_setup_kvm_info(void)
2076 {
2077         int irq;
2078
2079         if (!gic_acpi_collect_virt_info()) {
2080                 pr_warn("Unable to get hardware information used for virtualization\n");
2081                 return;
2082         }
2083
2084         gic_v3_kvm_info.type = GIC_V3;
2085
2086         irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
2087                                 acpi_data.maint_irq_mode,
2088                                 ACPI_ACTIVE_HIGH);
2089         if (irq <= 0)
2090                 return;
2091
2092         gic_v3_kvm_info.maint_irq = irq;
2093
2094         if (acpi_data.vcpu_base) {
2095                 struct resource *vcpu = &gic_v3_kvm_info.vcpu;
2096
2097                 vcpu->flags = IORESOURCE_MEM;
2098                 vcpu->start = acpi_data.vcpu_base;
2099                 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
2100         }
2101
2102         gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
2103         gic_set_kvm_info(&gic_v3_kvm_info);
2104 }
2105
2106 static int __init
2107 gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end)
2108 {
2109         struct acpi_madt_generic_distributor *dist;
2110         struct fwnode_handle *domain_handle;
2111         size_t size;
2112         int i, err;
2113
2114         /* Get distributor base address */
2115         dist = (struct acpi_madt_generic_distributor *)header;
2116         acpi_data.dist_base = ioremap(dist->base_address,
2117                                       ACPI_GICV3_DIST_MEM_SIZE);
2118         if (!acpi_data.dist_base) {
2119                 pr_err("Unable to map GICD registers\n");
2120                 return -ENOMEM;
2121         }
2122
2123         err = gic_validate_dist_version(acpi_data.dist_base);
2124         if (err) {
2125                 pr_err("No distributor detected at @%p, giving up\n",
2126                        acpi_data.dist_base);
2127                 goto out_dist_unmap;
2128         }
2129
2130         size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions;
2131         acpi_data.redist_regs = kzalloc(size, GFP_KERNEL);
2132         if (!acpi_data.redist_regs) {
2133                 err = -ENOMEM;
2134                 goto out_dist_unmap;
2135         }
2136
2137         err = gic_acpi_collect_gicr_base();
2138         if (err)
2139                 goto out_redist_unmap;
2140
2141         domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
2142         if (!domain_handle) {
2143                 err = -ENOMEM;
2144                 goto out_redist_unmap;
2145         }
2146
2147         err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs,
2148                              acpi_data.nr_redist_regions, 0, domain_handle);
2149         if (err)
2150                 goto out_fwhandle_free;
2151
2152         acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
2153
2154         if (static_branch_likely(&supports_deactivate_key))
2155                 gic_acpi_setup_kvm_info();
2156
2157         return 0;
2158
2159 out_fwhandle_free:
2160         irq_domain_free_fwnode(domain_handle);
2161 out_redist_unmap:
2162         for (i = 0; i < acpi_data.nr_redist_regions; i++)
2163                 if (acpi_data.redist_regs[i].redist_base)
2164                         iounmap(acpi_data.redist_regs[i].redist_base);
2165         kfree(acpi_data.redist_regs);
2166 out_dist_unmap:
2167         iounmap(acpi_data.dist_base);
2168         return err;
2169 }
2170 IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2171                      acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3,
2172                      gic_acpi_init);
2173 IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2174                      acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4,
2175                      gic_acpi_init);
2176 IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2177                      acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE,
2178                      gic_acpi_init);
2179 #endif