1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
7 #include <linux/acpi.h>
8 #include <linux/acpi_iort.h>
9 #include <linux/bitfield.h>
10 #include <linux/bitmap.h>
11 #include <linux/cpu.h>
12 #include <linux/crash_dump.h>
13 #include <linux/delay.h>
14 #include <linux/efi.h>
15 #include <linux/interrupt.h>
16 #include <linux/iommu.h>
17 #include <linux/iopoll.h>
18 #include <linux/irqdomain.h>
19 #include <linux/list.h>
20 #include <linux/log2.h>
21 #include <linux/memblock.h>
23 #include <linux/msi.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_pci.h>
28 #include <linux/of_platform.h>
29 #include <linux/percpu.h>
30 #include <linux/slab.h>
31 #include <linux/syscore_ops.h>
33 #include <linux/irqchip.h>
34 #include <linux/irqchip/arm-gic-v3.h>
35 #include <linux/irqchip/arm-gic-v4.h>
37 #include <asm/cputype.h>
38 #include <asm/exception.h>
40 #include "irq-gic-common.h"
42 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
43 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
44 #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
45 #define ITS_FLAGS_FORCE_NON_SHAREABLE (1ULL << 3)
47 #define RD_LOCAL_LPI_ENABLED BIT(0)
48 #define RD_LOCAL_PENDTABLE_PREALLOCATED BIT(1)
49 #define RD_LOCAL_MEMRESERVE_DONE BIT(2)
51 static u32 lpi_id_bits;
54 * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
55 * deal with (one configuration byte per interrupt). PENDBASE has to
56 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
58 #define LPI_NRBITS lpi_id_bits
59 #define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
60 #define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
62 #define LPI_PROP_DEFAULT_PRIO GICD_INT_DEF_PRI
65 * Collection structure - just an ID, and a redistributor address to
66 * ping. We use one per CPU as a bag of interrupts assigned to this
69 struct its_collection {
75 * The ITS_BASER structure - contains memory information, cached
76 * value of BASER register configuration and ITS page size.
88 * The ITS structure - contains most of the infrastructure, with the
89 * top-level MSI domain, the command queue, the collections, and the
90 * list of devices writing to it.
92 * dev_alloc_lock has to be taken for device allocations, while the
93 * spinlock must be taken to parse data structures such as the device
98 struct mutex dev_alloc_lock;
99 struct list_head entry;
101 void __iomem *sgir_base;
102 phys_addr_t phys_base;
103 struct its_cmd_block *cmd_base;
104 struct its_cmd_block *cmd_write;
105 struct its_baser tables[GITS_BASER_NR_REGS];
106 struct its_collection *collections;
107 struct fwnode_handle *fwnode_handle;
108 u64 (*get_msi_base)(struct its_device *its_dev);
113 struct list_head its_device_list;
115 unsigned long list_nr;
117 unsigned int msi_domain_flags;
118 u32 pre_its_base; /* for Socionext Synquacer */
119 int vlpi_redist_offset;
122 #define is_v4(its) (!!((its)->typer & GITS_TYPER_VLPIS))
123 #define is_v4_1(its) (!!((its)->typer & GITS_TYPER_VMAPP))
124 #define device_ids(its) (FIELD_GET(GITS_TYPER_DEVBITS, (its)->typer) + 1)
126 #define ITS_ITT_ALIGN SZ_256
128 /* The maximum number of VPEID bits supported by VLPI commands */
129 #define ITS_MAX_VPEID_BITS \
132 if (gic_rdists->has_rvpeid && \
133 gic_rdists->gicd_typer2 & GICD_TYPER2_VIL) \
134 nvpeid = 1 + (gic_rdists->gicd_typer2 & \
139 #define ITS_MAX_VPEID (1 << (ITS_MAX_VPEID_BITS))
141 /* Convert page order to size in bytes */
142 #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o))
144 struct event_lpi_map {
145 unsigned long *lpi_map;
147 irq_hw_number_t lpi_base;
149 raw_spinlock_t vlpi_lock;
151 struct its_vlpi_map *vlpi_maps;
156 * The ITS view of a device - belongs to an ITS, owns an interrupt
157 * translation table, and a list of interrupts. If it some of its
158 * LPIs are injected into a guest (GICv4), the event_map.vm field
159 * indicates which one.
162 struct list_head entry;
163 struct its_node *its;
164 struct event_lpi_map event_map;
173 struct its_device *dev;
174 struct its_vpe **vpes;
178 struct cpu_lpi_count {
183 static DEFINE_PER_CPU(struct cpu_lpi_count, cpu_lpi_count);
185 static LIST_HEAD(its_nodes);
186 static DEFINE_RAW_SPINLOCK(its_lock);
187 static struct rdists *gic_rdists;
188 static struct irq_domain *its_parent;
190 static unsigned long its_list_map;
191 static u16 vmovp_seq_num;
192 static DEFINE_RAW_SPINLOCK(vmovp_lock);
194 static DEFINE_IDA(its_vpeid_ida);
196 #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
197 #define gic_data_rdist_cpu(cpu) (per_cpu_ptr(gic_rdists->rdist, cpu))
198 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
199 #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)
202 * Skip ITSs that have no vLPIs mapped, unless we're on GICv4.1, as we
203 * always have vSGIs mapped.
205 static bool require_its_list_vmovp(struct its_vm *vm, struct its_node *its)
207 return (gic_rdists->has_rvpeid || vm->vlpi_count[its->list_nr]);
210 static u16 get_its_list(struct its_vm *vm)
212 struct its_node *its;
213 unsigned long its_list = 0;
215 list_for_each_entry(its, &its_nodes, entry) {
219 if (require_its_list_vmovp(vm, its))
220 __set_bit(its->list_nr, &its_list);
223 return (u16)its_list;
226 static inline u32 its_get_event_id(struct irq_data *d)
228 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
229 return d->hwirq - its_dev->event_map.lpi_base;
232 static struct its_collection *dev_event_to_col(struct its_device *its_dev,
235 struct its_node *its = its_dev->its;
237 return its->collections + its_dev->event_map.col_map[event];
240 static struct its_vlpi_map *dev_event_to_vlpi_map(struct its_device *its_dev,
243 if (WARN_ON_ONCE(event >= its_dev->event_map.nr_lpis))
246 return &its_dev->event_map.vlpi_maps[event];
249 static struct its_vlpi_map *get_vlpi_map(struct irq_data *d)
251 if (irqd_is_forwarded_to_vcpu(d)) {
252 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
253 u32 event = its_get_event_id(d);
255 return dev_event_to_vlpi_map(its_dev, event);
261 static int vpe_to_cpuid_lock(struct its_vpe *vpe, unsigned long *flags)
263 raw_spin_lock_irqsave(&vpe->vpe_lock, *flags);
267 static void vpe_to_cpuid_unlock(struct its_vpe *vpe, unsigned long flags)
269 raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);
272 static struct irq_chip its_vpe_irq_chip;
274 static int irq_to_cpuid_lock(struct irq_data *d, unsigned long *flags)
276 struct its_vpe *vpe = NULL;
279 if (d->chip == &its_vpe_irq_chip) {
280 vpe = irq_data_get_irq_chip_data(d);
282 struct its_vlpi_map *map = get_vlpi_map(d);
288 cpu = vpe_to_cpuid_lock(vpe, flags);
290 /* Physical LPIs are already locked via the irq_desc lock */
291 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
292 cpu = its_dev->event_map.col_map[its_get_event_id(d)];
293 /* Keep GCC quiet... */
300 static void irq_to_cpuid_unlock(struct irq_data *d, unsigned long flags)
302 struct its_vpe *vpe = NULL;
304 if (d->chip == &its_vpe_irq_chip) {
305 vpe = irq_data_get_irq_chip_data(d);
307 struct its_vlpi_map *map = get_vlpi_map(d);
313 vpe_to_cpuid_unlock(vpe, flags);
316 static struct its_collection *valid_col(struct its_collection *col)
318 if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0)))
324 static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe)
326 if (valid_col(its->collections + vpe->col_idx))
333 * ITS command descriptors - parameters to be encoded in a command
336 struct its_cmd_desc {
339 struct its_device *dev;
344 struct its_device *dev;
349 struct its_device *dev;
354 struct its_device *dev;
359 struct its_collection *col;
364 struct its_device *dev;
370 struct its_device *dev;
371 struct its_collection *col;
376 struct its_device *dev;
381 struct its_collection *col;
390 struct its_collection *col;
396 struct its_device *dev;
404 struct its_device *dev;
411 struct its_collection *col;
432 * The ITS command block, which is what the ITS actually parses.
434 struct its_cmd_block {
437 __le64 raw_cmd_le[4];
441 #define ITS_CMD_QUEUE_SZ SZ_64K
442 #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
444 typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *,
445 struct its_cmd_block *,
446 struct its_cmd_desc *);
448 typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *,
449 struct its_cmd_block *,
450 struct its_cmd_desc *);
452 static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
454 u64 mask = GENMASK_ULL(h, l);
456 *raw_cmd |= (val << l) & mask;
459 static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
461 its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
464 static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
466 its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
469 static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
471 its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
474 static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
476 its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
479 static void its_encode_size(struct its_cmd_block *cmd, u8 size)
481 its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
484 static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
486 its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8);
489 static void its_encode_valid(struct its_cmd_block *cmd, int valid)
491 its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
494 static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
496 its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16);
499 static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
501 its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
504 static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)
506 its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32);
509 static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)
511 its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0);
514 static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)
516 its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32);
519 static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)
521 its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0);
524 static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)
526 its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32);
529 static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)
531 its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0);
534 static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)
536 its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16);
539 static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)
541 its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0);
544 static void its_encode_vconf_addr(struct its_cmd_block *cmd, u64 vconf_pa)
546 its_mask_encode(&cmd->raw_cmd[0], vconf_pa >> 16, 51, 16);
549 static void its_encode_alloc(struct its_cmd_block *cmd, bool alloc)
551 its_mask_encode(&cmd->raw_cmd[0], alloc, 8, 8);
554 static void its_encode_ptz(struct its_cmd_block *cmd, bool ptz)
556 its_mask_encode(&cmd->raw_cmd[0], ptz, 9, 9);
559 static void its_encode_vmapp_default_db(struct its_cmd_block *cmd,
562 its_mask_encode(&cmd->raw_cmd[1], vpe_db_lpi, 31, 0);
565 static void its_encode_vmovp_default_db(struct its_cmd_block *cmd,
568 its_mask_encode(&cmd->raw_cmd[3], vpe_db_lpi, 31, 0);
571 static void its_encode_db(struct its_cmd_block *cmd, bool db)
573 its_mask_encode(&cmd->raw_cmd[2], db, 63, 63);
576 static void its_encode_sgi_intid(struct its_cmd_block *cmd, u8 sgi)
578 its_mask_encode(&cmd->raw_cmd[0], sgi, 35, 32);
581 static void its_encode_sgi_priority(struct its_cmd_block *cmd, u8 prio)
583 its_mask_encode(&cmd->raw_cmd[0], prio >> 4, 23, 20);
586 static void its_encode_sgi_group(struct its_cmd_block *cmd, bool grp)
588 its_mask_encode(&cmd->raw_cmd[0], grp, 10, 10);
591 static void its_encode_sgi_clear(struct its_cmd_block *cmd, bool clr)
593 its_mask_encode(&cmd->raw_cmd[0], clr, 9, 9);
596 static void its_encode_sgi_enable(struct its_cmd_block *cmd, bool en)
598 its_mask_encode(&cmd->raw_cmd[0], en, 8, 8);
601 static inline void its_fixup_cmd(struct its_cmd_block *cmd)
603 /* Let's fixup BE commands */
604 cmd->raw_cmd_le[0] = cpu_to_le64(cmd->raw_cmd[0]);
605 cmd->raw_cmd_le[1] = cpu_to_le64(cmd->raw_cmd[1]);
606 cmd->raw_cmd_le[2] = cpu_to_le64(cmd->raw_cmd[2]);
607 cmd->raw_cmd_le[3] = cpu_to_le64(cmd->raw_cmd[3]);
610 static struct its_collection *its_build_mapd_cmd(struct its_node *its,
611 struct its_cmd_block *cmd,
612 struct its_cmd_desc *desc)
614 unsigned long itt_addr;
615 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
617 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
618 itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
620 its_encode_cmd(cmd, GITS_CMD_MAPD);
621 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
622 its_encode_size(cmd, size - 1);
623 its_encode_itt(cmd, itt_addr);
624 its_encode_valid(cmd, desc->its_mapd_cmd.valid);
631 static struct its_collection *its_build_mapc_cmd(struct its_node *its,
632 struct its_cmd_block *cmd,
633 struct its_cmd_desc *desc)
635 its_encode_cmd(cmd, GITS_CMD_MAPC);
636 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
637 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
638 its_encode_valid(cmd, desc->its_mapc_cmd.valid);
642 return desc->its_mapc_cmd.col;
645 static struct its_collection *its_build_mapti_cmd(struct its_node *its,
646 struct its_cmd_block *cmd,
647 struct its_cmd_desc *desc)
649 struct its_collection *col;
651 col = dev_event_to_col(desc->its_mapti_cmd.dev,
652 desc->its_mapti_cmd.event_id);
654 its_encode_cmd(cmd, GITS_CMD_MAPTI);
655 its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
656 its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
657 its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
658 its_encode_collection(cmd, col->col_id);
662 return valid_col(col);
665 static struct its_collection *its_build_movi_cmd(struct its_node *its,
666 struct its_cmd_block *cmd,
667 struct its_cmd_desc *desc)
669 struct its_collection *col;
671 col = dev_event_to_col(desc->its_movi_cmd.dev,
672 desc->its_movi_cmd.event_id);
674 its_encode_cmd(cmd, GITS_CMD_MOVI);
675 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
676 its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
677 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
681 return valid_col(col);
684 static struct its_collection *its_build_discard_cmd(struct its_node *its,
685 struct its_cmd_block *cmd,
686 struct its_cmd_desc *desc)
688 struct its_collection *col;
690 col = dev_event_to_col(desc->its_discard_cmd.dev,
691 desc->its_discard_cmd.event_id);
693 its_encode_cmd(cmd, GITS_CMD_DISCARD);
694 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
695 its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
699 return valid_col(col);
702 static struct its_collection *its_build_inv_cmd(struct its_node *its,
703 struct its_cmd_block *cmd,
704 struct its_cmd_desc *desc)
706 struct its_collection *col;
708 col = dev_event_to_col(desc->its_inv_cmd.dev,
709 desc->its_inv_cmd.event_id);
711 its_encode_cmd(cmd, GITS_CMD_INV);
712 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
713 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
717 return valid_col(col);
720 static struct its_collection *its_build_int_cmd(struct its_node *its,
721 struct its_cmd_block *cmd,
722 struct its_cmd_desc *desc)
724 struct its_collection *col;
726 col = dev_event_to_col(desc->its_int_cmd.dev,
727 desc->its_int_cmd.event_id);
729 its_encode_cmd(cmd, GITS_CMD_INT);
730 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
731 its_encode_event_id(cmd, desc->its_int_cmd.event_id);
735 return valid_col(col);
738 static struct its_collection *its_build_clear_cmd(struct its_node *its,
739 struct its_cmd_block *cmd,
740 struct its_cmd_desc *desc)
742 struct its_collection *col;
744 col = dev_event_to_col(desc->its_clear_cmd.dev,
745 desc->its_clear_cmd.event_id);
747 its_encode_cmd(cmd, GITS_CMD_CLEAR);
748 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
749 its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
753 return valid_col(col);
756 static struct its_collection *its_build_invall_cmd(struct its_node *its,
757 struct its_cmd_block *cmd,
758 struct its_cmd_desc *desc)
760 its_encode_cmd(cmd, GITS_CMD_INVALL);
761 its_encode_collection(cmd, desc->its_invall_cmd.col->col_id);
765 return desc->its_invall_cmd.col;
768 static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,
769 struct its_cmd_block *cmd,
770 struct its_cmd_desc *desc)
772 its_encode_cmd(cmd, GITS_CMD_VINVALL);
773 its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);
777 return valid_vpe(its, desc->its_vinvall_cmd.vpe);
780 static struct its_vpe *its_build_vmapp_cmd(struct its_node *its,
781 struct its_cmd_block *cmd,
782 struct its_cmd_desc *desc)
784 unsigned long vpt_addr, vconf_addr;
788 its_encode_cmd(cmd, GITS_CMD_VMAPP);
789 its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);
790 its_encode_valid(cmd, desc->its_vmapp_cmd.valid);
792 if (!desc->its_vmapp_cmd.valid) {
794 alloc = !atomic_dec_return(&desc->its_vmapp_cmd.vpe->vmapp_count);
795 its_encode_alloc(cmd, alloc);
801 vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));
802 target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset;
804 its_encode_target(cmd, target);
805 its_encode_vpt_addr(cmd, vpt_addr);
806 its_encode_vpt_size(cmd, LPI_NRBITS - 1);
811 vconf_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->its_vm->vprop_page));
813 alloc = !atomic_fetch_inc(&desc->its_vmapp_cmd.vpe->vmapp_count);
815 its_encode_alloc(cmd, alloc);
818 * GICv4.1 provides a way to get the VLPI state, which needs the vPE
819 * to be unmapped first, and in this case, we may remap the vPE
820 * back while the VPT is not empty. So we can't assume that the
821 * VPT is empty on map. This is why we never advertise PTZ.
823 its_encode_ptz(cmd, false);
824 its_encode_vconf_addr(cmd, vconf_addr);
825 its_encode_vmapp_default_db(cmd, desc->its_vmapp_cmd.vpe->vpe_db_lpi);
830 return valid_vpe(its, desc->its_vmapp_cmd.vpe);
833 static struct its_vpe *its_build_vmapti_cmd(struct its_node *its,
834 struct its_cmd_block *cmd,
835 struct its_cmd_desc *desc)
839 if (!is_v4_1(its) && desc->its_vmapti_cmd.db_enabled)
840 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;
844 its_encode_cmd(cmd, GITS_CMD_VMAPTI);
845 its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id);
846 its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);
847 its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id);
848 its_encode_db_phys_id(cmd, db);
849 its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id);
853 return valid_vpe(its, desc->its_vmapti_cmd.vpe);
856 static struct its_vpe *its_build_vmovi_cmd(struct its_node *its,
857 struct its_cmd_block *cmd,
858 struct its_cmd_desc *desc)
862 if (!is_v4_1(its) && desc->its_vmovi_cmd.db_enabled)
863 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;
867 its_encode_cmd(cmd, GITS_CMD_VMOVI);
868 its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id);
869 its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);
870 its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id);
871 its_encode_db_phys_id(cmd, db);
872 its_encode_db_valid(cmd, true);
876 return valid_vpe(its, desc->its_vmovi_cmd.vpe);
879 static struct its_vpe *its_build_vmovp_cmd(struct its_node *its,
880 struct its_cmd_block *cmd,
881 struct its_cmd_desc *desc)
885 target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset;
886 its_encode_cmd(cmd, GITS_CMD_VMOVP);
887 its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num);
888 its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list);
889 its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);
890 its_encode_target(cmd, target);
893 its_encode_db(cmd, true);
894 its_encode_vmovp_default_db(cmd, desc->its_vmovp_cmd.vpe->vpe_db_lpi);
899 return valid_vpe(its, desc->its_vmovp_cmd.vpe);
902 static struct its_vpe *its_build_vinv_cmd(struct its_node *its,
903 struct its_cmd_block *cmd,
904 struct its_cmd_desc *desc)
906 struct its_vlpi_map *map;
908 map = dev_event_to_vlpi_map(desc->its_inv_cmd.dev,
909 desc->its_inv_cmd.event_id);
911 its_encode_cmd(cmd, GITS_CMD_INV);
912 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
913 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
917 return valid_vpe(its, map->vpe);
920 static struct its_vpe *its_build_vint_cmd(struct its_node *its,
921 struct its_cmd_block *cmd,
922 struct its_cmd_desc *desc)
924 struct its_vlpi_map *map;
926 map = dev_event_to_vlpi_map(desc->its_int_cmd.dev,
927 desc->its_int_cmd.event_id);
929 its_encode_cmd(cmd, GITS_CMD_INT);
930 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
931 its_encode_event_id(cmd, desc->its_int_cmd.event_id);
935 return valid_vpe(its, map->vpe);
938 static struct its_vpe *its_build_vclear_cmd(struct its_node *its,
939 struct its_cmd_block *cmd,
940 struct its_cmd_desc *desc)
942 struct its_vlpi_map *map;
944 map = dev_event_to_vlpi_map(desc->its_clear_cmd.dev,
945 desc->its_clear_cmd.event_id);
947 its_encode_cmd(cmd, GITS_CMD_CLEAR);
948 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
949 its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
953 return valid_vpe(its, map->vpe);
956 static struct its_vpe *its_build_invdb_cmd(struct its_node *its,
957 struct its_cmd_block *cmd,
958 struct its_cmd_desc *desc)
960 if (WARN_ON(!is_v4_1(its)))
963 its_encode_cmd(cmd, GITS_CMD_INVDB);
964 its_encode_vpeid(cmd, desc->its_invdb_cmd.vpe->vpe_id);
968 return valid_vpe(its, desc->its_invdb_cmd.vpe);
971 static struct its_vpe *its_build_vsgi_cmd(struct its_node *its,
972 struct its_cmd_block *cmd,
973 struct its_cmd_desc *desc)
975 if (WARN_ON(!is_v4_1(its)))
978 its_encode_cmd(cmd, GITS_CMD_VSGI);
979 its_encode_vpeid(cmd, desc->its_vsgi_cmd.vpe->vpe_id);
980 its_encode_sgi_intid(cmd, desc->its_vsgi_cmd.sgi);
981 its_encode_sgi_priority(cmd, desc->its_vsgi_cmd.priority);
982 its_encode_sgi_group(cmd, desc->its_vsgi_cmd.group);
983 its_encode_sgi_clear(cmd, desc->its_vsgi_cmd.clear);
984 its_encode_sgi_enable(cmd, desc->its_vsgi_cmd.enable);
988 return valid_vpe(its, desc->its_vsgi_cmd.vpe);
991 static u64 its_cmd_ptr_to_offset(struct its_node *its,
992 struct its_cmd_block *ptr)
994 return (ptr - its->cmd_base) * sizeof(*ptr);
997 static int its_queue_full(struct its_node *its)
1002 widx = its->cmd_write - its->cmd_base;
1003 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
1005 /* This is incredibly unlikely to happen, unless the ITS locks up. */
1006 if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
1012 static struct its_cmd_block *its_allocate_entry(struct its_node *its)
1014 struct its_cmd_block *cmd;
1015 u32 count = 1000000; /* 1s! */
1017 while (its_queue_full(its)) {
1020 pr_err_ratelimited("ITS queue not draining\n");
1027 cmd = its->cmd_write++;
1029 /* Handle queue wrapping */
1030 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
1031 its->cmd_write = its->cmd_base;
1034 cmd->raw_cmd[0] = 0;
1035 cmd->raw_cmd[1] = 0;
1036 cmd->raw_cmd[2] = 0;
1037 cmd->raw_cmd[3] = 0;
1042 static struct its_cmd_block *its_post_commands(struct its_node *its)
1044 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
1046 writel_relaxed(wr, its->base + GITS_CWRITER);
1048 return its->cmd_write;
1051 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
1054 * Make sure the commands written to memory are observable by
1057 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
1058 gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
1063 static int its_wait_for_range_completion(struct its_node *its,
1065 struct its_cmd_block *to)
1067 u64 rd_idx, to_idx, linear_idx;
1068 u32 count = 1000000; /* 1s! */
1070 /* Linearize to_idx if the command set has wrapped around */
1071 to_idx = its_cmd_ptr_to_offset(its, to);
1072 if (to_idx < prev_idx)
1073 to_idx += ITS_CMD_QUEUE_SZ;
1075 linear_idx = prev_idx;
1080 rd_idx = readl_relaxed(its->base + GITS_CREADR);
1083 * Compute the read pointer progress, taking the
1084 * potential wrap-around into account.
1086 delta = rd_idx - prev_idx;
1087 if (rd_idx < prev_idx)
1088 delta += ITS_CMD_QUEUE_SZ;
1090 linear_idx += delta;
1091 if (linear_idx >= to_idx)
1096 pr_err_ratelimited("ITS queue timeout (%llu %llu)\n",
1097 to_idx, linear_idx);
1108 /* Warning, macro hell follows */
1109 #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \
1110 void name(struct its_node *its, \
1111 buildtype builder, \
1112 struct its_cmd_desc *desc) \
1114 struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \
1115 synctype *sync_obj; \
1116 unsigned long flags; \
1119 raw_spin_lock_irqsave(&its->lock, flags); \
1121 cmd = its_allocate_entry(its); \
1122 if (!cmd) { /* We're soooooo screewed... */ \
1123 raw_spin_unlock_irqrestore(&its->lock, flags); \
1126 sync_obj = builder(its, cmd, desc); \
1127 its_flush_cmd(its, cmd); \
1130 sync_cmd = its_allocate_entry(its); \
1134 buildfn(its, sync_cmd, sync_obj); \
1135 its_flush_cmd(its, sync_cmd); \
1139 rd_idx = readl_relaxed(its->base + GITS_CREADR); \
1140 next_cmd = its_post_commands(its); \
1141 raw_spin_unlock_irqrestore(&its->lock, flags); \
1143 if (its_wait_for_range_completion(its, rd_idx, next_cmd)) \
1144 pr_err_ratelimited("ITS cmd %ps failed\n", builder); \
1147 static void its_build_sync_cmd(struct its_node *its,
1148 struct its_cmd_block *sync_cmd,
1149 struct its_collection *sync_col)
1151 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
1152 its_encode_target(sync_cmd, sync_col->target_address);
1154 its_fixup_cmd(sync_cmd);
1157 static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
1158 struct its_collection, its_build_sync_cmd)
1160 static void its_build_vsync_cmd(struct its_node *its,
1161 struct its_cmd_block *sync_cmd,
1162 struct its_vpe *sync_vpe)
1164 its_encode_cmd(sync_cmd, GITS_CMD_VSYNC);
1165 its_encode_vpeid(sync_cmd, sync_vpe->vpe_id);
1167 its_fixup_cmd(sync_cmd);
1170 static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,
1171 struct its_vpe, its_build_vsync_cmd)
1173 static void its_send_int(struct its_device *dev, u32 event_id)
1175 struct its_cmd_desc desc;
1177 desc.its_int_cmd.dev = dev;
1178 desc.its_int_cmd.event_id = event_id;
1180 its_send_single_command(dev->its, its_build_int_cmd, &desc);
1183 static void its_send_clear(struct its_device *dev, u32 event_id)
1185 struct its_cmd_desc desc;
1187 desc.its_clear_cmd.dev = dev;
1188 desc.its_clear_cmd.event_id = event_id;
1190 its_send_single_command(dev->its, its_build_clear_cmd, &desc);
1193 static void its_send_inv(struct its_device *dev, u32 event_id)
1195 struct its_cmd_desc desc;
1197 desc.its_inv_cmd.dev = dev;
1198 desc.its_inv_cmd.event_id = event_id;
1200 its_send_single_command(dev->its, its_build_inv_cmd, &desc);
1203 static void its_send_mapd(struct its_device *dev, int valid)
1205 struct its_cmd_desc desc;
1207 desc.its_mapd_cmd.dev = dev;
1208 desc.its_mapd_cmd.valid = !!valid;
1210 its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
1213 static void its_send_mapc(struct its_node *its, struct its_collection *col,
1216 struct its_cmd_desc desc;
1218 desc.its_mapc_cmd.col = col;
1219 desc.its_mapc_cmd.valid = !!valid;
1221 its_send_single_command(its, its_build_mapc_cmd, &desc);
1224 static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
1226 struct its_cmd_desc desc;
1228 desc.its_mapti_cmd.dev = dev;
1229 desc.its_mapti_cmd.phys_id = irq_id;
1230 desc.its_mapti_cmd.event_id = id;
1232 its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
1235 static void its_send_movi(struct its_device *dev,
1236 struct its_collection *col, u32 id)
1238 struct its_cmd_desc desc;
1240 desc.its_movi_cmd.dev = dev;
1241 desc.its_movi_cmd.col = col;
1242 desc.its_movi_cmd.event_id = id;
1244 its_send_single_command(dev->its, its_build_movi_cmd, &desc);
1247 static void its_send_discard(struct its_device *dev, u32 id)
1249 struct its_cmd_desc desc;
1251 desc.its_discard_cmd.dev = dev;
1252 desc.its_discard_cmd.event_id = id;
1254 its_send_single_command(dev->its, its_build_discard_cmd, &desc);
1257 static void its_send_invall(struct its_node *its, struct its_collection *col)
1259 struct its_cmd_desc desc;
1261 desc.its_invall_cmd.col = col;
1263 its_send_single_command(its, its_build_invall_cmd, &desc);
1266 static void its_send_vmapti(struct its_device *dev, u32 id)
1268 struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id);
1269 struct its_cmd_desc desc;
1271 desc.its_vmapti_cmd.vpe = map->vpe;
1272 desc.its_vmapti_cmd.dev = dev;
1273 desc.its_vmapti_cmd.virt_id = map->vintid;
1274 desc.its_vmapti_cmd.event_id = id;
1275 desc.its_vmapti_cmd.db_enabled = map->db_enabled;
1277 its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc);
1280 static void its_send_vmovi(struct its_device *dev, u32 id)
1282 struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id);
1283 struct its_cmd_desc desc;
1285 desc.its_vmovi_cmd.vpe = map->vpe;
1286 desc.its_vmovi_cmd.dev = dev;
1287 desc.its_vmovi_cmd.event_id = id;
1288 desc.its_vmovi_cmd.db_enabled = map->db_enabled;
1290 its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc);
1293 static void its_send_vmapp(struct its_node *its,
1294 struct its_vpe *vpe, bool valid)
1296 struct its_cmd_desc desc;
1298 desc.its_vmapp_cmd.vpe = vpe;
1299 desc.its_vmapp_cmd.valid = valid;
1300 desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];
1302 its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
1305 static void its_send_vmovp(struct its_vpe *vpe)
1307 struct its_cmd_desc desc = {};
1308 struct its_node *its;
1309 unsigned long flags;
1310 int col_id = vpe->col_idx;
1312 desc.its_vmovp_cmd.vpe = vpe;
1314 if (!its_list_map) {
1315 its = list_first_entry(&its_nodes, struct its_node, entry);
1316 desc.its_vmovp_cmd.col = &its->collections[col_id];
1317 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1322 * Yet another marvel of the architecture. If using the
1323 * its_list "feature", we need to make sure that all ITSs
1324 * receive all VMOVP commands in the same order. The only way
1325 * to guarantee this is to make vmovp a serialization point.
1329 raw_spin_lock_irqsave(&vmovp_lock, flags);
1331 desc.its_vmovp_cmd.seq_num = vmovp_seq_num++;
1332 desc.its_vmovp_cmd.its_list = get_its_list(vpe->its_vm);
1335 list_for_each_entry(its, &its_nodes, entry) {
1339 if (!require_its_list_vmovp(vpe->its_vm, its))
1342 desc.its_vmovp_cmd.col = &its->collections[col_id];
1343 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1346 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1349 static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
1351 struct its_cmd_desc desc;
1353 desc.its_vinvall_cmd.vpe = vpe;
1354 its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
1357 static void its_send_vinv(struct its_device *dev, u32 event_id)
1359 struct its_cmd_desc desc;
1362 * There is no real VINV command. This is just a normal INV,
1363 * with a VSYNC instead of a SYNC.
1365 desc.its_inv_cmd.dev = dev;
1366 desc.its_inv_cmd.event_id = event_id;
1368 its_send_single_vcommand(dev->its, its_build_vinv_cmd, &desc);
1371 static void its_send_vint(struct its_device *dev, u32 event_id)
1373 struct its_cmd_desc desc;
1376 * There is no real VINT command. This is just a normal INT,
1377 * with a VSYNC instead of a SYNC.
1379 desc.its_int_cmd.dev = dev;
1380 desc.its_int_cmd.event_id = event_id;
1382 its_send_single_vcommand(dev->its, its_build_vint_cmd, &desc);
1385 static void its_send_vclear(struct its_device *dev, u32 event_id)
1387 struct its_cmd_desc desc;
1390 * There is no real VCLEAR command. This is just a normal CLEAR,
1391 * with a VSYNC instead of a SYNC.
1393 desc.its_clear_cmd.dev = dev;
1394 desc.its_clear_cmd.event_id = event_id;
1396 its_send_single_vcommand(dev->its, its_build_vclear_cmd, &desc);
1399 static void its_send_invdb(struct its_node *its, struct its_vpe *vpe)
1401 struct its_cmd_desc desc;
1403 desc.its_invdb_cmd.vpe = vpe;
1404 its_send_single_vcommand(its, its_build_invdb_cmd, &desc);
1408 * irqchip functions - assumes MSI, mostly.
1410 static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
1412 struct its_vlpi_map *map = get_vlpi_map(d);
1413 irq_hw_number_t hwirq;
1418 va = page_address(map->vm->vprop_page);
1419 hwirq = map->vintid;
1421 /* Remember the updated property */
1422 map->properties &= ~clr;
1423 map->properties |= set | LPI_PROP_GROUP1;
1425 va = gic_rdists->prop_table_va;
1429 cfg = va + hwirq - 8192;
1431 *cfg |= set | LPI_PROP_GROUP1;
1434 * Make the above write visible to the redistributors.
1435 * And yes, we're flushing exactly: One. Single. Byte.
1438 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
1439 gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
1444 static void wait_for_syncr(void __iomem *rdbase)
1446 while (readl_relaxed(rdbase + GICR_SYNCR) & 1)
1450 static void __direct_lpi_inv(struct irq_data *d, u64 val)
1452 void __iomem *rdbase;
1453 unsigned long flags;
1456 /* Target the redistributor this LPI is currently routed to */
1457 cpu = irq_to_cpuid_lock(d, &flags);
1458 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
1460 rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
1461 gic_write_lpir(val, rdbase + GICR_INVLPIR);
1462 wait_for_syncr(rdbase);
1464 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
1465 irq_to_cpuid_unlock(d, flags);
1468 static void direct_lpi_inv(struct irq_data *d)
1470 struct its_vlpi_map *map = get_vlpi_map(d);
1474 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1476 WARN_ON(!is_v4_1(its_dev->its));
1478 val = GICR_INVLPIR_V;
1479 val |= FIELD_PREP(GICR_INVLPIR_VPEID, map->vpe->vpe_id);
1480 val |= FIELD_PREP(GICR_INVLPIR_INTID, map->vintid);
1485 __direct_lpi_inv(d, val);
1488 static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
1490 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1492 lpi_write_config(d, clr, set);
1493 if (gic_rdists->has_direct_lpi &&
1494 (is_v4_1(its_dev->its) || !irqd_is_forwarded_to_vcpu(d)))
1496 else if (!irqd_is_forwarded_to_vcpu(d))
1497 its_send_inv(its_dev, its_get_event_id(d));
1499 its_send_vinv(its_dev, its_get_event_id(d));
1502 static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)
1504 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1505 u32 event = its_get_event_id(d);
1506 struct its_vlpi_map *map;
1509 * GICv4.1 does away with the per-LPI nonsense, nothing to do
1512 if (is_v4_1(its_dev->its))
1515 map = dev_event_to_vlpi_map(its_dev, event);
1517 if (map->db_enabled == enable)
1520 map->db_enabled = enable;
1523 * More fun with the architecture:
1525 * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
1526 * value or to 1023, depending on the enable bit. But that
1527 * would be issuing a mapping for an /existing/ DevID+EventID
1528 * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI
1529 * to the /same/ vPE, using this opportunity to adjust the
1530 * doorbell. Mouahahahaha. We loves it, Precious.
1532 its_send_vmovi(its_dev, event);
1535 static void its_mask_irq(struct irq_data *d)
1537 if (irqd_is_forwarded_to_vcpu(d))
1538 its_vlpi_set_doorbell(d, false);
1540 lpi_update_config(d, LPI_PROP_ENABLED, 0);
1543 static void its_unmask_irq(struct irq_data *d)
1545 if (irqd_is_forwarded_to_vcpu(d))
1546 its_vlpi_set_doorbell(d, true);
1548 lpi_update_config(d, 0, LPI_PROP_ENABLED);
1551 static __maybe_unused u32 its_read_lpi_count(struct irq_data *d, int cpu)
1553 if (irqd_affinity_is_managed(d))
1554 return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1556 return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1559 static void its_inc_lpi_count(struct irq_data *d, int cpu)
1561 if (irqd_affinity_is_managed(d))
1562 atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1564 atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1567 static void its_dec_lpi_count(struct irq_data *d, int cpu)
1569 if (irqd_affinity_is_managed(d))
1570 atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1572 atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1575 static unsigned int cpumask_pick_least_loaded(struct irq_data *d,
1576 const struct cpumask *cpu_mask)
1578 unsigned int cpu = nr_cpu_ids, tmp;
1579 int count = S32_MAX;
1581 for_each_cpu(tmp, cpu_mask) {
1582 int this_count = its_read_lpi_count(d, tmp);
1583 if (this_count < count) {
1593 * As suggested by Thomas Gleixner in:
1594 * https://lore.kernel.org/r/87h80q2aoc.fsf@nanos.tec.linutronix.de
1596 static int its_select_cpu(struct irq_data *d,
1597 const struct cpumask *aff_mask)
1599 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1600 static DEFINE_RAW_SPINLOCK(tmpmask_lock);
1601 static struct cpumask __tmpmask;
1602 struct cpumask *tmpmask;
1603 unsigned long flags;
1605 node = its_dev->its->numa_node;
1606 tmpmask = &__tmpmask;
1608 raw_spin_lock_irqsave(&tmpmask_lock, flags);
1610 if (!irqd_affinity_is_managed(d)) {
1611 /* First try the NUMA node */
1612 if (node != NUMA_NO_NODE) {
1614 * Try the intersection of the affinity mask and the
1615 * node mask (and the online mask, just to be safe).
1617 cpumask_and(tmpmask, cpumask_of_node(node), aff_mask);
1618 cpumask_and(tmpmask, tmpmask, cpu_online_mask);
1621 * Ideally, we would check if the mask is empty, and
1622 * try again on the full node here.
1624 * But it turns out that the way ACPI describes the
1625 * affinity for ITSs only deals about memory, and
1626 * not target CPUs, so it cannot describe a single
1627 * ITS placed next to two NUMA nodes.
1629 * Instead, just fallback on the online mask. This
1630 * diverges from Thomas' suggestion above.
1632 cpu = cpumask_pick_least_loaded(d, tmpmask);
1633 if (cpu < nr_cpu_ids)
1636 /* If we can't cross sockets, give up */
1637 if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144))
1640 /* If the above failed, expand the search */
1643 /* Try the intersection of the affinity and online masks */
1644 cpumask_and(tmpmask, aff_mask, cpu_online_mask);
1646 /* If that doesn't fly, the online mask is the last resort */
1647 if (cpumask_empty(tmpmask))
1648 cpumask_copy(tmpmask, cpu_online_mask);
1650 cpu = cpumask_pick_least_loaded(d, tmpmask);
1652 cpumask_copy(tmpmask, aff_mask);
1654 /* If we cannot cross sockets, limit the search to that node */
1655 if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) &&
1656 node != NUMA_NO_NODE)
1657 cpumask_and(tmpmask, tmpmask, cpumask_of_node(node));
1659 cpu = cpumask_pick_least_loaded(d, tmpmask);
1662 raw_spin_unlock_irqrestore(&tmpmask_lock, flags);
1664 pr_debug("IRQ%d -> %*pbl CPU%d\n", d->irq, cpumask_pr_args(aff_mask), cpu);
1668 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1671 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1672 struct its_collection *target_col;
1673 u32 id = its_get_event_id(d);
1676 /* A forwarded interrupt should use irq_set_vcpu_affinity */
1677 if (irqd_is_forwarded_to_vcpu(d))
1680 prev_cpu = its_dev->event_map.col_map[id];
1681 its_dec_lpi_count(d, prev_cpu);
1684 cpu = its_select_cpu(d, mask_val);
1686 cpu = cpumask_pick_least_loaded(d, mask_val);
1688 if (cpu < 0 || cpu >= nr_cpu_ids)
1691 /* don't set the affinity when the target cpu is same as current one */
1692 if (cpu != prev_cpu) {
1693 target_col = &its_dev->its->collections[cpu];
1694 its_send_movi(its_dev, target_col, id);
1695 its_dev->event_map.col_map[id] = cpu;
1696 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1699 its_inc_lpi_count(d, cpu);
1701 return IRQ_SET_MASK_OK_DONE;
1704 its_inc_lpi_count(d, prev_cpu);
1708 static u64 its_irq_get_msi_base(struct its_device *its_dev)
1710 struct its_node *its = its_dev->its;
1712 return its->phys_base + GITS_TRANSLATER;
1715 static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
1717 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1718 struct its_node *its;
1722 addr = its->get_msi_base(its_dev);
1724 msg->address_lo = lower_32_bits(addr);
1725 msg->address_hi = upper_32_bits(addr);
1726 msg->data = its_get_event_id(d);
1728 iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg);
1731 static int its_irq_set_irqchip_state(struct irq_data *d,
1732 enum irqchip_irq_state which,
1735 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1736 u32 event = its_get_event_id(d);
1738 if (which != IRQCHIP_STATE_PENDING)
1741 if (irqd_is_forwarded_to_vcpu(d)) {
1743 its_send_vint(its_dev, event);
1745 its_send_vclear(its_dev, event);
1748 its_send_int(its_dev, event);
1750 its_send_clear(its_dev, event);
1756 static int its_irq_retrigger(struct irq_data *d)
1758 return !its_irq_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true);
1762 * Two favourable cases:
1764 * (a) Either we have a GICv4.1, and all vPEs have to be mapped at all times
1767 * (b) Or the ITSs do not use a list map, meaning that VMOVP is cheap enough
1768 * and we're better off mapping all VPEs always
1770 * If neither (a) nor (b) is true, then we map vPEs on demand.
1773 static bool gic_requires_eager_mapping(void)
1775 if (!its_list_map || gic_rdists->has_rvpeid)
1781 static void its_map_vm(struct its_node *its, struct its_vm *vm)
1783 unsigned long flags;
1785 if (gic_requires_eager_mapping())
1788 raw_spin_lock_irqsave(&vmovp_lock, flags);
1791 * If the VM wasn't mapped yet, iterate over the vpes and get
1794 vm->vlpi_count[its->list_nr]++;
1796 if (vm->vlpi_count[its->list_nr] == 1) {
1799 for (i = 0; i < vm->nr_vpes; i++) {
1800 struct its_vpe *vpe = vm->vpes[i];
1801 struct irq_data *d = irq_get_irq_data(vpe->irq);
1803 /* Map the VPE to the first possible CPU */
1804 vpe->col_idx = cpumask_first(cpu_online_mask);
1805 its_send_vmapp(its, vpe, true);
1806 its_send_vinvall(its, vpe);
1807 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
1811 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1814 static void its_unmap_vm(struct its_node *its, struct its_vm *vm)
1816 unsigned long flags;
1818 /* Not using the ITS list? Everything is always mapped. */
1819 if (gic_requires_eager_mapping())
1822 raw_spin_lock_irqsave(&vmovp_lock, flags);
1824 if (!--vm->vlpi_count[its->list_nr]) {
1827 for (i = 0; i < vm->nr_vpes; i++)
1828 its_send_vmapp(its, vm->vpes[i], false);
1831 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1834 static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
1836 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1837 u32 event = its_get_event_id(d);
1843 raw_spin_lock(&its_dev->event_map.vlpi_lock);
1845 if (!its_dev->event_map.vm) {
1846 struct its_vlpi_map *maps;
1848 maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps),
1855 its_dev->event_map.vm = info->map->vm;
1856 its_dev->event_map.vlpi_maps = maps;
1857 } else if (its_dev->event_map.vm != info->map->vm) {
1862 /* Get our private copy of the mapping information */
1863 its_dev->event_map.vlpi_maps[event] = *info->map;
1865 if (irqd_is_forwarded_to_vcpu(d)) {
1866 /* Already mapped, move it around */
1867 its_send_vmovi(its_dev, event);
1869 /* Ensure all the VPEs are mapped on this ITS */
1870 its_map_vm(its_dev->its, info->map->vm);
1873 * Flag the interrupt as forwarded so that we can
1874 * start poking the virtual property table.
1876 irqd_set_forwarded_to_vcpu(d);
1878 /* Write out the property to the prop table */
1879 lpi_write_config(d, 0xff, info->map->properties);
1881 /* Drop the physical mapping */
1882 its_send_discard(its_dev, event);
1884 /* and install the virtual one */
1885 its_send_vmapti(its_dev, event);
1887 /* Increment the number of VLPIs */
1888 its_dev->event_map.nr_vlpis++;
1892 raw_spin_unlock(&its_dev->event_map.vlpi_lock);
1896 static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
1898 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1899 struct its_vlpi_map *map;
1902 raw_spin_lock(&its_dev->event_map.vlpi_lock);
1904 map = get_vlpi_map(d);
1906 if (!its_dev->event_map.vm || !map) {
1911 /* Copy our mapping information to the incoming request */
1915 raw_spin_unlock(&its_dev->event_map.vlpi_lock);
1919 static int its_vlpi_unmap(struct irq_data *d)
1921 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1922 u32 event = its_get_event_id(d);
1925 raw_spin_lock(&its_dev->event_map.vlpi_lock);
1927 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) {
1932 /* Drop the virtual mapping */
1933 its_send_discard(its_dev, event);
1935 /* and restore the physical one */
1936 irqd_clr_forwarded_to_vcpu(d);
1937 its_send_mapti(its_dev, d->hwirq, event);
1938 lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO |
1942 /* Potentially unmap the VM from this ITS */
1943 its_unmap_vm(its_dev->its, its_dev->event_map.vm);
1946 * Drop the refcount and make the device available again if
1947 * this was the last VLPI.
1949 if (!--its_dev->event_map.nr_vlpis) {
1950 its_dev->event_map.vm = NULL;
1951 kfree(its_dev->event_map.vlpi_maps);
1955 raw_spin_unlock(&its_dev->event_map.vlpi_lock);
1959 static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
1961 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1963 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
1966 if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)
1967 lpi_update_config(d, 0xff, info->config);
1969 lpi_write_config(d, 0xff, info->config);
1970 its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED));
1975 static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1977 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1978 struct its_cmd_info *info = vcpu_info;
1981 if (!is_v4(its_dev->its))
1984 /* Unmap request? */
1986 return its_vlpi_unmap(d);
1988 switch (info->cmd_type) {
1990 return its_vlpi_map(d, info);
1993 return its_vlpi_get(d, info);
1995 case PROP_UPDATE_VLPI:
1996 case PROP_UPDATE_AND_INV_VLPI:
1997 return its_vlpi_prop_update(d, info);
2004 static struct irq_chip its_irq_chip = {
2006 .irq_mask = its_mask_irq,
2007 .irq_unmask = its_unmask_irq,
2008 .irq_eoi = irq_chip_eoi_parent,
2009 .irq_set_affinity = its_set_affinity,
2010 .irq_compose_msi_msg = its_irq_compose_msi_msg,
2011 .irq_set_irqchip_state = its_irq_set_irqchip_state,
2012 .irq_retrigger = its_irq_retrigger,
2013 .irq_set_vcpu_affinity = its_irq_set_vcpu_affinity,
2018 * How we allocate LPIs:
2020 * lpi_range_list contains ranges of LPIs that are to available to
2021 * allocate from. To allocate LPIs, just pick the first range that
2022 * fits the required allocation, and reduce it by the required
2023 * amount. Once empty, remove the range from the list.
2025 * To free a range of LPIs, add a free range to the list, sort it and
2026 * merge the result if the new range happens to be adjacent to an
2027 * already free block.
2029 * The consequence of the above is that allocation is cost is low, but
2030 * freeing is expensive. We assumes that freeing rarely occurs.
2032 #define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */
2034 static DEFINE_MUTEX(lpi_range_lock);
2035 static LIST_HEAD(lpi_range_list);
2038 struct list_head entry;
2043 static struct lpi_range *mk_lpi_range(u32 base, u32 span)
2045 struct lpi_range *range;
2047 range = kmalloc(sizeof(*range), GFP_KERNEL);
2049 range->base_id = base;
2056 static int alloc_lpi_range(u32 nr_lpis, u32 *base)
2058 struct lpi_range *range, *tmp;
2061 mutex_lock(&lpi_range_lock);
2063 list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) {
2064 if (range->span >= nr_lpis) {
2065 *base = range->base_id;
2066 range->base_id += nr_lpis;
2067 range->span -= nr_lpis;
2069 if (range->span == 0) {
2070 list_del(&range->entry);
2079 mutex_unlock(&lpi_range_lock);
2081 pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis);
2085 static void merge_lpi_ranges(struct lpi_range *a, struct lpi_range *b)
2087 if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list)
2089 if (a->base_id + a->span != b->base_id)
2091 b->base_id = a->base_id;
2093 list_del(&a->entry);
2097 static int free_lpi_range(u32 base, u32 nr_lpis)
2099 struct lpi_range *new, *old;
2101 new = mk_lpi_range(base, nr_lpis);
2105 mutex_lock(&lpi_range_lock);
2107 list_for_each_entry_reverse(old, &lpi_range_list, entry) {
2108 if (old->base_id < base)
2112 * old is the last element with ->base_id smaller than base,
2113 * so new goes right after it. If there are no elements with
2114 * ->base_id smaller than base, &old->entry ends up pointing
2115 * at the head of the list, and inserting new it the start of
2116 * the list is the right thing to do in that case as well.
2118 list_add(&new->entry, &old->entry);
2120 * Now check if we can merge with the preceding and/or
2123 merge_lpi_ranges(old, new);
2124 merge_lpi_ranges(new, list_next_entry(new, entry));
2126 mutex_unlock(&lpi_range_lock);
2130 static int __init its_lpi_init(u32 id_bits)
2132 u32 lpis = (1UL << id_bits) - 8192;
2136 numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer);
2138 if (numlpis > 2 && !WARN_ON(numlpis > lpis)) {
2140 pr_info("ITS: Using hypervisor restricted LPI range [%u]\n",
2145 * Initializing the allocator is just the same as freeing the
2146 * full range of LPIs.
2148 err = free_lpi_range(8192, lpis);
2149 pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis);
2153 static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids)
2155 unsigned long *bitmap = NULL;
2159 err = alloc_lpi_range(nr_irqs, base);
2164 } while (nr_irqs > 0);
2172 bitmap = bitmap_zalloc(nr_irqs, GFP_ATOMIC);
2180 *base = *nr_ids = 0;
2185 static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids)
2187 WARN_ON(free_lpi_range(base, nr_ids));
2188 bitmap_free(bitmap);
2191 static void gic_reset_prop_table(void *va)
2193 /* Priority 0xa0, Group-1, disabled */
2194 memset(va, LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, LPI_PROPBASE_SZ);
2196 /* Make sure the GIC will observe the written configuration */
2197 gic_flush_dcache_to_poc(va, LPI_PROPBASE_SZ);
2200 static struct page *its_allocate_prop_table(gfp_t gfp_flags)
2202 struct page *prop_page;
2204 prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
2208 gic_reset_prop_table(page_address(prop_page));
2213 static void its_free_prop_table(struct page *prop_page)
2215 free_pages((unsigned long)page_address(prop_page),
2216 get_order(LPI_PROPBASE_SZ));
2219 static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size)
2221 phys_addr_t start, end, addr_end;
2225 * We don't bother checking for a kdump kernel as by
2226 * construction, the LPI tables are out of this kernel's
2229 if (is_kdump_kernel())
2232 addr_end = addr + size - 1;
2234 for_each_reserved_mem_range(i, &start, &end) {
2235 if (addr >= start && addr_end <= end)
2239 /* Not found, not a good sign... */
2240 pr_warn("GICv3: Expected reserved range [%pa:%pa], not found\n",
2242 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
2246 static int gic_reserve_range(phys_addr_t addr, unsigned long size)
2248 if (efi_enabled(EFI_CONFIG_TABLES))
2249 return efi_mem_reserve_persistent(addr, size);
2254 static int __init its_setup_lpi_prop_table(void)
2256 if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) {
2259 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
2260 lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1;
2262 gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12);
2263 gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa,
2266 gic_reset_prop_table(gic_rdists->prop_table_va);
2270 lpi_id_bits = min_t(u32,
2271 GICD_TYPER_ID_BITS(gic_rdists->gicd_typer),
2272 ITS_MAX_LPI_NRBITS);
2273 page = its_allocate_prop_table(GFP_NOWAIT);
2275 pr_err("Failed to allocate PROPBASE\n");
2279 gic_rdists->prop_table_pa = page_to_phys(page);
2280 gic_rdists->prop_table_va = page_address(page);
2281 WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa,
2285 pr_info("GICv3: using LPI property table @%pa\n",
2286 &gic_rdists->prop_table_pa);
2288 return its_lpi_init(lpi_id_bits);
2291 static const char *its_base_type_string[] = {
2292 [GITS_BASER_TYPE_DEVICE] = "Devices",
2293 [GITS_BASER_TYPE_VCPU] = "Virtual CPUs",
2294 [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)",
2295 [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections",
2296 [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)",
2297 [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)",
2298 [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)",
2301 static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
2303 u32 idx = baser - its->tables;
2305 return gits_read_baser(its->base + GITS_BASER + (idx << 3));
2308 static void its_write_baser(struct its_node *its, struct its_baser *baser,
2311 u32 idx = baser - its->tables;
2313 gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
2314 baser->val = its_read_baser(its, baser);
2317 static int its_setup_baser(struct its_node *its, struct its_baser *baser,
2318 u64 cache, u64 shr, u32 order, bool indirect)
2320 u64 val = its_read_baser(its, baser);
2321 u64 esz = GITS_BASER_ENTRY_SIZE(val);
2322 u64 type = GITS_BASER_TYPE(val);
2323 u64 baser_phys, tmp;
2324 u32 alloc_pages, psz;
2329 alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
2330 if (alloc_pages > GITS_BASER_PAGES_MAX) {
2331 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
2332 &its->phys_base, its_base_type_string[type],
2333 alloc_pages, GITS_BASER_PAGES_MAX);
2334 alloc_pages = GITS_BASER_PAGES_MAX;
2335 order = get_order(GITS_BASER_PAGES_MAX * psz);
2338 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
2342 base = (void *)page_address(page);
2343 baser_phys = virt_to_phys(base);
2345 /* Check if the physical address of the memory is above 48bits */
2346 if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {
2348 /* 52bit PA is supported only when PageSize=64K */
2349 if (psz != SZ_64K) {
2350 pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
2351 free_pages((unsigned long)base, order);
2355 /* Convert 52bit PA to 48bit field */
2356 baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
2361 (type << GITS_BASER_TYPE_SHIFT) |
2362 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
2363 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) |
2368 val |= indirect ? GITS_BASER_INDIRECT : 0x0;
2372 val |= GITS_BASER_PAGE_SIZE_4K;
2375 val |= GITS_BASER_PAGE_SIZE_16K;
2378 val |= GITS_BASER_PAGE_SIZE_64K;
2382 its_write_baser(its, baser, val);
2385 if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE)
2386 tmp &= ~GITS_BASER_SHAREABILITY_MASK;
2388 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
2390 * Shareability didn't stick. Just use
2391 * whatever the read reported, which is likely
2392 * to be the only thing this redistributor
2393 * supports. If that's zero, make it
2394 * non-cacheable as well.
2396 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
2398 cache = GITS_BASER_nC;
2399 gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
2405 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
2406 &its->phys_base, its_base_type_string[type],
2408 free_pages((unsigned long)base, order);
2412 baser->order = order;
2415 tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
2417 pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
2418 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
2419 its_base_type_string[type],
2420 (unsigned long)virt_to_phys(base),
2421 indirect ? "indirect" : "flat", (int)esz,
2422 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
2427 static bool its_parse_indirect_baser(struct its_node *its,
2428 struct its_baser *baser,
2429 u32 *order, u32 ids)
2431 u64 tmp = its_read_baser(its, baser);
2432 u64 type = GITS_BASER_TYPE(tmp);
2433 u64 esz = GITS_BASER_ENTRY_SIZE(tmp);
2434 u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
2435 u32 new_order = *order;
2436 u32 psz = baser->psz;
2437 bool indirect = false;
2439 /* No need to enable Indirection if memory requirement < (psz*2)bytes */
2440 if ((esz << ids) > (psz * 2)) {
2442 * Find out whether hw supports a single or two-level table by
2443 * table by reading bit at offset '62' after writing '1' to it.
2445 its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
2446 indirect = !!(baser->val & GITS_BASER_INDIRECT);
2450 * The size of the lvl2 table is equal to ITS page size
2451 * which is 'psz'. For computing lvl1 table size,
2452 * subtract ID bits that sparse lvl2 table from 'ids'
2453 * which is reported by ITS hardware times lvl1 table
2456 ids -= ilog2(psz / (int)esz);
2457 esz = GITS_LVL1_ENTRY_SIZE;
2462 * Allocate as many entries as required to fit the
2463 * range of device IDs that the ITS can grok... The ID
2464 * space being incredibly sparse, this results in a
2465 * massive waste of memory if two-level device table
2466 * feature is not supported by hardware.
2468 new_order = max_t(u32, get_order(esz << ids), new_order);
2469 if (new_order > MAX_ORDER) {
2470 new_order = MAX_ORDER;
2471 ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
2472 pr_warn("ITS@%pa: %s Table too large, reduce ids %llu->%u\n",
2473 &its->phys_base, its_base_type_string[type],
2474 device_ids(its), ids);
2482 static u32 compute_common_aff(u64 val)
2486 aff = FIELD_GET(GICR_TYPER_AFFINITY, val);
2487 clpiaff = FIELD_GET(GICR_TYPER_COMMON_LPI_AFF, val);
2489 return aff & ~(GENMASK(31, 0) >> (clpiaff * 8));
2492 static u32 compute_its_aff(struct its_node *its)
2498 * Reencode the ITS SVPET and MPIDR as a GICR_TYPER, and compute
2499 * the resulting affinity. We then use that to see if this match
2502 svpet = FIELD_GET(GITS_TYPER_SVPET, its->typer);
2503 val = FIELD_PREP(GICR_TYPER_COMMON_LPI_AFF, svpet);
2504 val |= FIELD_PREP(GICR_TYPER_AFFINITY, its->mpidr);
2505 return compute_common_aff(val);
2508 static struct its_node *find_sibling_its(struct its_node *cur_its)
2510 struct its_node *its;
2513 if (!FIELD_GET(GITS_TYPER_SVPET, cur_its->typer))
2516 aff = compute_its_aff(cur_its);
2518 list_for_each_entry(its, &its_nodes, entry) {
2521 if (!is_v4_1(its) || its == cur_its)
2524 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer))
2527 if (aff != compute_its_aff(its))
2530 /* GICv4.1 guarantees that the vPE table is GITS_BASER2 */
2531 baser = its->tables[2].val;
2532 if (!(baser & GITS_BASER_VALID))
2541 static void its_free_tables(struct its_node *its)
2545 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2546 if (its->tables[i].base) {
2547 free_pages((unsigned long)its->tables[i].base,
2548 its->tables[i].order);
2549 its->tables[i].base = NULL;
2554 static int its_probe_baser_psz(struct its_node *its, struct its_baser *baser)
2561 val = its_read_baser(its, baser);
2562 val &= ~GITS_BASER_PAGE_SIZE_MASK;
2566 gpsz = GITS_BASER_PAGE_SIZE_64K;
2569 gpsz = GITS_BASER_PAGE_SIZE_16K;
2573 gpsz = GITS_BASER_PAGE_SIZE_4K;
2577 gpsz >>= GITS_BASER_PAGE_SIZE_SHIFT;
2579 val |= FIELD_PREP(GITS_BASER_PAGE_SIZE_MASK, gpsz);
2580 its_write_baser(its, baser, val);
2582 if (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser->val) == gpsz)
2602 static int its_alloc_tables(struct its_node *its)
2604 u64 shr = GITS_BASER_InnerShareable;
2605 u64 cache = GITS_BASER_RaWaWb;
2608 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375)
2609 /* erratum 24313: ignore memory access type */
2610 cache = GITS_BASER_nCnB;
2612 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2613 struct its_baser *baser = its->tables + i;
2614 u64 val = its_read_baser(its, baser);
2615 u64 type = GITS_BASER_TYPE(val);
2616 bool indirect = false;
2619 if (type == GITS_BASER_TYPE_NONE)
2622 if (its_probe_baser_psz(its, baser)) {
2623 its_free_tables(its);
2627 order = get_order(baser->psz);
2630 case GITS_BASER_TYPE_DEVICE:
2631 indirect = its_parse_indirect_baser(its, baser, &order,
2635 case GITS_BASER_TYPE_VCPU:
2637 struct its_node *sibling;
2640 if ((sibling = find_sibling_its(its))) {
2641 *baser = sibling->tables[2];
2642 its_write_baser(its, baser, baser->val);
2647 indirect = its_parse_indirect_baser(its, baser, &order,
2648 ITS_MAX_VPEID_BITS);
2652 err = its_setup_baser(its, baser, cache, shr, order, indirect);
2654 its_free_tables(its);
2658 /* Update settings which will be used for next BASERn */
2659 cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
2660 shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
2666 static u64 inherit_vpe_l1_table_from_its(void)
2668 struct its_node *its;
2672 val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2673 aff = compute_common_aff(val);
2675 list_for_each_entry(its, &its_nodes, entry) {
2681 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer))
2684 if (aff != compute_its_aff(its))
2687 /* GICv4.1 guarantees that the vPE table is GITS_BASER2 */
2688 baser = its->tables[2].val;
2689 if (!(baser & GITS_BASER_VALID))
2692 /* We have a winner! */
2693 gic_data_rdist()->vpe_l1_base = its->tables[2].base;
2695 val = GICR_VPROPBASER_4_1_VALID;
2696 if (baser & GITS_BASER_INDIRECT)
2697 val |= GICR_VPROPBASER_4_1_INDIRECT;
2698 val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE,
2699 FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser));
2700 switch (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser)) {
2701 case GIC_PAGE_SIZE_64K:
2702 addr = GITS_BASER_ADDR_48_to_52(baser);
2705 addr = baser & GENMASK_ULL(47, 12);
2708 val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, addr >> 12);
2709 val |= FIELD_PREP(GICR_VPROPBASER_SHAREABILITY_MASK,
2710 FIELD_GET(GITS_BASER_SHAREABILITY_MASK, baser));
2711 val |= FIELD_PREP(GICR_VPROPBASER_INNER_CACHEABILITY_MASK,
2712 FIELD_GET(GITS_BASER_INNER_CACHEABILITY_MASK, baser));
2713 val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, GITS_BASER_NR_PAGES(baser) - 1);
2721 static u64 inherit_vpe_l1_table_from_rd(cpumask_t **mask)
2727 val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2728 aff = compute_common_aff(val);
2730 for_each_possible_cpu(cpu) {
2731 void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;
2733 if (!base || cpu == smp_processor_id())
2736 val = gic_read_typer(base + GICR_TYPER);
2737 if (aff != compute_common_aff(val))
2741 * At this point, we have a victim. This particular CPU
2742 * has already booted, and has an affinity that matches
2743 * ours wrt CommonLPIAff. Let's use its own VPROPBASER.
2744 * Make sure we don't write the Z bit in that case.
2746 val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER);
2747 val &= ~GICR_VPROPBASER_4_1_Z;
2749 gic_data_rdist()->vpe_l1_base = gic_data_rdist_cpu(cpu)->vpe_l1_base;
2750 *mask = gic_data_rdist_cpu(cpu)->vpe_table_mask;
2758 static bool allocate_vpe_l2_table(int cpu, u32 id)
2760 void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;
2761 unsigned int psz, esz, idx, npg, gpsz;
2766 if (!gic_rdists->has_rvpeid)
2769 /* Skip non-present CPUs */
2773 val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER);
2775 esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val) + 1;
2776 gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val);
2777 npg = FIELD_GET(GICR_VPROPBASER_4_1_SIZE, val) + 1;
2783 case GIC_PAGE_SIZE_4K:
2786 case GIC_PAGE_SIZE_16K:
2789 case GIC_PAGE_SIZE_64K:
2794 /* Don't allow vpe_id that exceeds single, flat table limit */
2795 if (!(val & GICR_VPROPBASER_4_1_INDIRECT))
2796 return (id < (npg * psz / (esz * SZ_8)));
2798 /* Compute 1st level table index & check if that exceeds table limit */
2799 idx = id >> ilog2(psz / (esz * SZ_8));
2800 if (idx >= (npg * psz / GITS_LVL1_ENTRY_SIZE))
2803 table = gic_data_rdist_cpu(cpu)->vpe_l1_base;
2805 /* Allocate memory for 2nd level table */
2807 page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(psz));
2811 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
2812 if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK))
2813 gic_flush_dcache_to_poc(page_address(page), psz);
2815 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
2817 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
2818 if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK))
2819 gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
2821 /* Ensure updated table contents are visible to RD hardware */
2828 static int allocate_vpe_l1_table(void)
2830 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2831 u64 val, gpsz, npg, pa;
2832 unsigned int psz = SZ_64K;
2833 unsigned int np, epp, esz;
2836 if (!gic_rdists->has_rvpeid)
2840 * if VPENDBASER.Valid is set, disable any previously programmed
2841 * VPE by setting PendingLast while clearing Valid. This has the
2842 * effect of making sure no doorbell will be generated and we can
2843 * then safely clear VPROPBASER.Valid.
2845 if (gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER) & GICR_VPENDBASER_Valid)
2846 gicr_write_vpendbaser(GICR_VPENDBASER_PendingLast,
2847 vlpi_base + GICR_VPENDBASER);
2850 * If we can inherit the configuration from another RD, let's do
2851 * so. Otherwise, we have to go through the allocation process. We
2852 * assume that all RDs have the exact same requirements, as
2853 * nothing will work otherwise.
2855 val = inherit_vpe_l1_table_from_rd(&gic_data_rdist()->vpe_table_mask);
2856 if (val & GICR_VPROPBASER_4_1_VALID)
2859 gic_data_rdist()->vpe_table_mask = kzalloc(sizeof(cpumask_t), GFP_ATOMIC);
2860 if (!gic_data_rdist()->vpe_table_mask)
2863 val = inherit_vpe_l1_table_from_its();
2864 if (val & GICR_VPROPBASER_4_1_VALID)
2867 /* First probe the page size */
2868 val = FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, GIC_PAGE_SIZE_64K);
2869 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2870 val = gicr_read_vpropbaser(vlpi_base + GICR_VPROPBASER);
2871 gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val);
2872 esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val);
2876 gpsz = GIC_PAGE_SIZE_4K;
2878 case GIC_PAGE_SIZE_4K:
2881 case GIC_PAGE_SIZE_16K:
2884 case GIC_PAGE_SIZE_64K:
2890 * Start populating the register from scratch, including RO fields
2891 * (which we want to print in debug cases...)
2894 val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, gpsz);
2895 val |= FIELD_PREP(GICR_VPROPBASER_4_1_ENTRY_SIZE, esz);
2897 /* How many entries per GIC page? */
2899 epp = psz / (esz * SZ_8);
2902 * If we need more than just a single L1 page, flag the table
2903 * as indirect and compute the number of required L1 pages.
2905 if (epp < ITS_MAX_VPEID) {
2908 val |= GICR_VPROPBASER_4_1_INDIRECT;
2910 /* Number of L2 pages required to cover the VPEID space */
2911 nl2 = DIV_ROUND_UP(ITS_MAX_VPEID, epp);
2913 /* Number of L1 pages to point to the L2 pages */
2914 npg = DIV_ROUND_UP(nl2 * SZ_8, psz);
2919 val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, npg - 1);
2921 /* Right, that's the number of CPU pages we need for L1 */
2922 np = DIV_ROUND_UP(npg * psz, PAGE_SIZE);
2924 pr_debug("np = %d, npg = %lld, psz = %d, epp = %d, esz = %d\n",
2925 np, npg, psz, epp, esz);
2926 page = alloc_pages(GFP_ATOMIC | __GFP_ZERO, get_order(np * PAGE_SIZE));
2930 gic_data_rdist()->vpe_l1_base = page_address(page);
2931 pa = virt_to_phys(page_address(page));
2932 WARN_ON(!IS_ALIGNED(pa, psz));
2934 val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, pa >> 12);
2935 val |= GICR_VPROPBASER_RaWb;
2936 val |= GICR_VPROPBASER_InnerShareable;
2937 val |= GICR_VPROPBASER_4_1_Z;
2938 val |= GICR_VPROPBASER_4_1_VALID;
2941 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2942 cpumask_set_cpu(smp_processor_id(), gic_data_rdist()->vpe_table_mask);
2944 pr_debug("CPU%d: VPROPBASER = %llx %*pbl\n",
2945 smp_processor_id(), val,
2946 cpumask_pr_args(gic_data_rdist()->vpe_table_mask));
2951 static int its_alloc_collections(struct its_node *its)
2955 its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections),
2957 if (!its->collections)
2960 for (i = 0; i < nr_cpu_ids; i++)
2961 its->collections[i].target_address = ~0ULL;
2966 static struct page *its_allocate_pending_table(gfp_t gfp_flags)
2968 struct page *pend_page;
2970 pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
2971 get_order(LPI_PENDBASE_SZ));
2975 /* Make sure the GIC will observe the zero-ed page */
2976 gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
2981 static void its_free_pending_table(struct page *pt)
2983 free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ));
2987 * Booting with kdump and LPIs enabled is generally fine. Any other
2988 * case is wrong in the absence of firmware/EFI support.
2990 static bool enabled_lpis_allowed(void)
2995 /* Check whether the property table is in a reserved region */
2996 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
2997 addr = val & GENMASK_ULL(51, 12);
2999 return gic_check_reserved_range(addr, LPI_PROPBASE_SZ);
3002 static int __init allocate_lpi_tables(void)
3008 * If LPIs are enabled while we run this from the boot CPU,
3009 * flag the RD tables as pre-allocated if the stars do align.
3011 val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR);
3012 if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) {
3013 gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED |
3014 RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING);
3015 pr_info("GICv3: Using preallocated redistributor tables\n");
3018 err = its_setup_lpi_prop_table();
3023 * We allocate all the pending tables anyway, as we may have a
3024 * mix of RDs that have had LPIs enabled, and some that
3025 * don't. We'll free the unused ones as each CPU comes online.
3027 for_each_possible_cpu(cpu) {
3028 struct page *pend_page;
3030 pend_page = its_allocate_pending_table(GFP_NOWAIT);
3032 pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu);
3036 gic_data_rdist_cpu(cpu)->pend_page = pend_page;
3042 static u64 read_vpend_dirty_clear(void __iomem *vlpi_base)
3044 u32 count = 1000000; /* 1s! */
3049 val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
3050 clean = !(val & GICR_VPENDBASER_Dirty);
3056 } while (!clean && count);
3058 if (unlikely(!clean))
3059 pr_err_ratelimited("ITS virtual pending table not cleaning\n");
3064 static u64 its_clear_vpend_valid(void __iomem *vlpi_base, u64 clr, u64 set)
3068 /* Make sure we wait until the RD is done with the initial scan */
3069 val = read_vpend_dirty_clear(vlpi_base);
3070 val &= ~GICR_VPENDBASER_Valid;
3073 gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
3075 val = read_vpend_dirty_clear(vlpi_base);
3076 if (unlikely(val & GICR_VPENDBASER_Dirty))
3077 val |= GICR_VPENDBASER_PendingLast;
3082 static void its_cpu_init_lpis(void)
3084 void __iomem *rbase = gic_data_rdist_rd_base();
3085 struct page *pend_page;
3089 if (gic_data_rdist()->flags & RD_LOCAL_LPI_ENABLED)
3092 val = readl_relaxed(rbase + GICR_CTLR);
3093 if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) &&
3094 (val & GICR_CTLR_ENABLE_LPIS)) {
3096 * Check that we get the same property table on all
3097 * RDs. If we don't, this is hopeless.
3099 paddr = gicr_read_propbaser(rbase + GICR_PROPBASER);
3100 paddr &= GENMASK_ULL(51, 12);
3101 if (WARN_ON(gic_rdists->prop_table_pa != paddr))
3102 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
3104 paddr = gicr_read_pendbaser(rbase + GICR_PENDBASER);
3105 paddr &= GENMASK_ULL(51, 16);
3107 WARN_ON(!gic_check_reserved_range(paddr, LPI_PENDBASE_SZ));
3108 gic_data_rdist()->flags |= RD_LOCAL_PENDTABLE_PREALLOCATED;
3113 pend_page = gic_data_rdist()->pend_page;
3114 paddr = page_to_phys(pend_page);
3117 val = (gic_rdists->prop_table_pa |
3118 GICR_PROPBASER_InnerShareable |
3119 GICR_PROPBASER_RaWaWb |
3120 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
3122 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
3123 tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
3125 if (gic_rdists->flags & RDIST_FLAGS_FORCE_NON_SHAREABLE)
3126 tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
3128 if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
3129 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
3131 * The HW reports non-shareable, we must
3132 * remove the cacheability attributes as
3135 val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
3136 GICR_PROPBASER_CACHEABILITY_MASK);
3137 val |= GICR_PROPBASER_nC;
3138 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
3140 pr_info_once("GIC: using cache flushing for LPI property table\n");
3141 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
3145 val = (page_to_phys(pend_page) |
3146 GICR_PENDBASER_InnerShareable |
3147 GICR_PENDBASER_RaWaWb);
3149 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
3150 tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
3152 if (gic_rdists->flags & RDIST_FLAGS_FORCE_NON_SHAREABLE)
3153 tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
3155 if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
3157 * The HW reports non-shareable, we must remove the
3158 * cacheability attributes as well.
3160 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
3161 GICR_PENDBASER_CACHEABILITY_MASK);
3162 val |= GICR_PENDBASER_nC;
3163 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
3167 val = readl_relaxed(rbase + GICR_CTLR);
3168 val |= GICR_CTLR_ENABLE_LPIS;
3169 writel_relaxed(val, rbase + GICR_CTLR);
3171 if (gic_rdists->has_vlpis && !gic_rdists->has_rvpeid) {
3172 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3175 * It's possible for CPU to receive VLPIs before it is
3176 * scheduled as a vPE, especially for the first CPU, and the
3177 * VLPI with INTID larger than 2^(IDbits+1) will be considered
3178 * as out of range and dropped by GIC.
3179 * So we initialize IDbits to known value to avoid VLPI drop.
3181 val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
3182 pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n",
3183 smp_processor_id(), val);
3184 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
3187 * Also clear Valid bit of GICR_VPENDBASER, in case some
3188 * ancient programming gets left in and has possibility of
3189 * corrupting memory.
3191 val = its_clear_vpend_valid(vlpi_base, 0, 0);
3194 if (allocate_vpe_l1_table()) {
3196 * If the allocation has failed, we're in massive trouble.
3197 * Disable direct injection, and pray that no VM was
3198 * already running...
3200 gic_rdists->has_rvpeid = false;
3201 gic_rdists->has_vlpis = false;
3204 /* Make sure the GIC has seen the above */
3207 gic_data_rdist()->flags |= RD_LOCAL_LPI_ENABLED;
3208 pr_info("GICv3: CPU%d: using %s LPI pending table @%pa\n",
3210 gic_data_rdist()->flags & RD_LOCAL_PENDTABLE_PREALLOCATED ?
3211 "reserved" : "allocated",
3215 static void its_cpu_init_collection(struct its_node *its)
3217 int cpu = smp_processor_id();
3220 /* avoid cross node collections and its mapping */
3221 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
3222 struct device_node *cpu_node;
3224 cpu_node = of_get_cpu_node(cpu, NULL);
3225 if (its->numa_node != NUMA_NO_NODE &&
3226 its->numa_node != of_node_to_nid(cpu_node))
3231 * We now have to bind each collection to its target
3234 if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
3236 * This ITS wants the physical address of the
3239 target = gic_data_rdist()->phys_base;
3241 /* This ITS wants a linear CPU number. */
3242 target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
3243 target = GICR_TYPER_CPU_NUMBER(target) << 16;
3246 /* Perform collection mapping */
3247 its->collections[cpu].target_address = target;
3248 its->collections[cpu].col_id = cpu;
3250 its_send_mapc(its, &its->collections[cpu], 1);
3251 its_send_invall(its, &its->collections[cpu]);
3254 static void its_cpu_init_collections(void)
3256 struct its_node *its;
3258 raw_spin_lock(&its_lock);
3260 list_for_each_entry(its, &its_nodes, entry)
3261 its_cpu_init_collection(its);
3263 raw_spin_unlock(&its_lock);
3266 static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
3268 struct its_device *its_dev = NULL, *tmp;
3269 unsigned long flags;
3271 raw_spin_lock_irqsave(&its->lock, flags);
3273 list_for_each_entry(tmp, &its->its_device_list, entry) {
3274 if (tmp->device_id == dev_id) {
3280 raw_spin_unlock_irqrestore(&its->lock, flags);
3285 static struct its_baser *its_get_baser(struct its_node *its, u32 type)
3289 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
3290 if (GITS_BASER_TYPE(its->tables[i].val) == type)
3291 return &its->tables[i];
3297 static bool its_alloc_table_entry(struct its_node *its,
3298 struct its_baser *baser, u32 id)
3304 /* Don't allow device id that exceeds single, flat table limit */
3305 esz = GITS_BASER_ENTRY_SIZE(baser->val);
3306 if (!(baser->val & GITS_BASER_INDIRECT))
3307 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
3309 /* Compute 1st level table index & check if that exceeds table limit */
3310 idx = id >> ilog2(baser->psz / esz);
3311 if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
3314 table = baser->base;
3316 /* Allocate memory for 2nd level table */
3318 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
3319 get_order(baser->psz));
3323 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
3324 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
3325 gic_flush_dcache_to_poc(page_address(page), baser->psz);
3327 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
3329 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
3330 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
3331 gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
3333 /* Ensure updated table contents are visible to ITS hardware */
3340 static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
3342 struct its_baser *baser;
3344 baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);
3346 /* Don't allow device id that exceeds ITS hardware limit */
3348 return (ilog2(dev_id) < device_ids(its));
3350 return its_alloc_table_entry(its, baser, dev_id);
3353 static bool its_alloc_vpe_table(u32 vpe_id)
3355 struct its_node *its;
3359 * Make sure the L2 tables are allocated on *all* v4 ITSs. We
3360 * could try and only do it on ITSs corresponding to devices
3361 * that have interrupts targeted at this VPE, but the
3362 * complexity becomes crazy (and you have tons of memory
3365 list_for_each_entry(its, &its_nodes, entry) {
3366 struct its_baser *baser;
3371 baser = its_get_baser(its, GITS_BASER_TYPE_VCPU);
3375 if (!its_alloc_table_entry(its, baser, vpe_id))
3379 /* Non v4.1? No need to iterate RDs and go back early. */
3380 if (!gic_rdists->has_rvpeid)
3384 * Make sure the L2 tables are allocated for all copies of
3385 * the L1 table on *all* v4.1 RDs.
3387 for_each_possible_cpu(cpu) {
3388 if (!allocate_vpe_l2_table(cpu, vpe_id))
3395 static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
3396 int nvecs, bool alloc_lpis)
3398 struct its_device *dev;
3399 unsigned long *lpi_map = NULL;
3400 unsigned long flags;
3401 u16 *col_map = NULL;
3408 if (!its_alloc_device_table(its, dev_id))
3411 if (WARN_ON(!is_power_of_2(nvecs)))
3412 nvecs = roundup_pow_of_two(nvecs);
3414 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
3416 * Even if the device wants a single LPI, the ITT must be
3417 * sized as a power of two (and you need at least one bit...).
3419 nr_ites = max(2, nvecs);
3420 sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
3421 sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
3422 itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
3424 lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
3426 col_map = kcalloc(nr_lpis, sizeof(*col_map),
3429 col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL);
3434 if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) {
3437 bitmap_free(lpi_map);
3442 gic_flush_dcache_to_poc(itt, sz);
3446 dev->nr_ites = nr_ites;
3447 dev->event_map.lpi_map = lpi_map;
3448 dev->event_map.col_map = col_map;
3449 dev->event_map.lpi_base = lpi_base;
3450 dev->event_map.nr_lpis = nr_lpis;
3451 raw_spin_lock_init(&dev->event_map.vlpi_lock);
3452 dev->device_id = dev_id;
3453 INIT_LIST_HEAD(&dev->entry);
3455 raw_spin_lock_irqsave(&its->lock, flags);
3456 list_add(&dev->entry, &its->its_device_list);
3457 raw_spin_unlock_irqrestore(&its->lock, flags);
3459 /* Map device to its ITT */
3460 its_send_mapd(dev, 1);
3465 static void its_free_device(struct its_device *its_dev)
3467 unsigned long flags;
3469 raw_spin_lock_irqsave(&its_dev->its->lock, flags);
3470 list_del(&its_dev->entry);
3471 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
3472 kfree(its_dev->event_map.col_map);
3473 kfree(its_dev->itt);
3477 static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq)
3481 /* Find a free LPI region in lpi_map and allocate them. */
3482 idx = bitmap_find_free_region(dev->event_map.lpi_map,
3483 dev->event_map.nr_lpis,
3484 get_count_order(nvecs));
3488 *hwirq = dev->event_map.lpi_base + idx;
3493 static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
3494 int nvec, msi_alloc_info_t *info)
3496 struct its_node *its;
3497 struct its_device *its_dev;
3498 struct msi_domain_info *msi_info;
3503 * We ignore "dev" entirely, and rely on the dev_id that has
3504 * been passed via the scratchpad. This limits this domain's
3505 * usefulness to upper layers that definitely know that they
3506 * are built on top of the ITS.
3508 dev_id = info->scratchpad[0].ul;
3510 msi_info = msi_get_domain_info(domain);
3511 its = msi_info->data;
3513 if (!gic_rdists->has_direct_lpi &&
3515 vpe_proxy.dev->its == its &&
3516 dev_id == vpe_proxy.dev->device_id) {
3517 /* Bad luck. Get yourself a better implementation */
3518 WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n",
3523 mutex_lock(&its->dev_alloc_lock);
3524 its_dev = its_find_device(its, dev_id);
3527 * We already have seen this ID, probably through
3528 * another alias (PCI bridge of some sort). No need to
3529 * create the device.
3531 its_dev->shared = true;
3532 pr_debug("Reusing ITT for devID %x\n", dev_id);
3536 its_dev = its_create_device(its, dev_id, nvec, true);
3542 if (info->flags & MSI_ALLOC_FLAGS_PROXY_DEVICE)
3543 its_dev->shared = true;
3545 pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
3547 mutex_unlock(&its->dev_alloc_lock);
3548 info->scratchpad[0].ptr = its_dev;
3552 static struct msi_domain_ops its_msi_domain_ops = {
3553 .msi_prepare = its_msi_prepare,
3556 static int its_irq_gic_domain_alloc(struct irq_domain *domain,
3558 irq_hw_number_t hwirq)
3560 struct irq_fwspec fwspec;
3562 if (irq_domain_get_of_node(domain->parent)) {
3563 fwspec.fwnode = domain->parent->fwnode;
3564 fwspec.param_count = 3;
3565 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
3566 fwspec.param[1] = hwirq;
3567 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
3568 } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
3569 fwspec.fwnode = domain->parent->fwnode;
3570 fwspec.param_count = 2;
3571 fwspec.param[0] = hwirq;
3572 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
3577 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
3580 static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
3581 unsigned int nr_irqs, void *args)
3583 msi_alloc_info_t *info = args;
3584 struct its_device *its_dev = info->scratchpad[0].ptr;
3585 struct its_node *its = its_dev->its;
3586 struct irq_data *irqd;
3587 irq_hw_number_t hwirq;
3591 err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq);
3595 err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev));
3599 for (i = 0; i < nr_irqs; i++) {
3600 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
3604 irq_domain_set_hwirq_and_chip(domain, virq + i,
3605 hwirq + i, &its_irq_chip, its_dev);
3606 irqd = irq_get_irq_data(virq + i);
3607 irqd_set_single_target(irqd);
3608 irqd_set_affinity_on_activate(irqd);
3609 irqd_set_resend_when_in_progress(irqd);
3610 pr_debug("ID:%d pID:%d vID:%d\n",
3611 (int)(hwirq + i - its_dev->event_map.lpi_base),
3612 (int)(hwirq + i), virq + i);
3618 static int its_irq_domain_activate(struct irq_domain *domain,
3619 struct irq_data *d, bool reserve)
3621 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3622 u32 event = its_get_event_id(d);
3625 cpu = its_select_cpu(d, cpu_online_mask);
3626 if (cpu < 0 || cpu >= nr_cpu_ids)
3629 its_inc_lpi_count(d, cpu);
3630 its_dev->event_map.col_map[event] = cpu;
3631 irq_data_update_effective_affinity(d, cpumask_of(cpu));
3633 /* Map the GIC IRQ and event to the device */
3634 its_send_mapti(its_dev, d->hwirq, event);
3638 static void its_irq_domain_deactivate(struct irq_domain *domain,
3641 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3642 u32 event = its_get_event_id(d);
3644 its_dec_lpi_count(d, its_dev->event_map.col_map[event]);
3645 /* Stop the delivery of interrupts */
3646 its_send_discard(its_dev, event);
3649 static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
3650 unsigned int nr_irqs)
3652 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
3653 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3654 struct its_node *its = its_dev->its;
3657 bitmap_release_region(its_dev->event_map.lpi_map,
3658 its_get_event_id(irq_domain_get_irq_data(domain, virq)),
3659 get_count_order(nr_irqs));
3661 for (i = 0; i < nr_irqs; i++) {
3662 struct irq_data *data = irq_domain_get_irq_data(domain,
3664 /* Nuke the entry in the domain */
3665 irq_domain_reset_irq_data(data);
3668 mutex_lock(&its->dev_alloc_lock);
3671 * If all interrupts have been freed, start mopping the
3672 * floor. This is conditioned on the device not being shared.
3674 if (!its_dev->shared &&
3675 bitmap_empty(its_dev->event_map.lpi_map,
3676 its_dev->event_map.nr_lpis)) {
3677 its_lpi_free(its_dev->event_map.lpi_map,
3678 its_dev->event_map.lpi_base,
3679 its_dev->event_map.nr_lpis);
3681 /* Unmap device/itt */
3682 its_send_mapd(its_dev, 0);
3683 its_free_device(its_dev);
3686 mutex_unlock(&its->dev_alloc_lock);
3688 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
3691 static const struct irq_domain_ops its_domain_ops = {
3692 .alloc = its_irq_domain_alloc,
3693 .free = its_irq_domain_free,
3694 .activate = its_irq_domain_activate,
3695 .deactivate = its_irq_domain_deactivate,
3701 * If a GICv4.0 doesn't implement Direct LPIs (which is extremely
3702 * likely), the only way to perform an invalidate is to use a fake
3703 * device to issue an INV command, implying that the LPI has first
3704 * been mapped to some event on that device. Since this is not exactly
3705 * cheap, we try to keep that mapping around as long as possible, and
3706 * only issue an UNMAP if we're short on available slots.
3708 * Broken by design(tm).
3710 * GICv4.1, on the other hand, mandates that we're able to invalidate
3711 * by writing to a MMIO register. It doesn't implement the whole of
3712 * DirectLPI, but that's good enough. And most of the time, we don't
3713 * even have to invalidate anything, as the redistributor can be told
3714 * whether to generate a doorbell or not (we thus leave it enabled,
3717 static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)
3719 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3720 if (gic_rdists->has_rvpeid)
3723 /* Already unmapped? */
3724 if (vpe->vpe_proxy_event == -1)
3727 its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);
3728 vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;
3731 * We don't track empty slots at all, so let's move the
3732 * next_victim pointer if we can quickly reuse that slot
3733 * instead of nuking an existing entry. Not clear that this is
3734 * always a win though, and this might just generate a ripple
3735 * effect... Let's just hope VPEs don't migrate too often.
3737 if (vpe_proxy.vpes[vpe_proxy.next_victim])
3738 vpe_proxy.next_victim = vpe->vpe_proxy_event;
3740 vpe->vpe_proxy_event = -1;
3743 static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)
3745 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3746 if (gic_rdists->has_rvpeid)
3749 if (!gic_rdists->has_direct_lpi) {
3750 unsigned long flags;
3752 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3753 its_vpe_db_proxy_unmap_locked(vpe);
3754 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3758 static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)
3760 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3761 if (gic_rdists->has_rvpeid)
3764 /* Already mapped? */
3765 if (vpe->vpe_proxy_event != -1)
3768 /* This slot was already allocated. Kick the other VPE out. */
3769 if (vpe_proxy.vpes[vpe_proxy.next_victim])
3770 its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]);
3772 /* Map the new VPE instead */
3773 vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;
3774 vpe->vpe_proxy_event = vpe_proxy.next_victim;
3775 vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites;
3777 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;
3778 its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);
3781 static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
3783 unsigned long flags;
3784 struct its_collection *target_col;
3786 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3787 if (gic_rdists->has_rvpeid)
3790 if (gic_rdists->has_direct_lpi) {
3791 void __iomem *rdbase;
3793 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base;
3794 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
3795 wait_for_syncr(rdbase);
3800 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3802 its_vpe_db_proxy_map_locked(vpe);
3804 target_col = &vpe_proxy.dev->its->collections[to];
3805 its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);
3806 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;
3808 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3811 static int its_vpe_set_affinity(struct irq_data *d,
3812 const struct cpumask *mask_val,
3815 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3816 int from, cpu = cpumask_first(mask_val);
3817 unsigned long flags;
3820 * Changing affinity is mega expensive, so let's be as lazy as
3821 * we can and only do it if we really have to. Also, if mapped
3822 * into the proxy device, we need to move the doorbell
3823 * interrupt to its new location.
3825 * Another thing is that changing the affinity of a vPE affects
3826 * *other interrupts* such as all the vLPIs that are routed to
3827 * this vPE. This means that the irq_desc lock is not enough to
3828 * protect us, and that we must ensure nobody samples vpe->col_idx
3829 * during the update, hence the lock below which must also be
3830 * taken on any vLPI handling path that evaluates vpe->col_idx.
3832 from = vpe_to_cpuid_lock(vpe, &flags);
3839 * GICv4.1 allows us to skip VMOVP if moving to a cpu whose RD
3840 * is sharing its VPE table with the current one.
3842 if (gic_data_rdist_cpu(cpu)->vpe_table_mask &&
3843 cpumask_test_cpu(from, gic_data_rdist_cpu(cpu)->vpe_table_mask))
3846 its_send_vmovp(vpe);
3847 its_vpe_db_proxy_move(vpe, from, cpu);
3850 irq_data_update_effective_affinity(d, cpumask_of(cpu));
3851 vpe_to_cpuid_unlock(vpe, flags);
3853 return IRQ_SET_MASK_OK_DONE;
3856 static void its_wait_vpt_parse_complete(void)
3858 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3861 if (!gic_rdists->has_vpend_valid_dirty)
3864 WARN_ON_ONCE(readq_relaxed_poll_timeout_atomic(vlpi_base + GICR_VPENDBASER,
3866 !(val & GICR_VPENDBASER_Dirty),
3870 static void its_vpe_schedule(struct its_vpe *vpe)
3872 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3875 /* Schedule the VPE */
3876 val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
3877 GENMASK_ULL(51, 12);
3878 val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
3879 val |= GICR_VPROPBASER_RaWb;
3880 val |= GICR_VPROPBASER_InnerShareable;
3881 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
3883 val = virt_to_phys(page_address(vpe->vpt_page)) &
3884 GENMASK_ULL(51, 16);
3885 val |= GICR_VPENDBASER_RaWaWb;
3886 val |= GICR_VPENDBASER_InnerShareable;
3888 * There is no good way of finding out if the pending table is
3889 * empty as we can race against the doorbell interrupt very
3890 * easily. So in the end, vpe->pending_last is only an
3891 * indication that the vcpu has something pending, not one
3892 * that the pending table is empty. A good implementation
3893 * would be able to read its coarse map pretty quickly anyway,
3894 * making this a tolerable issue.
3896 val |= GICR_VPENDBASER_PendingLast;
3897 val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
3898 val |= GICR_VPENDBASER_Valid;
3899 gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
3902 static void its_vpe_deschedule(struct its_vpe *vpe)
3904 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3907 val = its_clear_vpend_valid(vlpi_base, 0, 0);
3909 vpe->idai = !!(val & GICR_VPENDBASER_IDAI);
3910 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
3913 static void its_vpe_invall(struct its_vpe *vpe)
3915 struct its_node *its;
3917 list_for_each_entry(its, &its_nodes, entry) {
3921 if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])
3925 * Sending a VINVALL to a single ITS is enough, as all
3926 * we need is to reach the redistributors.
3928 its_send_vinvall(its, vpe);
3933 static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
3935 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3936 struct its_cmd_info *info = vcpu_info;
3938 switch (info->cmd_type) {
3940 its_vpe_schedule(vpe);
3943 case DESCHEDULE_VPE:
3944 its_vpe_deschedule(vpe);
3948 its_wait_vpt_parse_complete();
3952 its_vpe_invall(vpe);
3960 static void its_vpe_send_cmd(struct its_vpe *vpe,
3961 void (*cmd)(struct its_device *, u32))
3963 unsigned long flags;
3965 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3967 its_vpe_db_proxy_map_locked(vpe);
3968 cmd(vpe_proxy.dev, vpe->vpe_proxy_event);
3970 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3973 static void its_vpe_send_inv(struct irq_data *d)
3975 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3977 if (gic_rdists->has_direct_lpi)
3978 __direct_lpi_inv(d, d->parent_data->hwirq);
3980 its_vpe_send_cmd(vpe, its_send_inv);
3983 static void its_vpe_mask_irq(struct irq_data *d)
3986 * We need to unmask the LPI, which is described by the parent
3987 * irq_data. Instead of calling into the parent (which won't
3988 * exactly do the right thing, let's simply use the
3989 * parent_data pointer. Yes, I'm naughty.
3991 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
3992 its_vpe_send_inv(d);
3995 static void its_vpe_unmask_irq(struct irq_data *d)
3997 /* Same hack as above... */
3998 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
3999 its_vpe_send_inv(d);
4002 static int its_vpe_set_irqchip_state(struct irq_data *d,
4003 enum irqchip_irq_state which,
4006 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4008 if (which != IRQCHIP_STATE_PENDING)
4011 if (gic_rdists->has_direct_lpi) {
4012 void __iomem *rdbase;
4014 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
4016 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);
4018 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
4019 wait_for_syncr(rdbase);
4023 its_vpe_send_cmd(vpe, its_send_int);
4025 its_vpe_send_cmd(vpe, its_send_clear);
4031 static int its_vpe_retrigger(struct irq_data *d)
4033 return !its_vpe_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true);
4036 static struct irq_chip its_vpe_irq_chip = {
4037 .name = "GICv4-vpe",
4038 .irq_mask = its_vpe_mask_irq,
4039 .irq_unmask = its_vpe_unmask_irq,
4040 .irq_eoi = irq_chip_eoi_parent,
4041 .irq_set_affinity = its_vpe_set_affinity,
4042 .irq_retrigger = its_vpe_retrigger,
4043 .irq_set_irqchip_state = its_vpe_set_irqchip_state,
4044 .irq_set_vcpu_affinity = its_vpe_set_vcpu_affinity,
4047 static struct its_node *find_4_1_its(void)
4049 static struct its_node *its = NULL;
4052 list_for_each_entry(its, &its_nodes, entry) {
4064 static void its_vpe_4_1_send_inv(struct irq_data *d)
4066 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4067 struct its_node *its;
4070 * GICv4.1 wants doorbells to be invalidated using the
4071 * INVDB command in order to be broadcast to all RDs. Send
4072 * it to the first valid ITS, and let the HW do its magic.
4074 its = find_4_1_its();
4076 its_send_invdb(its, vpe);
4079 static void its_vpe_4_1_mask_irq(struct irq_data *d)
4081 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
4082 its_vpe_4_1_send_inv(d);
4085 static void its_vpe_4_1_unmask_irq(struct irq_data *d)
4087 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
4088 its_vpe_4_1_send_inv(d);
4091 static void its_vpe_4_1_schedule(struct its_vpe *vpe,
4092 struct its_cmd_info *info)
4094 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
4097 /* Schedule the VPE */
4098 val |= GICR_VPENDBASER_Valid;
4099 val |= info->g0en ? GICR_VPENDBASER_4_1_VGRP0EN : 0;
4100 val |= info->g1en ? GICR_VPENDBASER_4_1_VGRP1EN : 0;
4101 val |= FIELD_PREP(GICR_VPENDBASER_4_1_VPEID, vpe->vpe_id);
4103 gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
4106 static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
4107 struct its_cmd_info *info)
4109 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
4113 unsigned long flags;
4116 * vPE is going to block: make the vPE non-resident with
4117 * PendingLast clear and DB set. The GIC guarantees that if
4118 * we read-back PendingLast clear, then a doorbell will be
4119 * delivered when an interrupt comes.
4121 * Note the locking to deal with the concurrent update of
4122 * pending_last from the doorbell interrupt handler that can
4125 raw_spin_lock_irqsave(&vpe->vpe_lock, flags);
4126 val = its_clear_vpend_valid(vlpi_base,
4127 GICR_VPENDBASER_PendingLast,
4128 GICR_VPENDBASER_4_1_DB);
4129 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
4130 raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);
4133 * We're not blocking, so just make the vPE non-resident
4134 * with PendingLast set, indicating that we'll be back.
4136 val = its_clear_vpend_valid(vlpi_base,
4138 GICR_VPENDBASER_PendingLast);
4139 vpe->pending_last = true;
4143 static void its_vpe_4_1_invall(struct its_vpe *vpe)
4145 void __iomem *rdbase;
4146 unsigned long flags;
4150 val = GICR_INVALLR_V;
4151 val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id);
4153 /* Target the redistributor this vPE is currently known on */
4154 cpu = vpe_to_cpuid_lock(vpe, &flags);
4155 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
4156 rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
4157 gic_write_lpir(val, rdbase + GICR_INVALLR);
4159 wait_for_syncr(rdbase);
4160 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
4161 vpe_to_cpuid_unlock(vpe, flags);
4164 static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
4166 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4167 struct its_cmd_info *info = vcpu_info;
4169 switch (info->cmd_type) {
4171 its_vpe_4_1_schedule(vpe, info);
4174 case DESCHEDULE_VPE:
4175 its_vpe_4_1_deschedule(vpe, info);
4179 its_wait_vpt_parse_complete();
4183 its_vpe_4_1_invall(vpe);
4191 static struct irq_chip its_vpe_4_1_irq_chip = {
4192 .name = "GICv4.1-vpe",
4193 .irq_mask = its_vpe_4_1_mask_irq,
4194 .irq_unmask = its_vpe_4_1_unmask_irq,
4195 .irq_eoi = irq_chip_eoi_parent,
4196 .irq_set_affinity = its_vpe_set_affinity,
4197 .irq_set_vcpu_affinity = its_vpe_4_1_set_vcpu_affinity,
4200 static void its_configure_sgi(struct irq_data *d, bool clear)
4202 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4203 struct its_cmd_desc desc;
4205 desc.its_vsgi_cmd.vpe = vpe;
4206 desc.its_vsgi_cmd.sgi = d->hwirq;
4207 desc.its_vsgi_cmd.priority = vpe->sgi_config[d->hwirq].priority;
4208 desc.its_vsgi_cmd.enable = vpe->sgi_config[d->hwirq].enabled;
4209 desc.its_vsgi_cmd.group = vpe->sgi_config[d->hwirq].group;
4210 desc.its_vsgi_cmd.clear = clear;
4213 * GICv4.1 allows us to send VSGI commands to any ITS as long as the
4214 * destination VPE is mapped there. Since we map them eagerly at
4215 * activation time, we're pretty sure the first GICv4.1 ITS will do.
4217 its_send_single_vcommand(find_4_1_its(), its_build_vsgi_cmd, &desc);
4220 static void its_sgi_mask_irq(struct irq_data *d)
4222 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4224 vpe->sgi_config[d->hwirq].enabled = false;
4225 its_configure_sgi(d, false);
4228 static void its_sgi_unmask_irq(struct irq_data *d)
4230 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4232 vpe->sgi_config[d->hwirq].enabled = true;
4233 its_configure_sgi(d, false);
4236 static int its_sgi_set_affinity(struct irq_data *d,
4237 const struct cpumask *mask_val,
4241 * There is no notion of affinity for virtual SGIs, at least
4242 * not on the host (since they can only be targeting a vPE).
4243 * Tell the kernel we've done whatever it asked for.
4245 irq_data_update_effective_affinity(d, mask_val);
4246 return IRQ_SET_MASK_OK;
4249 static int its_sgi_set_irqchip_state(struct irq_data *d,
4250 enum irqchip_irq_state which,
4253 if (which != IRQCHIP_STATE_PENDING)
4257 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4258 struct its_node *its = find_4_1_its();
4261 val = FIELD_PREP(GITS_SGIR_VPEID, vpe->vpe_id);
4262 val |= FIELD_PREP(GITS_SGIR_VINTID, d->hwirq);
4263 writeq_relaxed(val, its->sgir_base + GITS_SGIR - SZ_128K);
4265 its_configure_sgi(d, true);
4271 static int its_sgi_get_irqchip_state(struct irq_data *d,
4272 enum irqchip_irq_state which, bool *val)
4274 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4276 unsigned long flags;
4277 u32 count = 1000000; /* 1s! */
4281 if (which != IRQCHIP_STATE_PENDING)
4285 * Locking galore! We can race against two different events:
4287 * - Concurrent vPE affinity change: we must make sure it cannot
4288 * happen, or we'll talk to the wrong redistributor. This is
4289 * identical to what happens with vLPIs.
4291 * - Concurrent VSGIPENDR access: As it involves accessing two
4292 * MMIO registers, this must be made atomic one way or another.
4294 cpu = vpe_to_cpuid_lock(vpe, &flags);
4295 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
4296 base = gic_data_rdist_cpu(cpu)->rd_base + SZ_128K;
4297 writel_relaxed(vpe->vpe_id, base + GICR_VSGIR);
4299 status = readl_relaxed(base + GICR_VSGIPENDR);
4300 if (!(status & GICR_VSGIPENDR_BUSY))
4305 pr_err_ratelimited("Unable to get SGI status\n");
4313 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
4314 vpe_to_cpuid_unlock(vpe, flags);
4319 *val = !!(status & (1 << d->hwirq));
4324 static int its_sgi_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
4326 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4327 struct its_cmd_info *info = vcpu_info;
4329 switch (info->cmd_type) {
4330 case PROP_UPDATE_VSGI:
4331 vpe->sgi_config[d->hwirq].priority = info->priority;
4332 vpe->sgi_config[d->hwirq].group = info->group;
4333 its_configure_sgi(d, false);
4341 static struct irq_chip its_sgi_irq_chip = {
4342 .name = "GICv4.1-sgi",
4343 .irq_mask = its_sgi_mask_irq,
4344 .irq_unmask = its_sgi_unmask_irq,
4345 .irq_set_affinity = its_sgi_set_affinity,
4346 .irq_set_irqchip_state = its_sgi_set_irqchip_state,
4347 .irq_get_irqchip_state = its_sgi_get_irqchip_state,
4348 .irq_set_vcpu_affinity = its_sgi_set_vcpu_affinity,
4351 static int its_sgi_irq_domain_alloc(struct irq_domain *domain,
4352 unsigned int virq, unsigned int nr_irqs,
4355 struct its_vpe *vpe = args;
4358 /* Yes, we do want 16 SGIs */
4359 WARN_ON(nr_irqs != 16);
4361 for (i = 0; i < 16; i++) {
4362 vpe->sgi_config[i].priority = 0;
4363 vpe->sgi_config[i].enabled = false;
4364 vpe->sgi_config[i].group = false;
4366 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
4367 &its_sgi_irq_chip, vpe);
4368 irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY);
4374 static void its_sgi_irq_domain_free(struct irq_domain *domain,
4376 unsigned int nr_irqs)
4381 static int its_sgi_irq_domain_activate(struct irq_domain *domain,
4382 struct irq_data *d, bool reserve)
4384 /* Write out the initial SGI configuration */
4385 its_configure_sgi(d, false);
4389 static void its_sgi_irq_domain_deactivate(struct irq_domain *domain,
4392 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4395 * The VSGI command is awkward:
4397 * - To change the configuration, CLEAR must be set to false,
4398 * leaving the pending bit unchanged.
4399 * - To clear the pending bit, CLEAR must be set to true, leaving
4400 * the configuration unchanged.
4402 * You just can't do both at once, hence the two commands below.
4404 vpe->sgi_config[d->hwirq].enabled = false;
4405 its_configure_sgi(d, false);
4406 its_configure_sgi(d, true);
4409 static const struct irq_domain_ops its_sgi_domain_ops = {
4410 .alloc = its_sgi_irq_domain_alloc,
4411 .free = its_sgi_irq_domain_free,
4412 .activate = its_sgi_irq_domain_activate,
4413 .deactivate = its_sgi_irq_domain_deactivate,
4416 static int its_vpe_id_alloc(void)
4418 return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL);
4421 static void its_vpe_id_free(u16 id)
4423 ida_simple_remove(&its_vpeid_ida, id);
4426 static int its_vpe_init(struct its_vpe *vpe)
4428 struct page *vpt_page;
4431 /* Allocate vpe_id */
4432 vpe_id = its_vpe_id_alloc();
4437 vpt_page = its_allocate_pending_table(GFP_KERNEL);
4439 its_vpe_id_free(vpe_id);
4443 if (!its_alloc_vpe_table(vpe_id)) {
4444 its_vpe_id_free(vpe_id);
4445 its_free_pending_table(vpt_page);
4449 raw_spin_lock_init(&vpe->vpe_lock);
4450 vpe->vpe_id = vpe_id;
4451 vpe->vpt_page = vpt_page;
4452 if (gic_rdists->has_rvpeid)
4453 atomic_set(&vpe->vmapp_count, 0);
4455 vpe->vpe_proxy_event = -1;
4460 static void its_vpe_teardown(struct its_vpe *vpe)
4462 its_vpe_db_proxy_unmap(vpe);
4463 its_vpe_id_free(vpe->vpe_id);
4464 its_free_pending_table(vpe->vpt_page);
4467 static void its_vpe_irq_domain_free(struct irq_domain *domain,
4469 unsigned int nr_irqs)
4471 struct its_vm *vm = domain->host_data;
4474 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
4476 for (i = 0; i < nr_irqs; i++) {
4477 struct irq_data *data = irq_domain_get_irq_data(domain,
4479 struct its_vpe *vpe = irq_data_get_irq_chip_data(data);
4481 BUG_ON(vm != vpe->its_vm);
4483 clear_bit(data->hwirq, vm->db_bitmap);
4484 its_vpe_teardown(vpe);
4485 irq_domain_reset_irq_data(data);
4488 if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
4489 its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
4490 its_free_prop_table(vm->vprop_page);
4494 static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
4495 unsigned int nr_irqs, void *args)
4497 struct irq_chip *irqchip = &its_vpe_irq_chip;
4498 struct its_vm *vm = args;
4499 unsigned long *bitmap;
4500 struct page *vprop_page;
4501 int base, nr_ids, i, err = 0;
4505 bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids);
4509 if (nr_ids < nr_irqs) {
4510 its_lpi_free(bitmap, base, nr_ids);
4514 vprop_page = its_allocate_prop_table(GFP_KERNEL);
4516 its_lpi_free(bitmap, base, nr_ids);
4520 vm->db_bitmap = bitmap;
4521 vm->db_lpi_base = base;
4522 vm->nr_db_lpis = nr_ids;
4523 vm->vprop_page = vprop_page;
4525 if (gic_rdists->has_rvpeid)
4526 irqchip = &its_vpe_4_1_irq_chip;
4528 for (i = 0; i < nr_irqs; i++) {
4529 vm->vpes[i]->vpe_db_lpi = base + i;
4530 err = its_vpe_init(vm->vpes[i]);
4533 err = its_irq_gic_domain_alloc(domain, virq + i,
4534 vm->vpes[i]->vpe_db_lpi);
4537 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
4538 irqchip, vm->vpes[i]);
4540 irqd_set_resend_when_in_progress(irq_get_irq_data(virq + i));
4545 its_vpe_irq_domain_free(domain, virq, i);
4547 its_lpi_free(bitmap, base, nr_ids);
4548 its_free_prop_table(vprop_page);
4554 static int its_vpe_irq_domain_activate(struct irq_domain *domain,
4555 struct irq_data *d, bool reserve)
4557 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4558 struct its_node *its;
4561 * If we use the list map, we issue VMAPP on demand... Unless
4562 * we're on a GICv4.1 and we eagerly map the VPE on all ITSs
4563 * so that VSGIs can work.
4565 if (!gic_requires_eager_mapping())
4568 /* Map the VPE to the first possible CPU */
4569 vpe->col_idx = cpumask_first(cpu_online_mask);
4571 list_for_each_entry(its, &its_nodes, entry) {
4575 its_send_vmapp(its, vpe, true);
4576 its_send_vinvall(its, vpe);
4579 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
4584 static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,
4587 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4588 struct its_node *its;
4591 * If we use the list map on GICv4.0, we unmap the VPE once no
4592 * VLPIs are associated with the VM.
4594 if (!gic_requires_eager_mapping())
4597 list_for_each_entry(its, &its_nodes, entry) {
4601 its_send_vmapp(its, vpe, false);
4605 * There may be a direct read to the VPT after unmapping the
4606 * vPE, to guarantee the validity of this, we make the VPT
4607 * memory coherent with the CPU caches here.
4609 if (find_4_1_its() && !atomic_read(&vpe->vmapp_count))
4610 gic_flush_dcache_to_poc(page_address(vpe->vpt_page),
4614 static const struct irq_domain_ops its_vpe_domain_ops = {
4615 .alloc = its_vpe_irq_domain_alloc,
4616 .free = its_vpe_irq_domain_free,
4617 .activate = its_vpe_irq_domain_activate,
4618 .deactivate = its_vpe_irq_domain_deactivate,
4621 static int its_force_quiescent(void __iomem *base)
4623 u32 count = 1000000; /* 1s */
4626 val = readl_relaxed(base + GITS_CTLR);
4628 * GIC architecture specification requires the ITS to be both
4629 * disabled and quiescent for writes to GITS_BASER<n> or
4630 * GITS_CBASER to not have UNPREDICTABLE results.
4632 if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))
4635 /* Disable the generation of all interrupts to this ITS */
4636 val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe);
4637 writel_relaxed(val, base + GITS_CTLR);
4639 /* Poll GITS_CTLR and wait until ITS becomes quiescent */
4641 val = readl_relaxed(base + GITS_CTLR);
4642 if (val & GITS_CTLR_QUIESCENT)
4654 static bool __maybe_unused its_enable_quirk_cavium_22375(void *data)
4656 struct its_node *its = data;
4658 /* erratum 22375: only alloc 8MB table size (20 bits) */
4659 its->typer &= ~GITS_TYPER_DEVBITS;
4660 its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, 20 - 1);
4661 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
4666 static bool __maybe_unused its_enable_quirk_cavium_23144(void *data)
4668 struct its_node *its = data;
4670 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
4675 static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)
4677 struct its_node *its = data;
4679 /* On QDF2400, the size of the ITE is 16Bytes */
4680 its->typer &= ~GITS_TYPER_ITT_ENTRY_SIZE;
4681 its->typer |= FIELD_PREP(GITS_TYPER_ITT_ENTRY_SIZE, 16 - 1);
4686 static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev)
4688 struct its_node *its = its_dev->its;
4691 * The Socionext Synquacer SoC has a so-called 'pre-ITS',
4692 * which maps 32-bit writes targeted at a separate window of
4693 * size '4 << device_id_bits' onto writes to GITS_TRANSLATER
4694 * with device ID taken from bits [device_id_bits + 1:2] of
4695 * the window offset.
4697 return its->pre_its_base + (its_dev->device_id << 2);
4700 static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data)
4702 struct its_node *its = data;
4703 u32 pre_its_window[2];
4706 if (!fwnode_property_read_u32_array(its->fwnode_handle,
4707 "socionext,synquacer-pre-its",
4709 ARRAY_SIZE(pre_its_window))) {
4711 its->pre_its_base = pre_its_window[0];
4712 its->get_msi_base = its_irq_get_msi_base_pre_its;
4714 ids = ilog2(pre_its_window[1]) - 2;
4715 if (device_ids(its) > ids) {
4716 its->typer &= ~GITS_TYPER_DEVBITS;
4717 its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, ids - 1);
4720 /* the pre-ITS breaks isolation, so disable MSI remapping */
4721 its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_ISOLATED_MSI;
4727 static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
4729 struct its_node *its = data;
4732 * Hip07 insists on using the wrong address for the VLPI
4733 * page. Trick it into doing the right thing...
4735 its->vlpi_redist_offset = SZ_128K;
4739 static bool __maybe_unused its_enable_rk3588001(void *data)
4741 struct its_node *its = data;
4743 if (!of_machine_is_compatible("rockchip,rk3588") &&
4744 !of_machine_is_compatible("rockchip,rk3588s"))
4747 its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE;
4748 gic_rdists->flags |= RDIST_FLAGS_FORCE_NON_SHAREABLE;
4753 static bool its_set_non_coherent(void *data)
4755 struct its_node *its = data;
4757 its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE;
4761 static const struct gic_quirk its_quirks[] = {
4762 #ifdef CONFIG_CAVIUM_ERRATUM_22375
4764 .desc = "ITS: Cavium errata 22375, 24313",
4765 .iidr = 0xa100034c, /* ThunderX pass 1.x */
4767 .init = its_enable_quirk_cavium_22375,
4770 #ifdef CONFIG_CAVIUM_ERRATUM_23144
4772 .desc = "ITS: Cavium erratum 23144",
4773 .iidr = 0xa100034c, /* ThunderX pass 1.x */
4775 .init = its_enable_quirk_cavium_23144,
4778 #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065
4780 .desc = "ITS: QDF2400 erratum 0065",
4781 .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */
4783 .init = its_enable_quirk_qdf2400_e0065,
4786 #ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS
4789 * The Socionext Synquacer SoC incorporates ARM's own GIC-500
4790 * implementation, but with a 'pre-ITS' added that requires
4791 * special handling in software.
4793 .desc = "ITS: Socionext Synquacer pre-ITS",
4796 .init = its_enable_quirk_socionext_synquacer,
4799 #ifdef CONFIG_HISILICON_ERRATUM_161600802
4801 .desc = "ITS: Hip07 erratum 161600802",
4804 .init = its_enable_quirk_hip07_161600802,
4807 #ifdef CONFIG_ROCKCHIP_ERRATUM_3588001
4809 .desc = "ITS: Rockchip erratum RK3588001",
4812 .init = its_enable_rk3588001,
4816 .desc = "ITS: non-coherent attribute",
4817 .property = "dma-noncoherent",
4818 .init = its_set_non_coherent,
4824 static void its_enable_quirks(struct its_node *its)
4826 u32 iidr = readl_relaxed(its->base + GITS_IIDR);
4828 gic_enable_quirks(iidr, its_quirks, its);
4830 if (is_of_node(its->fwnode_handle))
4831 gic_enable_of_quirks(to_of_node(its->fwnode_handle),
4835 static int its_save_disable(void)
4837 struct its_node *its;
4840 raw_spin_lock(&its_lock);
4841 list_for_each_entry(its, &its_nodes, entry) {
4845 its->ctlr_save = readl_relaxed(base + GITS_CTLR);
4846 err = its_force_quiescent(base);
4848 pr_err("ITS@%pa: failed to quiesce: %d\n",
4849 &its->phys_base, err);
4850 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4854 its->cbaser_save = gits_read_cbaser(base + GITS_CBASER);
4859 list_for_each_entry_continue_reverse(its, &its_nodes, entry) {
4863 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4866 raw_spin_unlock(&its_lock);
4871 static void its_restore_enable(void)
4873 struct its_node *its;
4876 raw_spin_lock(&its_lock);
4877 list_for_each_entry(its, &its_nodes, entry) {
4884 * Make sure that the ITS is disabled. If it fails to quiesce,
4885 * don't restore it since writing to CBASER or BASER<n>
4886 * registers is undefined according to the GIC v3 ITS
4889 * Firmware resuming with the ITS enabled is terminally broken.
4891 WARN_ON(readl_relaxed(base + GITS_CTLR) & GITS_CTLR_ENABLE);
4892 ret = its_force_quiescent(base);
4894 pr_err("ITS@%pa: failed to quiesce on resume: %d\n",
4895 &its->phys_base, ret);
4899 gits_write_cbaser(its->cbaser_save, base + GITS_CBASER);
4902 * Writing CBASER resets CREADR to 0, so make CWRITER and
4903 * cmd_write line up with it.
4905 its->cmd_write = its->cmd_base;
4906 gits_write_cwriter(0, base + GITS_CWRITER);
4908 /* Restore GITS_BASER from the value cache. */
4909 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
4910 struct its_baser *baser = &its->tables[i];
4912 if (!(baser->val & GITS_BASER_VALID))
4915 its_write_baser(its, baser, baser->val);
4917 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4920 * Reinit the collection if it's stored in the ITS. This is
4921 * indicated by the col_id being less than the HCC field.
4922 * CID < HCC as specified in the GIC v3 Documentation.
4924 if (its->collections[smp_processor_id()].col_id <
4925 GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
4926 its_cpu_init_collection(its);
4928 raw_spin_unlock(&its_lock);
4931 static struct syscore_ops its_syscore_ops = {
4932 .suspend = its_save_disable,
4933 .resume = its_restore_enable,
4936 static void __init __iomem *its_map_one(struct resource *res, int *err)
4938 void __iomem *its_base;
4941 its_base = ioremap(res->start, SZ_64K);
4943 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
4948 val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
4949 if (val != 0x30 && val != 0x40) {
4950 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
4955 *err = its_force_quiescent(its_base);
4957 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
4968 static int its_init_domain(struct its_node *its)
4970 struct irq_domain *inner_domain;
4971 struct msi_domain_info *info;
4973 info = kzalloc(sizeof(*info), GFP_KERNEL);
4977 info->ops = &its_msi_domain_ops;
4980 inner_domain = irq_domain_create_hierarchy(its_parent,
4981 its->msi_domain_flags, 0,
4982 its->fwnode_handle, &its_domain_ops,
4984 if (!inner_domain) {
4989 irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
4994 static int its_init_vpe_domain(void)
4996 struct its_node *its;
5000 if (gic_rdists->has_direct_lpi) {
5001 pr_info("ITS: Using DirectLPI for VPE invalidation\n");
5005 /* Any ITS will do, even if not v4 */
5006 its = list_first_entry(&its_nodes, struct its_node, entry);
5008 entries = roundup_pow_of_two(nr_cpu_ids);
5009 vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes),
5011 if (!vpe_proxy.vpes)
5014 /* Use the last possible DevID */
5015 devid = GENMASK(device_ids(its) - 1, 0);
5016 vpe_proxy.dev = its_create_device(its, devid, entries, false);
5017 if (!vpe_proxy.dev) {
5018 kfree(vpe_proxy.vpes);
5019 pr_err("ITS: Can't allocate GICv4 proxy device\n");
5023 BUG_ON(entries > vpe_proxy.dev->nr_ites);
5025 raw_spin_lock_init(&vpe_proxy.lock);
5026 vpe_proxy.next_victim = 0;
5027 pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n",
5028 devid, vpe_proxy.dev->nr_ites);
5033 static int __init its_compute_its_list_map(struct its_node *its)
5039 * This is assumed to be done early enough that we're
5040 * guaranteed to be single-threaded, hence no
5041 * locking. Should this change, we should address
5044 its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX);
5045 if (its_number >= GICv4_ITS_LIST_MAX) {
5046 pr_err("ITS@%pa: No ITSList entry available!\n",
5051 ctlr = readl_relaxed(its->base + GITS_CTLR);
5052 ctlr &= ~GITS_CTLR_ITS_NUMBER;
5053 ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT;
5054 writel_relaxed(ctlr, its->base + GITS_CTLR);
5055 ctlr = readl_relaxed(its->base + GITS_CTLR);
5056 if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {
5057 its_number = ctlr & GITS_CTLR_ITS_NUMBER;
5058 its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT;
5061 if (test_and_set_bit(its_number, &its_list_map)) {
5062 pr_err("ITS@%pa: Duplicate ITSList entry %d\n",
5063 &its->phys_base, its_number);
5070 static int __init its_probe_one(struct its_node *its)
5078 if (!(its->typer & GITS_TYPER_VMOVP)) {
5079 err = its_compute_its_list_map(its);
5085 pr_info("ITS@%pa: Using ITS number %d\n",
5086 &its->phys_base, err);
5088 pr_info("ITS@%pa: Single VMOVP capable\n", &its->phys_base);
5092 u32 svpet = FIELD_GET(GITS_TYPER_SVPET, its->typer);
5094 its->sgir_base = ioremap(its->phys_base + SZ_128K, SZ_64K);
5095 if (!its->sgir_base) {
5100 its->mpidr = readl_relaxed(its->base + GITS_MPIDR);
5102 pr_info("ITS@%pa: Using GICv4.1 mode %08x %08x\n",
5103 &its->phys_base, its->mpidr, svpet);
5107 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
5108 get_order(ITS_CMD_QUEUE_SZ));
5111 goto out_unmap_sgir;
5113 its->cmd_base = (void *)page_address(page);
5114 its->cmd_write = its->cmd_base;
5115 its->get_msi_base = its_irq_get_msi_base;
5116 its->msi_domain_flags = IRQ_DOMAIN_FLAG_ISOLATED_MSI;
5118 err = its_alloc_tables(its);
5122 err = its_alloc_collections(its);
5124 goto out_free_tables;
5126 baser = (virt_to_phys(its->cmd_base) |
5127 GITS_CBASER_RaWaWb |
5128 GITS_CBASER_InnerShareable |
5129 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
5132 gits_write_cbaser(baser, its->base + GITS_CBASER);
5133 tmp = gits_read_cbaser(its->base + GITS_CBASER);
5135 if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE)
5136 tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
5138 if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
5139 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
5141 * The HW reports non-shareable, we must
5142 * remove the cacheability attributes as
5145 baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
5146 GITS_CBASER_CACHEABILITY_MASK);
5147 baser |= GITS_CBASER_nC;
5148 gits_write_cbaser(baser, its->base + GITS_CBASER);
5150 pr_info("ITS: using cache flushing for cmd queue\n");
5151 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
5154 gits_write_cwriter(0, its->base + GITS_CWRITER);
5155 ctlr = readl_relaxed(its->base + GITS_CTLR);
5156 ctlr |= GITS_CTLR_ENABLE;
5158 ctlr |= GITS_CTLR_ImDe;
5159 writel_relaxed(ctlr, its->base + GITS_CTLR);
5161 err = its_init_domain(its);
5163 goto out_free_tables;
5165 raw_spin_lock(&its_lock);
5166 list_add(&its->entry, &its_nodes);
5167 raw_spin_unlock(&its_lock);
5172 its_free_tables(its);
5174 free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
5177 iounmap(its->sgir_base);
5179 pr_err("ITS@%pa: failed probing (%d)\n", &its->phys_base, err);
5183 static bool gic_rdists_supports_plpis(void)
5185 return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
5188 static int redist_disable_lpis(void)
5190 void __iomem *rbase = gic_data_rdist_rd_base();
5191 u64 timeout = USEC_PER_SEC;
5194 if (!gic_rdists_supports_plpis()) {
5195 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
5199 val = readl_relaxed(rbase + GICR_CTLR);
5200 if (!(val & GICR_CTLR_ENABLE_LPIS))
5204 * If coming via a CPU hotplug event, we don't need to disable
5205 * LPIs before trying to re-enable them. They are already
5206 * configured and all is well in the world.
5208 * If running with preallocated tables, there is nothing to do.
5210 if ((gic_data_rdist()->flags & RD_LOCAL_LPI_ENABLED) ||
5211 (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED))
5215 * From that point on, we only try to do some damage control.
5217 pr_warn("GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n",
5218 smp_processor_id());
5219 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
5222 val &= ~GICR_CTLR_ENABLE_LPIS;
5223 writel_relaxed(val, rbase + GICR_CTLR);
5225 /* Make sure any change to GICR_CTLR is observable by the GIC */
5229 * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs
5230 * from 1 to 0 before programming GICR_PEND{PROP}BASER registers.
5231 * Error out if we time out waiting for RWP to clear.
5233 while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {
5235 pr_err("CPU%d: Timeout while disabling LPIs\n",
5236 smp_processor_id());
5244 * After it has been written to 1, it is IMPLEMENTATION
5245 * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be
5246 * cleared to 0. Error out if clearing the bit failed.
5248 if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {
5249 pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id());
5256 int its_cpu_init(void)
5258 if (!list_empty(&its_nodes)) {
5261 ret = redist_disable_lpis();
5265 its_cpu_init_lpis();
5266 its_cpu_init_collections();
5272 static void rdist_memreserve_cpuhp_cleanup_workfn(struct work_struct *work)
5274 cpuhp_remove_state_nocalls(gic_rdists->cpuhp_memreserve_state);
5275 gic_rdists->cpuhp_memreserve_state = CPUHP_INVALID;
5278 static DECLARE_WORK(rdist_memreserve_cpuhp_cleanup_work,
5279 rdist_memreserve_cpuhp_cleanup_workfn);
5281 static int its_cpu_memreserve_lpi(unsigned int cpu)
5283 struct page *pend_page;
5286 /* This gets to run exactly once per CPU */
5287 if (gic_data_rdist()->flags & RD_LOCAL_MEMRESERVE_DONE)
5290 pend_page = gic_data_rdist()->pend_page;
5291 if (WARN_ON(!pend_page)) {
5296 * If the pending table was pre-programmed, free the memory we
5297 * preemptively allocated. Otherwise, reserve that memory for
5300 if (gic_data_rdist()->flags & RD_LOCAL_PENDTABLE_PREALLOCATED) {
5301 its_free_pending_table(pend_page);
5302 gic_data_rdist()->pend_page = NULL;
5304 phys_addr_t paddr = page_to_phys(pend_page);
5305 WARN_ON(gic_reserve_range(paddr, LPI_PENDBASE_SZ));
5309 /* Last CPU being brought up gets to issue the cleanup */
5310 if (!IS_ENABLED(CONFIG_SMP) ||
5311 cpumask_equal(&cpus_booted_once_mask, cpu_possible_mask))
5312 schedule_work(&rdist_memreserve_cpuhp_cleanup_work);
5314 gic_data_rdist()->flags |= RD_LOCAL_MEMRESERVE_DONE;
5318 /* Mark all the BASER registers as invalid before they get reprogrammed */
5319 static int __init its_reset_one(struct resource *res)
5321 void __iomem *its_base;
5324 its_base = its_map_one(res, &err);
5328 for (i = 0; i < GITS_BASER_NR_REGS; i++)
5329 gits_write_baser(0, its_base + GITS_BASER + (i << 3));
5335 static const struct of_device_id its_device_id[] = {
5336 { .compatible = "arm,gic-v3-its", },
5340 static struct its_node __init *its_node_init(struct resource *res,
5341 struct fwnode_handle *handle, int numa_node)
5343 void __iomem *its_base;
5344 struct its_node *its;
5347 its_base = its_map_one(res, &err);
5351 pr_info("ITS %pR\n", res);
5353 its = kzalloc(sizeof(*its), GFP_KERNEL);
5357 raw_spin_lock_init(&its->lock);
5358 mutex_init(&its->dev_alloc_lock);
5359 INIT_LIST_HEAD(&its->entry);
5360 INIT_LIST_HEAD(&its->its_device_list);
5362 its->typer = gic_read_typer(its_base + GITS_TYPER);
5363 its->base = its_base;
5364 its->phys_base = res->start;
5366 its->numa_node = numa_node;
5367 its->fwnode_handle = handle;
5376 static void its_node_destroy(struct its_node *its)
5382 static int __init its_of_probe(struct device_node *node)
5384 struct device_node *np;
5385 struct resource res;
5389 * Make sure *all* the ITS are reset before we probe any, as
5390 * they may be sharing memory. If any of the ITS fails to
5391 * reset, don't even try to go any further, as this could
5392 * result in something even worse.
5394 for (np = of_find_matching_node(node, its_device_id); np;
5395 np = of_find_matching_node(np, its_device_id)) {
5396 if (!of_device_is_available(np) ||
5397 !of_property_read_bool(np, "msi-controller") ||
5398 of_address_to_resource(np, 0, &res))
5401 err = its_reset_one(&res);
5406 for (np = of_find_matching_node(node, its_device_id); np;
5407 np = of_find_matching_node(np, its_device_id)) {
5408 struct its_node *its;
5410 if (!of_device_is_available(np))
5412 if (!of_property_read_bool(np, "msi-controller")) {
5413 pr_warn("%pOF: no msi-controller property, ITS ignored\n",
5418 if (of_address_to_resource(np, 0, &res)) {
5419 pr_warn("%pOF: no regs?\n", np);
5424 its = its_node_init(&res, &np->fwnode, of_node_to_nid(np));
5428 its_enable_quirks(its);
5429 err = its_probe_one(its);
5431 its_node_destroy(its);
5440 #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)
5442 #ifdef CONFIG_ACPI_NUMA
5443 struct its_srat_map {
5450 static struct its_srat_map *its_srat_maps __initdata;
5451 static int its_in_srat __initdata;
5453 static int __init acpi_get_its_numa_node(u32 its_id)
5457 for (i = 0; i < its_in_srat; i++) {
5458 if (its_id == its_srat_maps[i].its_id)
5459 return its_srat_maps[i].numa_node;
5461 return NUMA_NO_NODE;
5464 static int __init gic_acpi_match_srat_its(union acpi_subtable_headers *header,
5465 const unsigned long end)
5470 static int __init gic_acpi_parse_srat_its(union acpi_subtable_headers *header,
5471 const unsigned long end)
5474 struct acpi_srat_gic_its_affinity *its_affinity;
5476 its_affinity = (struct acpi_srat_gic_its_affinity *)header;
5480 if (its_affinity->header.length < sizeof(*its_affinity)) {
5481 pr_err("SRAT: Invalid header length %d in ITS affinity\n",
5482 its_affinity->header.length);
5487 * Note that in theory a new proximity node could be created by this
5488 * entry as it is an SRAT resource allocation structure.
5489 * We do not currently support doing so.
5491 node = pxm_to_node(its_affinity->proximity_domain);
5493 if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
5494 pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node);
5498 its_srat_maps[its_in_srat].numa_node = node;
5499 its_srat_maps[its_in_srat].its_id = its_affinity->its_id;
5501 pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n",
5502 its_affinity->proximity_domain, its_affinity->its_id, node);
5507 static void __init acpi_table_parse_srat_its(void)
5511 count = acpi_table_parse_entries(ACPI_SIG_SRAT,
5512 sizeof(struct acpi_table_srat),
5513 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
5514 gic_acpi_match_srat_its, 0);
5518 its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map),
5523 acpi_table_parse_entries(ACPI_SIG_SRAT,
5524 sizeof(struct acpi_table_srat),
5525 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
5526 gic_acpi_parse_srat_its, 0);
5529 /* free the its_srat_maps after ITS probing */
5530 static void __init acpi_its_srat_maps_free(void)
5532 kfree(its_srat_maps);
5535 static void __init acpi_table_parse_srat_its(void) { }
5536 static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }
5537 static void __init acpi_its_srat_maps_free(void) { }
5540 static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header,
5541 const unsigned long end)
5543 struct acpi_madt_generic_translator *its_entry;
5544 struct fwnode_handle *dom_handle;
5545 struct its_node *its;
5546 struct resource res;
5549 its_entry = (struct acpi_madt_generic_translator *)header;
5550 memset(&res, 0, sizeof(res));
5551 res.start = its_entry->base_address;
5552 res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1;
5553 res.flags = IORESOURCE_MEM;
5555 dom_handle = irq_domain_alloc_fwnode(&res.start);
5557 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n",
5562 err = iort_register_domain_token(its_entry->translation_id, res.start,
5565 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
5566 &res.start, its_entry->translation_id);
5570 its = its_node_init(&res, dom_handle,
5571 acpi_get_its_numa_node(its_entry->translation_id));
5577 err = its_probe_one(its);
5582 iort_deregister_domain_token(its_entry->translation_id);
5584 irq_domain_free_fwnode(dom_handle);
5588 static int __init its_acpi_reset(union acpi_subtable_headers *header,
5589 const unsigned long end)
5591 struct acpi_madt_generic_translator *its_entry;
5592 struct resource res;
5594 its_entry = (struct acpi_madt_generic_translator *)header;
5595 res = (struct resource) {
5596 .start = its_entry->base_address,
5597 .end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1,
5598 .flags = IORESOURCE_MEM,
5601 return its_reset_one(&res);
5604 static void __init its_acpi_probe(void)
5606 acpi_table_parse_srat_its();
5608 * Make sure *all* the ITS are reset before we probe any, as
5609 * they may be sharing memory. If any of the ITS fails to
5610 * reset, don't even try to go any further, as this could
5611 * result in something even worse.
5613 if (acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
5614 its_acpi_reset, 0) > 0)
5615 acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
5616 gic_acpi_parse_madt_its, 0);
5617 acpi_its_srat_maps_free();
5620 static void __init its_acpi_probe(void) { }
5623 int __init its_lpi_memreserve_init(void)
5627 if (!efi_enabled(EFI_CONFIG_TABLES))
5630 if (list_empty(&its_nodes))
5633 gic_rdists->cpuhp_memreserve_state = CPUHP_INVALID;
5634 state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
5635 "irqchip/arm/gicv3/memreserve:online",
5636 its_cpu_memreserve_lpi,
5641 gic_rdists->cpuhp_memreserve_state = state;
5646 int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
5647 struct irq_domain *parent_domain)
5649 struct device_node *of_node;
5650 struct its_node *its;
5651 bool has_v4 = false;
5652 bool has_v4_1 = false;
5655 gic_rdists = rdists;
5657 its_parent = parent_domain;
5658 of_node = to_of_node(handle);
5660 its_of_probe(of_node);
5664 if (list_empty(&its_nodes)) {
5665 pr_warn("ITS: No ITS available, not enabling LPIs\n");
5669 err = allocate_lpi_tables();
5673 list_for_each_entry(its, &its_nodes, entry) {
5674 has_v4 |= is_v4(its);
5675 has_v4_1 |= is_v4_1(its);
5678 /* Don't bother with inconsistent systems */
5679 if (WARN_ON(!has_v4_1 && rdists->has_rvpeid))
5680 rdists->has_rvpeid = false;
5682 if (has_v4 & rdists->has_vlpis) {
5683 const struct irq_domain_ops *sgi_ops;
5686 sgi_ops = &its_sgi_domain_ops;
5690 if (its_init_vpe_domain() ||
5691 its_init_v4(parent_domain, &its_vpe_domain_ops, sgi_ops)) {
5692 rdists->has_vlpis = false;
5693 pr_err("ITS: Disabling GICv4 support\n");
5697 register_syscore_ops(&its_syscore_ops);