2 * Broadcom BCM7038 style Level 1 interrupt controller driver
4 * Copyright (C) 2014 Broadcom Corporation
5 * Author: Kevin Cernekee
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14 #include <linux/bitops.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
19 #include <linux/ioport.h>
20 #include <linux/irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/module.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_address.h>
26 #include <linux/of_platform.h>
27 #include <linux/platform_device.h>
28 #include <linux/slab.h>
29 #include <linux/smp.h>
30 #include <linux/types.h>
31 #include <linux/irqchip.h>
32 #include <linux/irqchip/chained_irq.h>
34 #define IRQS_PER_WORD 32
35 #define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 4)
38 struct bcm7038_l1_cpu;
40 struct bcm7038_l1_chip {
43 struct irq_domain *domain;
44 struct bcm7038_l1_cpu *cpus[NR_CPUS];
45 u8 affinity[MAX_WORDS * IRQS_PER_WORD];
48 struct bcm7038_l1_cpu {
49 void __iomem *map_base;
54 * STATUS/MASK_STATUS/MASK_SET/MASK_CLEAR are packed one right after another:
57 * 0x1000_1400: W0_STATUS
58 * 0x1000_1404: W1_STATUS
59 * 0x1000_1408: W0_MASK_STATUS
60 * 0x1000_140c: W1_MASK_STATUS
61 * 0x1000_1410: W0_MASK_SET
62 * 0x1000_1414: W1_MASK_SET
63 * 0x1000_1418: W0_MASK_CLEAR
64 * 0x1000_141c: W1_MASK_CLEAR
67 * 0xf03e_1500: W0_STATUS
68 * 0xf03e_1504: W1_STATUS
69 * 0xf03e_1508: W2_STATUS
70 * 0xf03e_150c: W3_STATUS
71 * 0xf03e_1510: W4_STATUS
72 * 0xf03e_1514: W0_MASK_STATUS
73 * 0xf03e_1518: W1_MASK_STATUS
77 static inline unsigned int reg_status(struct bcm7038_l1_chip *intc,
80 return (0 * intc->n_words + word) * sizeof(u32);
83 static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc,
86 return (1 * intc->n_words + word) * sizeof(u32);
89 static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc,
92 return (2 * intc->n_words + word) * sizeof(u32);
95 static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc,
98 return (3 * intc->n_words + word) * sizeof(u32);
101 static inline u32 l1_readl(void __iomem *reg)
103 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
104 return ioread32be(reg);
109 static inline void l1_writel(u32 val, void __iomem *reg)
111 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
112 iowrite32be(val, reg);
117 static void bcm7038_l1_irq_handle(struct irq_desc *desc)
119 struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc);
120 struct bcm7038_l1_cpu *cpu;
121 struct irq_chip *chip = irq_desc_get_chip(desc);
125 cpu = intc->cpus[cpu_logical_map(smp_processor_id())];
130 chained_irq_enter(chip, desc);
132 for (idx = 0; idx < intc->n_words; idx++) {
133 int base = idx * IRQS_PER_WORD;
134 unsigned long pending, flags;
137 raw_spin_lock_irqsave(&intc->lock, flags);
138 pending = l1_readl(cpu->map_base + reg_status(intc, idx)) &
139 ~cpu->mask_cache[idx];
140 raw_spin_unlock_irqrestore(&intc->lock, flags);
142 for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
143 generic_handle_irq(irq_find_mapping(intc->domain,
148 chained_irq_exit(chip, desc);
151 static void __bcm7038_l1_unmask(struct irq_data *d, unsigned int cpu_idx)
153 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
154 u32 word = d->hwirq / IRQS_PER_WORD;
155 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
157 intc->cpus[cpu_idx]->mask_cache[word] &= ~mask;
158 l1_writel(mask, intc->cpus[cpu_idx]->map_base +
159 reg_mask_clr(intc, word));
162 static void __bcm7038_l1_mask(struct irq_data *d, unsigned int cpu_idx)
164 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
165 u32 word = d->hwirq / IRQS_PER_WORD;
166 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
168 intc->cpus[cpu_idx]->mask_cache[word] |= mask;
169 l1_writel(mask, intc->cpus[cpu_idx]->map_base +
170 reg_mask_set(intc, word));
173 static void bcm7038_l1_unmask(struct irq_data *d)
175 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
178 raw_spin_lock_irqsave(&intc->lock, flags);
179 __bcm7038_l1_unmask(d, intc->affinity[d->hwirq]);
180 raw_spin_unlock_irqrestore(&intc->lock, flags);
183 static void bcm7038_l1_mask(struct irq_data *d)
185 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
188 raw_spin_lock_irqsave(&intc->lock, flags);
189 __bcm7038_l1_mask(d, intc->affinity[d->hwirq]);
190 raw_spin_unlock_irqrestore(&intc->lock, flags);
193 static int bcm7038_l1_set_affinity(struct irq_data *d,
194 const struct cpumask *dest,
197 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
199 irq_hw_number_t hw = d->hwirq;
200 u32 word = hw / IRQS_PER_WORD;
201 u32 mask = BIT(hw % IRQS_PER_WORD);
202 unsigned int first_cpu = cpumask_any_and(dest, cpu_online_mask);
205 raw_spin_lock_irqsave(&intc->lock, flags);
207 was_disabled = !!(intc->cpus[intc->affinity[hw]]->mask_cache[word] &
209 __bcm7038_l1_mask(d, intc->affinity[hw]);
210 intc->affinity[hw] = first_cpu;
212 __bcm7038_l1_unmask(d, first_cpu);
214 raw_spin_unlock_irqrestore(&intc->lock, flags);
215 irq_data_update_effective_affinity(d, cpumask_of(first_cpu));
221 static void bcm7038_l1_cpu_offline(struct irq_data *d)
223 struct cpumask *mask = irq_data_get_affinity_mask(d);
224 int cpu = smp_processor_id();
225 cpumask_t new_affinity;
227 /* This CPU was not on the affinity mask */
228 if (!cpumask_test_cpu(cpu, mask))
231 if (cpumask_weight(mask) > 1) {
233 * Multiple CPU affinity, remove this CPU from the affinity
236 cpumask_copy(&new_affinity, mask);
237 cpumask_clear_cpu(cpu, &new_affinity);
239 /* Only CPU, put on the lowest online CPU */
240 cpumask_clear(&new_affinity);
241 cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
243 irq_set_affinity_locked(d, &new_affinity, false);
247 static int __init bcm7038_l1_init_one(struct device_node *dn,
249 struct bcm7038_l1_chip *intc)
253 struct bcm7038_l1_cpu *cpu;
254 unsigned int i, n_words, parent_irq;
256 if (of_address_to_resource(dn, idx, &res))
258 sz = resource_size(&res);
259 n_words = sz / REG_BYTES_PER_IRQ_WORD;
261 if (n_words > MAX_WORDS)
263 else if (!intc->n_words)
264 intc->n_words = n_words;
265 else if (intc->n_words != n_words)
268 cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
273 cpu->map_base = ioremap(res.start, sz);
277 for (i = 0; i < n_words; i++) {
278 l1_writel(0xffffffff, cpu->map_base + reg_mask_set(intc, i));
279 cpu->mask_cache[i] = 0xffffffff;
282 parent_irq = irq_of_parse_and_map(dn, idx);
284 pr_err("failed to map parent interrupt %d\n", parent_irq);
287 irq_set_chained_handler_and_data(parent_irq, bcm7038_l1_irq_handle,
293 static struct irq_chip bcm7038_l1_irq_chip = {
294 .name = "bcm7038-l1",
295 .irq_mask = bcm7038_l1_mask,
296 .irq_unmask = bcm7038_l1_unmask,
297 .irq_set_affinity = bcm7038_l1_set_affinity,
299 .irq_cpu_offline = bcm7038_l1_cpu_offline,
303 static int bcm7038_l1_map(struct irq_domain *d, unsigned int virq,
304 irq_hw_number_t hw_irq)
306 irq_set_chip_and_handler(virq, &bcm7038_l1_irq_chip, handle_level_irq);
307 irq_set_chip_data(virq, d->host_data);
308 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
312 static const struct irq_domain_ops bcm7038_l1_domain_ops = {
313 .xlate = irq_domain_xlate_onecell,
314 .map = bcm7038_l1_map,
317 int __init bcm7038_l1_of_init(struct device_node *dn,
318 struct device_node *parent)
320 struct bcm7038_l1_chip *intc;
323 intc = kzalloc(sizeof(*intc), GFP_KERNEL);
327 raw_spin_lock_init(&intc->lock);
328 for_each_possible_cpu(idx) {
329 ret = bcm7038_l1_init_one(dn, idx, intc);
333 pr_err("failed to remap intc L1 registers\n");
338 intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words,
339 &bcm7038_l1_domain_ops,
349 for_each_possible_cpu(idx) {
350 struct bcm7038_l1_cpu *cpu = intc->cpus[idx];
354 iounmap(cpu->map_base);
363 IRQCHIP_DECLARE(bcm7038_l1, "brcm,bcm7038-l1-intc", bcm7038_l1_of_init);