1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2010 Broadcom
4 * Copyright 2012 Simon Arlott, Chris Boot, Stephen Warren
6 * Quirk 1: Shortcut interrupts don't set the bank 1/2 register pending bits
8 * If an interrupt fires on bank 1 that isn't in the shortcuts list, bit 8
9 * on bank 0 is set to signify that an interrupt in bank 1 has fired, and
10 * to look in the bank 1 status register for more information.
12 * If an interrupt fires on bank 1 that _is_ in the shortcuts list, its
13 * shortcut bit in bank 0 is set as well as its interrupt bit in the bank 1
14 * status register, but bank 0 bit 8 is _not_ set.
16 * Quirk 2: You can't mask the register 1/2 pending interrupts
18 * In a proper cascaded interrupt controller, the interrupt lines with
19 * cascaded interrupt controllers on them are just normal interrupt lines.
20 * You can mask the interrupts and get on with things. With this controller
23 * Quirk 3: The shortcut interrupts can't be (un)masked in bank 0
25 * Those interrupts that have shortcuts can only be masked/unmasked in
26 * their respective banks' enable/disable registers. Doing so in the bank 0
27 * enable/disable registers has no effect.
29 * The FIQ control register:
30 * Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
31 * Bit 7: Enable FIQ generation
34 * An interrupt must be disabled before configuring it for FIQ generation
35 * otherwise both handlers will fire at the same time!
39 #include <linux/slab.h>
40 #include <linux/of_address.h>
41 #include <linux/of_irq.h>
42 #include <linux/irqchip.h>
43 #include <linux/irqdomain.h>
45 #include <asm/exception.h>
47 #include <asm/mach/irq.h>
50 /* Put the bank and irq (32 bits) into the hwirq */
51 #define MAKE_HWIRQ(b, n) (((b) << 5) | (n))
52 #define HWIRQ_BANK(i) (i >> 5)
53 #define HWIRQ_BIT(i) BIT(i & 0x1f)
55 #define NR_IRQS_BANK0 8
56 #define BANK0_HWIRQ_MASK 0xff
57 /* Shortcuts can't be disabled so any unknown new ones need to be masked */
58 #define SHORTCUT1_MASK 0x00007c00
59 #define SHORTCUT2_MASK 0x001f8000
60 #define SHORTCUT_SHIFT 10
61 #define BANK1_HWIRQ BIT(8)
62 #define BANK2_HWIRQ BIT(9)
63 #define BANK0_VALID_MASK (BANK0_HWIRQ_MASK | BANK1_HWIRQ | BANK2_HWIRQ \
64 | SHORTCUT1_MASK | SHORTCUT2_MASK)
66 #undef ARM_LOCAL_GPU_INT_ROUTING
67 #define ARM_LOCAL_GPU_INT_ROUTING 0x0c
69 #define REG_FIQ_CONTROL 0x0c
70 #define FIQ_CONTROL_ENABLE BIT(7)
71 #define REG_FIQ_ENABLE FIQ_CONTROL_ENABLE
72 #define REG_FIQ_DISABLE 0
75 #define IRQS_PER_BANK 32
76 #define NUMBER_IRQS MAKE_HWIRQ(NR_BANKS, 0)
78 static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };
79 static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
80 static const int reg_disable[] __initconst = { 0x24, 0x1c, 0x20 };
81 static const int bank_irqs[] __initconst = { 8, 32, 32 };
83 static const int shortcuts[] = {
84 7, 9, 10, 18, 19, /* Bank 1 */
85 21, 22, 23, 24, 25, 30 /* Bank 2 */
90 void __iomem *pending[NR_BANKS];
91 void __iomem *enable[NR_BANKS];
92 void __iomem *disable[NR_BANKS];
93 struct irq_domain *domain;
94 void __iomem *local_base;
97 static struct armctrl_ic intc __read_mostly;
98 static void __exception_irq_entry bcm2835_handle_irq(
99 struct pt_regs *regs);
100 static void bcm2836_chained_handle_irq(struct irq_desc *desc);
102 static inline unsigned int hwirq_to_fiq(unsigned long hwirq)
104 hwirq -= NUMBER_IRQS;
106 * The hwirq numbering used in this driver is:
107 * BASE (0-7) GPU1 (32-63) GPU2 (64-95).
108 * This differ from the one used in the FIQ register:
109 * GPU1 (0-31) GPU2 (32-63) BASE (64-71)
117 static void armctrl_mask_irq(struct irq_data *d)
119 if (d->hwirq >= NUMBER_IRQS)
120 writel_relaxed(REG_FIQ_DISABLE, intc.base + REG_FIQ_CONTROL);
122 writel_relaxed(HWIRQ_BIT(d->hwirq),
123 intc.disable[HWIRQ_BANK(d->hwirq)]);
126 static void armctrl_unmask_irq(struct irq_data *d)
128 if (d->hwirq >= NUMBER_IRQS) {
129 if (num_online_cpus() > 1) {
132 if (!intc.local_base) {
133 pr_err("FIQ is disabled due to missing arm_local_intc\n");
137 data = readl_relaxed(intc.local_base +
138 ARM_LOCAL_GPU_INT_ROUTING);
144 ARM_LOCAL_GPU_INT_ROUTING);
147 writel_relaxed(REG_FIQ_ENABLE | hwirq_to_fiq(d->hwirq),
148 intc.base + REG_FIQ_CONTROL);
150 writel_relaxed(HWIRQ_BIT(d->hwirq),
151 intc.enable[HWIRQ_BANK(d->hwirq)]);
156 void bcm2836_arm_irqchip_spin_gpu_irq(void);
158 static void armctrl_ack_irq(struct irq_data *d)
160 bcm2836_arm_irqchip_spin_gpu_irq();
165 static struct irq_chip armctrl_chip = {
166 .name = "ARMCTRL-level",
167 .irq_mask = armctrl_mask_irq,
168 .irq_unmask = armctrl_unmask_irq,
170 .irq_ack = armctrl_ack_irq
174 static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
175 const u32 *intspec, unsigned int intsize,
176 unsigned long *out_hwirq, unsigned int *out_type)
178 if (WARN_ON(intsize != 2))
181 if (WARN_ON(intspec[0] >= NR_BANKS))
184 if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
187 if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
190 *out_hwirq = MAKE_HWIRQ(intspec[0], intspec[1]);
191 *out_type = IRQ_TYPE_NONE;
195 static const struct irq_domain_ops armctrl_ops = {
196 .xlate = armctrl_xlate
199 static int __init armctrl_of_init(struct device_node *node,
200 struct device_node *parent,
204 int irq = 0, last_irq, b, i;
207 base = of_iomap(node, 0);
209 panic("%pOF: unable to map IC registers\n", node);
212 intc.domain = irq_domain_add_linear(node, NUMBER_IRQS * 2,
215 panic("%pOF: unable to create IRQ domain\n", node);
217 for (b = 0; b < NR_BANKS; b++) {
218 intc.pending[b] = base + reg_pending[b];
219 intc.enable[b] = base + reg_enable[b];
220 intc.disable[b] = base + reg_disable[b];
222 for (i = 0; i < bank_irqs[b]; i++) {
223 irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i));
225 irq_set_chip_and_handler(irq, &armctrl_chip,
230 reg = readl_relaxed(intc.enable[b]);
232 writel_relaxed(reg, intc.disable[b]);
233 pr_err(FW_BUG "Bootloader left irq enabled: "
234 "bank %d irq %*pbl\n", b, IRQS_PER_BANK, ®);
238 reg = readl_relaxed(base + REG_FIQ_CONTROL);
239 if (reg & FIQ_CONTROL_ENABLE) {
240 writel_relaxed(0, base + REG_FIQ_CONTROL);
241 pr_err(FW_BUG "Bootloader left fiq enabled\n");
247 int parent_irq = irq_of_parse_and_map(node, 0);
250 panic("%pOF: unable to get parent interrupt.\n",
253 irq_set_chained_handler(parent_irq, bcm2836_chained_handle_irq);
255 set_handle_irq(bcm2835_handle_irq);
259 extern void __iomem * __attribute__((weak)) arm_local_intc;
260 intc.local_base = arm_local_intc;
261 if (!intc.local_base)
262 pr_err("Failed to get local intc base. FIQ is disabled for cpus > 1\n");
265 /* Make a duplicate irq range which is used to enable FIQ */
266 for (b = 0; b < NR_BANKS; b++) {
267 for (i = 0; i < bank_irqs[b]; i++) {
268 irq = irq_create_mapping(intc.domain,
269 MAKE_HWIRQ(b, i) + NUMBER_IRQS);
271 irq_set_chip(irq, &armctrl_chip);
276 init_FIQ(irq - last_irq);
282 static int __init bcm2835_armctrl_of_init(struct device_node *node,
283 struct device_node *parent)
285 return armctrl_of_init(node, parent, false);
288 static int __init bcm2836_armctrl_of_init(struct device_node *node,
289 struct device_node *parent)
291 return armctrl_of_init(node, parent, true);
296 * Handle each interrupt across the entire interrupt controller. This reads the
297 * status register before handling each interrupt, which is necessary given that
298 * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
301 static u32 armctrl_translate_bank(int bank)
303 u32 stat = readl_relaxed(intc.pending[bank]);
305 return MAKE_HWIRQ(bank, ffs(stat) - 1);
308 static u32 armctrl_translate_shortcut(int bank, u32 stat)
310 return MAKE_HWIRQ(bank, shortcuts[ffs(stat >> SHORTCUT_SHIFT) - 1]);
313 static u32 get_next_armctrl_hwirq(void)
315 u32 stat = readl_relaxed(intc.pending[0]) & BANK0_VALID_MASK;
319 else if (stat & BANK0_HWIRQ_MASK)
320 return MAKE_HWIRQ(0, ffs(stat & BANK0_HWIRQ_MASK) - 1);
321 else if (stat & SHORTCUT1_MASK)
322 return armctrl_translate_shortcut(1, stat & SHORTCUT1_MASK);
323 else if (stat & SHORTCUT2_MASK)
324 return armctrl_translate_shortcut(2, stat & SHORTCUT2_MASK);
325 else if (stat & BANK1_HWIRQ)
326 return armctrl_translate_bank(1);
327 else if (stat & BANK2_HWIRQ)
328 return armctrl_translate_bank(2);
333 static void __exception_irq_entry bcm2835_handle_irq(
334 struct pt_regs *regs)
338 while ((hwirq = get_next_armctrl_hwirq()) != ~0)
339 handle_domain_irq(intc.domain, hwirq, regs);
342 static void bcm2836_chained_handle_irq(struct irq_desc *desc)
346 while ((hwirq = get_next_armctrl_hwirq()) != ~0)
347 generic_handle_domain_irq(intc.domain, hwirq);
350 IRQCHIP_DECLARE(bcm2835_armctrl_ic, "brcm,bcm2835-armctrl-ic",
351 bcm2835_armctrl_of_init);
352 IRQCHIP_DECLARE(bcm2836_armctrl_ic, "brcm,bcm2836-armctrl-ic",
353 bcm2836_armctrl_of_init);