1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "IRQ chip support"
6 depends on (OF_IRQ || ACPI_GENERIC_GSI)
11 select IRQ_DOMAIN_HIERARCHY
12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
22 default 2 if ARCH_REALVIEW
36 select IRQ_DOMAIN_HIERARCHY
37 select PARTITION_PERCPU
38 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
39 select HAVE_ARM_SMCCC_DISCOVERY
43 select GENERIC_MSI_IRQ
46 config ARM_GIC_V3_ITS_PCI
48 depends on ARM_GIC_V3_ITS
51 default ARM_GIC_V3_ITS
53 config ARM_GIC_V3_ITS_FSL_MC
55 depends on ARM_GIC_V3_ITS
57 default ARM_GIC_V3_ITS
61 select IRQ_DOMAIN_HIERARCHY
62 select GENERIC_IRQ_CHIP
70 default 4 if ARCH_S5PV210
74 The maximum number of VICs available in the system, for
77 config ARMADA_370_XP_IRQ
79 select GENERIC_IRQ_CHIP
81 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
87 select GENERIC_IRQ_CHIP
90 bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
93 select GENERIC_IRQ_CHIP
96 Support Amazon's Annapurna Labs Fabric Interrupt Controller.
100 select GENERIC_IRQ_CHIP
104 config ATMEL_AIC5_IRQ
106 select GENERIC_IRQ_CHIP
114 config BCM6345_L1_IRQ
116 select GENERIC_IRQ_CHIP
118 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
120 config BCM7038_L1_IRQ
121 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
122 depends on ARCH_BRCMSTB || BMIPS_GENERIC
123 default ARCH_BRCMSTB || BMIPS_GENERIC
124 select GENERIC_IRQ_CHIP
126 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
128 config BCM7120_L2_IRQ
129 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
130 depends on ARCH_BRCMSTB || BMIPS_GENERIC
131 default ARCH_BRCMSTB || BMIPS_GENERIC
132 select GENERIC_IRQ_CHIP
135 config BRCMSTB_L2_IRQ
136 tristate "Broadcom STB generic L2 interrupt controller driver"
137 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
138 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
139 select GENERIC_IRQ_CHIP
142 config DAVINCI_CP_INTC
144 select GENERIC_IRQ_CHIP
149 select GENERIC_IRQ_CHIP
150 select IRQ_DOMAIN_HIERARCHY
152 config FARADAY_FTINTC010
157 config HISILICON_IRQ_MBIGEN
160 select ARM_GIC_V3_ITS
164 select GENERIC_IRQ_CHIP
177 select GENERIC_IRQ_CHIP
178 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING
180 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
182 config CLPS711X_IRQCHIP
184 depends on ARCH_CLPS711X
198 select GENERIC_IRQ_CHIP
207 select GENERIC_IRQ_CHIP
211 bool "J-Core integrated AIC" if COMPILE_TEST
215 Support for the J-Core integrated AIC.
221 config RENESAS_INTC_IRQPIN
222 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
225 Enable support for the Renesas Interrupt Controller for external
226 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
229 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
230 select GENERIC_IRQ_CHIP
233 Enable support for the Renesas Interrupt Controller for external
234 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
236 config RENESAS_RZA1_IRQC
237 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
238 select IRQ_DOMAIN_HIERARCHY
240 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
241 to 8 external interrupts with configurable sense select.
243 config RENESAS_RZG2L_IRQC
244 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST
245 select GENERIC_IRQ_CHIP
246 select IRQ_DOMAIN_HIERARCHY
248 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller
249 for external devices.
252 bool "Kontron sl28cpld IRQ controller"
253 depends on MFD_SL28CPLD=y || COMPILE_TEST
256 Interrupt controller driver for the board management controller
257 found on the Kontron sl28 CPLD.
264 Enables SysCfg Controlled IRQs on STi based platforms.
271 select IRQ_DOMAIN_HIERARCHY
272 select IRQ_FASTEOI_HIERARCHY_HANDLERS
274 config SUNXI_NMI_INTC
276 select GENERIC_IRQ_CHIP
281 select GENERIC_IRQ_CHIP
284 tristate "TS-4800 IRQ controller"
287 depends on SOC_IMX51 || COMPILE_TEST
289 Support for the TS-4800 FPGA IRQ controller
291 config VERSATILE_FPGA_IRQ
295 config VERSATILE_FPGA_IRQ_NR
298 depends on VERSATILE_FPGA_IRQ
303 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
306 bool "Xilinx Interrupt Controller IP"
307 depends on OF_ADDRESS
310 Support for the Xilinx Interrupt Controller IP core.
311 This is used as a primary controller with MicroBlaze and can also
312 be used as a secondary chained controller on other platforms.
317 Support for a CROSSBAR ip that precedes the main interrupt controller.
318 The primary irqchip invokes the crossbar's callback which inturn allocates
319 a free irq and configures the IP. Thus the peripheral interrupts are
320 routed to one of the free irqchip interrupt lines.
323 tristate "Keystone 2 IRQ controller IP"
324 depends on ARCH_KEYSTONE
326 Support for Texas Instruments Keystone 2 IRQ controller IP which
327 is part of the Keystone 2 IPC mechanism
331 select GENERIC_IRQ_IPI if SMP
332 select IRQ_DOMAIN_HIERARCHY
337 depends on MACH_INGENIC
340 config INGENIC_TCU_IRQ
341 bool "Ingenic JZ47xx TCU interrupt controller"
343 depends on MIPS || COMPILE_TEST
345 select GENERIC_IRQ_CHIP
347 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
356 Enables the wakeup IRQs for IMX platforms with GPCv2 block
359 def_bool y if MACH_ASM9260 || ARCH_MXS
363 config MSCC_OCELOT_IRQ
366 select GENERIC_IRQ_CHIP
376 select GENERIC_MSI_IRQ
385 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
389 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
392 config PARTITION_PERCPU
398 select GENERIC_IRQ_CHIP
400 config QCOM_IRQ_COMBINER
401 bool "QCOM IRQ combiner support"
402 depends on ARCH_QCOM && ACPI
403 select IRQ_DOMAIN_HIERARCHY
405 Say yes here to add support for the IRQ combiner devices embedded
406 in Qualcomm Technologies chips.
408 config IRQ_UNIPHIER_AIDET
409 bool "UniPhier AIDET support" if COMPILE_TEST
410 depends on ARCH_UNIPHIER || COMPILE_TEST
411 default ARCH_UNIPHIER
412 select IRQ_DOMAIN_HIERARCHY
414 Support for the UniPhier AIDET (ARM Interrupt Detector).
416 config MESON_IRQ_GPIO
417 tristate "Meson GPIO Interrupt Multiplexer"
418 depends on ARCH_MESON || COMPILE_TEST
420 select IRQ_DOMAIN_HIERARCHY
422 Support Meson SoC Family GPIO Interrupt Multiplexer
425 bool "Goldfish programmable interrupt controller"
426 depends on MIPS && (GOLDFISH || COMPILE_TEST)
427 select GENERIC_IRQ_CHIP
430 Say yes here to enable Goldfish interrupt controller driver used
431 for Goldfish based virtual platforms.
436 select IRQ_DOMAIN_HIERARCHY
438 Power Domain Controller driver to manage and configure wakeup
439 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
445 select IRQ_DOMAIN_HIERARCHY
447 MSM Power Manager driver to manage and configure wakeup
448 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
454 Say yes here to enable C-SKY SMP interrupt controller driver used
455 for C-SKY SMP system.
456 In fact it's not mmio map in hardware and it uses ld/st to visit the
457 controller's register inside CPU.
460 bool "C-SKY APB Interrupt Controller"
463 Say yes here to enable C-SKY APB interrupt controller driver used
464 by C-SKY single core SOC system. It uses mmio map apb-bus to visit
465 the controller's register.
468 bool "i.MX IRQSTEER support"
469 depends on ARCH_MXC || COMPILE_TEST
473 Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
476 bool "i.MX INTMUX support" if COMPILE_TEST
477 default y if ARCH_MXC
480 Support for the i.MX INTMUX interrupt multiplexer.
483 tristate "i.MX MU used as MSI controller"
484 depends on OF && HAS_IOMEM
485 depends on ARCH_MXC || COMPILE_TEST
486 default m if ARCH_MXC
488 select IRQ_DOMAIN_HIERARCHY
489 select GENERIC_MSI_IRQ
491 Provide a driver for the i.MX Messaging Unit block used as a
492 CPU-to-CPU MSI controller. This requires a specially crafted DT
493 to make use of this driver.
498 bool "Loongson-1 Interrupt Controller"
499 depends on MACH_LOONGSON32
502 select GENERIC_IRQ_CHIP
504 Support for the Loongson-1 platform Interrupt Controller.
506 config TI_SCI_INTR_IRQCHIP
508 depends on TI_SCI_PROTOCOL
509 select IRQ_DOMAIN_HIERARCHY
511 This enables the irqchip driver support for K3 Interrupt router
512 over TI System Control Interface available on some new TI's SoCs.
513 If you wish to use interrupt router irq resources managed by the
514 TI System Controller, say Y here. Otherwise, say N.
516 config TI_SCI_INTA_IRQCHIP
518 depends on TI_SCI_PROTOCOL
519 select IRQ_DOMAIN_HIERARCHY
520 select TI_SCI_INTA_MSI_DOMAIN
522 This enables the irqchip driver support for K3 Interrupt aggregator
523 over TI System Control Interface available on some new TI's SoCs.
524 If you wish to use interrupt aggregator irq resources managed by the
525 TI System Controller, say Y here. Otherwise, say N.
533 This enables support for the PRU-ICSS Local Interrupt Controller
534 present within a PRU-ICSS subsystem present on various TI SoCs.
535 The PRUSS INTC enables various interrupts to be routed to multiple
536 different processors within the SoC.
541 select IRQ_DOMAIN_HIERARCHY
546 select IRQ_DOMAIN_HIERARCHY
547 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
549 config EXYNOS_IRQ_COMBINER
550 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
551 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
553 Say yes here to add support for the IRQ combiner devices embedded
554 in Samsung Exynos chips.
556 config IRQ_LOONGARCH_CPU
558 select GENERIC_IRQ_CHIP
560 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
561 select LOONGSON_HTVEC
562 select LOONGSON_LIOINTC
563 select LOONGSON_EIOINTC
564 select LOONGSON_PCH_PIC
565 select LOONGSON_PCH_MSI
566 select LOONGSON_PCH_LPC
568 Support for the LoongArch CPU Interrupt Controller. For details of
569 irq chip hierarchy on LoongArch platforms please read the document
570 Documentation/arch/loongarch/irq-chip-model.rst.
572 config LOONGSON_LIOINTC
573 bool "Loongson Local I/O Interrupt Controller"
574 depends on MACH_LOONGSON64
577 select GENERIC_IRQ_CHIP
579 Support for the Loongson Local I/O Interrupt Controller.
581 config LOONGSON_EIOINTC
582 bool "Loongson Extend I/O Interrupt Controller"
584 depends on MACH_LOONGSON64
585 default MACH_LOONGSON64
586 select IRQ_DOMAIN_HIERARCHY
587 select GENERIC_IRQ_CHIP
589 Support for the Loongson3 Extend I/O Interrupt Vector Controller.
591 config LOONGSON_HTPIC
592 bool "Loongson3 HyperTransport PIC Controller"
593 depends on MACH_LOONGSON64 && MIPS
596 select GENERIC_IRQ_CHIP
598 Support for the Loongson-3 HyperTransport PIC Controller.
600 config LOONGSON_HTVEC
601 bool "Loongson HyperTransport Interrupt Vector Controller"
602 depends on MACH_LOONGSON64
603 default MACH_LOONGSON64
604 select IRQ_DOMAIN_HIERARCHY
606 Support for the Loongson HyperTransport Interrupt Vector Controller.
608 config LOONGSON_PCH_PIC
609 bool "Loongson PCH PIC Controller"
610 depends on MACH_LOONGSON64
611 default MACH_LOONGSON64
612 select IRQ_DOMAIN_HIERARCHY
613 select IRQ_FASTEOI_HIERARCHY_HANDLERS
615 Support for the Loongson PCH PIC Controller.
617 config LOONGSON_PCH_MSI
618 bool "Loongson PCH MSI Controller"
619 depends on MACH_LOONGSON64
621 default MACH_LOONGSON64
622 select IRQ_DOMAIN_HIERARCHY
625 Support for the Loongson PCH MSI Controller.
627 config LOONGSON_PCH_LPC
628 bool "Loongson PCH LPC Controller"
630 depends on MACH_LOONGSON64
631 default MACH_LOONGSON64
632 select IRQ_DOMAIN_HIERARCHY
634 Support for the Loongson PCH LPC Controller.
637 bool "MStar Interrupt Controller"
638 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
639 default ARCH_MEDIATEK
641 select IRQ_DOMAIN_HIERARCHY
643 Support MStar Interrupt Controller.
646 bool "Nuvoton WPCM450 Advanced Interrupt Controller"
647 depends on ARCH_WPCM450
649 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC.
653 select GENERIC_IRQ_CHIP
657 bool "Apple Interrupt Controller (AIC)"
659 depends on ARCH_APPLE || COMPILE_TEST
660 select GENERIC_IRQ_IPI_MUX
662 Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
666 bool "Microchip External Interrupt Controller"
667 depends on ARCH_AT91 || COMPILE_TEST
669 select IRQ_DOMAIN_HIERARCHY
671 Support for Microchip External Interrupt Controller.
673 config SUNPLUS_SP7021_INTC
674 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST
677 Support for the Sunplus SP7021 Interrupt Controller IP core.
678 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a
679 chained controller, routing all interrupt source in P-Chip to
680 the primary controller on C-Chip.