1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "IRQ chip support"
10 select IRQ_DOMAIN_HIERARCHY
11 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
21 default 2 if ARCH_REALVIEW
35 select IRQ_DOMAIN_HIERARCHY
36 select PARTITION_PERCPU
37 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
41 select GENERIC_MSI_IRQ_DOMAIN
44 config ARM_GIC_V3_ITS_PCI
46 depends on ARM_GIC_V3_ITS
49 default ARM_GIC_V3_ITS
51 config ARM_GIC_V3_ITS_FSL_MC
53 depends on ARM_GIC_V3_ITS
55 default ARM_GIC_V3_ITS
59 select IRQ_DOMAIN_HIERARCHY
60 select GENERIC_IRQ_CHIP
68 default 4 if ARCH_S5PV210
72 The maximum number of VICs available in the system, for
75 config ARMADA_370_XP_IRQ
77 select GENERIC_IRQ_CHIP
79 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
85 select GENERIC_IRQ_CHIP
88 bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
89 depends on OF || COMPILE_TEST
90 select GENERIC_IRQ_CHIP
93 Support Amazon's Annapurna Labs Fabric Interrupt Controller.
97 select GENERIC_IRQ_CHIP
101 config ATMEL_AIC5_IRQ
103 select GENERIC_IRQ_CHIP
111 config BCM6345_L1_IRQ
113 select GENERIC_IRQ_CHIP
115 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
117 config BCM7038_L1_IRQ
119 select GENERIC_IRQ_CHIP
121 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
123 config BCM7120_L2_IRQ
125 select GENERIC_IRQ_CHIP
128 config BRCMSTB_L2_IRQ
130 select GENERIC_IRQ_CHIP
135 select GENERIC_IRQ_CHIP
138 config DAVINCI_CP_INTC
140 select GENERIC_IRQ_CHIP
145 select GENERIC_IRQ_CHIP
146 select IRQ_DOMAIN_HIERARCHY
148 config FARADAY_FTINTC010
153 config HISILICON_IRQ_MBIGEN
156 select ARM_GIC_V3_ITS
160 select GENERIC_IRQ_CHIP
173 select GENERIC_IRQ_CHIP
174 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING
176 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
178 config CLPS711X_IRQCHIP
180 depends on ARCH_CLPS711X
194 select GENERIC_IRQ_CHIP
203 select GENERIC_IRQ_CHIP
207 bool "J-Core integrated AIC" if COMPILE_TEST
211 Support for the J-Core integrated AIC.
217 config RENESAS_INTC_IRQPIN
218 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
221 Enable support for the Renesas Interrupt Controller for external
222 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
225 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
226 select GENERIC_IRQ_CHIP
229 Enable support for the Renesas Interrupt Controller for external
230 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
232 config RENESAS_RZA1_IRQC
233 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
234 select IRQ_DOMAIN_HIERARCHY
236 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
237 to 8 external interrupts with configurable sense select.
240 bool "Kontron sl28cpld IRQ controller"
241 depends on MFD_SL28CPLD=y || COMPILE_TEST
244 Interrupt controller driver for the board management controller
245 found on the Kontron sl28 CPLD.
252 Enables SysCfg Controlled IRQs on STi based platforms.
257 select GENERIC_IRQ_CHIP
260 tristate "TS-4800 IRQ controller"
263 depends on SOC_IMX51 || COMPILE_TEST
265 Support for the TS-4800 FPGA IRQ controller
267 config VERSATILE_FPGA_IRQ
271 config VERSATILE_FPGA_IRQ_NR
274 depends on VERSATILE_FPGA_IRQ
279 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
282 bool "Xilinx Interrupt Controller IP"
283 depends on MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP
286 Support for the Xilinx Interrupt Controller IP core.
287 This is used as a primary controller with MicroBlaze and can also
288 be used as a secondary chained controller on other platforms.
293 Support for a CROSSBAR ip that precedes the main interrupt controller.
294 The primary irqchip invokes the crossbar's callback which inturn allocates
295 a free irq and configures the IP. Thus the peripheral interrupts are
296 routed to one of the free irqchip interrupt lines.
299 tristate "Keystone 2 IRQ controller IP"
300 depends on ARCH_KEYSTONE
302 Support for Texas Instruments Keystone 2 IRQ controller IP which
303 is part of the Keystone 2 IPC mechanism
307 select GENERIC_IRQ_IPI if SMP
308 select IRQ_DOMAIN_HIERARCHY
313 depends on MACH_INGENIC
316 config INGENIC_TCU_IRQ
317 bool "Ingenic JZ47xx TCU interrupt controller"
319 depends on MIPS || COMPILE_TEST
321 select GENERIC_IRQ_CHIP
323 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
328 config RENESAS_H8300H_INTC
332 config RENESAS_H8S_INTC
333 bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST
336 Enable support for the Renesas H8/300 Interrupt Controller, as found
343 Enables the wakeup IRQs for IMX platforms with GPCv2 block
346 def_bool y if MACH_ASM9260 || ARCH_MXS
350 config MSCC_OCELOT_IRQ
353 select GENERIC_IRQ_CHIP
363 select GENERIC_MSI_IRQ_DOMAIN
372 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
376 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
377 depends on PCI && PCI_MSI
379 config PARTITION_PERCPU
385 select GENERIC_IRQ_CHIP
387 config QCOM_IRQ_COMBINER
388 bool "QCOM IRQ combiner support"
389 depends on ARCH_QCOM && ACPI
390 select IRQ_DOMAIN_HIERARCHY
392 Say yes here to add support for the IRQ combiner devices embedded
393 in Qualcomm Technologies chips.
395 config IRQ_UNIPHIER_AIDET
396 bool "UniPhier AIDET support" if COMPILE_TEST
397 depends on ARCH_UNIPHIER || COMPILE_TEST
398 default ARCH_UNIPHIER
399 select IRQ_DOMAIN_HIERARCHY
401 Support for the UniPhier AIDET (ARM Interrupt Detector).
403 config MESON_IRQ_GPIO
404 bool "Meson GPIO Interrupt Multiplexer"
405 depends on ARCH_MESON
406 select IRQ_DOMAIN_HIERARCHY
408 Support Meson SoC Family GPIO Interrupt Multiplexer
411 bool "Goldfish programmable interrupt controller"
412 depends on MIPS && (GOLDFISH || COMPILE_TEST)
413 select GENERIC_IRQ_CHIP
416 Say yes here to enable Goldfish interrupt controller driver used
417 for Goldfish based virtual platforms.
422 select IRQ_DOMAIN_HIERARCHY
424 Power Domain Controller driver to manage and configure wakeup
425 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
431 Say yes here to enable C-SKY SMP interrupt controller driver used
432 for C-SKY SMP system.
433 In fact it's not mmio map in hardware and it uses ld/st to visit the
434 controller's register inside CPU.
437 bool "C-SKY APB Interrupt Controller"
440 Say yes here to enable C-SKY APB interrupt controller driver used
441 by C-SKY single core SOC system. It uses mmio map apb-bus to visit
442 the controller's register.
445 bool "i.MX IRQSTEER support"
446 depends on ARCH_MXC || COMPILE_TEST
450 Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
453 bool "i.MX INTMUX support" if COMPILE_TEST
454 default y if ARCH_MXC
457 Support for the i.MX INTMUX interrupt multiplexer.
460 bool "Loongson-1 Interrupt Controller"
461 depends on MACH_LOONGSON32
464 select GENERIC_IRQ_CHIP
466 Support for the Loongson-1 platform Interrupt Controller.
468 config TI_SCI_INTR_IRQCHIP
470 depends on TI_SCI_PROTOCOL
471 select IRQ_DOMAIN_HIERARCHY
473 This enables the irqchip driver support for K3 Interrupt router
474 over TI System Control Interface available on some new TI's SoCs.
475 If you wish to use interrupt router irq resources managed by the
476 TI System Controller, say Y here. Otherwise, say N.
478 config TI_SCI_INTA_IRQCHIP
480 depends on TI_SCI_PROTOCOL
481 select IRQ_DOMAIN_HIERARCHY
482 select TI_SCI_INTA_MSI_DOMAIN
484 This enables the irqchip driver support for K3 Interrupt aggregator
485 over TI System Control Interface available on some new TI's SoCs.
486 If you wish to use interrupt aggregator irq resources managed by the
487 TI System Controller, say Y here. Otherwise, say N.
495 This enables support for the PRU-ICSS Local Interrupt Controller
496 present within a PRU-ICSS subsystem present on various TI SoCs.
497 The PRUSS INTC enables various interrupts to be routed to multiple
498 different processors within the SoC.
501 bool "RISC-V Local Interrupt Controller"
505 This enables support for the per-HART local interrupt controller
506 found in standard RISC-V systems. The per-HART local interrupt
507 controller handles timer interrupts, software interrupts, and
508 hardware interrupts. Without a per-HART local interrupt controller,
509 a RISC-V system will be unable to handle any interrupts.
511 If you don't know what to do here, say Y.
514 bool "SiFive Platform-Level Interrupt Controller"
516 select IRQ_DOMAIN_HIERARCHY
518 This enables support for the PLIC chip found in SiFive (and
519 potentially other) RISC-V systems. The PLIC controls devices
520 interrupts and connects them to each core's local interrupt
521 controller. Aside from timer and software interrupts, all other
522 interrupt sources are subordinate to the PLIC.
524 If you don't know what to do here, say Y.
526 config EXYNOS_IRQ_COMBINER
527 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
528 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
530 Say yes here to add support for the IRQ combiner devices embedded
531 in Samsung Exynos chips.
533 config LOONGSON_LIOINTC
534 bool "Loongson Local I/O Interrupt Controller"
535 depends on MACH_LOONGSON64
538 select GENERIC_IRQ_CHIP
540 Support for the Loongson Local I/O Interrupt Controller.
542 config LOONGSON_HTPIC
543 bool "Loongson3 HyperTransport PIC Controller"
544 depends on MACH_LOONGSON64
547 select GENERIC_IRQ_CHIP
549 Support for the Loongson-3 HyperTransport PIC Controller.
551 config LOONGSON_HTVEC
552 bool "Loongson3 HyperTransport Interrupt Vector Controller"
553 depends on MACH_LOONGSON64
554 default MACH_LOONGSON64
555 select IRQ_DOMAIN_HIERARCHY
557 Support for the Loongson3 HyperTransport Interrupt Vector Controller.
559 config LOONGSON_PCH_PIC
560 bool "Loongson PCH PIC Controller"
561 depends on MACH_LOONGSON64 || COMPILE_TEST
562 default MACH_LOONGSON64
563 select IRQ_DOMAIN_HIERARCHY
564 select IRQ_FASTEOI_HIERARCHY_HANDLERS
566 Support for the Loongson PCH PIC Controller.
568 config LOONGSON_PCH_MSI
569 bool "Loongson PCH MSI Controller"
570 depends on MACH_LOONGSON64 || COMPILE_TEST
572 default MACH_LOONGSON64
573 select IRQ_DOMAIN_HIERARCHY
576 Support for the Loongson PCH MSI Controller.
579 bool "MStar Interrupt Controller"
580 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
581 default ARCH_MEDIATEK
583 select IRQ_DOMAIN_HIERARCHY
585 Support MStar Interrupt Controller.
588 bool "Nuvoton WPCM450 Advanced Interrupt Controller"
589 depends on ARCH_WPCM450
591 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC.
595 select GENERIC_IRQ_CHIP
599 bool "Apple Interrupt Controller (AIC)"
601 depends on ARCH_APPLE || COMPILE_TEST
603 Support for the Apple Interrupt Controller found on Apple Silicon SoCs,