1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "IRQ chip support"
10 select IRQ_DOMAIN_HIERARCHY
11 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
21 default 2 if ARCH_REALVIEW
35 select IRQ_DOMAIN_HIERARCHY
36 select PARTITION_PERCPU
37 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
41 select GENERIC_MSI_IRQ_DOMAIN
44 config ARM_GIC_V3_ITS_PCI
46 depends on ARM_GIC_V3_ITS
49 default ARM_GIC_V3_ITS
51 config ARM_GIC_V3_ITS_FSL_MC
53 depends on ARM_GIC_V3_ITS
55 default ARM_GIC_V3_ITS
59 select IRQ_DOMAIN_HIERARCHY
60 select GENERIC_IRQ_CHIP
68 default 4 if ARCH_S5PV210
72 The maximum number of VICs available in the system, for
75 config ARMADA_370_XP_IRQ
77 select GENERIC_IRQ_CHIP
79 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
85 select GENERIC_IRQ_CHIP
88 bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
89 depends on OF || COMPILE_TEST
90 select GENERIC_IRQ_CHIP
93 Support Amazon's Annapurna Labs Fabric Interrupt Controller.
97 select GENERIC_IRQ_CHIP
101 config ATMEL_AIC5_IRQ
103 select GENERIC_IRQ_CHIP
111 config BCM6345_L1_IRQ
113 select GENERIC_IRQ_CHIP
115 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
117 config BCM7038_L1_IRQ
119 select GENERIC_IRQ_CHIP
121 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
123 config BCM7120_L2_IRQ
125 select GENERIC_IRQ_CHIP
128 config BRCMSTB_L2_IRQ
130 select GENERIC_IRQ_CHIP
135 select GENERIC_IRQ_CHIP
138 config DAVINCI_CP_INTC
140 select GENERIC_IRQ_CHIP
145 select GENERIC_IRQ_CHIP
146 select IRQ_DOMAIN_HIERARCHY
148 config FARADAY_FTINTC010
153 config HISILICON_IRQ_MBIGEN
156 select ARM_GIC_V3_ITS
160 select GENERIC_IRQ_CHIP
173 select GENERIC_IRQ_CHIP
174 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
176 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
178 config CLPS711X_IRQCHIP
180 depends on ARCH_CLPS711X
194 select GENERIC_IRQ_CHIP
203 select GENERIC_IRQ_CHIP
207 bool "J-Core integrated AIC" if COMPILE_TEST
211 Support for the J-Core integrated AIC.
217 config RENESAS_INTC_IRQPIN
218 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
221 Enable support for the Renesas Interrupt Controller for external
222 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
225 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
226 select GENERIC_IRQ_CHIP
229 Enable support for the Renesas Interrupt Controller for external
230 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
232 config RENESAS_RZA1_IRQC
233 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
234 select IRQ_DOMAIN_HIERARCHY
236 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
237 to 8 external interrupts with configurable sense select.
240 bool "Kontron sl28cpld IRQ controller"
241 depends on MFD_SL28CPLD=y || COMPILE_TEST
244 Interrupt controller driver for the board management controller
245 found on the Kontron sl28 CPLD.
252 Enables SysCfg Controlled IRQs on STi based platforms.
257 select GENERIC_IRQ_CHIP
260 tristate "TS-4800 IRQ controller"
263 depends on SOC_IMX51 || COMPILE_TEST
265 Support for the TS-4800 FPGA IRQ controller
267 config VERSATILE_FPGA_IRQ
271 config VERSATILE_FPGA_IRQ_NR
274 depends on VERSATILE_FPGA_IRQ
279 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
282 bool "Xilinx Interrupt Controller IP"
283 depends on MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP
286 Support for the Xilinx Interrupt Controller IP core.
287 This is used as a primary controller with MicroBlaze and can also
288 be used as a secondary chained controller on other platforms.
293 Support for a CROSSBAR ip that precedes the main interrupt controller.
294 The primary irqchip invokes the crossbar's callback which inturn allocates
295 a free irq and configures the IP. Thus the peripheral interrupts are
296 routed to one of the free irqchip interrupt lines.
299 tristate "Keystone 2 IRQ controller IP"
300 depends on ARCH_KEYSTONE
302 Support for Texas Instruments Keystone 2 IRQ controller IP which
303 is part of the Keystone 2 IPC mechanism
307 select GENERIC_IRQ_IPI
312 depends on MACH_INGENIC
315 config INGENIC_TCU_IRQ
316 bool "Ingenic JZ47xx TCU interrupt controller"
318 depends on MIPS || COMPILE_TEST
320 select GENERIC_IRQ_CHIP
322 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
327 config RENESAS_H8300H_INTC
331 config RENESAS_H8S_INTC
332 bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST
335 Enable support for the Renesas H8/300 Interrupt Controller, as found
342 Enables the wakeup IRQs for IMX platforms with GPCv2 block
345 def_bool y if MACH_ASM9260 || ARCH_MXS
349 config MSCC_OCELOT_IRQ
352 select GENERIC_IRQ_CHIP
362 select GENERIC_MSI_IRQ_DOMAIN
371 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
375 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
376 depends on PCI && PCI_MSI
378 config PARTITION_PERCPU
384 select GENERIC_IRQ_CHIP
386 config QCOM_IRQ_COMBINER
387 bool "QCOM IRQ combiner support"
388 depends on ARCH_QCOM && ACPI
389 select IRQ_DOMAIN_HIERARCHY
391 Say yes here to add support for the IRQ combiner devices embedded
392 in Qualcomm Technologies chips.
394 config IRQ_UNIPHIER_AIDET
395 bool "UniPhier AIDET support" if COMPILE_TEST
396 depends on ARCH_UNIPHIER || COMPILE_TEST
397 default ARCH_UNIPHIER
398 select IRQ_DOMAIN_HIERARCHY
400 Support for the UniPhier AIDET (ARM Interrupt Detector).
402 config MESON_IRQ_GPIO
403 bool "Meson GPIO Interrupt Multiplexer"
404 depends on ARCH_MESON
405 select IRQ_DOMAIN_HIERARCHY
407 Support Meson SoC Family GPIO Interrupt Multiplexer
410 bool "Goldfish programmable interrupt controller"
411 depends on MIPS && (GOLDFISH || COMPILE_TEST)
412 select GENERIC_IRQ_CHIP
415 Say yes here to enable Goldfish interrupt controller driver used
416 for Goldfish based virtual platforms.
421 select IRQ_DOMAIN_HIERARCHY
423 Power Domain Controller driver to manage and configure wakeup
424 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
430 Say yes here to enable C-SKY SMP interrupt controller driver used
431 for C-SKY SMP system.
432 In fact it's not mmio map in hardware and it uses ld/st to visit the
433 controller's register inside CPU.
436 bool "C-SKY APB Interrupt Controller"
439 Say yes here to enable C-SKY APB interrupt controller driver used
440 by C-SKY single core SOC system. It uses mmio map apb-bus to visit
441 the controller's register.
444 bool "i.MX IRQSTEER support"
445 depends on ARCH_MXC || COMPILE_TEST
449 Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
452 bool "i.MX INTMUX support" if COMPILE_TEST
453 default y if ARCH_MXC
456 Support for the i.MX INTMUX interrupt multiplexer.
459 bool "Loongson-1 Interrupt Controller"
460 depends on MACH_LOONGSON32
463 select GENERIC_IRQ_CHIP
465 Support for the Loongson-1 platform Interrupt Controller.
467 config TI_SCI_INTR_IRQCHIP
469 depends on TI_SCI_PROTOCOL
470 select IRQ_DOMAIN_HIERARCHY
472 This enables the irqchip driver support for K3 Interrupt router
473 over TI System Control Interface available on some new TI's SoCs.
474 If you wish to use interrupt router irq resources managed by the
475 TI System Controller, say Y here. Otherwise, say N.
477 config TI_SCI_INTA_IRQCHIP
479 depends on TI_SCI_PROTOCOL
480 select IRQ_DOMAIN_HIERARCHY
481 select TI_SCI_INTA_MSI_DOMAIN
483 This enables the irqchip driver support for K3 Interrupt aggregator
484 over TI System Control Interface available on some new TI's SoCs.
485 If you wish to use interrupt aggregator irq resources managed by the
486 TI System Controller, say Y here. Otherwise, say N.
494 This enables support for the PRU-ICSS Local Interrupt Controller
495 present within a PRU-ICSS subsystem present on various TI SoCs.
496 The PRUSS INTC enables various interrupts to be routed to multiple
497 different processors within the SoC.
500 bool "RISC-V Local Interrupt Controller"
504 This enables support for the per-HART local interrupt controller
505 found in standard RISC-V systems. The per-HART local interrupt
506 controller handles timer interrupts, software interrupts, and
507 hardware interrupts. Without a per-HART local interrupt controller,
508 a RISC-V system will be unable to handle any interrupts.
510 If you don't know what to do here, say Y.
513 bool "SiFive Platform-Level Interrupt Controller"
515 select IRQ_DOMAIN_HIERARCHY
517 This enables support for the PLIC chip found in SiFive (and
518 potentially other) RISC-V systems. The PLIC controls devices
519 interrupts and connects them to each core's local interrupt
520 controller. Aside from timer and software interrupts, all other
521 interrupt sources are subordinate to the PLIC.
523 If you don't know what to do here, say Y.
525 config EXYNOS_IRQ_COMBINER
526 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
527 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
529 Say yes here to add support for the IRQ combiner devices embedded
530 in Samsung Exynos chips.
532 config LOONGSON_LIOINTC
533 bool "Loongson Local I/O Interrupt Controller"
534 depends on MACH_LOONGSON64
537 select GENERIC_IRQ_CHIP
539 Support for the Loongson Local I/O Interrupt Controller.
541 config LOONGSON_HTPIC
542 bool "Loongson3 HyperTransport PIC Controller"
543 depends on MACH_LOONGSON64
546 select GENERIC_IRQ_CHIP
548 Support for the Loongson-3 HyperTransport PIC Controller.
550 config LOONGSON_HTVEC
551 bool "Loongson3 HyperTransport Interrupt Vector Controller"
552 depends on MACH_LOONGSON64
553 default MACH_LOONGSON64
554 select IRQ_DOMAIN_HIERARCHY
556 Support for the Loongson3 HyperTransport Interrupt Vector Controller.
558 config LOONGSON_PCH_PIC
559 bool "Loongson PCH PIC Controller"
560 depends on MACH_LOONGSON64 || COMPILE_TEST
561 default MACH_LOONGSON64
562 select IRQ_DOMAIN_HIERARCHY
563 select IRQ_FASTEOI_HIERARCHY_HANDLERS
565 Support for the Loongson PCH PIC Controller.
567 config LOONGSON_PCH_MSI
568 bool "Loongson PCH MSI Controller"
569 depends on MACH_LOONGSON64 || COMPILE_TEST
571 default MACH_LOONGSON64
572 select IRQ_DOMAIN_HIERARCHY
575 Support for the Loongson PCH MSI Controller.
578 bool "MStar Interrupt Controller"
579 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
580 default ARCH_MEDIATEK
582 select IRQ_DOMAIN_HIERARCHY
584 Support MStar Interrupt Controller.
587 bool "Nuvoton WPCM450 Advanced Interrupt Controller"
588 depends on ARCH_WPCM450
590 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC.
594 select GENERIC_IRQ_CHIP
598 bool "Apple Interrupt Controller (AIC)"
600 depends on ARCH_APPLE || COMPILE_TEST
602 Support for the Apple Interrupt Controller found on Apple Silicon SoCs,