1 menu "IRQ chip support"
9 select IRQ_DOMAIN_HIERARCHY
10 select GENERIC_IRQ_MULTI_HANDLER
11 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
21 default 2 if ARCH_REALVIEW
35 select GENERIC_IRQ_MULTI_HANDLER
36 select IRQ_DOMAIN_HIERARCHY
37 select PARTITION_PERCPU
38 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
42 select GENERIC_MSI_IRQ_DOMAIN
45 config ARM_GIC_V3_ITS_PCI
47 depends on ARM_GIC_V3_ITS
50 default ARM_GIC_V3_ITS
52 config ARM_GIC_V3_ITS_FSL_MC
54 depends on ARM_GIC_V3_ITS
56 default ARM_GIC_V3_ITS
60 select IRQ_DOMAIN_HIERARCHY
61 select GENERIC_IRQ_CHIP
66 select GENERIC_IRQ_MULTI_HANDLER
70 default 4 if ARCH_S5PV210
74 The maximum number of VICs available in the system, for
77 config ARMADA_370_XP_IRQ
79 select GENERIC_IRQ_CHIP
81 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
87 select GENERIC_IRQ_CHIP
91 select GENERIC_IRQ_CHIP
93 select GENERIC_IRQ_MULTI_HANDLER
98 select GENERIC_IRQ_CHIP
100 select GENERIC_IRQ_MULTI_HANDLER
107 config BCM6345_L1_IRQ
109 select GENERIC_IRQ_CHIP
111 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
113 config BCM7038_L1_IRQ
115 select GENERIC_IRQ_CHIP
117 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
119 config BCM7120_L2_IRQ
121 select GENERIC_IRQ_CHIP
124 config BRCMSTB_L2_IRQ
126 select GENERIC_IRQ_CHIP
131 select GENERIC_IRQ_CHIP
134 config DAVINCI_CP_INTC
136 select GENERIC_IRQ_CHIP
141 select GENERIC_IRQ_CHIP
144 config FARADAY_FTINTC010
147 select GENERIC_IRQ_MULTI_HANDLER
150 config HISILICON_IRQ_MBIGEN
153 select ARM_GIC_V3_ITS
157 select GENERIC_IRQ_CHIP
163 select GENERIC_IRQ_MULTI_HANDLER
171 select GENERIC_IRQ_CHIP
172 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
174 select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
175 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
177 config CLPS711X_IRQCHIP
179 depends on ARCH_CLPS711X
181 select GENERIC_IRQ_MULTI_HANDLER
194 select GENERIC_IRQ_CHIP
200 select GENERIC_IRQ_MULTI_HANDLER
204 select GENERIC_IRQ_CHIP
208 bool "J-Core integrated AIC" if COMPILE_TEST
212 Support for the J-Core integrated AIC.
218 config RENESAS_INTC_IRQPIN
224 select GENERIC_IRQ_CHIP
232 Enables SysCfg Controlled IRQs on STi based platforms.
237 select GENERIC_IRQ_CHIP
242 select GENERIC_IRQ_CHIP
245 tristate "TS-4800 IRQ controller"
248 depends on SOC_IMX51 || COMPILE_TEST
250 Support for the TS-4800 FPGA IRQ controller
252 config VERSATILE_FPGA_IRQ
256 config VERSATILE_FPGA_IRQ_NR
259 depends on VERSATILE_FPGA_IRQ
264 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
273 Support for a CROSSBAR ip that precedes the main interrupt controller.
274 The primary irqchip invokes the crossbar's callback which inturn allocates
275 a free irq and configures the IP. Thus the peripheral interrupts are
276 routed to one of the free irqchip interrupt lines.
279 tristate "Keystone 2 IRQ controller IP"
280 depends on ARCH_KEYSTONE
282 Support for Texas Instruments Keystone 2 IRQ controller IP which
283 is part of the Keystone 2 IPC mechanism
287 select GENERIC_IRQ_IPI
288 select IRQ_DOMAIN_HIERARCHY
293 depends on MACH_INGENIC
296 config RENESAS_H8300H_INTC
300 config RENESAS_H8S_INTC
308 Enables the wakeup IRQs for IMX platforms with GPCv2 block
311 def_bool y if MACH_ASM9260 || ARCH_MXS
315 config MSCC_OCELOT_IRQ
318 select GENERIC_IRQ_CHIP
328 select GENERIC_MSI_IRQ_DOMAIN
337 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
338 depends on PCI && PCI_MSI
340 config PARTITION_PERCPU
344 bool "NPS400 Global Interrupt Manager (GIM)"
345 depends on ARC || (COMPILE_TEST && !64BIT)
348 Support the EZchip NPS400 global interrupt controller
353 select GENERIC_IRQ_CHIP
355 config QCOM_IRQ_COMBINER
356 bool "QCOM IRQ combiner support"
357 depends on ARCH_QCOM && ACPI
358 select IRQ_DOMAIN_HIERARCHY
360 Say yes here to add support for the IRQ combiner devices embedded
361 in Qualcomm Technologies chips.
363 config IRQ_UNIPHIER_AIDET
364 bool "UniPhier AIDET support" if COMPILE_TEST
365 depends on ARCH_UNIPHIER || COMPILE_TEST
366 default ARCH_UNIPHIER
367 select IRQ_DOMAIN_HIERARCHY
369 Support for the UniPhier AIDET (ARM Interrupt Detector).
371 config MESON_IRQ_GPIO
372 bool "Meson GPIO Interrupt Multiplexer"
373 depends on ARCH_MESON
374 select IRQ_DOMAIN_HIERARCHY
376 Support Meson SoC Family GPIO Interrupt Multiplexer
379 bool "Goldfish programmable interrupt controller"
380 depends on MIPS && (GOLDFISH || COMPILE_TEST)
383 Say yes here to enable Goldfish interrupt controller driver used
384 for Goldfish based virtual platforms.
389 select IRQ_DOMAIN_HIERARCHY
391 Power Domain Controller driver to manage and configure wakeup
392 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
395 bool "C-SKY Multi Processor Interrupt Controller"
398 Say yes here to enable C-SKY SMP interrupt controller driver used
399 for C-SKY SMP system.
400 In fact it's not mmio map in hw and it use ld/st to visit the
401 controller's register inside CPU.
404 bool "C-SKY APB Interrupt Controller"
407 Say yes here to enable C-SKY APB interrupt controller driver used
408 by C-SKY single core SOC system. It use mmio map apb-bus to visit
409 the controller's register.
412 bool "i.MX IRQSTEER support"
413 depends on ARCH_MXC || COMPILE_TEST
417 Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
420 bool "Loongson-1 Interrupt Controller"
421 depends on MACH_LOONGSON32
424 select GENERIC_IRQ_CHIP
426 Support for the Loongson-1 platform Interrupt Controller.
428 config TI_SCI_INTR_IRQCHIP
430 depends on TI_SCI_PROTOCOL
431 select IRQ_DOMAIN_HIERARCHY
433 This enables the irqchip driver support for K3 Interrupt router
434 over TI System Control Interface available on some new TI's SoCs.
435 If you wish to use interrupt router irq resources managed by the
436 TI System Controller, say Y here. Otherwise, say N.
438 config TI_SCI_INTA_IRQCHIP
440 depends on TI_SCI_PROTOCOL
441 select IRQ_DOMAIN_HIERARCHY
442 select TI_SCI_INTA_MSI_DOMAIN
444 This enables the irqchip driver support for K3 Interrupt aggregator
445 over TI System Control Interface available on some new TI's SoCs.
446 If you wish to use interrupt aggregator irq resources managed by the
447 TI System Controller, say Y here. Otherwise, say N.
452 bool "SiFive Platform-Level Interrupt Controller"
455 This enables support for the PLIC chip found in SiFive (and
456 potentially other) RISC-V systems. The PLIC controls devices
457 interrupts and connects them to each core's local interrupt
458 controller. Aside from timer and software interrupts, all other
459 interrupt sources are subordinate to the PLIC.
461 If you don't know what to do here, say Y.