1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "IRQ chip support"
6 depends on (OF_IRQ || ACPI_GENERIC_GSI)
11 select IRQ_DOMAIN_HIERARCHY
12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
22 default 2 if ARCH_REALVIEW
36 select IRQ_DOMAIN_HIERARCHY
37 select PARTITION_PERCPU
38 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
39 select HAVE_ARM_SMCCC_DISCOVERY
43 select GENERIC_MSI_IRQ
46 config ARM_GIC_V3_ITS_PCI
48 depends on ARM_GIC_V3_ITS
51 default ARM_GIC_V3_ITS
53 config ARM_GIC_V3_ITS_FSL_MC
55 depends on ARM_GIC_V3_ITS
57 default ARM_GIC_V3_ITS
61 select IRQ_DOMAIN_HIERARCHY
62 select GENERIC_IRQ_CHIP
70 default 4 if ARCH_S5PV210
74 The maximum number of VICs available in the system, for
77 config ARMADA_370_XP_IRQ
79 select GENERIC_IRQ_CHIP
81 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
87 select GENERIC_IRQ_CHIP
90 bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
92 select GENERIC_IRQ_CHIP
95 Support Amazon's Annapurna Labs Fabric Interrupt Controller.
99 select GENERIC_IRQ_CHIP
103 config ATMEL_AIC5_IRQ
105 select GENERIC_IRQ_CHIP
113 config BCM6345_L1_IRQ
115 select GENERIC_IRQ_CHIP
117 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
119 config BCM7038_L1_IRQ
120 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
121 depends on ARCH_BRCMSTB || BMIPS_GENERIC
122 default ARCH_BRCMSTB || BMIPS_GENERIC
123 select GENERIC_IRQ_CHIP
125 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
127 config BCM7120_L2_IRQ
128 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
129 depends on ARCH_BRCMSTB || BMIPS_GENERIC
130 default ARCH_BRCMSTB || BMIPS_GENERIC
131 select GENERIC_IRQ_CHIP
134 config BRCMSTB_L2_IRQ
135 tristate "Broadcom STB generic L2 interrupt controller driver"
136 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
137 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
138 select GENERIC_IRQ_CHIP
141 config DAVINCI_CP_INTC
143 select GENERIC_IRQ_CHIP
148 select GENERIC_IRQ_CHIP
149 select IRQ_DOMAIN_HIERARCHY
151 config FARADAY_FTINTC010
156 config HISILICON_IRQ_MBIGEN
159 select ARM_GIC_V3_ITS
163 select GENERIC_IRQ_CHIP
176 select GENERIC_IRQ_CHIP
177 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING
179 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
181 config CLPS711X_IRQCHIP
183 depends on ARCH_CLPS711X
197 select GENERIC_IRQ_CHIP
206 select GENERIC_IRQ_CHIP
210 bool "J-Core integrated AIC" if COMPILE_TEST
214 Support for the J-Core integrated AIC.
220 config RENESAS_INTC_IRQPIN
221 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
224 Enable support for the Renesas Interrupt Controller for external
225 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
228 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
229 select GENERIC_IRQ_CHIP
232 Enable support for the Renesas Interrupt Controller for external
233 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
235 config RENESAS_RZA1_IRQC
236 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
237 select IRQ_DOMAIN_HIERARCHY
239 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
240 to 8 external interrupts with configurable sense select.
242 config RENESAS_RZG2L_IRQC
243 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST
244 select GENERIC_IRQ_CHIP
245 select IRQ_DOMAIN_HIERARCHY
247 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller
248 for external devices.
251 bool "Kontron sl28cpld IRQ controller"
252 depends on MFD_SL28CPLD=y || COMPILE_TEST
255 Interrupt controller driver for the board management controller
256 found on the Kontron sl28 CPLD.
263 Enables SysCfg Controlled IRQs on STi based platforms.
270 select IRQ_DOMAIN_HIERARCHY
271 select IRQ_FASTEOI_HIERARCHY_HANDLERS
273 config SUNXI_NMI_INTC
275 select GENERIC_IRQ_CHIP
280 select GENERIC_IRQ_CHIP
283 tristate "TS-4800 IRQ controller"
286 depends on SOC_IMX51 || COMPILE_TEST
288 Support for the TS-4800 FPGA IRQ controller
290 config VERSATILE_FPGA_IRQ
294 config VERSATILE_FPGA_IRQ_NR
297 depends on VERSATILE_FPGA_IRQ
302 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
305 bool "Xilinx Interrupt Controller IP"
306 depends on OF_ADDRESS
309 Support for the Xilinx Interrupt Controller IP core.
310 This is used as a primary controller with MicroBlaze and can also
311 be used as a secondary chained controller on other platforms.
316 Support for a CROSSBAR ip that precedes the main interrupt controller.
317 The primary irqchip invokes the crossbar's callback which inturn allocates
318 a free irq and configures the IP. Thus the peripheral interrupts are
319 routed to one of the free irqchip interrupt lines.
322 tristate "Keystone 2 IRQ controller IP"
323 depends on ARCH_KEYSTONE
325 Support for Texas Instruments Keystone 2 IRQ controller IP which
326 is part of the Keystone 2 IPC mechanism
330 select GENERIC_IRQ_IPI if SMP
331 select IRQ_DOMAIN_HIERARCHY
336 depends on MACH_INGENIC
339 config INGENIC_TCU_IRQ
340 bool "Ingenic JZ47xx TCU interrupt controller"
342 depends on MIPS || COMPILE_TEST
344 select GENERIC_IRQ_CHIP
346 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
355 Enables the wakeup IRQs for IMX platforms with GPCv2 block
358 def_bool y if MACH_ASM9260 || ARCH_MXS
362 config MSCC_OCELOT_IRQ
365 select GENERIC_IRQ_CHIP
375 select GENERIC_MSI_IRQ
384 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
388 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
391 config PARTITION_PERCPU
397 select GENERIC_IRQ_CHIP
399 config QCOM_IRQ_COMBINER
400 bool "QCOM IRQ combiner support"
401 depends on ARCH_QCOM && ACPI
402 select IRQ_DOMAIN_HIERARCHY
404 Say yes here to add support for the IRQ combiner devices embedded
405 in Qualcomm Technologies chips.
407 config IRQ_UNIPHIER_AIDET
408 bool "UniPhier AIDET support" if COMPILE_TEST
409 depends on ARCH_UNIPHIER || COMPILE_TEST
410 default ARCH_UNIPHIER
411 select IRQ_DOMAIN_HIERARCHY
413 Support for the UniPhier AIDET (ARM Interrupt Detector).
415 config MESON_IRQ_GPIO
416 tristate "Meson GPIO Interrupt Multiplexer"
417 depends on ARCH_MESON || COMPILE_TEST
419 select IRQ_DOMAIN_HIERARCHY
421 Support Meson SoC Family GPIO Interrupt Multiplexer
424 bool "Goldfish programmable interrupt controller"
425 depends on MIPS && (GOLDFISH || COMPILE_TEST)
426 select GENERIC_IRQ_CHIP
429 Say yes here to enable Goldfish interrupt controller driver used
430 for Goldfish based virtual platforms.
435 select IRQ_DOMAIN_HIERARCHY
437 Power Domain Controller driver to manage and configure wakeup
438 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
444 select IRQ_DOMAIN_HIERARCHY
446 MSM Power Manager driver to manage and configure wakeup
447 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
453 Say yes here to enable C-SKY SMP interrupt controller driver used
454 for C-SKY SMP system.
455 In fact it's not mmio map in hardware and it uses ld/st to visit the
456 controller's register inside CPU.
459 bool "C-SKY APB Interrupt Controller"
462 Say yes here to enable C-SKY APB interrupt controller driver used
463 by C-SKY single core SOC system. It uses mmio map apb-bus to visit
464 the controller's register.
467 bool "i.MX IRQSTEER support"
468 depends on ARCH_MXC || COMPILE_TEST
472 Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
475 bool "i.MX INTMUX support" if COMPILE_TEST
476 default y if ARCH_MXC
479 Support for the i.MX INTMUX interrupt multiplexer.
482 tristate "i.MX MU used as MSI controller"
483 depends on OF && HAS_IOMEM
484 depends on ARCH_MXC || COMPILE_TEST
485 default m if ARCH_MXC
487 select IRQ_DOMAIN_HIERARCHY
488 select GENERIC_MSI_IRQ
490 Provide a driver for the i.MX Messaging Unit block used as a
491 CPU-to-CPU MSI controller. This requires a specially crafted DT
492 to make use of this driver.
497 bool "Loongson-1 Interrupt Controller"
498 depends on MACH_LOONGSON32
501 select GENERIC_IRQ_CHIP
503 Support for the Loongson-1 platform Interrupt Controller.
505 config TI_SCI_INTR_IRQCHIP
507 depends on TI_SCI_PROTOCOL
508 select IRQ_DOMAIN_HIERARCHY
510 This enables the irqchip driver support for K3 Interrupt router
511 over TI System Control Interface available on some new TI's SoCs.
512 If you wish to use interrupt router irq resources managed by the
513 TI System Controller, say Y here. Otherwise, say N.
515 config TI_SCI_INTA_IRQCHIP
517 depends on TI_SCI_PROTOCOL
518 select IRQ_DOMAIN_HIERARCHY
519 select TI_SCI_INTA_MSI_DOMAIN
521 This enables the irqchip driver support for K3 Interrupt aggregator
522 over TI System Control Interface available on some new TI's SoCs.
523 If you wish to use interrupt aggregator irq resources managed by the
524 TI System Controller, say Y here. Otherwise, say N.
532 This enables support for the PRU-ICSS Local Interrupt Controller
533 present within a PRU-ICSS subsystem present on various TI SoCs.
534 The PRUSS INTC enables various interrupts to be routed to multiple
535 different processors within the SoC.
540 select IRQ_DOMAIN_HIERARCHY
545 select IRQ_DOMAIN_HIERARCHY
546 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
548 config EXYNOS_IRQ_COMBINER
549 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
550 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
552 Say yes here to add support for the IRQ combiner devices embedded
553 in Samsung Exynos chips.
555 config IRQ_LOONGARCH_CPU
557 select GENERIC_IRQ_CHIP
559 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
560 select LOONGSON_HTVEC
561 select LOONGSON_LIOINTC
562 select LOONGSON_EIOINTC
563 select LOONGSON_PCH_PIC
564 select LOONGSON_PCH_MSI
565 select LOONGSON_PCH_LPC
567 Support for the LoongArch CPU Interrupt Controller. For details of
568 irq chip hierarchy on LoongArch platforms please read the document
569 Documentation/loongarch/irq-chip-model.rst.
571 config LOONGSON_LIOINTC
572 bool "Loongson Local I/O Interrupt Controller"
573 depends on MACH_LOONGSON64
576 select GENERIC_IRQ_CHIP
578 Support for the Loongson Local I/O Interrupt Controller.
580 config LOONGSON_EIOINTC
581 bool "Loongson Extend I/O Interrupt Controller"
583 depends on MACH_LOONGSON64
584 default MACH_LOONGSON64
585 select IRQ_DOMAIN_HIERARCHY
586 select GENERIC_IRQ_CHIP
588 Support for the Loongson3 Extend I/O Interrupt Vector Controller.
590 config LOONGSON_HTPIC
591 bool "Loongson3 HyperTransport PIC Controller"
592 depends on MACH_LOONGSON64 && MIPS
595 select GENERIC_IRQ_CHIP
597 Support for the Loongson-3 HyperTransport PIC Controller.
599 config LOONGSON_HTVEC
600 bool "Loongson HyperTransport Interrupt Vector Controller"
601 depends on MACH_LOONGSON64
602 default MACH_LOONGSON64
603 select IRQ_DOMAIN_HIERARCHY
605 Support for the Loongson HyperTransport Interrupt Vector Controller.
607 config LOONGSON_PCH_PIC
608 bool "Loongson PCH PIC Controller"
609 depends on MACH_LOONGSON64
610 default MACH_LOONGSON64
611 select IRQ_DOMAIN_HIERARCHY
612 select IRQ_FASTEOI_HIERARCHY_HANDLERS
614 Support for the Loongson PCH PIC Controller.
616 config LOONGSON_PCH_MSI
617 bool "Loongson PCH MSI Controller"
618 depends on MACH_LOONGSON64
620 default MACH_LOONGSON64
621 select IRQ_DOMAIN_HIERARCHY
624 Support for the Loongson PCH MSI Controller.
626 config LOONGSON_PCH_LPC
627 bool "Loongson PCH LPC Controller"
629 depends on MACH_LOONGSON64
630 default MACH_LOONGSON64
631 select IRQ_DOMAIN_HIERARCHY
633 Support for the Loongson PCH LPC Controller.
636 bool "MStar Interrupt Controller"
637 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
638 default ARCH_MEDIATEK
640 select IRQ_DOMAIN_HIERARCHY
642 Support MStar Interrupt Controller.
645 bool "Nuvoton WPCM450 Advanced Interrupt Controller"
646 depends on ARCH_WPCM450
648 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC.
652 select GENERIC_IRQ_CHIP
656 bool "Apple Interrupt Controller (AIC)"
658 depends on ARCH_APPLE || COMPILE_TEST
659 select GENERIC_IRQ_IPI_MUX
661 Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
665 bool "Microchip External Interrupt Controller"
666 depends on ARCH_AT91 || COMPILE_TEST
668 select IRQ_DOMAIN_HIERARCHY
670 Support for Microchip External Interrupt Controller.
672 config SUNPLUS_SP7021_INTC
673 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST
676 Support for the Sunplus SP7021 Interrupt Controller IP core.
677 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a
678 chained controller, routing all interrupt source in P-Chip to
679 the primary controller on C-Chip.