1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for Rockchip
5 * Module Authors: Simon Xue <xxm@rock-chips.com>
6 * Daniel Kurtz <djkurtz@chromium.org>
10 #include <linux/compiler.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/dma-iommu.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/errno.h>
16 #include <linux/interrupt.h>
18 #include <linux/iommu.h>
19 #include <linux/iopoll.h>
20 #include <linux/list.h>
22 #include <linux/init.h>
24 #include <linux/of_iommu.h>
25 #include <linux/of_platform.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/slab.h>
29 #include <linux/spinlock.h>
31 /** MMU register offsets */
32 #define RK_MMU_DTE_ADDR 0x00 /* Directory table address */
33 #define RK_MMU_STATUS 0x04
34 #define RK_MMU_COMMAND 0x08
35 #define RK_MMU_PAGE_FAULT_ADDR 0x0C /* IOVA of last page fault */
36 #define RK_MMU_ZAP_ONE_LINE 0x10 /* Shootdown one IOTLB entry */
37 #define RK_MMU_INT_RAWSTAT 0x14 /* IRQ status ignoring mask */
38 #define RK_MMU_INT_CLEAR 0x18 /* Acknowledge and re-arm irq */
39 #define RK_MMU_INT_MASK 0x1C /* IRQ enable */
40 #define RK_MMU_INT_STATUS 0x20 /* IRQ status after masking */
41 #define RK_MMU_AUTO_GATING 0x24
43 #define DTE_ADDR_DUMMY 0xCAFEBABE
45 #define RK_MMU_POLL_PERIOD_US 100
46 #define RK_MMU_FORCE_RESET_TIMEOUT_US 100000
47 #define RK_MMU_POLL_TIMEOUT_US 1000
49 /* RK_MMU_STATUS fields */
50 #define RK_MMU_STATUS_PAGING_ENABLED BIT(0)
51 #define RK_MMU_STATUS_PAGE_FAULT_ACTIVE BIT(1)
52 #define RK_MMU_STATUS_STALL_ACTIVE BIT(2)
53 #define RK_MMU_STATUS_IDLE BIT(3)
54 #define RK_MMU_STATUS_REPLAY_BUFFER_EMPTY BIT(4)
55 #define RK_MMU_STATUS_PAGE_FAULT_IS_WRITE BIT(5)
56 #define RK_MMU_STATUS_STALL_NOT_ACTIVE BIT(31)
58 /* RK_MMU_COMMAND command values */
59 #define RK_MMU_CMD_ENABLE_PAGING 0 /* Enable memory translation */
60 #define RK_MMU_CMD_DISABLE_PAGING 1 /* Disable memory translation */
61 #define RK_MMU_CMD_ENABLE_STALL 2 /* Stall paging to allow other cmds */
62 #define RK_MMU_CMD_DISABLE_STALL 3 /* Stop stall re-enables paging */
63 #define RK_MMU_CMD_ZAP_CACHE 4 /* Shoot down entire IOTLB */
64 #define RK_MMU_CMD_PAGE_FAULT_DONE 5 /* Clear page fault */
65 #define RK_MMU_CMD_FORCE_RESET 6 /* Reset all registers */
67 /* RK_MMU_INT_* register fields */
68 #define RK_MMU_IRQ_PAGE_FAULT 0x01 /* page fault */
69 #define RK_MMU_IRQ_BUS_ERROR 0x02 /* bus read error */
70 #define RK_MMU_IRQ_MASK (RK_MMU_IRQ_PAGE_FAULT | RK_MMU_IRQ_BUS_ERROR)
72 #define NUM_DT_ENTRIES 1024
73 #define NUM_PT_ENTRIES 1024
75 #define SPAGE_ORDER 12
76 #define SPAGE_SIZE (1 << SPAGE_ORDER)
79 * Support mapping any size that fits in one page table:
82 #define RK_IOMMU_PGSIZE_BITMAP 0x007ff000
84 struct rk_iommu_domain {
85 struct list_head iommus;
86 u32 *dt; /* page directory table */
88 spinlock_t iommus_lock; /* lock for iommus list */
89 spinlock_t dt_lock; /* lock for modifying page directory table */
91 struct iommu_domain domain;
94 /* list of clocks required by IOMMU */
95 static const char * const rk_iommu_clocks[] = {
100 phys_addr_t (*pt_address)(u32 dte);
101 u32 (*mk_dtentries)(dma_addr_t pt_dma);
102 u32 (*mk_ptentries)(phys_addr_t page, int prot);
103 phys_addr_t (*dte_addr_phys)(u32 addr);
104 u32 (*dma_addr_dte)(dma_addr_t dt_dma);
110 void __iomem **bases;
113 struct clk_bulk_data *clocks;
116 struct iommu_device iommu;
117 struct list_head node; /* entry in rk_iommu_domain.iommus */
118 struct iommu_domain *domain; /* domain to which iommu is attached */
119 struct iommu_group *group;
122 struct rk_iommudata {
123 struct device_link *link; /* runtime PM link from IOMMU to master */
124 struct rk_iommu *iommu;
127 static struct device *dma_dev;
128 static const struct rk_iommu_ops *rk_ops;
130 static inline void rk_table_flush(struct rk_iommu_domain *dom, dma_addr_t dma,
133 size_t size = count * sizeof(u32); /* count of u32 entry */
135 dma_sync_single_for_device(dma_dev, dma, size, DMA_TO_DEVICE);
138 static struct rk_iommu_domain *to_rk_domain(struct iommu_domain *dom)
140 return container_of(dom, struct rk_iommu_domain, domain);
144 * The Rockchip rk3288 iommu uses a 2-level page table.
145 * The first level is the "Directory Table" (DT).
146 * The DT consists of 1024 4-byte Directory Table Entries (DTEs), each pointing
148 * The second level is the 1024 Page Tables (PT).
149 * Each PT consists of 1024 4-byte Page Table Entries (PTEs), each pointing to
150 * a 4 KB page of physical memory.
152 * The DT and each PT fits in a single 4 KB page (4-bytes * 1024 entries).
153 * Each iommu device has a MMU_DTE_ADDR register that contains the physical
154 * address of the start of the DT page.
156 * The structure of the page table is as follows:
159 * MMU_DTE_ADDR -> +-----+
165 * | | | PTE | -> +-----+
166 * +-----+ +-----+ | |
176 * Each DTE has a PT address and a valid bit:
177 * +---------------------+-----------+-+
178 * | PT address | Reserved |V|
179 * +---------------------+-----------+-+
180 * 31:12 - PT address (PTs always starts on a 4 KB boundary)
182 * 0 - 1 if PT @ PT address is valid
184 #define RK_DTE_PT_ADDRESS_MASK 0xfffff000
185 #define RK_DTE_PT_VALID BIT(0)
187 static inline phys_addr_t rk_dte_pt_address(u32 dte)
189 return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK;
192 static inline bool rk_dte_is_pt_valid(u32 dte)
194 return dte & RK_DTE_PT_VALID;
197 static inline u32 rk_mk_dte(dma_addr_t pt_dma)
199 return (pt_dma & RK_DTE_PT_ADDRESS_MASK) | RK_DTE_PT_VALID;
203 * Each PTE has a Page address, some flags and a valid bit:
204 * +---------------------+---+-------+-+
205 * | Page address |Rsv| Flags |V|
206 * +---------------------+---+-------+-+
207 * 31:12 - Page address (Pages always start on a 4 KB boundary)
210 * 8 - Read allocate - allocate cache space on read misses
211 * 7 - Read cache - enable cache & prefetch of data
212 * 6 - Write buffer - enable delaying writes on their way to memory
213 * 5 - Write allocate - allocate cache space on write misses
214 * 4 - Write cache - different writes can be merged together
215 * 3 - Override cache attributes
216 * if 1, bits 4-8 control cache attributes
217 * if 0, the system bus defaults are used
220 * 0 - 1 if Page @ Page address is valid
222 #define RK_PTE_PAGE_ADDRESS_MASK 0xfffff000
223 #define RK_PTE_PAGE_FLAGS_MASK 0x000001fe
224 #define RK_PTE_PAGE_WRITABLE BIT(2)
225 #define RK_PTE_PAGE_READABLE BIT(1)
226 #define RK_PTE_PAGE_VALID BIT(0)
228 static inline bool rk_pte_is_page_valid(u32 pte)
230 return pte & RK_PTE_PAGE_VALID;
233 /* TODO: set cache flags per prot IOMMU_CACHE */
234 static u32 rk_mk_pte(phys_addr_t page, int prot)
237 flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE : 0;
238 flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE : 0;
239 page &= RK_PTE_PAGE_ADDRESS_MASK;
240 return page | flags | RK_PTE_PAGE_VALID;
243 static u32 rk_mk_pte_invalid(u32 pte)
245 return pte & ~RK_PTE_PAGE_VALID;
249 * rk3288 iova (IOMMU Virtual Address) format
251 * +-----------+-----------+-------------+
252 * | DTE index | PTE index | Page offset |
253 * +-----------+-----------+-------------+
254 * 31:22 - DTE index - index of DTE in DT
255 * 21:12 - PTE index - index of PTE in PT @ DTE.pt_address
256 * 11: 0 - Page offset - offset into page @ PTE.page_address
258 #define RK_IOVA_DTE_MASK 0xffc00000
259 #define RK_IOVA_DTE_SHIFT 22
260 #define RK_IOVA_PTE_MASK 0x003ff000
261 #define RK_IOVA_PTE_SHIFT 12
262 #define RK_IOVA_PAGE_MASK 0x00000fff
263 #define RK_IOVA_PAGE_SHIFT 0
265 static u32 rk_iova_dte_index(dma_addr_t iova)
267 return (u32)(iova & RK_IOVA_DTE_MASK) >> RK_IOVA_DTE_SHIFT;
270 static u32 rk_iova_pte_index(dma_addr_t iova)
272 return (u32)(iova & RK_IOVA_PTE_MASK) >> RK_IOVA_PTE_SHIFT;
275 static u32 rk_iova_page_offset(dma_addr_t iova)
277 return (u32)(iova & RK_IOVA_PAGE_MASK) >> RK_IOVA_PAGE_SHIFT;
280 static u32 rk_iommu_read(void __iomem *base, u32 offset)
282 return readl(base + offset);
285 static void rk_iommu_write(void __iomem *base, u32 offset, u32 value)
287 writel(value, base + offset);
290 static void rk_iommu_command(struct rk_iommu *iommu, u32 command)
294 for (i = 0; i < iommu->num_mmu; i++)
295 writel(command, iommu->bases[i] + RK_MMU_COMMAND);
298 static void rk_iommu_base_command(void __iomem *base, u32 command)
300 writel(command, base + RK_MMU_COMMAND);
302 static void rk_iommu_zap_lines(struct rk_iommu *iommu, dma_addr_t iova_start,
306 dma_addr_t iova_end = iova_start + size;
308 * TODO(djkurtz): Figure out when it is more efficient to shootdown the
309 * entire iotlb rather than iterate over individual iovas.
311 for (i = 0; i < iommu->num_mmu; i++) {
314 for (iova = iova_start; iova < iova_end; iova += SPAGE_SIZE)
315 rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova);
319 static bool rk_iommu_is_stall_active(struct rk_iommu *iommu)
324 for (i = 0; i < iommu->num_mmu; i++)
325 active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) &
326 RK_MMU_STATUS_STALL_ACTIVE);
331 static bool rk_iommu_is_paging_enabled(struct rk_iommu *iommu)
336 for (i = 0; i < iommu->num_mmu; i++)
337 enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) &
338 RK_MMU_STATUS_PAGING_ENABLED);
343 static bool rk_iommu_is_reset_done(struct rk_iommu *iommu)
348 for (i = 0; i < iommu->num_mmu; i++)
349 done &= rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0;
354 static int rk_iommu_enable_stall(struct rk_iommu *iommu)
359 if (rk_iommu_is_stall_active(iommu))
362 /* Stall can only be enabled if paging is enabled */
363 if (!rk_iommu_is_paging_enabled(iommu))
366 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_STALL);
368 ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val,
369 val, RK_MMU_POLL_PERIOD_US,
370 RK_MMU_POLL_TIMEOUT_US);
372 for (i = 0; i < iommu->num_mmu; i++)
373 dev_err(iommu->dev, "Enable stall request timed out, status: %#08x\n",
374 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
379 static int rk_iommu_disable_stall(struct rk_iommu *iommu)
384 if (!rk_iommu_is_stall_active(iommu))
387 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_STALL);
389 ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val,
390 !val, RK_MMU_POLL_PERIOD_US,
391 RK_MMU_POLL_TIMEOUT_US);
393 for (i = 0; i < iommu->num_mmu; i++)
394 dev_err(iommu->dev, "Disable stall request timed out, status: %#08x\n",
395 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
400 static int rk_iommu_enable_paging(struct rk_iommu *iommu)
405 if (rk_iommu_is_paging_enabled(iommu))
408 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_PAGING);
410 ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val,
411 val, RK_MMU_POLL_PERIOD_US,
412 RK_MMU_POLL_TIMEOUT_US);
414 for (i = 0; i < iommu->num_mmu; i++)
415 dev_err(iommu->dev, "Enable paging request timed out, status: %#08x\n",
416 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
421 static int rk_iommu_disable_paging(struct rk_iommu *iommu)
426 if (!rk_iommu_is_paging_enabled(iommu))
429 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_PAGING);
431 ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val,
432 !val, RK_MMU_POLL_PERIOD_US,
433 RK_MMU_POLL_TIMEOUT_US);
435 for (i = 0; i < iommu->num_mmu; i++)
436 dev_err(iommu->dev, "Disable paging request timed out, status: %#08x\n",
437 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
442 static int rk_iommu_force_reset(struct rk_iommu *iommu)
448 if (iommu->reset_disabled)
452 * Check if register DTE_ADDR is working by writing DTE_ADDR_DUMMY
453 * and verifying that upper 5 nybbles are read back.
455 for (i = 0; i < iommu->num_mmu; i++) {
456 dte_addr = rk_ops->pt_address(DTE_ADDR_DUMMY);
457 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, dte_addr);
459 if (dte_addr != rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR)) {
460 dev_err(iommu->dev, "Error during raw reset. MMU_DTE_ADDR is not functioning\n");
465 rk_iommu_command(iommu, RK_MMU_CMD_FORCE_RESET);
467 ret = readx_poll_timeout(rk_iommu_is_reset_done, iommu, val,
468 val, RK_MMU_FORCE_RESET_TIMEOUT_US,
469 RK_MMU_POLL_TIMEOUT_US);
471 dev_err(iommu->dev, "FORCE_RESET command timed out\n");
478 static inline phys_addr_t rk_dte_addr_phys(u32 addr)
480 return (phys_addr_t)addr;
483 static inline u32 rk_dma_addr_dte(dma_addr_t dt_dma)
488 static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova)
490 void __iomem *base = iommu->bases[index];
491 u32 dte_index, pte_index, page_offset;
493 phys_addr_t mmu_dte_addr_phys, dte_addr_phys;
496 phys_addr_t pte_addr_phys = 0;
497 u32 *pte_addr = NULL;
499 phys_addr_t page_addr_phys = 0;
502 dte_index = rk_iova_dte_index(iova);
503 pte_index = rk_iova_pte_index(iova);
504 page_offset = rk_iova_page_offset(iova);
506 mmu_dte_addr = rk_iommu_read(base, RK_MMU_DTE_ADDR);
507 mmu_dte_addr_phys = rk_ops->dte_addr_phys(mmu_dte_addr);
509 dte_addr_phys = mmu_dte_addr_phys + (4 * dte_index);
510 dte_addr = phys_to_virt(dte_addr_phys);
513 if (!rk_dte_is_pt_valid(dte))
516 pte_addr_phys = rk_ops->pt_address(dte) + (pte_index * 4);
517 pte_addr = phys_to_virt(pte_addr_phys);
520 if (!rk_pte_is_page_valid(pte))
523 page_addr_phys = rk_ops->pt_address(pte) + page_offset;
524 page_flags = pte & RK_PTE_PAGE_FLAGS_MASK;
527 dev_err(iommu->dev, "iova = %pad: dte_index: %#03x pte_index: %#03x page_offset: %#03x\n",
528 &iova, dte_index, pte_index, page_offset);
529 dev_err(iommu->dev, "mmu_dte_addr: %pa dte@%pa: %#08x valid: %u pte@%pa: %#08x valid: %u page@%pa flags: %#03x\n",
530 &mmu_dte_addr_phys, &dte_addr_phys, dte,
531 rk_dte_is_pt_valid(dte), &pte_addr_phys, pte,
532 rk_pte_is_page_valid(pte), &page_addr_phys, page_flags);
535 static irqreturn_t rk_iommu_irq(int irq, void *dev_id)
537 struct rk_iommu *iommu = dev_id;
541 irqreturn_t ret = IRQ_NONE;
544 err = pm_runtime_get_if_in_use(iommu->dev);
545 if (!err || WARN_ON_ONCE(err < 0))
548 if (WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks)))
551 for (i = 0; i < iommu->num_mmu; i++) {
552 int_status = rk_iommu_read(iommu->bases[i], RK_MMU_INT_STATUS);
557 iova = rk_iommu_read(iommu->bases[i], RK_MMU_PAGE_FAULT_ADDR);
559 if (int_status & RK_MMU_IRQ_PAGE_FAULT) {
562 status = rk_iommu_read(iommu->bases[i], RK_MMU_STATUS);
563 flags = (status & RK_MMU_STATUS_PAGE_FAULT_IS_WRITE) ?
564 IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
566 dev_err(iommu->dev, "Page fault at %pad of type %s\n",
568 (flags == IOMMU_FAULT_WRITE) ? "write" : "read");
570 log_iova(iommu, i, iova);
573 * Report page fault to any installed handlers.
574 * Ignore the return code, though, since we always zap cache
575 * and clear the page fault anyway.
578 report_iommu_fault(iommu->domain, iommu->dev, iova,
581 dev_err(iommu->dev, "Page fault while iommu not attached to domain?\n");
583 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE);
584 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_PAGE_FAULT_DONE);
587 if (int_status & RK_MMU_IRQ_BUS_ERROR)
588 dev_err(iommu->dev, "BUS_ERROR occurred at %pad\n", &iova);
590 if (int_status & ~RK_MMU_IRQ_MASK)
591 dev_err(iommu->dev, "unexpected int_status: %#08x\n",
594 rk_iommu_write(iommu->bases[i], RK_MMU_INT_CLEAR, int_status);
597 clk_bulk_disable(iommu->num_clocks, iommu->clocks);
600 pm_runtime_put(iommu->dev);
604 static phys_addr_t rk_iommu_iova_to_phys(struct iommu_domain *domain,
607 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
609 phys_addr_t pt_phys, phys = 0;
613 spin_lock_irqsave(&rk_domain->dt_lock, flags);
615 dte = rk_domain->dt[rk_iova_dte_index(iova)];
616 if (!rk_dte_is_pt_valid(dte))
619 pt_phys = rk_ops->pt_address(dte);
620 page_table = (u32 *)phys_to_virt(pt_phys);
621 pte = page_table[rk_iova_pte_index(iova)];
622 if (!rk_pte_is_page_valid(pte))
625 phys = rk_ops->pt_address(pte) + rk_iova_page_offset(iova);
627 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
632 static void rk_iommu_zap_iova(struct rk_iommu_domain *rk_domain,
633 dma_addr_t iova, size_t size)
635 struct list_head *pos;
638 /* shootdown these iova from all iommus using this domain */
639 spin_lock_irqsave(&rk_domain->iommus_lock, flags);
640 list_for_each(pos, &rk_domain->iommus) {
641 struct rk_iommu *iommu;
644 iommu = list_entry(pos, struct rk_iommu, node);
646 /* Only zap TLBs of IOMMUs that are powered on. */
647 ret = pm_runtime_get_if_in_use(iommu->dev);
648 if (WARN_ON_ONCE(ret < 0))
651 WARN_ON(clk_bulk_enable(iommu->num_clocks,
653 rk_iommu_zap_lines(iommu, iova, size);
654 clk_bulk_disable(iommu->num_clocks, iommu->clocks);
655 pm_runtime_put(iommu->dev);
658 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
661 static void rk_iommu_zap_iova_first_last(struct rk_iommu_domain *rk_domain,
662 dma_addr_t iova, size_t size)
664 rk_iommu_zap_iova(rk_domain, iova, SPAGE_SIZE);
665 if (size > SPAGE_SIZE)
666 rk_iommu_zap_iova(rk_domain, iova + size - SPAGE_SIZE,
670 static u32 *rk_dte_get_page_table(struct rk_iommu_domain *rk_domain,
673 u32 *page_table, *dte_addr;
678 assert_spin_locked(&rk_domain->dt_lock);
680 dte_index = rk_iova_dte_index(iova);
681 dte_addr = &rk_domain->dt[dte_index];
683 if (rk_dte_is_pt_valid(dte))
686 page_table = (u32 *)get_zeroed_page(GFP_ATOMIC | GFP_DMA32);
688 return ERR_PTR(-ENOMEM);
690 pt_dma = dma_map_single(dma_dev, page_table, SPAGE_SIZE, DMA_TO_DEVICE);
691 if (dma_mapping_error(dma_dev, pt_dma)) {
692 dev_err(dma_dev, "DMA mapping error while allocating page table\n");
693 free_page((unsigned long)page_table);
694 return ERR_PTR(-ENOMEM);
697 dte = rk_ops->mk_dtentries(pt_dma);
700 rk_table_flush(rk_domain,
701 rk_domain->dt_dma + dte_index * sizeof(u32), 1);
703 pt_phys = rk_ops->pt_address(dte);
704 return (u32 *)phys_to_virt(pt_phys);
707 static size_t rk_iommu_unmap_iova(struct rk_iommu_domain *rk_domain,
708 u32 *pte_addr, dma_addr_t pte_dma,
711 unsigned int pte_count;
712 unsigned int pte_total = size / SPAGE_SIZE;
714 assert_spin_locked(&rk_domain->dt_lock);
716 for (pte_count = 0; pte_count < pte_total; pte_count++) {
717 u32 pte = pte_addr[pte_count];
718 if (!rk_pte_is_page_valid(pte))
721 pte_addr[pte_count] = rk_mk_pte_invalid(pte);
724 rk_table_flush(rk_domain, pte_dma, pte_count);
726 return pte_count * SPAGE_SIZE;
729 static int rk_iommu_map_iova(struct rk_iommu_domain *rk_domain, u32 *pte_addr,
730 dma_addr_t pte_dma, dma_addr_t iova,
731 phys_addr_t paddr, size_t size, int prot)
733 unsigned int pte_count;
734 unsigned int pte_total = size / SPAGE_SIZE;
735 phys_addr_t page_phys;
737 assert_spin_locked(&rk_domain->dt_lock);
739 for (pte_count = 0; pte_count < pte_total; pte_count++) {
740 u32 pte = pte_addr[pte_count];
742 if (rk_pte_is_page_valid(pte))
745 pte_addr[pte_count] = rk_ops->mk_ptentries(paddr, prot);
750 rk_table_flush(rk_domain, pte_dma, pte_total);
753 * Zap the first and last iova to evict from iotlb any previously
754 * mapped cachelines holding stale values for its dte and pte.
755 * We only zap the first and last iova, since only they could have
756 * dte or pte shared with an existing mapping.
758 rk_iommu_zap_iova_first_last(rk_domain, iova, size);
762 /* Unmap the range of iovas that we just mapped */
763 rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma,
764 pte_count * SPAGE_SIZE);
766 iova += pte_count * SPAGE_SIZE;
767 page_phys = rk_ops->pt_address(pte_addr[pte_count]);
768 pr_err("iova: %pad already mapped to %pa cannot remap to phys: %pa prot: %#x\n",
769 &iova, &page_phys, &paddr, prot);
774 static int rk_iommu_map(struct iommu_domain *domain, unsigned long _iova,
775 phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
777 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
779 dma_addr_t pte_dma, iova = (dma_addr_t)_iova;
780 u32 *page_table, *pte_addr;
781 u32 dte_index, pte_index;
784 spin_lock_irqsave(&rk_domain->dt_lock, flags);
787 * pgsize_bitmap specifies iova sizes that fit in one page table
788 * (1024 4-KiB pages = 4 MiB).
789 * So, size will always be 4096 <= size <= 4194304.
790 * Since iommu_map() guarantees that both iova and size will be
791 * aligned, we will always only be mapping from a single dte here.
793 page_table = rk_dte_get_page_table(rk_domain, iova);
794 if (IS_ERR(page_table)) {
795 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
796 return PTR_ERR(page_table);
799 dte_index = rk_domain->dt[rk_iova_dte_index(iova)];
800 pte_index = rk_iova_pte_index(iova);
801 pte_addr = &page_table[pte_index];
803 pte_dma = rk_ops->pt_address(dte_index) + pte_index * sizeof(u32);
804 ret = rk_iommu_map_iova(rk_domain, pte_addr, pte_dma, iova,
807 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
812 static size_t rk_iommu_unmap(struct iommu_domain *domain, unsigned long _iova,
813 size_t size, struct iommu_iotlb_gather *gather)
815 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
817 dma_addr_t pte_dma, iova = (dma_addr_t)_iova;
823 spin_lock_irqsave(&rk_domain->dt_lock, flags);
826 * pgsize_bitmap specifies iova sizes that fit in one page table
827 * (1024 4-KiB pages = 4 MiB).
828 * So, size will always be 4096 <= size <= 4194304.
829 * Since iommu_unmap() guarantees that both iova and size will be
830 * aligned, we will always only be unmapping from a single dte here.
832 dte = rk_domain->dt[rk_iova_dte_index(iova)];
833 /* Just return 0 if iova is unmapped */
834 if (!rk_dte_is_pt_valid(dte)) {
835 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
839 pt_phys = rk_ops->pt_address(dte);
840 pte_addr = (u32 *)phys_to_virt(pt_phys) + rk_iova_pte_index(iova);
841 pte_dma = pt_phys + rk_iova_pte_index(iova) * sizeof(u32);
842 unmap_size = rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma, size);
844 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
846 /* Shootdown iotlb entries for iova range that was just unmapped */
847 rk_iommu_zap_iova(rk_domain, iova, unmap_size);
852 static struct rk_iommu *rk_iommu_from_dev(struct device *dev)
854 struct rk_iommudata *data = dev_iommu_priv_get(dev);
856 return data ? data->iommu : NULL;
859 /* Must be called with iommu powered on and attached */
860 static void rk_iommu_disable(struct rk_iommu *iommu)
864 /* Ignore error while disabling, just keep going */
865 WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks));
866 rk_iommu_enable_stall(iommu);
867 rk_iommu_disable_paging(iommu);
868 for (i = 0; i < iommu->num_mmu; i++) {
869 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, 0);
870 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, 0);
872 rk_iommu_disable_stall(iommu);
873 clk_bulk_disable(iommu->num_clocks, iommu->clocks);
876 /* Must be called with iommu powered on and attached */
877 static int rk_iommu_enable(struct rk_iommu *iommu)
879 struct iommu_domain *domain = iommu->domain;
880 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
883 ret = clk_bulk_enable(iommu->num_clocks, iommu->clocks);
887 ret = rk_iommu_enable_stall(iommu);
889 goto out_disable_clocks;
891 ret = rk_iommu_force_reset(iommu);
893 goto out_disable_stall;
895 for (i = 0; i < iommu->num_mmu; i++) {
896 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR,
897 rk_ops->dma_addr_dte(rk_domain->dt_dma));
898 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE);
899 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK);
902 ret = rk_iommu_enable_paging(iommu);
905 rk_iommu_disable_stall(iommu);
907 clk_bulk_disable(iommu->num_clocks, iommu->clocks);
911 static void rk_iommu_detach_device(struct iommu_domain *domain,
914 struct rk_iommu *iommu;
915 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
919 /* Allow 'virtual devices' (eg drm) to detach from domain */
920 iommu = rk_iommu_from_dev(dev);
924 dev_dbg(dev, "Detaching from iommu domain\n");
926 /* iommu already detached */
927 if (iommu->domain != domain)
930 iommu->domain = NULL;
932 spin_lock_irqsave(&rk_domain->iommus_lock, flags);
933 list_del_init(&iommu->node);
934 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
936 ret = pm_runtime_get_if_in_use(iommu->dev);
937 WARN_ON_ONCE(ret < 0);
939 rk_iommu_disable(iommu);
940 pm_runtime_put(iommu->dev);
944 static int rk_iommu_attach_device(struct iommu_domain *domain,
947 struct rk_iommu *iommu;
948 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
953 * Allow 'virtual devices' (e.g., drm) to attach to domain.
954 * Such a device does not belong to an iommu group.
956 iommu = rk_iommu_from_dev(dev);
960 dev_dbg(dev, "Attaching to iommu domain\n");
962 /* iommu already attached */
963 if (iommu->domain == domain)
967 rk_iommu_detach_device(iommu->domain, dev);
969 iommu->domain = domain;
971 spin_lock_irqsave(&rk_domain->iommus_lock, flags);
972 list_add_tail(&iommu->node, &rk_domain->iommus);
973 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
975 ret = pm_runtime_get_if_in_use(iommu->dev);
976 if (!ret || WARN_ON_ONCE(ret < 0))
979 ret = rk_iommu_enable(iommu);
981 rk_iommu_detach_device(iommu->domain, dev);
983 pm_runtime_put(iommu->dev);
988 static struct iommu_domain *rk_iommu_domain_alloc(unsigned type)
990 struct rk_iommu_domain *rk_domain;
992 if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
998 rk_domain = kzalloc(sizeof(*rk_domain), GFP_KERNEL);
1002 if (type == IOMMU_DOMAIN_DMA &&
1003 iommu_get_dma_cookie(&rk_domain->domain))
1004 goto err_free_domain;
1007 * rk32xx iommus use a 2 level pagetable.
1008 * Each level1 (dt) and level2 (pt) table has 1024 4-byte entries.
1009 * Allocate one 4 KiB page for each table.
1011 rk_domain->dt = (u32 *)get_zeroed_page(GFP_KERNEL | GFP_DMA32);
1013 goto err_put_cookie;
1015 rk_domain->dt_dma = dma_map_single(dma_dev, rk_domain->dt,
1016 SPAGE_SIZE, DMA_TO_DEVICE);
1017 if (dma_mapping_error(dma_dev, rk_domain->dt_dma)) {
1018 dev_err(dma_dev, "DMA map error for DT\n");
1022 spin_lock_init(&rk_domain->iommus_lock);
1023 spin_lock_init(&rk_domain->dt_lock);
1024 INIT_LIST_HEAD(&rk_domain->iommus);
1026 rk_domain->domain.geometry.aperture_start = 0;
1027 rk_domain->domain.geometry.aperture_end = DMA_BIT_MASK(32);
1028 rk_domain->domain.geometry.force_aperture = true;
1030 return &rk_domain->domain;
1033 free_page((unsigned long)rk_domain->dt);
1035 if (type == IOMMU_DOMAIN_DMA)
1036 iommu_put_dma_cookie(&rk_domain->domain);
1043 static void rk_iommu_domain_free(struct iommu_domain *domain)
1045 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
1048 WARN_ON(!list_empty(&rk_domain->iommus));
1050 for (i = 0; i < NUM_DT_ENTRIES; i++) {
1051 u32 dte = rk_domain->dt[i];
1052 if (rk_dte_is_pt_valid(dte)) {
1053 phys_addr_t pt_phys = rk_ops->pt_address(dte);
1054 u32 *page_table = phys_to_virt(pt_phys);
1055 dma_unmap_single(dma_dev, pt_phys,
1056 SPAGE_SIZE, DMA_TO_DEVICE);
1057 free_page((unsigned long)page_table);
1061 dma_unmap_single(dma_dev, rk_domain->dt_dma,
1062 SPAGE_SIZE, DMA_TO_DEVICE);
1063 free_page((unsigned long)rk_domain->dt);
1065 if (domain->type == IOMMU_DOMAIN_DMA)
1066 iommu_put_dma_cookie(&rk_domain->domain);
1070 static struct iommu_device *rk_iommu_probe_device(struct device *dev)
1072 struct rk_iommudata *data;
1073 struct rk_iommu *iommu;
1075 data = dev_iommu_priv_get(dev);
1077 return ERR_PTR(-ENODEV);
1079 iommu = rk_iommu_from_dev(dev);
1081 data->link = device_link_add(dev, iommu->dev,
1082 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME);
1084 return &iommu->iommu;
1087 static void rk_iommu_release_device(struct device *dev)
1089 struct rk_iommudata *data = dev_iommu_priv_get(dev);
1091 device_link_del(data->link);
1094 static struct iommu_group *rk_iommu_device_group(struct device *dev)
1096 struct rk_iommu *iommu;
1098 iommu = rk_iommu_from_dev(dev);
1100 return iommu_group_ref_get(iommu->group);
1103 static int rk_iommu_of_xlate(struct device *dev,
1104 struct of_phandle_args *args)
1106 struct platform_device *iommu_dev;
1107 struct rk_iommudata *data;
1109 data = devm_kzalloc(dma_dev, sizeof(*data), GFP_KERNEL);
1113 iommu_dev = of_find_device_by_node(args->np);
1115 data->iommu = platform_get_drvdata(iommu_dev);
1116 dev_iommu_priv_set(dev, data);
1118 platform_device_put(iommu_dev);
1123 static const struct iommu_ops rk_iommu_ops = {
1124 .domain_alloc = rk_iommu_domain_alloc,
1125 .domain_free = rk_iommu_domain_free,
1126 .attach_dev = rk_iommu_attach_device,
1127 .detach_dev = rk_iommu_detach_device,
1128 .map = rk_iommu_map,
1129 .unmap = rk_iommu_unmap,
1130 .probe_device = rk_iommu_probe_device,
1131 .release_device = rk_iommu_release_device,
1132 .iova_to_phys = rk_iommu_iova_to_phys,
1133 .device_group = rk_iommu_device_group,
1134 .pgsize_bitmap = RK_IOMMU_PGSIZE_BITMAP,
1135 .of_xlate = rk_iommu_of_xlate,
1138 static int rk_iommu_probe(struct platform_device *pdev)
1140 struct device *dev = &pdev->dev;
1141 struct rk_iommu *iommu;
1142 struct resource *res;
1143 const struct rk_iommu_ops *ops;
1144 int num_res = pdev->num_resources;
1147 iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL);
1151 platform_set_drvdata(pdev, iommu);
1155 ops = of_device_get_match_data(dev);
1160 * That should not happen unless different versions of the
1161 * hardware block are embedded the same SoC
1163 if (WARN_ON(rk_ops != ops))
1166 iommu->bases = devm_kcalloc(dev, num_res, sizeof(*iommu->bases),
1171 for (i = 0; i < num_res; i++) {
1172 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1175 iommu->bases[i] = devm_ioremap_resource(&pdev->dev, res);
1176 if (IS_ERR(iommu->bases[i]))
1180 if (iommu->num_mmu == 0)
1181 return PTR_ERR(iommu->bases[0]);
1183 iommu->num_irq = platform_irq_count(pdev);
1184 if (iommu->num_irq < 0)
1185 return iommu->num_irq;
1187 iommu->reset_disabled = device_property_read_bool(dev,
1188 "rockchip,disable-mmu-reset");
1190 iommu->num_clocks = ARRAY_SIZE(rk_iommu_clocks);
1191 iommu->clocks = devm_kcalloc(iommu->dev, iommu->num_clocks,
1192 sizeof(*iommu->clocks), GFP_KERNEL);
1196 for (i = 0; i < iommu->num_clocks; ++i)
1197 iommu->clocks[i].id = rk_iommu_clocks[i];
1200 * iommu clocks should be present for all new devices and devicetrees
1201 * but there are older devicetrees without clocks out in the wild.
1202 * So clocks as optional for the time being.
1204 err = devm_clk_bulk_get(iommu->dev, iommu->num_clocks, iommu->clocks);
1206 iommu->num_clocks = 0;
1210 err = clk_bulk_prepare(iommu->num_clocks, iommu->clocks);
1214 iommu->group = iommu_group_alloc();
1215 if (IS_ERR(iommu->group)) {
1216 err = PTR_ERR(iommu->group);
1217 goto err_unprepare_clocks;
1220 err = iommu_device_sysfs_add(&iommu->iommu, dev, NULL, dev_name(dev));
1224 err = iommu_device_register(&iommu->iommu, &rk_iommu_ops, dev);
1226 goto err_remove_sysfs;
1229 * Use the first registered IOMMU device for domain to use with DMA
1230 * API, since a domain might not physically correspond to a single
1234 dma_dev = &pdev->dev;
1236 bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
1238 pm_runtime_enable(dev);
1240 for (i = 0; i < iommu->num_irq; i++) {
1241 int irq = platform_get_irq(pdev, i);
1246 err = devm_request_irq(iommu->dev, irq, rk_iommu_irq,
1247 IRQF_SHARED, dev_name(dev), iommu);
1249 pm_runtime_disable(dev);
1250 goto err_remove_sysfs;
1254 dma_set_mask_and_coherent(dev, rk_ops->dma_bit_mask);
1258 iommu_device_sysfs_remove(&iommu->iommu);
1260 iommu_group_put(iommu->group);
1261 err_unprepare_clocks:
1262 clk_bulk_unprepare(iommu->num_clocks, iommu->clocks);
1266 static void rk_iommu_shutdown(struct platform_device *pdev)
1268 struct rk_iommu *iommu = platform_get_drvdata(pdev);
1271 for (i = 0; i < iommu->num_irq; i++) {
1272 int irq = platform_get_irq(pdev, i);
1274 devm_free_irq(iommu->dev, irq, iommu);
1277 pm_runtime_force_suspend(&pdev->dev);
1280 static int __maybe_unused rk_iommu_suspend(struct device *dev)
1282 struct rk_iommu *iommu = dev_get_drvdata(dev);
1287 rk_iommu_disable(iommu);
1291 static int __maybe_unused rk_iommu_resume(struct device *dev)
1293 struct rk_iommu *iommu = dev_get_drvdata(dev);
1298 return rk_iommu_enable(iommu);
1301 static const struct dev_pm_ops rk_iommu_pm_ops = {
1302 SET_RUNTIME_PM_OPS(rk_iommu_suspend, rk_iommu_resume, NULL)
1303 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1304 pm_runtime_force_resume)
1307 static struct rk_iommu_ops iommu_data_ops_v1 = {
1308 .pt_address = &rk_dte_pt_address,
1309 .mk_dtentries = &rk_mk_dte,
1310 .mk_ptentries = &rk_mk_pte,
1311 .dte_addr_phys = &rk_dte_addr_phys,
1312 .dma_addr_dte = &rk_dma_addr_dte,
1313 .dma_bit_mask = DMA_BIT_MASK(32),
1317 static const struct of_device_id rk_iommu_dt_ids[] = {
1318 { .compatible = "rockchip,iommu",
1319 .data = &iommu_data_ops_v1,
1324 static struct platform_driver rk_iommu_driver = {
1325 .probe = rk_iommu_probe,
1326 .shutdown = rk_iommu_shutdown,
1329 .of_match_table = rk_iommu_dt_ids,
1330 .pm = &rk_iommu_pm_ops,
1331 .suppress_bind_attrs = true,
1335 static int __init rk_iommu_init(void)
1337 return platform_driver_register(&rk_iommu_driver);
1339 subsys_initcall(rk_iommu_init);